| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.93 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.26 |
| T1003 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.960997023 | Sep 01 11:07:44 PM UTC 24 | Sep 01 11:07:47 PM UTC 24 | 40614881 ps | ||
| T1004 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.94539583 | Sep 01 11:07:42 PM UTC 24 | Sep 01 11:07:48 PM UTC 24 | 1061501842 ps | ||
| T1005 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.99578235 | Sep 01 11:07:47 PM UTC 24 | Sep 01 11:07:49 PM UTC 24 | 38664754 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2995320701 | Sep 01 11:07:47 PM UTC 24 | Sep 01 11:07:49 PM UTC 24 | 101163241 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3173321380 | Sep 01 11:07:45 PM UTC 24 | Sep 01 11:07:49 PM UTC 24 | 1065423667 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3463514737 | Sep 01 11:07:45 PM UTC 24 | Sep 01 11:07:49 PM UTC 24 | 280053874 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.271806845 | Sep 01 11:07:42 PM UTC 24 | Sep 01 11:07:50 PM UTC 24 | 1934432045 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2067110911 | Sep 01 11:07:47 PM UTC 24 | Sep 01 11:07:50 PM UTC 24 | 34292849 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.125093504 | Sep 01 11:07:45 PM UTC 24 | Sep 01 11:07:51 PM UTC 24 | 480470935 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2769797585 | Sep 01 11:07:50 PM UTC 24 | Sep 01 11:07:52 PM UTC 24 | 15051261 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1683791959 | Sep 01 11:07:50 PM UTC 24 | Sep 01 11:07:52 PM UTC 24 | 134928763 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1193722560 | Sep 01 11:07:50 PM UTC 24 | Sep 01 11:07:52 PM UTC 24 | 26013647 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3685257619 | Sep 01 11:07:50 PM UTC 24 | Sep 01 11:07:53 PM UTC 24 | 255850191 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3694893924 | Sep 01 11:07:47 PM UTC 24 | Sep 01 11:07:53 PM UTC 24 | 2200922925 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3182536475 | Sep 01 11:07:52 PM UTC 24 | Sep 01 11:07:54 PM UTC 24 | 54454371 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.956839727 | Sep 01 11:07:48 PM UTC 24 | Sep 01 11:07:54 PM UTC 24 | 50949648 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1597922618 | Sep 01 11:07:53 PM UTC 24 | Sep 01 11:07:55 PM UTC 24 | 23898803 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3209737395 | Sep 01 11:07:52 PM UTC 24 | Sep 01 11:07:56 PM UTC 24 | 181586541 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1056671395 | Sep 01 11:07:52 PM UTC 24 | Sep 01 11:07:56 PM UTC 24 | 222833065 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2116262198 | Sep 01 11:07:55 PM UTC 24 | Sep 01 11:07:57 PM UTC 24 | 23769414 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3994125117 | Sep 01 11:07:53 PM UTC 24 | Sep 01 11:07:57 PM UTC 24 | 138270709 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2226492954 | Sep 01 11:07:52 PM UTC 24 | Sep 01 11:07:57 PM UTC 24 | 1162947080 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4220118455 | Sep 01 11:07:55 PM UTC 24 | Sep 01 11:07:58 PM UTC 24 | 274386208 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2902235830 | Sep 01 11:07:53 PM UTC 24 | Sep 01 11:07:58 PM UTC 24 | 385598117 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2885427200 | Sep 01 11:07:56 PM UTC 24 | Sep 01 11:07:58 PM UTC 24 | 41625640 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1714014838 | Sep 01 11:07:55 PM UTC 24 | Sep 01 11:08:00 PM UTC 24 | 298058426 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1777724813 | Sep 01 11:07:57 PM UTC 24 | Sep 01 11:08:00 PM UTC 24 | 429716216 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.232677368 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2465142909 ps |
| CPU time | 8.96 seconds |
| Started | Sep 01 09:45:15 PM UTC 24 |
| Finished | Sep 01 09:45:25 PM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232677368 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.232677368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1631327331 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1431109761 ps |
| CPU time | 336.82 seconds |
| Started | Sep 01 09:45:16 PM UTC 24 |
| Finished | Sep 01 09:50:58 PM UTC 24 |
| Peak memory | 370808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631327331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1631327331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3448148968 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1428693501 ps |
| CPU time | 51.75 seconds |
| Started | Sep 01 10:02:27 PM UTC 24 |
| Finished | Sep 01 10:03:20 PM UTC 24 |
| Peak memory | 319336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448148968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3448148968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1701516269 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1166816540 ps |
| CPU time | 4.04 seconds |
| Started | Sep 01 09:46:23 PM UTC 24 |
| Finished | Sep 01 09:46:28 PM UTC 24 |
| Peak memory | 250188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701516269 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1701516269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3727551687 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 89057772 ps |
| CPU time | 4.05 seconds |
| Started | Sep 01 09:45:16 PM UTC 24 |
| Finished | Sep 01 09:45:21 PM UTC 24 |
| Peak memory | 223844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727551687 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.3727551687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2690082768 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 147869451 ps |
| CPU time | 3 seconds |
| Started | Sep 01 11:05:58 PM UTC 24 |
| Finished | Sep 01 11:06:03 PM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26900 82768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_in tg_err.2690082768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1508961640 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 23620948064 ps |
| CPU time | 547.14 seconds |
| Started | Sep 01 09:46:01 PM UTC 24 |
| Finished | Sep 01 09:55:15 PM UTC 24 |
| Peak memory | 376688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508961640 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.1508961640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.427628315 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 82471510079 ps |
| CPU time | 619.34 seconds |
| Started | Sep 01 09:45:35 PM UTC 24 |
| Finished | Sep 01 09:56:03 PM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427628315 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acces s_b2b.427628315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3693692633 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 168291920 ps |
| CPU time | 117.82 seconds |
| Started | Sep 01 09:45:41 PM UTC 24 |
| Finished | Sep 01 09:47:42 PM UTC 24 |
| Peak memory | 381100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3693692633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th roughput_w_partial_write.3693692633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.874484869 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 23918120948 ps |
| CPU time | 1337.46 seconds |
| Started | Sep 01 09:52:57 PM UTC 24 |
| Finished | Sep 01 10:15:30 PM UTC 24 |
| Peak memory | 384944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874484869 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.874484869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1988677232 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 443418926 ps |
| CPU time | 4.65 seconds |
| Started | Sep 01 11:06:08 PM UTC 24 |
| Finished | Sep 01 11:06:14 PM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 88677232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pa ssthru_mem_tl_intg_err.1988677232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.921862446 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 30267491 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:45:16 PM UTC 24 |
| Finished | Sep 01 09:45:18 PM UTC 24 |
| Peak memory | 213160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921862446 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.921862446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.874584218 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 11003782383 ps |
| CPU time | 1224.28 seconds |
| Started | Sep 01 09:47:18 PM UTC 24 |
| Finished | Sep 01 10:07:57 PM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874584218 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.874584218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3261655597 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 39962420 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 09:45:23 PM UTC 24 |
| Finished | Sep 01 09:45:25 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261655597 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3261655597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3261738386 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 686062291 ps |
| CPU time | 3.13 seconds |
| Started | Sep 01 11:07:32 PM UTC 24 |
| Finished | Sep 01 11:07:36 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32617 38386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i ntg_err.3261738386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3854167831 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 51904157379 ps |
| CPU time | 2094.09 seconds |
| Started | Sep 01 09:56:24 PM UTC 24 |
| Finished | Sep 01 10:31:41 PM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385416783 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.3854167831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3140213512 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2426261995 ps |
| CPU time | 92.84 seconds |
| Started | Sep 01 09:45:15 PM UTC 24 |
| Finished | Sep 01 09:46:50 PM UTC 24 |
| Peak memory | 362340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140213512 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.3140213512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2794032108 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 258796886 ps |
| CPU time | 5.91 seconds |
| Started | Sep 01 10:14:41 PM UTC 24 |
| Finished | Sep 01 10:14:48 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794032108 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2794032108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4197373517 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 362211121 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 11:07:36 PM UTC 24 |
| Finished | Sep 01 11:07:39 PM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41973 73517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i ntg_err.4197373517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.297439431 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 360084928 ps |
| CPU time | 3.09 seconds |
| Started | Sep 01 11:07:40 PM UTC 24 |
| Finished | Sep 01 11:07:44 PM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29743 9431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_in tg_err.297439431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.125093504 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 480470935 ps |
| CPU time | 4.19 seconds |
| Started | Sep 01 11:07:45 PM UTC 24 |
| Finished | Sep 01 11:07:51 PM UTC 24 |
| Peak memory | 223624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12509 3504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_in tg_err.125093504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2005153337 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 713004958 ps |
| CPU time | 2.76 seconds |
| Started | Sep 01 11:06:54 PM UTC 24 |
| Finished | Sep 01 11:06:58 PM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20051 53337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in tg_err.2005153337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.718153558 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2453174137 ps |
| CPU time | 267.96 seconds |
| Started | Sep 01 09:45:15 PM UTC 24 |
| Finished | Sep 01 09:49:47 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718153558 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acces s_b2b.718153558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2140836129 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 55326285130 ps |
| CPU time | 991.47 seconds |
| Started | Sep 01 09:45:16 PM UTC 24 |
| Finished | Sep 01 10:01:58 PM UTC 24 |
| Peak memory | 376760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140836129 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2140836129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2332939532 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 17395395 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 11:06:04 PM UTC 24 |
| Finished | Sep 01 11:06:06 PM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23329395 32 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alia sing.2332939532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2007805605 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 625270988 ps |
| CPU time | 3.34 seconds |
| Started | Sep 01 11:06:04 PM UTC 24 |
| Finished | Sep 01 11:06:08 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20078056 05 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_ bash.2007805605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.310627567 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27223514 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 11:06:00 PM UTC 24 |
| Finished | Sep 01 11:06:03 PM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31062756 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_re set.310627567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.674401016 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 31572163 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 11:06:07 PM UTC 24 |
| Finished | Sep 01 11:06:10 PM UTC 24 |
| Peak memory | 221716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=674401016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.674401016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1297174811 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 19886030 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 11:06:02 PM UTC 24 |
| Finished | Sep 01 11:06:04 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297174811 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.1297174811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1708920909 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1914573468 ps |
| CPU time | 4.18 seconds |
| Started | Sep 01 11:05:52 PM UTC 24 |
| Finished | Sep 01 11:05:57 PM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 08920909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa ssthru_mem_tl_intg_err.1708920909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3287391630 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 145618671 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 11:06:05 PM UTC 24 |
| Finished | Sep 01 11:06:07 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3287391630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c trl_same_csr_outstanding.3287391630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1645257386 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 59893933 ps |
| CPU time | 3.25 seconds |
| Started | Sep 01 11:05:55 PM UTC 24 |
| Finished | Sep 01 11:05:59 PM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645257386 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.1645257386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.736255890 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 35506302 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 11:06:18 PM UTC 24 |
| Finished | Sep 01 11:06:20 PM UTC 24 |
| Peak memory | 210360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73625589 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alias ing.736255890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3858817368 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 485221707 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 11:06:17 PM UTC 24 |
| Finished | Sep 01 11:06:21 PM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38588173 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_ bash.3858817368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1444873784 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 13273746 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 11:06:15 PM UTC 24 |
| Finished | Sep 01 11:06:16 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14448737 84 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r eset.1444873784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2557288339 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 40608353 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 11:06:22 PM UTC 24 |
| Finished | Sep 01 11:06:24 PM UTC 24 |
| Peak memory | 220608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2557288339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2557288339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3376430225 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 22276799 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 11:06:16 PM UTC 24 |
| Finished | Sep 01 11:06:18 PM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376430225 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.3376430225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1896364497 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 29804993 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 11:06:18 PM UTC 24 |
| Finished | Sep 01 11:06:20 PM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1896364497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c trl_same_csr_outstanding.1896364497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.966291220 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 541280959 ps |
| CPU time | 6.49 seconds |
| Started | Sep 01 11:06:09 PM UTC 24 |
| Finished | Sep 01 11:06:17 PM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966291220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.966291220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2719391563 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 77882863 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 11:06:11 PM UTC 24 |
| Finished | Sep 01 11:06:14 PM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27193 91563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_in tg_err.2719391563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3774065118 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 94309172 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 11:07:26 PM UTC 24 |
| Finished | Sep 01 11:07:29 PM UTC 24 |
| Peak memory | 220608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3774065118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3774065118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2634597805 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 17489307 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 11:07:23 PM UTC 24 |
| Finished | Sep 01 11:07:25 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634597805 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2634597805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2286355607 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 875659617 ps |
| CPU time | 2.9 seconds |
| Started | Sep 01 11:07:22 PM UTC 24 |
| Finished | Sep 01 11:07:26 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 86355607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p assthru_mem_tl_intg_err.2286355607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2418589126 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 77078637 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 11:07:26 PM UTC 24 |
| Finished | Sep 01 11:07:28 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2418589126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ ctrl_same_csr_outstanding.2418589126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.511883239 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 220050215 ps |
| CPU time | 5.83 seconds |
| Started | Sep 01 11:07:23 PM UTC 24 |
| Finished | Sep 01 11:07:30 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511883239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.511883239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.478463563 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 805109263 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 11:07:23 PM UTC 24 |
| Finished | Sep 01 11:07:27 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47846 3563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_in tg_err.478463563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1216476186 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 54655468 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 11:07:30 PM UTC 24 |
| Finished | Sep 01 11:07:34 PM UTC 24 |
| Peak memory | 221716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1216476186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1216476186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1470958329 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 15468519 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 11:07:29 PM UTC 24 |
| Finished | Sep 01 11:07:31 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470958329 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.1470958329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1112907335 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 394108818 ps |
| CPU time | 4.96 seconds |
| Started | Sep 01 11:07:26 PM UTC 24 |
| Finished | Sep 01 11:07:32 PM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 12907335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p assthru_mem_tl_intg_err.1112907335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1648029540 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 40727516 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 11:07:29 PM UTC 24 |
| Finished | Sep 01 11:07:31 PM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1648029540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ ctrl_same_csr_outstanding.1648029540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4253213896 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 128524151 ps |
| CPU time | 5.98 seconds |
| Started | Sep 01 11:07:27 PM UTC 24 |
| Finished | Sep 01 11:07:35 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253213896 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.4253213896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.446179853 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 285404669 ps |
| CPU time | 3.75 seconds |
| Started | Sep 01 11:07:27 PM UTC 24 |
| Finished | Sep 01 11:07:33 PM UTC 24 |
| Peak memory | 221640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44617 9853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_in tg_err.446179853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2311272988 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 370057291 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 11:07:34 PM UTC 24 |
| Finished | Sep 01 11:07:37 PM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2311272988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2311272988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4117547332 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 18323433 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 11:07:32 PM UTC 24 |
| Finished | Sep 01 11:07:34 PM UTC 24 |
| Peak memory | 210332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117547332 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.4117547332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.217502843 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1285490423 ps |
| CPU time | 6.13 seconds |
| Started | Sep 01 11:07:30 PM UTC 24 |
| Finished | Sep 01 11:07:38 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 7502843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_pa ssthru_mem_tl_intg_err.217502843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2589366637 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 24703526 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 11:07:33 PM UTC 24 |
| Finished | Sep 01 11:07:36 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2589366637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ ctrl_same_csr_outstanding.2589366637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2686027596 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 47102962 ps |
| CPU time | 5.03 seconds |
| Started | Sep 01 11:07:32 PM UTC 24 |
| Finished | Sep 01 11:07:38 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686027596 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.2686027596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1641115353 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 124944817 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 11:07:38 PM UTC 24 |
| Finished | Sep 01 11:07:41 PM UTC 24 |
| Peak memory | 221444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1641115353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1641115353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4080721694 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 13262318 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 11:07:38 PM UTC 24 |
| Finished | Sep 01 11:07:40 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080721694 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.4080721694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3378315312 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 430467196 ps |
| CPU time | 2.98 seconds |
| Started | Sep 01 11:07:34 PM UTC 24 |
| Finished | Sep 01 11:07:38 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 78315312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p assthru_mem_tl_intg_err.3378315312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3724458280 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 65265354 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 11:07:38 PM UTC 24 |
| Finished | Sep 01 11:07:40 PM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3724458280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ ctrl_same_csr_outstanding.3724458280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2519896972 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 215557510 ps |
| CPU time | 5.18 seconds |
| Started | Sep 01 11:07:36 PM UTC 24 |
| Finished | Sep 01 11:07:42 PM UTC 24 |
| Peak memory | 221680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519896972 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.2519896972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3164106751 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 95836660 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 11:07:42 PM UTC 24 |
| Finished | Sep 01 11:07:44 PM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3164106751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3164106751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2820058501 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 21274536 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 11:07:40 PM UTC 24 |
| Finished | Sep 01 11:07:42 PM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820058501 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.2820058501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3558674722 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2778011902 ps |
| CPU time | 6.28 seconds |
| Started | Sep 01 11:07:38 PM UTC 24 |
| Finished | Sep 01 11:07:46 PM UTC 24 |
| Peak memory | 211732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 58674722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_p assthru_mem_tl_intg_err.3558674722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3309487572 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 36520398 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 11:07:40 PM UTC 24 |
| Finished | Sep 01 11:07:43 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3309487572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ ctrl_same_csr_outstanding.3309487572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4182984595 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 79769186 ps |
| CPU time | 4.14 seconds |
| Started | Sep 01 11:07:38 PM UTC 24 |
| Finished | Sep 01 11:07:44 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182984595 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.4182984595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.960997023 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 40614881 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 11:07:44 PM UTC 24 |
| Finished | Sep 01 11:07:47 PM UTC 24 |
| Peak memory | 221764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=960997023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.960997023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1703885267 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 23518188 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 11:07:44 PM UTC 24 |
| Finished | Sep 01 11:07:46 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703885267 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.1703885267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.94539583 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 1061501842 ps |
| CPU time | 5.15 seconds |
| Started | Sep 01 11:07:42 PM UTC 24 |
| Finished | Sep 01 11:07:48 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94 539583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_pas sthru_mem_tl_intg_err.94539583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2350145374 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 18376375 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 11:07:44 PM UTC 24 |
| Finished | Sep 01 11:07:46 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2350145374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ ctrl_same_csr_outstanding.2350145374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.271806845 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 1934432045 ps |
| CPU time | 6.68 seconds |
| Started | Sep 01 11:07:42 PM UTC 24 |
| Finished | Sep 01 11:07:50 PM UTC 24 |
| Peak memory | 221732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271806845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.271806845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.179269027 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 653265949 ps |
| CPU time | 2.82 seconds |
| Started | Sep 01 11:07:42 PM UTC 24 |
| Finished | Sep 01 11:07:46 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17926 9027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_in tg_err.179269027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2067110911 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 34292849 ps |
| CPU time | 2.44 seconds |
| Started | Sep 01 11:07:47 PM UTC 24 |
| Finished | Sep 01 11:07:50 PM UTC 24 |
| Peak memory | 221844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2067110911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2067110911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.99578235 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 38664754 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 11:07:47 PM UTC 24 |
| Finished | Sep 01 11:07:49 PM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99578235 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.99578235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3173321380 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 1065423667 ps |
| CPU time | 2.85 seconds |
| Started | Sep 01 11:07:45 PM UTC 24 |
| Finished | Sep 01 11:07:49 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 73321380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p assthru_mem_tl_intg_err.3173321380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2995320701 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 101163241 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 11:07:47 PM UTC 24 |
| Finished | Sep 01 11:07:49 PM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2995320701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ ctrl_same_csr_outstanding.2995320701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3463514737 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 280053874 ps |
| CPU time | 3.03 seconds |
| Started | Sep 01 11:07:45 PM UTC 24 |
| Finished | Sep 01 11:07:49 PM UTC 24 |
| Peak memory | 221736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463514737 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.3463514737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1193722560 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 26013647 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 11:07:50 PM UTC 24 |
| Finished | Sep 01 11:07:52 PM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1193722560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1193722560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2769797585 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 15051261 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 11:07:50 PM UTC 24 |
| Finished | Sep 01 11:07:52 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769797585 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.2769797585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3694893924 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 2200922925 ps |
| CPU time | 5.48 seconds |
| Started | Sep 01 11:07:47 PM UTC 24 |
| Finished | Sep 01 11:07:53 PM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 94893924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_p assthru_mem_tl_intg_err.3694893924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1683791959 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 134928763 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 11:07:50 PM UTC 24 |
| Finished | Sep 01 11:07:52 PM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1683791959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ ctrl_same_csr_outstanding.1683791959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.956839727 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 50949648 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 11:07:48 PM UTC 24 |
| Finished | Sep 01 11:07:54 PM UTC 24 |
| Peak memory | 221712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956839727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.956839727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3685257619 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 255850191 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 11:07:50 PM UTC 24 |
| Finished | Sep 01 11:07:53 PM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36852 57619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.3685257619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3994125117 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 138270709 ps |
| CPU time | 2.79 seconds |
| Started | Sep 01 11:07:53 PM UTC 24 |
| Finished | Sep 01 11:07:57 PM UTC 24 |
| Peak memory | 221912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3994125117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3994125117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3182536475 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 54454371 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 11:07:52 PM UTC 24 |
| Finished | Sep 01 11:07:54 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182536475 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.3182536475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2226492954 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 1162947080 ps |
| CPU time | 4.49 seconds |
| Started | Sep 01 11:07:52 PM UTC 24 |
| Finished | Sep 01 11:07:57 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 26492954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p assthru_mem_tl_intg_err.2226492954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1597922618 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 23898803 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 11:07:53 PM UTC 24 |
| Finished | Sep 01 11:07:55 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1597922618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ ctrl_same_csr_outstanding.1597922618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1056671395 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 222833065 ps |
| CPU time | 3.12 seconds |
| Started | Sep 01 11:07:52 PM UTC 24 |
| Finished | Sep 01 11:07:56 PM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056671395 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.1056671395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3209737395 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 181586541 ps |
| CPU time | 3.05 seconds |
| Started | Sep 01 11:07:52 PM UTC 24 |
| Finished | Sep 01 11:07:56 PM UTC 24 |
| Peak memory | 221720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32097 37395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i ntg_err.3209737395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1777724813 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 429716216 ps |
| CPU time | 2.44 seconds |
| Started | Sep 01 11:07:57 PM UTC 24 |
| Finished | Sep 01 11:08:00 PM UTC 24 |
| Peak memory | 221840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1777724813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1777724813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2116262198 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 23769414 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 11:07:55 PM UTC 24 |
| Finished | Sep 01 11:07:57 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116262198 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.2116262198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2902235830 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 385598117 ps |
| CPU time | 3.48 seconds |
| Started | Sep 01 11:07:53 PM UTC 24 |
| Finished | Sep 01 11:07:58 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 02235830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_p assthru_mem_tl_intg_err.2902235830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2885427200 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 41625640 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 11:07:56 PM UTC 24 |
| Finished | Sep 01 11:07:58 PM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2885427200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ ctrl_same_csr_outstanding.2885427200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1714014838 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 298058426 ps |
| CPU time | 3.68 seconds |
| Started | Sep 01 11:07:55 PM UTC 24 |
| Finished | Sep 01 11:08:00 PM UTC 24 |
| Peak memory | 221656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714014838 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.1714014838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4220118455 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 274386208 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 11:07:55 PM UTC 24 |
| Finished | Sep 01 11:07:58 PM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42201 18455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i ntg_err.4220118455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2854158846 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 43574050 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 11:06:29 PM UTC 24 |
| Finished | Sep 01 11:06:31 PM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28541588 46 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alia sing.2854158846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2777388868 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 241794654 ps |
| CPU time | 2.15 seconds |
| Started | Sep 01 11:06:29 PM UTC 24 |
| Finished | Sep 01 11:06:32 PM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27773888 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_ bash.2777388868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2052725053 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 56931501 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 11:06:26 PM UTC 24 |
| Finished | Sep 01 11:06:29 PM UTC 24 |
| Peak memory | 209836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20527250 53 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r eset.2052725053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1562415759 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 129329993 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 11:06:30 PM UTC 24 |
| Finished | Sep 01 11:06:33 PM UTC 24 |
| Peak memory | 220280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1562415759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1562415759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1951929982 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 32744611 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 11:06:28 PM UTC 24 |
| Finished | Sep 01 11:06:30 PM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951929982 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1951929982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4272186937 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 917260328 ps |
| CPU time | 2.96 seconds |
| Started | Sep 01 11:06:22 PM UTC 24 |
| Finished | Sep 01 11:06:26 PM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 72186937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa ssthru_mem_tl_intg_err.4272186937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3931472775 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 31425769 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 11:06:30 PM UTC 24 |
| Finished | Sep 01 11:06:33 PM UTC 24 |
| Peak memory | 210476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3931472775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c trl_same_csr_outstanding.3931472775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2140619306 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 107683965 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 11:06:23 PM UTC 24 |
| Finished | Sep 01 11:06:27 PM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140619306 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.2140619306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2078067784 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 193963922 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 11:06:25 PM UTC 24 |
| Finished | Sep 01 11:06:28 PM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20780 67784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_in tg_err.2078067784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3063022786 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 57880479 ps |
| CPU time | 1 seconds |
| Started | Sep 01 11:06:40 PM UTC 24 |
| Finished | Sep 01 11:06:42 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30630227 86 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia sing.3063022786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3311195271 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 30927507 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 11:06:40 PM UTC 24 |
| Finished | Sep 01 11:06:43 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33111952 71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_ bash.3311195271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3795048796 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 17896523 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 11:06:34 PM UTC 24 |
| Finished | Sep 01 11:06:36 PM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37950487 96 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_r eset.3795048796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1748890443 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 33449278 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 11:06:38 PM UTC 24 |
| Finished | Sep 01 11:06:40 PM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748890443 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.1748890443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2606871305 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 478275371 ps |
| CPU time | 5.04 seconds |
| Started | Sep 01 11:06:33 PM UTC 24 |
| Finished | Sep 01 11:06:39 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 06871305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pa ssthru_mem_tl_intg_err.2606871305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1447646306 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 13964697 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 11:06:41 PM UTC 24 |
| Finished | Sep 01 11:06:43 PM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1447646306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c trl_same_csr_outstanding.1447646306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.771659731 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 141020718 ps |
| CPU time | 5.51 seconds |
| Started | Sep 01 11:06:34 PM UTC 24 |
| Finished | Sep 01 11:06:41 PM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771659731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.771659731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3797197411 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 249508021 ps |
| CPU time | 3.55 seconds |
| Started | Sep 01 11:06:34 PM UTC 24 |
| Finished | Sep 01 11:06:39 PM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37971 97411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in tg_err.3797197411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1910092206 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 27707303 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 11:06:50 PM UTC 24 |
| Finished | Sep 01 11:06:52 PM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19100922 06 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia sing.1910092206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.119507266 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 375108218 ps |
| CPU time | 3.56 seconds |
| Started | Sep 01 11:06:49 PM UTC 24 |
| Finished | Sep 01 11:06:53 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11950726 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_b ash.119507266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1492598865 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 18658008 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 11:06:46 PM UTC 24 |
| Finished | Sep 01 11:06:48 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14925988 65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_r eset.1492598865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2732655257 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 56300663 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 11:06:52 PM UTC 24 |
| Finished | Sep 01 11:06:55 PM UTC 24 |
| Peak memory | 221908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2732655257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2732655257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.730262199 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 30818708 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 11:06:49 PM UTC 24 |
| Finished | Sep 01 11:06:51 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730262199 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.730262199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3990918364 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1081964121 ps |
| CPU time | 5.19 seconds |
| Started | Sep 01 11:06:42 PM UTC 24 |
| Finished | Sep 01 11:06:49 PM UTC 24 |
| Peak memory | 211664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 90918364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pa ssthru_mem_tl_intg_err.3990918364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.906136080 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 202886681 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 11:06:50 PM UTC 24 |
| Finished | Sep 01 11:06:52 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=906136080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ct rl_same_csr_outstanding.906136080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2501952970 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 144072635 ps |
| CPU time | 4.04 seconds |
| Started | Sep 01 11:06:44 PM UTC 24 |
| Finished | Sep 01 11:06:49 PM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501952970 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.2501952970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1767599276 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1670018524 ps |
| CPU time | 2.53 seconds |
| Started | Sep 01 11:06:44 PM UTC 24 |
| Finished | Sep 01 11:06:47 PM UTC 24 |
| Peak memory | 221716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17675 99276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in tg_err.1767599276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1478347379 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 57245501 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:06:59 PM UTC 24 |
| Finished | Sep 01 11:07:02 PM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1478347379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1478347379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1384827989 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 36386325 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 11:06:57 PM UTC 24 |
| Finished | Sep 01 11:06:59 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384827989 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.1384827989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1314226925 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1577839542 ps |
| CPU time | 4.72 seconds |
| Started | Sep 01 11:06:53 PM UTC 24 |
| Finished | Sep 01 11:06:59 PM UTC 24 |
| Peak memory | 211800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 14226925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa ssthru_mem_tl_intg_err.1314226925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.464469785 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 46758258 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 11:06:59 PM UTC 24 |
| Finished | Sep 01 11:07:02 PM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=464469785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ct rl_same_csr_outstanding.464469785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.862660310 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 144062488 ps |
| CPU time | 7.55 seconds |
| Started | Sep 01 11:06:53 PM UTC 24 |
| Finished | Sep 01 11:07:02 PM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862660310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.862660310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1884104346 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 127628899 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 11:07:05 PM UTC 24 |
| Finished | Sep 01 11:07:08 PM UTC 24 |
| Peak memory | 221668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1884104346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.1884104346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.90480050 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 59438487 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 11:07:02 PM UTC 24 |
| Finished | Sep 01 11:07:04 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90480050 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.90480050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3402575676 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1867730714 ps |
| CPU time | 4.34 seconds |
| Started | Sep 01 11:07:01 PM UTC 24 |
| Finished | Sep 01 11:07:06 PM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34 02575676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa ssthru_mem_tl_intg_err.3402575676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4282019513 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 26600714 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 11:07:03 PM UTC 24 |
| Finished | Sep 01 11:07:06 PM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4282019513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c trl_same_csr_outstanding.4282019513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1531633979 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 585791647 ps |
| CPU time | 4.97 seconds |
| Started | Sep 01 11:07:01 PM UTC 24 |
| Finished | Sep 01 11:07:07 PM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531633979 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.1531633979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3756050647 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 142108566 ps |
| CPU time | 3.14 seconds |
| Started | Sep 01 11:07:02 PM UTC 24 |
| Finished | Sep 01 11:07:06 PM UTC 24 |
| Peak memory | 221668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37560 50647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in tg_err.3756050647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3004286067 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 98630854 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 11:07:12 PM UTC 24 |
| Finished | Sep 01 11:07:15 PM UTC 24 |
| Peak memory | 220560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3004286067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3004286067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4116324622 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 12499663 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 11:07:08 PM UTC 24 |
| Finished | Sep 01 11:07:11 PM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116324622 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.4116324622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.113212570 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 754698550 ps |
| CPU time | 2.73 seconds |
| Started | Sep 01 11:07:07 PM UTC 24 |
| Finished | Sep 01 11:07:11 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 3212570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pas sthru_mem_tl_intg_err.113212570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.948316358 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 48666229 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 11:07:09 PM UTC 24 |
| Finished | Sep 01 11:07:11 PM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=948316358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ct rl_same_csr_outstanding.948316358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1649373443 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 116405622 ps |
| CPU time | 5.6 seconds |
| Started | Sep 01 11:07:07 PM UTC 24 |
| Finished | Sep 01 11:07:14 PM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649373443 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.1649373443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1038767082 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 708972814 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 11:07:07 PM UTC 24 |
| Finished | Sep 01 11:07:12 PM UTC 24 |
| Peak memory | 221668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10387 67082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in tg_err.1038767082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3013991178 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 74865426 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 11:07:16 PM UTC 24 |
| Finished | Sep 01 11:07:19 PM UTC 24 |
| Peak memory | 220284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3013991178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3013991178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3783957827 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 14648654 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 11:07:15 PM UTC 24 |
| Finished | Sep 01 11:07:17 PM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783957827 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.3783957827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1761833883 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 428432751 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 11:07:12 PM UTC 24 |
| Finished | Sep 01 11:07:16 PM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 61833883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa ssthru_mem_tl_intg_err.1761833883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2297082343 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 64428185 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 11:07:15 PM UTC 24 |
| Finished | Sep 01 11:07:17 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2297082343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c trl_same_csr_outstanding.2297082343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1095014714 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 161705879 ps |
| CPU time | 7.45 seconds |
| Started | Sep 01 11:07:12 PM UTC 24 |
| Finished | Sep 01 11:07:21 PM UTC 24 |
| Peak memory | 221784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095014714 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1095014714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.902205349 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 776141092 ps |
| CPU time | 3.4 seconds |
| Started | Sep 01 11:07:14 PM UTC 24 |
| Finished | Sep 01 11:07:18 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90220 5349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_int g_err.902205349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3507048662 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 86526303 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 11:07:22 PM UTC 24 |
| Finished | Sep 01 11:07:24 PM UTC 24 |
| Peak memory | 220280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3507048662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3507048662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2928027387 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 15420542 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 11:07:19 PM UTC 24 |
| Finished | Sep 01 11:07:21 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928027387 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.2928027387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1036515845 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 217313883 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 11:07:18 PM UTC 24 |
| Finished | Sep 01 11:07:22 PM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10 36515845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa ssthru_mem_tl_intg_err.1036515845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3489193768 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 156876888 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 11:07:20 PM UTC 24 |
| Finished | Sep 01 11:07:23 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3489193768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c trl_same_csr_outstanding.3489193768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3675312247 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 146199328 ps |
| CPU time | 5.81 seconds |
| Started | Sep 01 11:07:18 PM UTC 24 |
| Finished | Sep 01 11:07:25 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675312247 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.3675312247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1132226335 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 141645509 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 11:07:18 PM UTC 24 |
| Finished | Sep 01 11:07:21 PM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11322 26335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_in tg_err.1132226335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2267422197 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3931144354 ps |
| CPU time | 1273.52 seconds |
| Started | Sep 01 09:45:15 PM UTC 24 |
| Finished | Sep 01 10:06:43 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267422197 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_ key_req.2267422197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.2225649119 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 962198928 ps |
| CPU time | 18.89 seconds |
| Started | Sep 01 09:45:14 PM UTC 24 |
| Finished | Sep 01 09:45:35 PM UTC 24 |
| Peak memory | 213820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225649119 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.2225649119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.3975952184 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 31063541375 ps |
| CPU time | 728.98 seconds |
| Started | Sep 01 09:45:16 PM UTC 24 |
| Finished | Sep 01 09:57:34 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975952184 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.3975952184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1615868835 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 115074729 ps |
| CPU time | 64.68 seconds |
| Started | Sep 01 09:45:15 PM UTC 24 |
| Finished | Sep 01 09:46:21 PM UTC 24 |
| Peak memory | 350052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 615868835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max _throughput.1615868835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2416608985 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1773419813 ps |
| CPU time | 16.1 seconds |
| Started | Sep 01 09:45:16 PM UTC 24 |
| Finished | Sep 01 09:45:33 PM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416608985 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2416608985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.572200112 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 4121086155 ps |
| CPU time | 1027.31 seconds |
| Started | Sep 01 09:45:14 PM UTC 24 |
| Finished | Sep 01 10:02:33 PM UTC 24 |
| Peak memory | 384816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572200112 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.572200112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2827842902 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 467280258 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 09:45:22 PM UTC 24 |
| Finished | Sep 01 09:45:27 PM UTC 24 |
| Peak memory | 250144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827842902 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2827842902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.3125335763 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 327580349 ps |
| CPU time | 6.97 seconds |
| Started | Sep 01 09:45:13 PM UTC 24 |
| Finished | Sep 01 09:45:21 PM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125335763 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3125335763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2041187228 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 85674153099 ps |
| CPU time | 190.31 seconds |
| Started | Sep 01 09:45:19 PM UTC 24 |
| Finished | Sep 01 09:48:33 PM UTC 24 |
| Peak memory | 226452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204118722 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.2041187228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.3672772268 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4432982738 ps |
| CPU time | 323.85 seconds |
| Started | Sep 01 09:45:15 PM UTC 24 |
| Finished | Sep 01 09:50:43 PM UTC 24 |
| Peak memory | 213952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672772268 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.3672772268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3967332204 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 546023006 ps |
| CPU time | 117.53 seconds |
| Started | Sep 01 09:45:15 PM UTC 24 |
| Finished | Sep 01 09:47:15 PM UTC 24 |
| Peak memory | 380008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3967332204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th roughput_w_partial_write.3967332204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3647853073 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2138194730 ps |
| CPU time | 835.71 seconds |
| Started | Sep 01 09:45:52 PM UTC 24 |
| Finished | Sep 01 09:59:59 PM UTC 24 |
| Peak memory | 385076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647853073 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_ key_req.3647853073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3533064053 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 50455023 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 09:46:24 PM UTC 24 |
| Finished | Sep 01 09:46:27 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533064053 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3533064053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.2121282690 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1195474033 ps |
| CPU time | 38.47 seconds |
| Started | Sep 01 09:45:28 PM UTC 24 |
| Finished | Sep 01 09:46:08 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121282690 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.2121282690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3341189958 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 99770989 ps |
| CPU time | 2.71 seconds |
| Started | Sep 01 09:45:47 PM UTC 24 |
| Finished | Sep 01 09:45:52 PM UTC 24 |
| Peak memory | 214052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341189958 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3341189958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1426943930 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 92331793 ps |
| CPU time | 26.88 seconds |
| Started | Sep 01 09:45:40 PM UTC 24 |
| Finished | Sep 01 09:46:09 PM UTC 24 |
| Peak memory | 302956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 426943930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max _throughput.1426943930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3300403568 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 245194996 ps |
| CPU time | 7.4 seconds |
| Started | Sep 01 09:46:12 PM UTC 24 |
| Finished | Sep 01 09:46:21 PM UTC 24 |
| Peak memory | 224344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300403568 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.3300403568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2884909322 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 140219146 ps |
| CPU time | 13.37 seconds |
| Started | Sep 01 09:46:10 PM UTC 24 |
| Finished | Sep 01 09:46:24 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884909322 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2884909322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3444981043 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 14111979468 ps |
| CPU time | 946.11 seconds |
| Started | Sep 01 09:45:26 PM UTC 24 |
| Finished | Sep 01 10:01:23 PM UTC 24 |
| Peak memory | 378724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444981043 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.3444981043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3348166799 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3543724321 ps |
| CPU time | 28.7 seconds |
| Started | Sep 01 09:45:35 PM UTC 24 |
| Finished | Sep 01 09:46:05 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348166799 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.3348166799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3395117418 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 212705995 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:46:09 PM UTC 24 |
| Finished | Sep 01 09:46:11 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395117418 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3395117418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1465797589 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15363366066 ps |
| CPU time | 411.57 seconds |
| Started | Sep 01 09:46:06 PM UTC 24 |
| Finished | Sep 01 09:53:03 PM UTC 24 |
| Peak memory | 383148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465797589 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1465797589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.406032852 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 520846757 ps |
| CPU time | 12.33 seconds |
| Started | Sep 01 09:45:26 PM UTC 24 |
| Finished | Sep 01 09:45:39 PM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406032852 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.406032852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2345729502 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 27296588887 ps |
| CPU time | 2344.94 seconds |
| Started | Sep 01 09:46:22 PM UTC 24 |
| Finished | Sep 01 10:25:52 PM UTC 24 |
| Peak memory | 386928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234572950 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.2345729502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.1872580110 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2248321370 ps |
| CPU time | 253.64 seconds |
| Started | Sep 01 09:45:34 PM UTC 24 |
| Finished | Sep 01 09:49:52 PM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872580110 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.1872580110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.297181717 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 15767219957 ps |
| CPU time | 1077.52 seconds |
| Started | Sep 01 10:04:00 PM UTC 24 |
| Finished | Sep 01 10:22:09 PM UTC 24 |
| Peak memory | 380744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297181717 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during_ key_req.297181717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.794722587 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 57169068 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 10:04:55 PM UTC 24 |
| Finished | Sep 01 10:04:57 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794722587 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.794722587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1419678815 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3364224637 ps |
| CPU time | 110.2 seconds |
| Started | Sep 01 10:02:33 PM UTC 24 |
| Finished | Sep 01 10:04:25 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419678815 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.1419678815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2861981711 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 106304837496 ps |
| CPU time | 1679.29 seconds |
| Started | Sep 01 10:04:04 PM UTC 24 |
| Finished | Sep 01 10:32:21 PM UTC 24 |
| Peak memory | 381056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861981711 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2861981711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.4012668399 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 6248220393 ps |
| CPU time | 10.98 seconds |
| Started | Sep 01 10:03:56 PM UTC 24 |
| Finished | Sep 01 10:04:08 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012668399 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.4012668399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.181859414 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 337101298 ps |
| CPU time | 21.54 seconds |
| Started | Sep 01 10:03:40 PM UTC 24 |
| Finished | Sep 01 10:04:03 PM UTC 24 |
| Peak memory | 296752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 81859414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_max _throughput.181859414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2686578330 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 102578394 ps |
| CPU time | 3.53 seconds |
| Started | Sep 01 10:04:26 PM UTC 24 |
| Finished | Sep 01 10:04:31 PM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686578330 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.2686578330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1939573127 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 595480043 ps |
| CPU time | 10.69 seconds |
| Started | Sep 01 10:04:13 PM UTC 24 |
| Finished | Sep 01 10:04:25 PM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939573127 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.1939573127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3640304878 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3941738879 ps |
| CPU time | 1462.18 seconds |
| Started | Sep 01 10:02:33 PM UTC 24 |
| Finished | Sep 01 10:27:11 PM UTC 24 |
| Peak memory | 383088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640304878 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.3640304878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1109648487 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 309758216 ps |
| CPU time | 64.39 seconds |
| Started | Sep 01 10:02:53 PM UTC 24 |
| Finished | Sep 01 10:03:59 PM UTC 24 |
| Peak memory | 339812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109648487 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.1109648487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1779567009 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 37012340459 ps |
| CPU time | 462.47 seconds |
| Started | Sep 01 10:03:21 PM UTC 24 |
| Finished | Sep 01 10:11:10 PM UTC 24 |
| Peak memory | 214300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779567009 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc ess_b2b.1779567009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.233509509 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 30769362 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 10:04:10 PM UTC 24 |
| Finished | Sep 01 10:04:12 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233509509 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.233509509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.2057755706 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4059362914 ps |
| CPU time | 247.05 seconds |
| Started | Sep 01 10:04:09 PM UTC 24 |
| Finished | Sep 01 10:08:20 PM UTC 24 |
| Peak memory | 333752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057755706 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2057755706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.922012616 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 291623389 ps |
| CPU time | 20.75 seconds |
| Started | Sep 01 10:02:30 PM UTC 24 |
| Finished | Sep 01 10:02:52 PM UTC 24 |
| Peak memory | 270124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922012616 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.922012616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3382806216 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 6547975706 ps |
| CPU time | 2686.63 seconds |
| Started | Sep 01 10:04:32 PM UTC 24 |
| Finished | Sep 01 10:49:48 PM UTC 24 |
| Peak memory | 395188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338280621 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.3382806216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3912376292 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1308452187 ps |
| CPU time | 125.83 seconds |
| Started | Sep 01 10:04:26 PM UTC 24 |
| Finished | Sep 01 10:06:35 PM UTC 24 |
| Peak memory | 391028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912376292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3912376292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3241344622 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8654414933 ps |
| CPU time | 324.61 seconds |
| Started | Sep 01 10:02:34 PM UTC 24 |
| Finished | Sep 01 10:08:03 PM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241344622 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3241344622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1520672936 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 168836063 ps |
| CPU time | 123.66 seconds |
| Started | Sep 01 10:03:48 PM UTC 24 |
| Finished | Sep 01 10:05:54 PM UTC 24 |
| Peak memory | 380716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1520672936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t hroughput_w_partial_write.1520672936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.732198599 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 5689420485 ps |
| CPU time | 645.24 seconds |
| Started | Sep 01 10:06:06 PM UTC 24 |
| Finished | Sep 01 10:16:59 PM UTC 24 |
| Peak memory | 385196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732198599 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_ key_req.732198599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1390852602 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 38344850 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 10:06:36 PM UTC 24 |
| Finished | Sep 01 10:06:38 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390852602 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1390852602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3869685337 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3179534026 ps |
| CPU time | 90.73 seconds |
| Started | Sep 01 10:05:28 PM UTC 24 |
| Finished | Sep 01 10:07:01 PM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869685337 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.3869685337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2943812268 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 13097581009 ps |
| CPU time | 1020.17 seconds |
| Started | Sep 01 10:06:15 PM UTC 24 |
| Finished | Sep 01 10:23:26 PM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943812268 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2943812268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3766699624 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1655071380 ps |
| CPU time | 7.46 seconds |
| Started | Sep 01 10:05:57 PM UTC 24 |
| Finished | Sep 01 10:06:05 PM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766699624 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.3766699624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.54969108 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 504217645 ps |
| CPU time | 119.2 seconds |
| Started | Sep 01 10:05:56 PM UTC 24 |
| Finished | Sep 01 10:07:57 PM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 4969108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_max_ throughput.54969108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.60839182 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 361019082 ps |
| CPU time | 4.41 seconds |
| Started | Sep 01 10:06:24 PM UTC 24 |
| Finished | Sep 01 10:06:30 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60839182 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.60839182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3305439968 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1433831812 ps |
| CPU time | 13.21 seconds |
| Started | Sep 01 10:06:23 PM UTC 24 |
| Finished | Sep 01 10:06:38 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305439968 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.3305439968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1171522410 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 30379393359 ps |
| CPU time | 1631.92 seconds |
| Started | Sep 01 10:05:02 PM UTC 24 |
| Finished | Sep 01 10:32:33 PM UTC 24 |
| Peak memory | 385264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171522410 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.1171522410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2331816622 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 420120066 ps |
| CPU time | 103.37 seconds |
| Started | Sep 01 10:05:39 PM UTC 24 |
| Finished | Sep 01 10:07:25 PM UTC 24 |
| Peak memory | 374904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331816622 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.2331816622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3697328429 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 25900069313 ps |
| CPU time | 398.69 seconds |
| Started | Sep 01 10:05:42 PM UTC 24 |
| Finished | Sep 01 10:12:27 PM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697328429 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc ess_b2b.3697328429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3009226601 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 88900730 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 10:06:21 PM UTC 24 |
| Finished | Sep 01 10:06:23 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009226601 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3009226601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.1810733716 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 6522829292 ps |
| CPU time | 684.66 seconds |
| Started | Sep 01 10:06:20 PM UTC 24 |
| Finished | Sep 01 10:17:53 PM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810733716 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1810733716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1073411691 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 37177023 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 10:04:59 PM UTC 24 |
| Finished | Sep 01 10:05:01 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073411691 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1073411691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3074520620 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 7834394292 ps |
| CPU time | 2333.08 seconds |
| Started | Sep 01 10:06:34 PM UTC 24 |
| Finished | Sep 01 10:45:52 PM UTC 24 |
| Peak memory | 395052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307452062 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.3074520620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1813660603 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7981429243 ps |
| CPU time | 122.11 seconds |
| Started | Sep 01 10:06:30 PM UTC 24 |
| Finished | Sep 01 10:08:35 PM UTC 24 |
| Peak memory | 307184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813660603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1813660603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2902818407 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 15212512756 ps |
| CPU time | 247.07 seconds |
| Started | Sep 01 10:05:32 PM UTC 24 |
| Finished | Sep 01 10:09:43 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902818407 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.2902818407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.354682609 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 133910992 ps |
| CPU time | 24.43 seconds |
| Started | Sep 01 10:05:57 PM UTC 24 |
| Finished | Sep 01 10:06:22 PM UTC 24 |
| Peak memory | 286496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 354682609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_th roughput_w_partial_write.354682609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.289400960 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2784224754 ps |
| CPU time | 233.36 seconds |
| Started | Sep 01 10:07:32 PM UTC 24 |
| Finished | Sep 01 10:11:29 PM UTC 24 |
| Peak memory | 378800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289400960 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_ key_req.289400960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3884782935 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 50376772 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 10:08:04 PM UTC 24 |
| Finished | Sep 01 10:08:06 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884782935 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3884782935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.3542864878 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2005620906 ps |
| CPU time | 38.39 seconds |
| Started | Sep 01 10:06:44 PM UTC 24 |
| Finished | Sep 01 10:07:24 PM UTC 24 |
| Peak memory | 213772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542864878 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.3542864878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3205040018 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 6071963453 ps |
| CPU time | 208.23 seconds |
| Started | Sep 01 10:07:33 PM UTC 24 |
| Finished | Sep 01 10:11:04 PM UTC 24 |
| Peak memory | 341868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205040018 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.3205040018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1808359319 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 242653870 ps |
| CPU time | 5.22 seconds |
| Started | Sep 01 10:07:26 PM UTC 24 |
| Finished | Sep 01 10:07:33 PM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808359319 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.1808359319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1373961295 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 69889001 ps |
| CPU time | 9.22 seconds |
| Started | Sep 01 10:07:25 PM UTC 24 |
| Finished | Sep 01 10:07:35 PM UTC 24 |
| Peak memory | 247612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 373961295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma x_throughput.1373961295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.4023337614 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 167314743 ps |
| CPU time | 7.1 seconds |
| Started | Sep 01 10:07:57 PM UTC 24 |
| Finished | Sep 01 10:08:06 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023337614 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.4023337614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.245846374 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 236417560 ps |
| CPU time | 7.98 seconds |
| Started | Sep 01 10:07:49 PM UTC 24 |
| Finished | Sep 01 10:07:58 PM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245846374 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.245846374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1200431087 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1783608693 ps |
| CPU time | 186.95 seconds |
| Started | Sep 01 10:06:39 PM UTC 24 |
| Finished | Sep 01 10:09:48 PM UTC 24 |
| Peak memory | 378992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200431087 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.1200431087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.787647477 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3190898677 ps |
| CPU time | 88.53 seconds |
| Started | Sep 01 10:07:01 PM UTC 24 |
| Finished | Sep 01 10:08:32 PM UTC 24 |
| Peak memory | 356204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787647477 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.787647477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.123237129 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 70932286721 ps |
| CPU time | 543.84 seconds |
| Started | Sep 01 10:07:08 PM UTC 24 |
| Finished | Sep 01 10:16:19 PM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123237129 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acce ss_b2b.123237129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2990501592 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 77871430 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 10:07:46 PM UTC 24 |
| Finished | Sep 01 10:07:48 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990501592 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2990501592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3885283954 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 40781840790 ps |
| CPU time | 652.81 seconds |
| Started | Sep 01 10:07:36 PM UTC 24 |
| Finished | Sep 01 10:18:37 PM UTC 24 |
| Peak memory | 387000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885283954 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3885283954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.254790341 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1064575616 ps |
| CPU time | 27.04 seconds |
| Started | Sep 01 10:06:39 PM UTC 24 |
| Finished | Sep 01 10:07:07 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254790341 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.254790341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1348928089 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 70030713491 ps |
| CPU time | 995.08 seconds |
| Started | Sep 01 10:08:00 PM UTC 24 |
| Finished | Sep 01 10:24:46 PM UTC 24 |
| Peak memory | 378808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134892808 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.1348928089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3124541298 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1506689684 ps |
| CPU time | 40.98 seconds |
| Started | Sep 01 10:07:58 PM UTC 24 |
| Finished | Sep 01 10:08:41 PM UTC 24 |
| Peak memory | 266088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124541298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3124541298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3166547352 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2850676620 ps |
| CPU time | 322.95 seconds |
| Started | Sep 01 10:06:49 PM UTC 24 |
| Finished | Sep 01 10:12:17 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166547352 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.3166547352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4260139707 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 596056206 ps |
| CPU time | 4.75 seconds |
| Started | Sep 01 10:07:25 PM UTC 24 |
| Finished | Sep 01 10:07:30 PM UTC 24 |
| Peak memory | 235628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4260139707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t hroughput_w_partial_write.4260139707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2561019860 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 7836767923 ps |
| CPU time | 207.61 seconds |
| Started | Sep 01 10:08:36 PM UTC 24 |
| Finished | Sep 01 10:12:07 PM UTC 24 |
| Peak memory | 358236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561019860 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during _key_req.2561019860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1958839299 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 11914686 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 10:09:11 PM UTC 24 |
| Finished | Sep 01 10:09:13 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958839299 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1958839299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.212393400 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 786136170 ps |
| CPU time | 57.56 seconds |
| Started | Sep 01 10:08:06 PM UTC 24 |
| Finished | Sep 01 10:09:05 PM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212393400 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.212393400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.3352083975 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 97519642403 ps |
| CPU time | 893.52 seconds |
| Started | Sep 01 10:08:41 PM UTC 24 |
| Finished | Sep 01 10:23:45 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352083975 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.3352083975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1264116012 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1822906143 ps |
| CPU time | 6.44 seconds |
| Started | Sep 01 10:08:33 PM UTC 24 |
| Finished | Sep 01 10:08:40 PM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264116012 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.1264116012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3191173730 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 526092164 ps |
| CPU time | 124.17 seconds |
| Started | Sep 01 10:08:21 PM UTC 24 |
| Finished | Sep 01 10:10:27 PM UTC 24 |
| Peak memory | 382828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 191173730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ma x_throughput.3191173730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2526228382 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1108125388 ps |
| CPU time | 7.95 seconds |
| Started | Sep 01 10:09:01 PM UTC 24 |
| Finished | Sep 01 10:09:10 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526228382 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2526228382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.4081365246 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 77223522 ps |
| CPU time | 5.38 seconds |
| Started | Sep 01 10:08:54 PM UTC 24 |
| Finished | Sep 01 10:09:00 PM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081365246 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.4081365246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1156717553 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 70401257906 ps |
| CPU time | 510.52 seconds |
| Started | Sep 01 10:08:06 PM UTC 24 |
| Finished | Sep 01 10:16:43 PM UTC 24 |
| Peak memory | 379116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156717553 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.1156717553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3942093436 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 208836343 ps |
| CPU time | 3.38 seconds |
| Started | Sep 01 10:08:14 PM UTC 24 |
| Finished | Sep 01 10:08:19 PM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942093436 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.3942093436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.1649694111 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 48791155668 ps |
| CPU time | 333.5 seconds |
| Started | Sep 01 10:08:20 PM UTC 24 |
| Finished | Sep 01 10:13:58 PM UTC 24 |
| Peak memory | 213956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649694111 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc ess_b2b.1649694111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.660182008 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 29228275 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 10:08:50 PM UTC 24 |
| Finished | Sep 01 10:08:53 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660182008 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.660182008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.36094660 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2987953596 ps |
| CPU time | 110.96 seconds |
| Started | Sep 01 10:08:42 PM UTC 24 |
| Finished | Sep 01 10:10:35 PM UTC 24 |
| Peak memory | 321344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36094660 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.36094660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.1401294398 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 108655840 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 10:08:05 PM UTC 24 |
| Finished | Sep 01 10:08:07 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401294398 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1401294398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.916360883 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 12637343712 ps |
| CPU time | 63.71 seconds |
| Started | Sep 01 10:09:06 PM UTC 24 |
| Finished | Sep 01 10:10:11 PM UTC 24 |
| Peak memory | 253836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916360883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.916360883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3634713294 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3739104767 ps |
| CPU time | 276.66 seconds |
| Started | Sep 01 10:09:04 PM UTC 24 |
| Finished | Sep 01 10:13:45 PM UTC 24 |
| Peak memory | 389360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634713294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3634713294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1952471391 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 12282268275 ps |
| CPU time | 176.06 seconds |
| Started | Sep 01 10:08:08 PM UTC 24 |
| Finished | Sep 01 10:11:07 PM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952471391 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.1952471391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1925324515 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 92551413 ps |
| CPU time | 25.11 seconds |
| Started | Sep 01 10:08:23 PM UTC 24 |
| Finished | Sep 01 10:08:49 PM UTC 24 |
| Peak memory | 292644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1925324515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t hroughput_w_partial_write.1925324515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3437708212 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1695779694 ps |
| CPU time | 178.84 seconds |
| Started | Sep 01 10:10:35 PM UTC 24 |
| Finished | Sep 01 10:13:38 PM UTC 24 |
| Peak memory | 339764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437708212 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during _key_req.3437708212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.293937427 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 14702351 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 10:11:08 PM UTC 24 |
| Finished | Sep 01 10:11:10 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293937427 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.293937427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.3312718024 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 9110484442 ps |
| CPU time | 70.19 seconds |
| Started | Sep 01 10:09:43 PM UTC 24 |
| Finished | Sep 01 10:10:56 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312718024 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.3312718024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3814424995 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 13808067679 ps |
| CPU time | 95.04 seconds |
| Started | Sep 01 10:10:37 PM UTC 24 |
| Finished | Sep 01 10:12:14 PM UTC 24 |
| Peak memory | 335800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814424995 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.3814424995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1725375733 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2886395572 ps |
| CPU time | 4.94 seconds |
| Started | Sep 01 10:10:28 PM UTC 24 |
| Finished | Sep 01 10:10:35 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725375733 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.1725375733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4260851734 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 167496920 ps |
| CPU time | 31.89 seconds |
| Started | Sep 01 10:10:18 PM UTC 24 |
| Finished | Sep 01 10:10:52 PM UTC 24 |
| Peak memory | 296740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 260851734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma x_throughput.4260851734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2794308313 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 102878740 ps |
| CPU time | 4.57 seconds |
| Started | Sep 01 10:10:58 PM UTC 24 |
| Finished | Sep 01 10:11:04 PM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794308313 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2794308313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2977905584 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 351677690 ps |
| CPU time | 14.6 seconds |
| Started | Sep 01 10:10:56 PM UTC 24 |
| Finished | Sep 01 10:11:12 PM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977905584 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2977905584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1817016853 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 15005196153 ps |
| CPU time | 1402.4 seconds |
| Started | Sep 01 10:09:24 PM UTC 24 |
| Finished | Sep 01 10:33:02 PM UTC 24 |
| Peak memory | 380844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817016853 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.1817016853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.149997589 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 680805663 ps |
| CPU time | 4.98 seconds |
| Started | Sep 01 10:10:13 PM UTC 24 |
| Finished | Sep 01 10:10:19 PM UTC 24 |
| Peak memory | 213784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149997589 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.149997589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.957899421 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 25407603363 ps |
| CPU time | 356.34 seconds |
| Started | Sep 01 10:10:14 PM UTC 24 |
| Finished | Sep 01 10:16:15 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957899421 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acce ss_b2b.957899421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2228316732 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 91101427 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 10:10:55 PM UTC 24 |
| Finished | Sep 01 10:10:57 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228316732 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2228316732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.176345873 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 53586854120 ps |
| CPU time | 749.92 seconds |
| Started | Sep 01 10:10:53 PM UTC 24 |
| Finished | Sep 01 10:23:31 PM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176345873 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.176345873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.260751011 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 218761605 ps |
| CPU time | 8.57 seconds |
| Started | Sep 01 10:09:14 PM UTC 24 |
| Finished | Sep 01 10:09:24 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260751011 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.260751011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3050865605 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 14533624588 ps |
| CPU time | 919.69 seconds |
| Started | Sep 01 10:11:05 PM UTC 24 |
| Finished | Sep 01 10:26:36 PM UTC 24 |
| Peak memory | 382900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305086560 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.3050865605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1108381238 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1150129396 ps |
| CPU time | 236.57 seconds |
| Started | Sep 01 10:11:04 PM UTC 24 |
| Finished | Sep 01 10:15:05 PM UTC 24 |
| Peak memory | 350380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108381238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1108381238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2587667215 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 9947755036 ps |
| CPU time | 244.12 seconds |
| Started | Sep 01 10:09:50 PM UTC 24 |
| Finished | Sep 01 10:13:57 PM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587667215 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.2587667215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.668591019 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 237408274 ps |
| CPU time | 54.54 seconds |
| Started | Sep 01 10:10:20 PM UTC 24 |
| Finished | Sep 01 10:11:16 PM UTC 24 |
| Peak memory | 331552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 668591019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_th roughput_w_partial_write.668591019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3404923593 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1926599252 ps |
| CPU time | 720.43 seconds |
| Started | Sep 01 10:11:58 PM UTC 24 |
| Finished | Sep 01 10:24:07 PM UTC 24 |
| Peak memory | 378728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404923593 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during _key_req.3404923593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1703114219 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 15518787 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 10:12:18 PM UTC 24 |
| Finished | Sep 01 10:12:19 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703114219 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1703114219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.2188928900 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3822185321 ps |
| CPU time | 80.07 seconds |
| Started | Sep 01 10:11:13 PM UTC 24 |
| Finished | Sep 01 10:12:35 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188928900 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.2188928900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.4007658808 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 11634236435 ps |
| CPU time | 1493.62 seconds |
| Started | Sep 01 10:12:00 PM UTC 24 |
| Finished | Sep 01 10:37:10 PM UTC 24 |
| Peak memory | 385268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007658808 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.4007658808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3740942908 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 327055219 ps |
| CPU time | 2.55 seconds |
| Started | Sep 01 10:11:56 PM UTC 24 |
| Finished | Sep 01 10:11:59 PM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740942908 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.3740942908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3205867109 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1269371380 ps |
| CPU time | 76.5 seconds |
| Started | Sep 01 10:11:48 PM UTC 24 |
| Finished | Sep 01 10:13:07 PM UTC 24 |
| Peak memory | 380716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 205867109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma x_throughput.3205867109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2154605126 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 232223515 ps |
| CPU time | 5.11 seconds |
| Started | Sep 01 10:12:10 PM UTC 24 |
| Finished | Sep 01 10:12:16 PM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154605126 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.2154605126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2952541309 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 691661568 ps |
| CPU time | 16.26 seconds |
| Started | Sep 01 10:12:08 PM UTC 24 |
| Finished | Sep 01 10:12:26 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952541309 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.2952541309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1862626259 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 724796335 ps |
| CPU time | 143.18 seconds |
| Started | Sep 01 10:11:12 PM UTC 24 |
| Finished | Sep 01 10:13:37 PM UTC 24 |
| Peak memory | 349992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862626259 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.1862626259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.40024559 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1139846716 ps |
| CPU time | 15.75 seconds |
| Started | Sep 01 10:11:30 PM UTC 24 |
| Finished | Sep 01 10:11:47 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40024559 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.40024559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3845607143 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 72097352682 ps |
| CPU time | 338.15 seconds |
| Started | Sep 01 10:11:31 PM UTC 24 |
| Finished | Sep 01 10:17:14 PM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845607143 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acc ess_b2b.3845607143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1783322252 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 31777915 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 10:12:07 PM UTC 24 |
| Finished | Sep 01 10:12:09 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783322252 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1783322252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1948971260 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 28031172603 ps |
| CPU time | 948.41 seconds |
| Started | Sep 01 10:12:06 PM UTC 24 |
| Finished | Sep 01 10:28:04 PM UTC 24 |
| Peak memory | 384952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948971260 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1948971260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.3470789709 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 641551474 ps |
| CPU time | 18.63 seconds |
| Started | Sep 01 10:11:11 PM UTC 24 |
| Finished | Sep 01 10:11:30 PM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470789709 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3470789709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.30293291 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 26801586923 ps |
| CPU time | 2153.17 seconds |
| Started | Sep 01 10:12:17 PM UTC 24 |
| Finished | Sep 01 10:48:34 PM UTC 24 |
| Peak memory | 405420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30293291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.30293291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2313340909 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4048220334 ps |
| CPU time | 18.52 seconds |
| Started | Sep 01 10:12:14 PM UTC 24 |
| Finished | Sep 01 10:12:34 PM UTC 24 |
| Peak memory | 224552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313340909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2313340909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.4216880784 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 22323734814 ps |
| CPU time | 371.03 seconds |
| Started | Sep 01 10:11:17 PM UTC 24 |
| Finished | Sep 01 10:17:33 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216880784 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.4216880784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3467986759 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 270962039 ps |
| CPU time | 15 seconds |
| Started | Sep 01 10:11:50 PM UTC 24 |
| Finished | Sep 01 10:12:06 PM UTC 24 |
| Peak memory | 264044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3467986759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.3467986759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.747028746 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3449684554 ps |
| CPU time | 666.46 seconds |
| Started | Sep 01 10:13:24 PM UTC 24 |
| Finished | Sep 01 10:24:39 PM UTC 24 |
| Peak memory | 378796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747028746 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during_ key_req.747028746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1074791031 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 33705296 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 10:13:47 PM UTC 24 |
| Finished | Sep 01 10:13:49 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074791031 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1074791031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.2440103566 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1244108798 ps |
| CPU time | 34.48 seconds |
| Started | Sep 01 10:12:28 PM UTC 24 |
| Finished | Sep 01 10:13:04 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440103566 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.2440103566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2762190694 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 19656045646 ps |
| CPU time | 730.87 seconds |
| Started | Sep 01 10:13:32 PM UTC 24 |
| Finished | Sep 01 10:25:52 PM UTC 24 |
| Peak memory | 385208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762190694 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.2762190694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.924283243 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1419558795 ps |
| CPU time | 6.23 seconds |
| Started | Sep 01 10:13:23 PM UTC 24 |
| Finished | Sep 01 10:13:31 PM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924283243 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.924283243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1102903694 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 162903028 ps |
| CPU time | 29.86 seconds |
| Started | Sep 01 10:13:04 PM UTC 24 |
| Finished | Sep 01 10:13:36 PM UTC 24 |
| Peak memory | 297076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 102903694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ma x_throughput.1102903694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1666525492 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 84359748 ps |
| CPU time | 3.76 seconds |
| Started | Sep 01 10:13:42 PM UTC 24 |
| Finished | Sep 01 10:13:46 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666525492 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.1666525492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.228639614 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 96364509 ps |
| CPU time | 6.27 seconds |
| Started | Sep 01 10:13:38 PM UTC 24 |
| Finished | Sep 01 10:13:46 PM UTC 24 |
| Peak memory | 224076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228639614 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.228639614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.4247186869 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5472811326 ps |
| CPU time | 363.91 seconds |
| Started | Sep 01 10:12:27 PM UTC 24 |
| Finished | Sep 01 10:18:35 PM UTC 24 |
| Peak memory | 384944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247186869 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.4247186869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2203553438 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2313490468 ps |
| CPU time | 121.03 seconds |
| Started | Sep 01 10:12:36 PM UTC 24 |
| Finished | Sep 01 10:14:40 PM UTC 24 |
| Peak memory | 364536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203553438 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.2203553438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.290741714 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 50039521275 ps |
| CPU time | 327.47 seconds |
| Started | Sep 01 10:12:54 PM UTC 24 |
| Finished | Sep 01 10:18:27 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290741714 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acce ss_b2b.290741714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.4125211755 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 351377527 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 10:13:38 PM UTC 24 |
| Finished | Sep 01 10:13:41 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125211755 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.4125211755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3034586038 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 7016925183 ps |
| CPU time | 1515.78 seconds |
| Started | Sep 01 10:13:37 PM UTC 24 |
| Finished | Sep 01 10:39:10 PM UTC 24 |
| Peak memory | 386948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034586038 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3034586038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3371658753 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 459999360 ps |
| CPU time | 60.48 seconds |
| Started | Sep 01 10:12:21 PM UTC 24 |
| Finished | Sep 01 10:13:23 PM UTC 24 |
| Peak memory | 323404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371658753 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3371658753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1742329829 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 38407227751 ps |
| CPU time | 3231.15 seconds |
| Started | Sep 01 10:13:47 PM UTC 24 |
| Finished | Sep 01 11:08:13 PM UTC 24 |
| Peak memory | 387000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174232982 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.1742329829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.161886491 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 18753842303 ps |
| CPU time | 392.86 seconds |
| Started | Sep 01 10:13:46 PM UTC 24 |
| Finished | Sep 01 10:20:24 PM UTC 24 |
| Peak memory | 389104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161886491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.161886491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3549790322 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 16783376542 ps |
| CPU time | 443.14 seconds |
| Started | Sep 01 10:12:35 PM UTC 24 |
| Finished | Sep 01 10:20:04 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549790322 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.3549790322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1911815833 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 444636359 ps |
| CPU time | 50.99 seconds |
| Started | Sep 01 10:13:08 PM UTC 24 |
| Finished | Sep 01 10:14:01 PM UTC 24 |
| Peak memory | 321264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1911815833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t hroughput_w_partial_write.1911815833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1771378219 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 13924223738 ps |
| CPU time | 693.38 seconds |
| Started | Sep 01 10:14:49 PM UTC 24 |
| Finished | Sep 01 10:26:31 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771378219 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during _key_req.1771378219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1053743518 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 14880183 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 10:15:21 PM UTC 24 |
| Finished | Sep 01 10:15:23 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053743518 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1053743518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.999900650 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3515119157 ps |
| CPU time | 52.81 seconds |
| Started | Sep 01 10:13:58 PM UTC 24 |
| Finished | Sep 01 10:14:53 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999900650 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.999900650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.2068087097 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 21091731132 ps |
| CPU time | 1459.66 seconds |
| Started | Sep 01 10:14:53 PM UTC 24 |
| Finished | Sep 01 10:39:29 PM UTC 24 |
| Peak memory | 378804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068087097 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.2068087097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.1010572808 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 97975708 ps |
| CPU time | 46.24 seconds |
| Started | Sep 01 10:14:25 PM UTC 24 |
| Finished | Sep 01 10:15:13 PM UTC 24 |
| Peak memory | 313452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 010572808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma x_throughput.1010572808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1107279590 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 229026173 ps |
| CPU time | 7.19 seconds |
| Started | Sep 01 10:15:12 PM UTC 24 |
| Finished | Sep 01 10:15:20 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107279590 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.1107279590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4268973511 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 457615779 ps |
| CPU time | 14.27 seconds |
| Started | Sep 01 10:15:09 PM UTC 24 |
| Finished | Sep 01 10:15:24 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268973511 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.4268973511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.233508457 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 6542191967 ps |
| CPU time | 1420.74 seconds |
| Started | Sep 01 10:13:58 PM UTC 24 |
| Finished | Sep 01 10:37:54 PM UTC 24 |
| Peak memory | 385200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233508457 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.233508457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2032721273 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 632147690 ps |
| CPU time | 7.05 seconds |
| Started | Sep 01 10:14:16 PM UTC 24 |
| Finished | Sep 01 10:14:24 PM UTC 24 |
| Peak memory | 237432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032721273 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.2032721273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1036362234 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 34431662521 ps |
| CPU time | 227.41 seconds |
| Started | Sep 01 10:14:17 PM UTC 24 |
| Finished | Sep 01 10:18:08 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036362234 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acc ess_b2b.1036362234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3335771809 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 75230714 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 10:15:06 PM UTC 24 |
| Finished | Sep 01 10:15:08 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335771809 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3335771809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3031658702 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 37898033099 ps |
| CPU time | 619.19 seconds |
| Started | Sep 01 10:14:54 PM UTC 24 |
| Finished | Sep 01 10:25:21 PM UTC 24 |
| Peak memory | 364468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031658702 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3031658702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3734824010 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1421766006 ps |
| CPU time | 83 seconds |
| Started | Sep 01 10:13:50 PM UTC 24 |
| Finished | Sep 01 10:15:15 PM UTC 24 |
| Peak memory | 366388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734824010 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3734824010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2123302534 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 17927798147 ps |
| CPU time | 1011.06 seconds |
| Started | Sep 01 10:15:16 PM UTC 24 |
| Finished | Sep 01 10:32:18 PM UTC 24 |
| Peak memory | 391020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212330253 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.2123302534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2827064436 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 639006787 ps |
| CPU time | 24.56 seconds |
| Started | Sep 01 10:15:13 PM UTC 24 |
| Finished | Sep 01 10:15:39 PM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827064436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2827064436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1095266744 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1839898576 ps |
| CPU time | 186.16 seconds |
| Started | Sep 01 10:14:01 PM UTC 24 |
| Finished | Sep 01 10:17:10 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095266744 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.1095266744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1982840489 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 361963255 ps |
| CPU time | 33.31 seconds |
| Started | Sep 01 10:14:36 PM UTC 24 |
| Finished | Sep 01 10:15:11 PM UTC 24 |
| Peak memory | 297128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1982840489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_t hroughput_w_partial_write.1982840489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1326534552 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 23757298265 ps |
| CPU time | 1036.24 seconds |
| Started | Sep 01 10:16:21 PM UTC 24 |
| Finished | Sep 01 10:33:49 PM UTC 24 |
| Peak memory | 387240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326534552 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during _key_req.1326534552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2189529707 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 18645953 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 10:16:55 PM UTC 24 |
| Finished | Sep 01 10:16:57 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189529707 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2189529707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.1559110467 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2916744900 ps |
| CPU time | 40.88 seconds |
| Started | Sep 01 10:15:28 PM UTC 24 |
| Finished | Sep 01 10:16:10 PM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559110467 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.1559110467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.2204927231 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 23661663645 ps |
| CPU time | 1216.23 seconds |
| Started | Sep 01 10:16:31 PM UTC 24 |
| Finished | Sep 01 10:37:00 PM UTC 24 |
| Peak memory | 382840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204927231 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.2204927231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3477831544 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2159611507 ps |
| CPU time | 9.44 seconds |
| Started | Sep 01 10:16:20 PM UTC 24 |
| Finished | Sep 01 10:16:30 PM UTC 24 |
| Peak memory | 224184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477831544 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.3477831544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.3217819402 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 138681048 ps |
| CPU time | 19.45 seconds |
| Started | Sep 01 10:16:11 PM UTC 24 |
| Finished | Sep 01 10:16:32 PM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 217819402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ma x_throughput.3217819402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3253517139 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 174441710 ps |
| CPU time | 9.14 seconds |
| Started | Sep 01 10:16:43 PM UTC 24 |
| Finished | Sep 01 10:16:54 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253517139 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.3253517139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.4056782306 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 457436376 ps |
| CPU time | 7.31 seconds |
| Started | Sep 01 10:16:36 PM UTC 24 |
| Finished | Sep 01 10:16:45 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056782306 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.4056782306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1044734307 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2715971132 ps |
| CPU time | 1154.01 seconds |
| Started | Sep 01 10:15:25 PM UTC 24 |
| Finished | Sep 01 10:34:52 PM UTC 24 |
| Peak memory | 385264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044734307 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.1044734307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.42762532 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 237399607 ps |
| CPU time | 60.25 seconds |
| Started | Sep 01 10:15:40 PM UTC 24 |
| Finished | Sep 01 10:16:42 PM UTC 24 |
| Peak memory | 331888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42762532 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.42762532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2198401737 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6372737484 ps |
| CPU time | 240.75 seconds |
| Started | Sep 01 10:15:56 PM UTC 24 |
| Finished | Sep 01 10:20:01 PM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198401737 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc ess_b2b.2198401737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2829210397 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 69046513 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 10:16:33 PM UTC 24 |
| Finished | Sep 01 10:16:35 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829210397 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2829210397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.846455334 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 7305745500 ps |
| CPU time | 698.87 seconds |
| Started | Sep 01 10:16:31 PM UTC 24 |
| Finished | Sep 01 10:28:18 PM UTC 24 |
| Peak memory | 384900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846455334 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.846455334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3888518331 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 111040989 ps |
| CPU time | 52.95 seconds |
| Started | Sep 01 10:15:24 PM UTC 24 |
| Finished | Sep 01 10:16:19 PM UTC 24 |
| Peak memory | 323396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888518331 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3888518331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.525459082 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 52678417284 ps |
| CPU time | 4445.74 seconds |
| Started | Sep 01 10:16:45 PM UTC 24 |
| Finished | Sep 01 11:31:42 PM UTC 24 |
| Peak memory | 396984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525459082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.525459082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.970157276 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1183167027 ps |
| CPU time | 64.44 seconds |
| Started | Sep 01 10:16:43 PM UTC 24 |
| Finished | Sep 01 10:17:49 PM UTC 24 |
| Peak memory | 315256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970157276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.970157276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.4154431571 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1525426248 ps |
| CPU time | 173.44 seconds |
| Started | Sep 01 10:15:31 PM UTC 24 |
| Finished | Sep 01 10:18:27 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154431571 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.4154431571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2066047904 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 632204861 ps |
| CPU time | 85.76 seconds |
| Started | Sep 01 10:16:16 PM UTC 24 |
| Finished | Sep 01 10:17:44 PM UTC 24 |
| Peak memory | 383080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2066047904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t hroughput_w_partial_write.2066047904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3282507099 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3614459670 ps |
| CPU time | 1360.9 seconds |
| Started | Sep 01 10:17:54 PM UTC 24 |
| Finished | Sep 01 10:40:49 PM UTC 24 |
| Peak memory | 381096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282507099 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during _key_req.3282507099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3847073769 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 23173090 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 10:18:37 PM UTC 24 |
| Finished | Sep 01 10:18:39 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847073769 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3847073769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1454862259 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3651294782 ps |
| CPU time | 95.27 seconds |
| Started | Sep 01 10:17:11 PM UTC 24 |
| Finished | Sep 01 10:18:48 PM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454862259 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1454862259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1044119593 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 9054775250 ps |
| CPU time | 427.16 seconds |
| Started | Sep 01 10:17:59 PM UTC 24 |
| Finished | Sep 01 10:25:12 PM UTC 24 |
| Peak memory | 364416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044119593 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.1044119593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.2232687516 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1337035067 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 10:17:51 PM UTC 24 |
| Finished | Sep 01 10:17:58 PM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232687516 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.2232687516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1321695701 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 112099622 ps |
| CPU time | 55.56 seconds |
| Started | Sep 01 10:17:46 PM UTC 24 |
| Finished | Sep 01 10:18:43 PM UTC 24 |
| Peak memory | 337776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 321695701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma x_throughput.1321695701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1486221851 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 785365842 ps |
| CPU time | 8.03 seconds |
| Started | Sep 01 10:18:27 PM UTC 24 |
| Finished | Sep 01 10:18:37 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486221851 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1486221851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2812478 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 516132636 ps |
| CPU time | 16.16 seconds |
| Started | Sep 01 10:18:18 PM UTC 24 |
| Finished | Sep 01 10:18:36 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812478 -assert nopostpr oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.2812478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.892864989 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2128209060 ps |
| CPU time | 520.8 seconds |
| Started | Sep 01 10:17:00 PM UTC 24 |
| Finished | Sep 01 10:25:47 PM UTC 24 |
| Peak memory | 382836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892864989 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.892864989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3965343967 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 936464558 ps |
| CPU time | 17.73 seconds |
| Started | Sep 01 10:17:30 PM UTC 24 |
| Finished | Sep 01 10:17:50 PM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965343967 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.3965343967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2566807579 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 21443582919 ps |
| CPU time | 700.14 seconds |
| Started | Sep 01 10:17:34 PM UTC 24 |
| Finished | Sep 01 10:29:24 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566807579 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc ess_b2b.2566807579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1394486683 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 48396916 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 10:18:15 PM UTC 24 |
| Finished | Sep 01 10:18:17 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394486683 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1394486683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.1940881926 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 4579746915 ps |
| CPU time | 654.61 seconds |
| Started | Sep 01 10:18:08 PM UTC 24 |
| Finished | Sep 01 10:29:10 PM UTC 24 |
| Peak memory | 385204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940881926 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1940881926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2370087457 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 667734917 ps |
| CPU time | 30.7 seconds |
| Started | Sep 01 10:16:58 PM UTC 24 |
| Finished | Sep 01 10:17:30 PM UTC 24 |
| Peak memory | 288452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370087457 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2370087457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.39291915 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 87159250350 ps |
| CPU time | 1661.9 seconds |
| Started | Sep 01 10:18:37 PM UTC 24 |
| Finished | Sep 01 10:46:37 PM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39291915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.39291915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3046642333 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 6457292449 ps |
| CPU time | 320.2 seconds |
| Started | Sep 01 10:18:29 PM UTC 24 |
| Finished | Sep 01 10:23:53 PM UTC 24 |
| Peak memory | 346100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046642333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3046642333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2072040897 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 26123658389 ps |
| CPU time | 291.24 seconds |
| Started | Sep 01 10:17:15 PM UTC 24 |
| Finished | Sep 01 10:22:11 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072040897 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.2072040897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.796553903 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 563897929 ps |
| CPU time | 91.6 seconds |
| Started | Sep 01 10:17:51 PM UTC 24 |
| Finished | Sep 01 10:19:24 PM UTC 24 |
| Peak memory | 374892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 796553903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_th roughput_w_partial_write.796553903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.315439282 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 21321335376 ps |
| CPU time | 802.05 seconds |
| Started | Sep 01 09:47:16 PM UTC 24 |
| Finished | Sep 01 10:00:48 PM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315439282 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_k ey_req.315439282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3446242775 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 29678882 ps |
| CPU time | 1 seconds |
| Started | Sep 01 09:47:56 PM UTC 24 |
| Finished | Sep 01 09:47:58 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446242775 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3446242775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.303853439 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5137821611 ps |
| CPU time | 37.23 seconds |
| Started | Sep 01 09:46:30 PM UTC 24 |
| Finished | Sep 01 09:47:08 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303853439 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.303853439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2846222287 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1336831483 ps |
| CPU time | 8.59 seconds |
| Started | Sep 01 09:47:15 PM UTC 24 |
| Finished | Sep 01 09:47:25 PM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846222287 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.2846222287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1473604959 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1600700011 ps |
| CPU time | 40.73 seconds |
| Started | Sep 01 09:47:09 PM UTC 24 |
| Finished | Sep 01 09:47:52 PM UTC 24 |
| Peak memory | 319528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 473604959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max _throughput.1473604959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2030103265 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 65039817 ps |
| CPU time | 5.73 seconds |
| Started | Sep 01 09:47:43 PM UTC 24 |
| Finished | Sep 01 09:47:50 PM UTC 24 |
| Peak memory | 223964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030103265 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.2030103265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.699551654 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 242012221 ps |
| CPU time | 6.54 seconds |
| Started | Sep 01 09:47:37 PM UTC 24 |
| Finished | Sep 01 09:47:44 PM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699551654 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.699551654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.149321783 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3756055296 ps |
| CPU time | 1093.81 seconds |
| Started | Sep 01 09:46:28 PM UTC 24 |
| Finished | Sep 01 10:04:54 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149321783 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.149321783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.901635819 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 732566924 ps |
| CPU time | 13.87 seconds |
| Started | Sep 01 09:46:51 PM UTC 24 |
| Finished | Sep 01 09:47:06 PM UTC 24 |
| Peak memory | 213976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901635819 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.901635819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3076262744 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 16941813210 ps |
| CPU time | 611.23 seconds |
| Started | Sep 01 09:47:07 PM UTC 24 |
| Finished | Sep 01 09:57:26 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076262744 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce ss_b2b.3076262744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2582187361 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 114150111 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:47:34 PM UTC 24 |
| Finished | Sep 01 09:47:36 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582187361 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2582187361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.491093690 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1657922236 ps |
| CPU time | 54.09 seconds |
| Started | Sep 01 09:47:26 PM UTC 24 |
| Finished | Sep 01 09:48:21 PM UTC 24 |
| Peak memory | 278264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491093690 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.491093690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3720023886 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 262681266 ps |
| CPU time | 4.64 seconds |
| Started | Sep 01 09:47:52 PM UTC 24 |
| Finished | Sep 01 09:47:58 PM UTC 24 |
| Peak memory | 250084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720023886 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3720023886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1697273727 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 365486308 ps |
| CPU time | 12.66 seconds |
| Started | Sep 01 09:46:25 PM UTC 24 |
| Finished | Sep 01 09:46:39 PM UTC 24 |
| Peak memory | 264060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697273727 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1697273727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2846932534 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 14449127772 ps |
| CPU time | 2081.76 seconds |
| Started | Sep 01 09:47:50 PM UTC 24 |
| Finished | Sep 01 10:22:55 PM UTC 24 |
| Peak memory | 395188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284693253 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.2846932534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3011267339 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 588240817 ps |
| CPU time | 8.92 seconds |
| Started | Sep 01 09:47:45 PM UTC 24 |
| Finished | Sep 01 09:47:55 PM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011267339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3011267339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3856098621 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2784151262 ps |
| CPU time | 332.72 seconds |
| Started | Sep 01 09:46:40 PM UTC 24 |
| Finished | Sep 01 09:52:17 PM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856098621 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.3856098621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.503570106 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 158868726 ps |
| CPU time | 111.19 seconds |
| Started | Sep 01 09:47:14 PM UTC 24 |
| Finished | Sep 01 09:49:08 PM UTC 24 |
| Peak memory | 380912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 503570106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_thr oughput_w_partial_write.503570106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2253892360 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 5070292635 ps |
| CPU time | 901.39 seconds |
| Started | Sep 01 10:19:25 PM UTC 24 |
| Finished | Sep 01 10:34:36 PM UTC 24 |
| Peak memory | 380840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253892360 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during _key_req.2253892360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1085717298 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 36154062 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 10:20:05 PM UTC 24 |
| Finished | Sep 01 10:20:07 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085717298 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1085717298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.1190927841 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2196568507 ps |
| CPU time | 43.07 seconds |
| Started | Sep 01 10:18:39 PM UTC 24 |
| Finished | Sep 01 10:19:24 PM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190927841 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.1190927841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.2005082453 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 44299024777 ps |
| CPU time | 1560.08 seconds |
| Started | Sep 01 10:19:34 PM UTC 24 |
| Finished | Sep 01 10:45:53 PM UTC 24 |
| Peak memory | 380780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005082453 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.2005082453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2638224950 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 754512615 ps |
| CPU time | 6.65 seconds |
| Started | Sep 01 10:19:25 PM UTC 24 |
| Finished | Sep 01 10:19:33 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638224950 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.2638224950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.234214971 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 106764096 ps |
| CPU time | 62.4 seconds |
| Started | Sep 01 10:18:56 PM UTC 24 |
| Finished | Sep 01 10:20:00 PM UTC 24 |
| Peak memory | 321404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 34214971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max _throughput.234214971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3196018378 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 215832692 ps |
| CPU time | 4.3 seconds |
| Started | Sep 01 10:20:01 PM UTC 24 |
| Finished | Sep 01 10:20:06 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196018378 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3196018378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.63393661 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 975645757 ps |
| CPU time | 6.68 seconds |
| Started | Sep 01 10:19:54 PM UTC 24 |
| Finished | Sep 01 10:20:02 PM UTC 24 |
| Peak memory | 224412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63393661 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.63393661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.120731618 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 12041895144 ps |
| CPU time | 571.3 seconds |
| Started | Sep 01 10:18:38 PM UTC 24 |
| Finished | Sep 01 10:28:16 PM UTC 24 |
| Peak memory | 383152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120731618 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.120731618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2952011678 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2759232469 ps |
| CPU time | 20.69 seconds |
| Started | Sep 01 10:18:49 PM UTC 24 |
| Finished | Sep 01 10:19:11 PM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952011678 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.2952011678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2888770706 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 15894807598 ps |
| CPU time | 431.94 seconds |
| Started | Sep 01 10:18:53 PM UTC 24 |
| Finished | Sep 01 10:26:10 PM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888770706 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc ess_b2b.2888770706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3100743900 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 28877917 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 10:19:51 PM UTC 24 |
| Finished | Sep 01 10:19:53 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100743900 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3100743900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.1658962681 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4628157855 ps |
| CPU time | 1018.97 seconds |
| Started | Sep 01 10:19:35 PM UTC 24 |
| Finished | Sep 01 10:36:46 PM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658962681 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1658962681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2557537602 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 117536290 ps |
| CPU time | 55.13 seconds |
| Started | Sep 01 10:18:38 PM UTC 24 |
| Finished | Sep 01 10:19:35 PM UTC 24 |
| Peak memory | 331892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557537602 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2557537602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.4142412250 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 92278059950 ps |
| CPU time | 8128.03 seconds |
| Started | Sep 01 10:20:02 PM UTC 24 |
| Finished | Sep 02 12:37:03 AM UTC 24 |
| Peak memory | 390700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414241225 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.4142412250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1750006150 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4222459089 ps |
| CPU time | 262.44 seconds |
| Started | Sep 01 10:20:02 PM UTC 24 |
| Finished | Sep 01 10:24:28 PM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750006150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1750006150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1771465050 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 13369934565 ps |
| CPU time | 335.86 seconds |
| Started | Sep 01 10:18:43 PM UTC 24 |
| Finished | Sep 01 10:24:24 PM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771465050 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.1771465050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2205406021 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 583570252 ps |
| CPU time | 123.7 seconds |
| Started | Sep 01 10:19:12 PM UTC 24 |
| Finished | Sep 01 10:21:18 PM UTC 24 |
| Peak memory | 380780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2205406021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t hroughput_w_partial_write.2205406021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3577070704 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 6673353984 ps |
| CPU time | 1082.27 seconds |
| Started | Sep 01 10:22:17 PM UTC 24 |
| Finished | Sep 01 10:40:31 PM UTC 24 |
| Peak memory | 386888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577070704 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during _key_req.3577070704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3956182322 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 40588838 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 10:23:04 PM UTC 24 |
| Finished | Sep 01 10:23:06 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956182322 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.3956182322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.3712580237 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 20540100331 ps |
| CPU time | 39.21 seconds |
| Started | Sep 01 10:20:14 PM UTC 24 |
| Finished | Sep 01 10:20:54 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712580237 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.3712580237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.92896108 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 4692751472 ps |
| CPU time | 1066.65 seconds |
| Started | Sep 01 10:22:25 PM UTC 24 |
| Finished | Sep 01 10:40:24 PM UTC 24 |
| Peak memory | 378996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92896108 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.92896108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.90089245 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3196341678 ps |
| CPU time | 3.54 seconds |
| Started | Sep 01 10:22:12 PM UTC 24 |
| Finished | Sep 01 10:22:16 PM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90089245 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.90089245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.2022251184 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 128781345 ps |
| CPU time | 97.46 seconds |
| Started | Sep 01 10:21:19 PM UTC 24 |
| Finished | Sep 01 10:22:59 PM UTC 24 |
| Peak memory | 368424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 022251184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma x_throughput.2022251184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.408992026 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 117563694 ps |
| CPU time | 6.54 seconds |
| Started | Sep 01 10:22:56 PM UTC 24 |
| Finished | Sep 01 10:23:03 PM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408992026 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.408992026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1297616051 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2508424183 ps |
| CPU time | 16.83 seconds |
| Started | Sep 01 10:22:42 PM UTC 24 |
| Finished | Sep 01 10:23:00 PM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297616051 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1297616051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.3001205138 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 11019225370 ps |
| CPU time | 864.63 seconds |
| Started | Sep 01 10:20:08 PM UTC 24 |
| Finished | Sep 01 10:34:44 PM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001205138 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.3001205138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1560188756 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 106037535 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 10:20:55 PM UTC 24 |
| Finished | Sep 01 10:20:58 PM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560188756 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.1560188756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.4114078503 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 7528413454 ps |
| CPU time | 284.11 seconds |
| Started | Sep 01 10:20:59 PM UTC 24 |
| Finished | Sep 01 10:25:47 PM UTC 24 |
| Peak memory | 214148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114078503 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc ess_b2b.4114078503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1434585792 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 32001464 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 10:22:38 PM UTC 24 |
| Finished | Sep 01 10:22:41 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434585792 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1434585792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.2385608596 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4146028775 ps |
| CPU time | 124.86 seconds |
| Started | Sep 01 10:22:35 PM UTC 24 |
| Finished | Sep 01 10:24:43 PM UTC 24 |
| Peak memory | 286572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385608596 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2385608596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.1878990950 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 111554703 ps |
| CPU time | 4.1 seconds |
| Started | Sep 01 10:20:07 PM UTC 24 |
| Finished | Sep 01 10:20:12 PM UTC 24 |
| Peak memory | 214132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878990950 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1878990950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1400327517 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 53813083208 ps |
| CPU time | 4609.4 seconds |
| Started | Sep 01 10:23:01 PM UTC 24 |
| Finished | Sep 01 11:40:41 PM UTC 24 |
| Peak memory | 388720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140032751 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.1400327517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2564479293 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1730294525 ps |
| CPU time | 196.27 seconds |
| Started | Sep 01 10:23:00 PM UTC 24 |
| Finished | Sep 01 10:26:19 PM UTC 24 |
| Peak memory | 374956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564479293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2564479293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.1927067268 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3686402077 ps |
| CPU time | 422.51 seconds |
| Started | Sep 01 10:20:25 PM UTC 24 |
| Finished | Sep 01 10:27:33 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927067268 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.1927067268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2892024901 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 264435457 ps |
| CPU time | 92.88 seconds |
| Started | Sep 01 10:22:10 PM UTC 24 |
| Finished | Sep 01 10:23:44 PM UTC 24 |
| Peak memory | 364392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2892024901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_t hroughput_w_partial_write.2892024901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1532888476 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 6169590479 ps |
| CPU time | 1038.23 seconds |
| Started | Sep 01 10:24:15 PM UTC 24 |
| Finished | Sep 01 10:41:46 PM UTC 24 |
| Peak memory | 385204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532888476 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during _key_req.1532888476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1234028979 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 13412519 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 10:24:42 PM UTC 24 |
| Finished | Sep 01 10:24:44 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234028979 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1234028979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3879798040 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 15877087107 ps |
| CPU time | 27.09 seconds |
| Started | Sep 01 10:23:27 PM UTC 24 |
| Finished | Sep 01 10:23:56 PM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879798040 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.3879798040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3680382698 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 10296943697 ps |
| CPU time | 304.28 seconds |
| Started | Sep 01 10:24:17 PM UTC 24 |
| Finished | Sep 01 10:29:26 PM UTC 24 |
| Peak memory | 327480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680382698 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.3680382698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3361751521 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 235550795 ps |
| CPU time | 5.09 seconds |
| Started | Sep 01 10:24:08 PM UTC 24 |
| Finished | Sep 01 10:24:14 PM UTC 24 |
| Peak memory | 213796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361751521 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.3361751521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.3323552279 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 218721974 ps |
| CPU time | 39.45 seconds |
| Started | Sep 01 10:23:54 PM UTC 24 |
| Finished | Sep 01 10:24:35 PM UTC 24 |
| Peak memory | 306996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 323552279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ma x_throughput.3323552279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.2532941151 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 122136504 ps |
| CPU time | 4.24 seconds |
| Started | Sep 01 10:24:36 PM UTC 24 |
| Finished | Sep 01 10:24:41 PM UTC 24 |
| Peak memory | 224312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532941151 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.2532941151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3664109516 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 466186904 ps |
| CPU time | 7.11 seconds |
| Started | Sep 01 10:24:32 PM UTC 24 |
| Finished | Sep 01 10:24:40 PM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664109516 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.3664109516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2934916737 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 698262000 ps |
| CPU time | 486.51 seconds |
| Started | Sep 01 10:23:27 PM UTC 24 |
| Finished | Sep 01 10:31:39 PM UTC 24 |
| Peak memory | 378608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934916737 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.2934916737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3399238201 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2610552460 ps |
| CPU time | 77.58 seconds |
| Started | Sep 01 10:23:46 PM UTC 24 |
| Finished | Sep 01 10:25:05 PM UTC 24 |
| Peak memory | 339844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399238201 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.3399238201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1211690702 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 5014003423 ps |
| CPU time | 428.23 seconds |
| Started | Sep 01 10:23:46 PM UTC 24 |
| Finished | Sep 01 10:31:00 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211690702 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc ess_b2b.1211690702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.2976240543 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 167662751 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 10:24:29 PM UTC 24 |
| Finished | Sep 01 10:24:31 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976240543 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2976240543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.552326429 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 17618040487 ps |
| CPU time | 1037.05 seconds |
| Started | Sep 01 10:24:25 PM UTC 24 |
| Finished | Sep 01 10:41:53 PM UTC 24 |
| Peak memory | 382896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552326429 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.552326429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.896578948 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1255281690 ps |
| CPU time | 17.86 seconds |
| Started | Sep 01 10:23:07 PM UTC 24 |
| Finished | Sep 01 10:23:26 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896578948 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.896578948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.764465069 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 368172160926 ps |
| CPU time | 3762.28 seconds |
| Started | Sep 01 10:24:41 PM UTC 24 |
| Finished | Sep 01 11:28:04 PM UTC 24 |
| Peak memory | 396908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764465069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.764465069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1140421683 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 9957986690 ps |
| CPU time | 752.38 seconds |
| Started | Sep 01 10:24:40 PM UTC 24 |
| Finished | Sep 01 10:37:21 PM UTC 24 |
| Peak memory | 391076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140421683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1140421683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.3576142274 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4786996340 ps |
| CPU time | 247.88 seconds |
| Started | Sep 01 10:23:33 PM UTC 24 |
| Finished | Sep 01 10:27:44 PM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576142274 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.3576142274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3116354313 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 117675394 ps |
| CPU time | 51.03 seconds |
| Started | Sep 01 10:23:57 PM UTC 24 |
| Finished | Sep 01 10:24:50 PM UTC 24 |
| Peak memory | 321452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3116354313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t hroughput_w_partial_write.3116354313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2803841440 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 13367955295 ps |
| CPU time | 844.06 seconds |
| Started | Sep 01 10:25:12 PM UTC 24 |
| Finished | Sep 01 10:39:26 PM UTC 24 |
| Peak memory | 383220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803841440 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during _key_req.2803841440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3621152984 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 21148179 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 10:25:48 PM UTC 24 |
| Finished | Sep 01 10:25:50 PM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621152984 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3621152984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.301324019 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1960252880 ps |
| CPU time | 48.49 seconds |
| Started | Sep 01 10:24:47 PM UTC 24 |
| Finished | Sep 01 10:25:37 PM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301324019 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.301324019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.662961363 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 5469525724 ps |
| CPU time | 445.11 seconds |
| Started | Sep 01 10:25:19 PM UTC 24 |
| Finished | Sep 01 10:32:49 PM UTC 24 |
| Peak memory | 380704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662961363 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.662961363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.681232122 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 5200574612 ps |
| CPU time | 9.14 seconds |
| Started | Sep 01 10:25:11 PM UTC 24 |
| Finished | Sep 01 10:25:22 PM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681232122 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.681232122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1941170895 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 440323586 ps |
| CPU time | 63.63 seconds |
| Started | Sep 01 10:25:05 PM UTC 24 |
| Finished | Sep 01 10:26:10 PM UTC 24 |
| Peak memory | 338036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 941170895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma x_throughput.1941170895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.291361864 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 328238484 ps |
| CPU time | 7.6 seconds |
| Started | Sep 01 10:25:36 PM UTC 24 |
| Finished | Sep 01 10:25:45 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291361864 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.291361864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2808123510 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 880633153 ps |
| CPU time | 7.81 seconds |
| Started | Sep 01 10:25:26 PM UTC 24 |
| Finished | Sep 01 10:25:35 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808123510 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2808123510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.724305176 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 6883314579 ps |
| CPU time | 296.14 seconds |
| Started | Sep 01 10:24:45 PM UTC 24 |
| Finished | Sep 01 10:29:46 PM UTC 24 |
| Peak memory | 382936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724305176 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.724305176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1961476989 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 858590997 ps |
| CPU time | 16.55 seconds |
| Started | Sep 01 10:24:47 PM UTC 24 |
| Finished | Sep 01 10:25:05 PM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961476989 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.1961476989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1743606535 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 9721995095 ps |
| CPU time | 512.65 seconds |
| Started | Sep 01 10:24:51 PM UTC 24 |
| Finished | Sep 01 10:33:30 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743606535 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acc ess_b2b.1743606535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.1255253103 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 51900217 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 10:25:23 PM UTC 24 |
| Finished | Sep 01 10:25:25 PM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255253103 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1255253103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.2890893578 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1809432721 ps |
| CPU time | 615.27 seconds |
| Started | Sep 01 10:25:23 PM UTC 24 |
| Finished | Sep 01 10:35:45 PM UTC 24 |
| Peak memory | 380732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890893578 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2890893578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.1987812812 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 778019193 ps |
| CPU time | 24.94 seconds |
| Started | Sep 01 10:24:44 PM UTC 24 |
| Finished | Sep 01 10:25:11 PM UTC 24 |
| Peak memory | 213936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987812812 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1987812812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2381077612 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 4421448268 ps |
| CPU time | 615.15 seconds |
| Started | Sep 01 10:25:46 PM UTC 24 |
| Finished | Sep 01 10:36:09 PM UTC 24 |
| Peak memory | 380856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238107761 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.2381077612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.254019528 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5917471182 ps |
| CPU time | 187.03 seconds |
| Started | Sep 01 10:25:38 PM UTC 24 |
| Finished | Sep 01 10:28:48 PM UTC 24 |
| Peak memory | 352244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254019528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.254019528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.21456925 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 3943873018 ps |
| CPU time | 374.6 seconds |
| Started | Sep 01 10:24:47 PM UTC 24 |
| Finished | Sep 01 10:31:06 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21456925 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.21456925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.166870580 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 478429314 ps |
| CPU time | 41.02 seconds |
| Started | Sep 01 10:25:06 PM UTC 24 |
| Finished | Sep 01 10:25:49 PM UTC 24 |
| Peak memory | 315496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 166870580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_th roughput_w_partial_write.166870580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1715901317 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 686104654 ps |
| CPU time | 94.64 seconds |
| Started | Sep 01 10:26:21 PM UTC 24 |
| Finished | Sep 01 10:27:57 PM UTC 24 |
| Peak memory | 313388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715901317 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during _key_req.1715901317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3916605081 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 12259704 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 10:27:12 PM UTC 24 |
| Finished | Sep 01 10:27:14 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916605081 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3916605081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3770345361 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5067574278 ps |
| CPU time | 90.59 seconds |
| Started | Sep 01 10:25:51 PM UTC 24 |
| Finished | Sep 01 10:27:23 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770345361 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3770345361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3796547242 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 8174000081 ps |
| CPU time | 683.2 seconds |
| Started | Sep 01 10:26:28 PM UTC 24 |
| Finished | Sep 01 10:37:59 PM UTC 24 |
| Peak memory | 370612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796547242 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.3796547242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.3022050618 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 9044105089 ps |
| CPU time | 14.5 seconds |
| Started | Sep 01 10:26:11 PM UTC 24 |
| Finished | Sep 01 10:26:27 PM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022050618 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.3022050618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.821756065 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 562049859 ps |
| CPU time | 116.42 seconds |
| Started | Sep 01 10:26:07 PM UTC 24 |
| Finished | Sep 01 10:28:06 PM UTC 24 |
| Peak memory | 380720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 21756065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_max _throughput.821756065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1960354917 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 199452158 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 10:26:49 PM UTC 24 |
| Finished | Sep 01 10:26:55 PM UTC 24 |
| Peak memory | 224408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960354917 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.1960354917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.512566003 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1728993252 ps |
| CPU time | 6.75 seconds |
| Started | Sep 01 10:26:40 PM UTC 24 |
| Finished | Sep 01 10:26:48 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512566003 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.512566003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3644524888 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 26384820431 ps |
| CPU time | 449.35 seconds |
| Started | Sep 01 10:25:50 PM UTC 24 |
| Finished | Sep 01 10:33:25 PM UTC 24 |
| Peak memory | 385144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644524888 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.3644524888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2127693366 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 126419315 ps |
| CPU time | 6.1 seconds |
| Started | Sep 01 10:25:53 PM UTC 24 |
| Finished | Sep 01 10:26:00 PM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127693366 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.2127693366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.4086129191 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 18783918690 ps |
| CPU time | 561.52 seconds |
| Started | Sep 01 10:26:01 PM UTC 24 |
| Finished | Sep 01 10:35:30 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086129191 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc ess_b2b.4086129191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1126455829 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 43066585 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 10:26:37 PM UTC 24 |
| Finished | Sep 01 10:26:39 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126455829 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1126455829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.650088413 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 8056912339 ps |
| CPU time | 593.85 seconds |
| Started | Sep 01 10:26:32 PM UTC 24 |
| Finished | Sep 01 10:36:33 PM UTC 24 |
| Peak memory | 385204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650088413 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.650088413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.1942793225 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 581927192 ps |
| CPU time | 105.34 seconds |
| Started | Sep 01 10:25:48 PM UTC 24 |
| Finished | Sep 01 10:27:36 PM UTC 24 |
| Peak memory | 366388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942793225 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1942793225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3714593595 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 85888574325 ps |
| CPU time | 1655.07 seconds |
| Started | Sep 01 10:27:04 PM UTC 24 |
| Finished | Sep 01 10:54:56 PM UTC 24 |
| Peak memory | 382900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371459359 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.3714593595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2011968521 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3025546865 ps |
| CPU time | 341.42 seconds |
| Started | Sep 01 10:25:53 PM UTC 24 |
| Finished | Sep 01 10:31:39 PM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011968521 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.2011968521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.589304385 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 462301160 ps |
| CPU time | 50.05 seconds |
| Started | Sep 01 10:26:11 PM UTC 24 |
| Finished | Sep 01 10:27:03 PM UTC 24 |
| Peak memory | 317292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 589304385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_th roughput_w_partial_write.589304385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2353235534 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1549236936 ps |
| CPU time | 117.87 seconds |
| Started | Sep 01 10:28:05 PM UTC 24 |
| Finished | Sep 01 10:30:05 PM UTC 24 |
| Peak memory | 335648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353235534 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during _key_req.2353235534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1921905275 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 75576585 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 10:28:30 PM UTC 24 |
| Finished | Sep 01 10:28:32 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921905275 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1921905275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1468199772 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2880434259 ps |
| CPU time | 60.69 seconds |
| Started | Sep 01 10:27:34 PM UTC 24 |
| Finished | Sep 01 10:28:37 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468199772 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.1468199772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.3374599048 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 5420594430 ps |
| CPU time | 414.7 seconds |
| Started | Sep 01 10:28:05 PM UTC 24 |
| Finished | Sep 01 10:35:05 PM UTC 24 |
| Peak memory | 378816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374599048 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.3374599048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3793188848 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 583365794 ps |
| CPU time | 5.2 seconds |
| Started | Sep 01 10:28:02 PM UTC 24 |
| Finished | Sep 01 10:28:08 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793188848 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.3793188848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1230256915 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 82805580 ps |
| CPU time | 4.06 seconds |
| Started | Sep 01 10:27:59 PM UTC 24 |
| Finished | Sep 01 10:28:04 PM UTC 24 |
| Peak memory | 231576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 230256915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma x_throughput.1230256915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1815289767 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 155013914 ps |
| CPU time | 2.85 seconds |
| Started | Sep 01 10:28:18 PM UTC 24 |
| Finished | Sep 01 10:28:22 PM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815289767 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.1815289767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3543501935 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 481096896 ps |
| CPU time | 15.55 seconds |
| Started | Sep 01 10:28:13 PM UTC 24 |
| Finished | Sep 01 10:28:29 PM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543501935 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.3543501935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.4051223644 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 46169993038 ps |
| CPU time | 795.22 seconds |
| Started | Sep 01 10:27:24 PM UTC 24 |
| Finished | Sep 01 10:40:49 PM UTC 24 |
| Peak memory | 370604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051223644 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.4051223644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.1699360916 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1145052309 ps |
| CPU time | 21.82 seconds |
| Started | Sep 01 10:27:37 PM UTC 24 |
| Finished | Sep 01 10:28:01 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699360916 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.1699360916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.2812178935 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 73603607333 ps |
| CPU time | 533.3 seconds |
| Started | Sep 01 10:27:45 PM UTC 24 |
| Finished | Sep 01 10:36:45 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812178935 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc ess_b2b.2812178935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3570320858 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 51248774 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 10:28:09 PM UTC 24 |
| Finished | Sep 01 10:28:12 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570320858 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3570320858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1917830252 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 22073980002 ps |
| CPU time | 456.95 seconds |
| Started | Sep 01 10:28:06 PM UTC 24 |
| Finished | Sep 01 10:35:49 PM UTC 24 |
| Peak memory | 378940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917830252 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1917830252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.3426920344 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 319907851 ps |
| CPU time | 19.26 seconds |
| Started | Sep 01 10:27:15 PM UTC 24 |
| Finished | Sep 01 10:27:35 PM UTC 24 |
| Peak memory | 288612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426920344 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3426920344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1551090812 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 142399986187 ps |
| CPU time | 3062.06 seconds |
| Started | Sep 01 10:28:22 PM UTC 24 |
| Finished | Sep 01 11:19:56 PM UTC 24 |
| Peak memory | 387164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155109081 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.1551090812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3585746293 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 7864980765 ps |
| CPU time | 758.58 seconds |
| Started | Sep 01 10:28:19 PM UTC 24 |
| Finished | Sep 01 10:41:06 PM UTC 24 |
| Peak memory | 391148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585746293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3585746293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2287817063 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4350902954 ps |
| CPU time | 413.45 seconds |
| Started | Sep 01 10:27:36 PM UTC 24 |
| Finished | Sep 01 10:34:36 PM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287817063 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.2287817063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3675073882 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 483045140 ps |
| CPU time | 41.34 seconds |
| Started | Sep 01 10:27:59 PM UTC 24 |
| Finished | Sep 01 10:28:42 PM UTC 24 |
| Peak memory | 335656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3675073882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t hroughput_w_partial_write.3675073882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2281336934 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 20061825455 ps |
| CPU time | 1466.58 seconds |
| Started | Sep 01 10:29:27 PM UTC 24 |
| Finished | Sep 01 10:54:11 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281336934 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during _key_req.2281336934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.3189036040 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 44065538 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 10:30:47 PM UTC 24 |
| Finished | Sep 01 10:30:49 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189036040 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.3189036040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1120158272 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 4756974554 ps |
| CPU time | 90.81 seconds |
| Started | Sep 01 10:28:43 PM UTC 24 |
| Finished | Sep 01 10:30:16 PM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120158272 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.1120158272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3184371380 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2972369883 ps |
| CPU time | 1369.71 seconds |
| Started | Sep 01 10:29:36 PM UTC 24 |
| Finished | Sep 01 10:52:41 PM UTC 24 |
| Peak memory | 382968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184371380 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.3184371380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1808669874 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2154580125 ps |
| CPU time | 10.43 seconds |
| Started | Sep 01 10:29:24 PM UTC 24 |
| Finished | Sep 01 10:29:36 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808669874 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.1808669874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2836311460 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 897290435 ps |
| CPU time | 121.84 seconds |
| Started | Sep 01 10:28:55 PM UTC 24 |
| Finished | Sep 01 10:31:00 PM UTC 24 |
| Peak memory | 380980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 836311460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ma x_throughput.2836311460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1003910494 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 123828692 ps |
| CPU time | 6.21 seconds |
| Started | Sep 01 10:30:17 PM UTC 24 |
| Finished | Sep 01 10:30:24 PM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003910494 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.1003910494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2068929060 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1454260477 ps |
| CPU time | 13.89 seconds |
| Started | Sep 01 10:30:09 PM UTC 24 |
| Finished | Sep 01 10:30:24 PM UTC 24 |
| Peak memory | 224004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068929060 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.2068929060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.4200759618 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 5444107310 ps |
| CPU time | 821.45 seconds |
| Started | Sep 01 10:28:38 PM UTC 24 |
| Finished | Sep 01 10:42:29 PM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200759618 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.4200759618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3196164564 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 262744422 ps |
| CPU time | 4.21 seconds |
| Started | Sep 01 10:28:49 PM UTC 24 |
| Finished | Sep 01 10:28:54 PM UTC 24 |
| Peak memory | 231232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196164564 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.3196164564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.3864928641 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 133226459539 ps |
| CPU time | 473.07 seconds |
| Started | Sep 01 10:28:50 PM UTC 24 |
| Finished | Sep 01 10:36:49 PM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864928641 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc ess_b2b.3864928641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3352797370 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 45878638 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 10:30:06 PM UTC 24 |
| Finished | Sep 01 10:30:08 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352797370 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3352797370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3344088114 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 6382373621 ps |
| CPU time | 454.04 seconds |
| Started | Sep 01 10:29:47 PM UTC 24 |
| Finished | Sep 01 10:37:26 PM UTC 24 |
| Peak memory | 368832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344088114 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3344088114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.766045809 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 320951468 ps |
| CPU time | 13.43 seconds |
| Started | Sep 01 10:28:33 PM UTC 24 |
| Finished | Sep 01 10:28:48 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766045809 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.766045809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3497970608 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 60864775829 ps |
| CPU time | 3393.29 seconds |
| Started | Sep 01 10:30:25 PM UTC 24 |
| Finished | Sep 01 11:27:34 PM UTC 24 |
| Peak memory | 388716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349797060 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.3497970608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2700493509 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 368772110 ps |
| CPU time | 103.43 seconds |
| Started | Sep 01 10:30:25 PM UTC 24 |
| Finished | Sep 01 10:32:11 PM UTC 24 |
| Peak memory | 343920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700493509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2700493509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3648831920 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 11389415473 ps |
| CPU time | 335.59 seconds |
| Started | Sep 01 10:28:49 PM UTC 24 |
| Finished | Sep 01 10:34:29 PM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648831920 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.3648831920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3231266717 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 582195138 ps |
| CPU time | 93.63 seconds |
| Started | Sep 01 10:29:11 PM UTC 24 |
| Finished | Sep 01 10:30:47 PM UTC 24 |
| Peak memory | 376612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3231266717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t hroughput_w_partial_write.3231266717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3223117517 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 10897520348 ps |
| CPU time | 838.19 seconds |
| Started | Sep 01 10:31:41 PM UTC 24 |
| Finished | Sep 01 10:45:48 PM UTC 24 |
| Peak memory | 384944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223117517 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during _key_req.3223117517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.697565638 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 38184580 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 10:32:28 PM UTC 24 |
| Finished | Sep 01 10:32:30 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697565638 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.697565638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3720691982 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 933203214 ps |
| CPU time | 18.04 seconds |
| Started | Sep 01 10:31:01 PM UTC 24 |
| Finished | Sep 01 10:31:20 PM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720691982 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.3720691982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.4115566481 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 9076030642 ps |
| CPU time | 835.55 seconds |
| Started | Sep 01 10:31:42 PM UTC 24 |
| Finished | Sep 01 10:45:47 PM UTC 24 |
| Peak memory | 374708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115566481 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.4115566481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1761359379 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 8270882845 ps |
| CPU time | 11.52 seconds |
| Started | Sep 01 10:31:41 PM UTC 24 |
| Finished | Sep 01 10:31:53 PM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761359379 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.1761359379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3690516969 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 274960995 ps |
| CPU time | 98.15 seconds |
| Started | Sep 01 10:31:25 PM UTC 24 |
| Finished | Sep 01 10:33:06 PM UTC 24 |
| Peak memory | 380716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 690516969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ma x_throughput.3690516969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3166590043 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 102998110 ps |
| CPU time | 4.06 seconds |
| Started | Sep 01 10:32:19 PM UTC 24 |
| Finished | Sep 01 10:32:25 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166590043 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.3166590043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1200619819 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 635471391 ps |
| CPU time | 10.64 seconds |
| Started | Sep 01 10:32:15 PM UTC 24 |
| Finished | Sep 01 10:32:27 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200619819 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.1200619819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2542324039 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 57419215446 ps |
| CPU time | 1367.56 seconds |
| Started | Sep 01 10:31:01 PM UTC 24 |
| Finished | Sep 01 10:54:03 PM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542324039 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2542324039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.425651507 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 741529887 ps |
| CPU time | 13.87 seconds |
| Started | Sep 01 10:31:09 PM UTC 24 |
| Finished | Sep 01 10:31:24 PM UTC 24 |
| Peak memory | 213832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425651507 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.425651507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3013570061 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 14027449441 ps |
| CPU time | 397.45 seconds |
| Started | Sep 01 10:31:21 PM UTC 24 |
| Finished | Sep 01 10:38:04 PM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013570061 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acc ess_b2b.3013570061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.1655584560 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 29492914 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 10:32:12 PM UTC 24 |
| Finished | Sep 01 10:32:15 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655584560 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1655584560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.866039285 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3363226483 ps |
| CPU time | 874.19 seconds |
| Started | Sep 01 10:31:54 PM UTC 24 |
| Finished | Sep 01 10:46:38 PM UTC 24 |
| Peak memory | 385204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866039285 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.866039285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.278599392 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2391913249 ps |
| CPU time | 15.82 seconds |
| Started | Sep 01 10:30:50 PM UTC 24 |
| Finished | Sep 01 10:31:07 PM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278599392 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.278599392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.4206763856 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 9155947413 ps |
| CPU time | 2715.57 seconds |
| Started | Sep 01 10:32:26 PM UTC 24 |
| Finished | Sep 01 11:18:11 PM UTC 24 |
| Peak memory | 386996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420676385 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.4206763856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3351220818 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 918327938 ps |
| CPU time | 39.69 seconds |
| Started | Sep 01 10:32:23 PM UTC 24 |
| Finished | Sep 01 10:33:04 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351220818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3351220818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.172631392 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 28999034754 ps |
| CPU time | 343.42 seconds |
| Started | Sep 01 10:31:08 PM UTC 24 |
| Finished | Sep 01 10:36:56 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172631392 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.172631392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.319615866 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 616295169 ps |
| CPU time | 114.56 seconds |
| Started | Sep 01 10:31:39 PM UTC 24 |
| Finished | Sep 01 10:33:35 PM UTC 24 |
| Peak memory | 380976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 319615866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_th roughput_w_partial_write.319615866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2888156936 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2589268406 ps |
| CPU time | 770.84 seconds |
| Started | Sep 01 10:33:27 PM UTC 24 |
| Finished | Sep 01 10:46:28 PM UTC 24 |
| Peak memory | 382824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888156936 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during _key_req.2888156936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1100347914 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 36798885 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 10:33:57 PM UTC 24 |
| Finished | Sep 01 10:33:59 PM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100347914 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1100347914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.315055868 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 4901936032 ps |
| CPU time | 26.81 seconds |
| Started | Sep 01 10:32:35 PM UTC 24 |
| Finished | Sep 01 10:33:03 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315055868 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.315055868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.1450422547 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 11789867382 ps |
| CPU time | 960.52 seconds |
| Started | Sep 01 10:33:31 PM UTC 24 |
| Finished | Sep 01 10:49:43 PM UTC 24 |
| Peak memory | 382828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450422547 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.1450422547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1291631218 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3382637396 ps |
| CPU time | 11.36 seconds |
| Started | Sep 01 10:33:26 PM UTC 24 |
| Finished | Sep 01 10:33:39 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291631218 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.1291631218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.446312444 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 246256886 ps |
| CPU time | 91.1 seconds |
| Started | Sep 01 10:33:05 PM UTC 24 |
| Finished | Sep 01 10:34:38 PM UTC 24 |
| Peak memory | 362288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 46312444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max _throughput.446312444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3416215152 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 67637977 ps |
| CPU time | 5.82 seconds |
| Started | Sep 01 10:33:50 PM UTC 24 |
| Finished | Sep 01 10:33:57 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416215152 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.3416215152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.986030069 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 693816535 ps |
| CPU time | 10.43 seconds |
| Started | Sep 01 10:33:42 PM UTC 24 |
| Finished | Sep 01 10:33:54 PM UTC 24 |
| Peak memory | 224076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986030069 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.986030069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1490385898 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 15115973879 ps |
| CPU time | 1485.26 seconds |
| Started | Sep 01 10:32:33 PM UTC 24 |
| Finished | Sep 01 10:57:34 PM UTC 24 |
| Peak memory | 386988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490385898 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.1490385898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2468939731 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 287509661 ps |
| CPU time | 21.79 seconds |
| Started | Sep 01 10:33:03 PM UTC 24 |
| Finished | Sep 01 10:33:26 PM UTC 24 |
| Peak memory | 276348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468939731 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.2468939731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.4005955406 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 16965804235 ps |
| CPU time | 557.29 seconds |
| Started | Sep 01 10:33:05 PM UTC 24 |
| Finished | Sep 01 10:42:29 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005955406 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acc ess_b2b.4005955406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1351503205 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 32890075 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 10:33:39 PM UTC 24 |
| Finished | Sep 01 10:33:41 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351503205 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1351503205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.1342322645 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 7088484548 ps |
| CPU time | 189.81 seconds |
| Started | Sep 01 10:33:36 PM UTC 24 |
| Finished | Sep 01 10:36:49 PM UTC 24 |
| Peak memory | 276408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342322645 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1342322645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.3784889147 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 40840032 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 10:32:31 PM UTC 24 |
| Finished | Sep 01 10:32:35 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784889147 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3784889147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.4890105 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 41079254255 ps |
| CPU time | 2113.7 seconds |
| Started | Sep 01 10:33:55 PM UTC 24 |
| Finished | Sep 01 11:09:31 PM UTC 24 |
| Peak memory | 385196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4890105 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.4890105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3135592144 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2800588195 ps |
| CPU time | 294.89 seconds |
| Started | Sep 01 10:32:50 PM UTC 24 |
| Finished | Sep 01 10:37:49 PM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135592144 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.3135592144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3884045252 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1066438860 ps |
| CPU time | 91.34 seconds |
| Started | Sep 01 10:33:07 PM UTC 24 |
| Finished | Sep 01 10:34:40 PM UTC 24 |
| Peak memory | 380780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3884045252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t hroughput_w_partial_write.3884045252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3799415367 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4068437823 ps |
| CPU time | 936.12 seconds |
| Started | Sep 01 10:34:54 PM UTC 24 |
| Finished | Sep 01 10:50:40 PM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799415367 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.3799415367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.427872829 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 16908917 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 10:35:31 PM UTC 24 |
| Finished | Sep 01 10:35:33 PM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427872829 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.427872829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.222912176 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 655925883 ps |
| CPU time | 44.17 seconds |
| Started | Sep 01 10:34:29 PM UTC 24 |
| Finished | Sep 01 10:35:15 PM UTC 24 |
| Peak memory | 213780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222912176 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.222912176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3998680583 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2526499517 ps |
| CPU time | 656.19 seconds |
| Started | Sep 01 10:35:03 PM UTC 24 |
| Finished | Sep 01 10:46:07 PM UTC 24 |
| Peak memory | 381112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998680583 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3998680583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.4049870899 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1554454964 ps |
| CPU time | 7.83 seconds |
| Started | Sep 01 10:34:53 PM UTC 24 |
| Finished | Sep 01 10:35:02 PM UTC 24 |
| Peak memory | 214200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049870899 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.4049870899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.4217524295 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 149458995 ps |
| CPU time | 44.67 seconds |
| Started | Sep 01 10:34:41 PM UTC 24 |
| Finished | Sep 01 10:35:27 PM UTC 24 |
| Peak memory | 317616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 217524295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma x_throughput.4217524295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1403082358 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 395777997 ps |
| CPU time | 8.53 seconds |
| Started | Sep 01 10:35:21 PM UTC 24 |
| Finished | Sep 01 10:35:30 PM UTC 24 |
| Peak memory | 224288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403082358 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.1403082358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3117908901 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 363254633 ps |
| CPU time | 12.34 seconds |
| Started | Sep 01 10:35:20 PM UTC 24 |
| Finished | Sep 01 10:35:33 PM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117908901 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.3117908901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1383426065 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 188692919062 ps |
| CPU time | 1820.72 seconds |
| Started | Sep 01 10:34:12 PM UTC 24 |
| Finished | Sep 01 11:04:53 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383426065 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.1383426065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.842291020 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1194040727 ps |
| CPU time | 14.09 seconds |
| Started | Sep 01 10:34:38 PM UTC 24 |
| Finished | Sep 01 10:34:53 PM UTC 24 |
| Peak memory | 213728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842291020 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.842291020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1524710973 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 71431574810 ps |
| CPU time | 526.58 seconds |
| Started | Sep 01 10:34:39 PM UTC 24 |
| Finished | Sep 01 10:43:33 PM UTC 24 |
| Peak memory | 214044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524710973 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc ess_b2b.1524710973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3276500212 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 28748924 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 10:35:17 PM UTC 24 |
| Finished | Sep 01 10:35:19 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276500212 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3276500212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.2745455629 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 67978765642 ps |
| CPU time | 1708.36 seconds |
| Started | Sep 01 10:35:06 PM UTC 24 |
| Finished | Sep 01 11:03:53 PM UTC 24 |
| Peak memory | 385076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745455629 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2745455629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.61370040 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 889552524 ps |
| CPU time | 10.27 seconds |
| Started | Sep 01 10:34:00 PM UTC 24 |
| Finished | Sep 01 10:34:11 PM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61370040 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.61370040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.559980429 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 87024476653 ps |
| CPU time | 3488 seconds |
| Started | Sep 01 10:35:31 PM UTC 24 |
| Finished | Sep 01 11:34:18 PM UTC 24 |
| Peak memory | 388792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559980429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.559980429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1419715878 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 12744213636 ps |
| CPU time | 345.26 seconds |
| Started | Sep 01 10:34:37 PM UTC 24 |
| Finished | Sep 01 10:40:27 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419715878 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.1419715878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1216649363 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 577199455 ps |
| CPU time | 55.18 seconds |
| Started | Sep 01 10:34:45 PM UTC 24 |
| Finished | Sep 01 10:35:42 PM UTC 24 |
| Peak memory | 356204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1216649363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t hroughput_w_partial_write.1216649363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.96419727 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 17170497432 ps |
| CPU time | 1537.56 seconds |
| Started | Sep 01 09:48:56 PM UTC 24 |
| Finished | Sep 01 10:14:53 PM UTC 24 |
| Peak memory | 386984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96419727 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_ke y_req.96419727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.3772689273 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 13765424 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 09:49:52 PM UTC 24 |
| Finished | Sep 01 09:49:54 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772689273 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3772689273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3617291339 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3542933369 ps |
| CPU time | 109.49 seconds |
| Started | Sep 01 09:48:14 PM UTC 24 |
| Finished | Sep 01 09:50:05 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617291339 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3617291339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.3243823457 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 7825247836 ps |
| CPU time | 579.39 seconds |
| Started | Sep 01 09:48:59 PM UTC 24 |
| Finished | Sep 01 09:58:45 PM UTC 24 |
| Peak memory | 385272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243823457 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.3243823457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3695124294 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 533089500 ps |
| CPU time | 4.58 seconds |
| Started | Sep 01 09:48:50 PM UTC 24 |
| Finished | Sep 01 09:48:56 PM UTC 24 |
| Peak memory | 228208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695124294 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.3695124294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1472877947 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 139605104 ps |
| CPU time | 109.19 seconds |
| Started | Sep 01 09:48:30 PM UTC 24 |
| Finished | Sep 01 09:50:22 PM UTC 24 |
| Peak memory | 381032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 472877947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max _throughput.1472877947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2051868153 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 165936420 ps |
| CPU time | 3.83 seconds |
| Started | Sep 01 09:49:21 PM UTC 24 |
| Finished | Sep 01 09:49:26 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051868153 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.2051868153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1424075225 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1358857412 ps |
| CPU time | 18.55 seconds |
| Started | Sep 01 09:49:17 PM UTC 24 |
| Finished | Sep 01 09:49:36 PM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424075225 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.1424075225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.3738109054 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 19614030263 ps |
| CPU time | 1428.89 seconds |
| Started | Sep 01 09:47:59 PM UTC 24 |
| Finished | Sep 01 10:12:05 PM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738109054 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.3738109054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.890847926 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 346938123 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 09:48:23 PM UTC 24 |
| Finished | Sep 01 09:48:29 PM UTC 24 |
| Peak memory | 222680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890847926 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.890847926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2523947080 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 11067867214 ps |
| CPU time | 259.3 seconds |
| Started | Sep 01 09:48:23 PM UTC 24 |
| Finished | Sep 01 09:52:46 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523947080 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce ss_b2b.2523947080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.677521446 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 32005151 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:49:14 PM UTC 24 |
| Finished | Sep 01 09:49:16 PM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677521446 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.677521446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.288807376 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15014896245 ps |
| CPU time | 633.55 seconds |
| Started | Sep 01 09:49:08 PM UTC 24 |
| Finished | Sep 01 09:59:51 PM UTC 24 |
| Peak memory | 383116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288807376 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.288807376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1800655688 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 244343570 ps |
| CPU time | 4.63 seconds |
| Started | Sep 01 09:49:48 PM UTC 24 |
| Finished | Sep 01 09:49:54 PM UTC 24 |
| Peak memory | 250024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800655688 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.1800655688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3607323900 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 723284883 ps |
| CPU time | 20.06 seconds |
| Started | Sep 01 09:47:58 PM UTC 24 |
| Finished | Sep 01 09:48:20 PM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607323900 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3607323900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2671179524 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 119412432020 ps |
| CPU time | 2119 seconds |
| Started | Sep 01 09:49:37 PM UTC 24 |
| Finished | Sep 01 10:25:18 PM UTC 24 |
| Peak memory | 395120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267117952 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.2671179524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1329442383 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8346829160 ps |
| CPU time | 191.23 seconds |
| Started | Sep 01 09:49:27 PM UTC 24 |
| Finished | Sep 01 09:52:41 PM UTC 24 |
| Peak memory | 391152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329442383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1329442383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.682727106 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2140282133 ps |
| CPU time | 247.78 seconds |
| Started | Sep 01 09:48:21 PM UTC 24 |
| Finished | Sep 01 09:52:32 PM UTC 24 |
| Peak memory | 214132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682727106 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.682727106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3986297061 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 246233956 ps |
| CPU time | 36.96 seconds |
| Started | Sep 01 09:48:34 PM UTC 24 |
| Finished | Sep 01 09:49:13 PM UTC 24 |
| Peak memory | 319264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3986297061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th roughput_w_partial_write.3986297061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1104912578 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 706410308 ps |
| CPU time | 78.89 seconds |
| Started | Sep 01 10:36:42 PM UTC 24 |
| Finished | Sep 01 10:38:02 PM UTC 24 |
| Peak memory | 325480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104912578 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during _key_req.1104912578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2416299802 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 10931135 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 10:36:50 PM UTC 24 |
| Finished | Sep 01 10:36:52 PM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416299802 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.2416299802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.3684339029 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 772729531 ps |
| CPU time | 61.96 seconds |
| Started | Sep 01 10:35:43 PM UTC 24 |
| Finished | Sep 01 10:36:47 PM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684339029 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.3684339029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.1303062005 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3246793820 ps |
| CPU time | 127.44 seconds |
| Started | Sep 01 10:36:45 PM UTC 24 |
| Finished | Sep 01 10:38:55 PM UTC 24 |
| Peak memory | 374980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303062005 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.1303062005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.277386591 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1463841389 ps |
| CPU time | 9.3 seconds |
| Started | Sep 01 10:36:33 PM UTC 24 |
| Finished | Sep 01 10:36:44 PM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277386591 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.277386591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3033641937 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 230786950 ps |
| CPU time | 13.91 seconds |
| Started | Sep 01 10:36:10 PM UTC 24 |
| Finished | Sep 01 10:36:25 PM UTC 24 |
| Peak memory | 263976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 033641937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma x_throughput.3033641937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1688265525 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 152327170 ps |
| CPU time | 6.74 seconds |
| Started | Sep 01 10:36:47 PM UTC 24 |
| Finished | Sep 01 10:36:55 PM UTC 24 |
| Peak memory | 224056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688265525 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.1688265525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1025274644 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 4366294439 ps |
| CPU time | 16.2 seconds |
| Started | Sep 01 10:36:46 PM UTC 24 |
| Finished | Sep 01 10:37:04 PM UTC 24 |
| Peak memory | 224204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025274644 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.1025274644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2478370619 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 10265486365 ps |
| CPU time | 966.48 seconds |
| Started | Sep 01 10:35:34 PM UTC 24 |
| Finished | Sep 01 10:51:52 PM UTC 24 |
| Peak memory | 386912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478370619 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2478370619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2587522795 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4882471219 ps |
| CPU time | 56.91 seconds |
| Started | Sep 01 10:35:46 PM UTC 24 |
| Finished | Sep 01 10:36:44 PM UTC 24 |
| Peak memory | 341884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587522795 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.2587522795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.4139434646 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 61891596654 ps |
| CPU time | 381.94 seconds |
| Started | Sep 01 10:35:50 PM UTC 24 |
| Finished | Sep 01 10:42:17 PM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139434646 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acc ess_b2b.4139434646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1476335051 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 213990844 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 10:36:46 PM UTC 24 |
| Finished | Sep 01 10:36:48 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476335051 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1476335051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.42444594 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 11552707890 ps |
| CPU time | 624.18 seconds |
| Started | Sep 01 10:36:45 PM UTC 24 |
| Finished | Sep 01 10:47:17 PM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42444594 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.42444594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.857733844 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 669210666 ps |
| CPU time | 109.36 seconds |
| Started | Sep 01 10:35:34 PM UTC 24 |
| Finished | Sep 01 10:37:26 PM UTC 24 |
| Peak memory | 381044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857733844 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.857733844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1845748433 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 133066424966 ps |
| CPU time | 2686.48 seconds |
| Started | Sep 01 10:36:49 PM UTC 24 |
| Finished | Sep 01 11:22:05 PM UTC 24 |
| Peak memory | 395184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184574843 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.1845748433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2956922934 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 226865186 ps |
| CPU time | 10.81 seconds |
| Started | Sep 01 10:36:48 PM UTC 24 |
| Finished | Sep 01 10:37:00 PM UTC 24 |
| Peak memory | 231264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956922934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2956922934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.445567698 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 8966415616 ps |
| CPU time | 335.5 seconds |
| Started | Sep 01 10:35:45 PM UTC 24 |
| Finished | Sep 01 10:41:25 PM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445567698 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.445567698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.425025106 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1089014427 ps |
| CPU time | 24.69 seconds |
| Started | Sep 01 10:36:26 PM UTC 24 |
| Finished | Sep 01 10:36:52 PM UTC 24 |
| Peak memory | 297008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 425025106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_th roughput_w_partial_write.425025106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.11960997 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 9847379926 ps |
| CPU time | 1257.67 seconds |
| Started | Sep 01 10:37:16 PM UTC 24 |
| Finished | Sep 01 10:58:28 PM UTC 24 |
| Peak memory | 386908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11960997 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during_k ey_req.11960997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2628229918 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 52057491 ps |
| CPU time | 1 seconds |
| Started | Sep 01 10:37:28 PM UTC 24 |
| Finished | Sep 01 10:37:30 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628229918 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2628229918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.480471712 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1210199973 ps |
| CPU time | 66.21 seconds |
| Started | Sep 01 10:36:54 PM UTC 24 |
| Finished | Sep 01 10:38:02 PM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480471712 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.480471712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.3601540905 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 12290217827 ps |
| CPU time | 949.29 seconds |
| Started | Sep 01 10:37:20 PM UTC 24 |
| Finished | Sep 01 10:53:20 PM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601540905 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.3601540905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2323642577 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 597535861 ps |
| CPU time | 11.27 seconds |
| Started | Sep 01 10:37:11 PM UTC 24 |
| Finished | Sep 01 10:37:24 PM UTC 24 |
| Peak memory | 228144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323642577 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.2323642577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2463377757 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 142786813 ps |
| CPU time | 13.13 seconds |
| Started | Sep 01 10:37:01 PM UTC 24 |
| Finished | Sep 01 10:37:15 PM UTC 24 |
| Peak memory | 270192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 463377757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma x_throughput.2463377757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1500761660 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 366339657 ps |
| CPU time | 7.76 seconds |
| Started | Sep 01 10:37:25 PM UTC 24 |
| Finished | Sep 01 10:37:34 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500761660 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1500761660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1683288992 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 136507092 ps |
| CPU time | 11.66 seconds |
| Started | Sep 01 10:37:25 PM UTC 24 |
| Finished | Sep 01 10:37:38 PM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683288992 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.1683288992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2572937603 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2737959382 ps |
| CPU time | 869.32 seconds |
| Started | Sep 01 10:36:54 PM UTC 24 |
| Finished | Sep 01 10:51:32 PM UTC 24 |
| Peak memory | 387312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572937603 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.2572937603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1677296247 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 492216651 ps |
| CPU time | 21.08 seconds |
| Started | Sep 01 10:36:57 PM UTC 24 |
| Finished | Sep 01 10:37:19 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677296247 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1677296247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1781512999 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2842203560 ps |
| CPU time | 240.4 seconds |
| Started | Sep 01 10:37:01 PM UTC 24 |
| Finished | Sep 01 10:41:05 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781512999 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc ess_b2b.1781512999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2691100039 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 341197080 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 10:37:22 PM UTC 24 |
| Finished | Sep 01 10:37:24 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691100039 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2691100039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2542630170 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 76898957 ps |
| CPU time | 27.18 seconds |
| Started | Sep 01 10:36:51 PM UTC 24 |
| Finished | Sep 01 10:37:19 PM UTC 24 |
| Peak memory | 286484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542630170 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2542630170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1601450612 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 5971629815 ps |
| CPU time | 447.46 seconds |
| Started | Sep 01 10:37:27 PM UTC 24 |
| Finished | Sep 01 10:45:01 PM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160145061 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.1601450612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3797240708 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 5083082117 ps |
| CPU time | 167.03 seconds |
| Started | Sep 01 10:37:26 PM UTC 24 |
| Finished | Sep 01 10:40:16 PM UTC 24 |
| Peak memory | 375000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797240708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3797240708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.710500453 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 11991291372 ps |
| CPU time | 385.44 seconds |
| Started | Sep 01 10:36:56 PM UTC 24 |
| Finished | Sep 01 10:43:27 PM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710500453 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.710500453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1957554222 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 93844563 ps |
| CPU time | 21.24 seconds |
| Started | Sep 01 10:37:04 PM UTC 24 |
| Finished | Sep 01 10:37:27 PM UTC 24 |
| Peak memory | 286828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1957554222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t hroughput_w_partial_write.1957554222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2432169635 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4658818237 ps |
| CPU time | 396.42 seconds |
| Started | Sep 01 10:38:05 PM UTC 24 |
| Finished | Sep 01 10:44:46 PM UTC 24 |
| Peak memory | 384944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432169635 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.2432169635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.989229298 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 81904197 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 10:39:06 PM UTC 24 |
| Finished | Sep 01 10:39:08 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989229298 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.989229298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1648551470 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 9623152205 ps |
| CPU time | 83.82 seconds |
| Started | Sep 01 10:37:39 PM UTC 24 |
| Finished | Sep 01 10:39:05 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648551470 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.1648551470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3106847309 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 70205782951 ps |
| CPU time | 993.2 seconds |
| Started | Sep 01 10:38:13 PM UTC 24 |
| Finished | Sep 01 10:54:57 PM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106847309 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.3106847309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2763253275 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 317207294 ps |
| CPU time | 6.01 seconds |
| Started | Sep 01 10:38:05 PM UTC 24 |
| Finished | Sep 01 10:38:12 PM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763253275 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.2763253275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1776862236 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 301229880 ps |
| CPU time | 23.18 seconds |
| Started | Sep 01 10:38:02 PM UTC 24 |
| Finished | Sep 01 10:38:27 PM UTC 24 |
| Peak memory | 288628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 776862236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma x_throughput.1776862236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1386761219 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1306404521 ps |
| CPU time | 7.89 seconds |
| Started | Sep 01 10:38:51 PM UTC 24 |
| Finished | Sep 01 10:39:00 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386761219 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.1386761219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.93410544 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1467973954 ps |
| CPU time | 14.05 seconds |
| Started | Sep 01 10:38:35 PM UTC 24 |
| Finished | Sep 01 10:38:51 PM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93410544 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.93410544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.650501116 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2258855758 ps |
| CPU time | 734.07 seconds |
| Started | Sep 01 10:37:35 PM UTC 24 |
| Finished | Sep 01 10:49:59 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650501116 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.650501116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2569908952 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 279943600 ps |
| CPU time | 7.92 seconds |
| Started | Sep 01 10:37:55 PM UTC 24 |
| Finished | Sep 01 10:38:04 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569908952 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.2569908952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3324860854 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 29143637003 ps |
| CPU time | 684.51 seconds |
| Started | Sep 01 10:38:00 PM UTC 24 |
| Finished | Sep 01 10:49:33 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324860854 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acc ess_b2b.3324860854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2660841886 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 71870468 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 10:38:32 PM UTC 24 |
| Finished | Sep 01 10:38:34 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660841886 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2660841886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.1375730112 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 20305226294 ps |
| CPU time | 1063.74 seconds |
| Started | Sep 01 10:38:28 PM UTC 24 |
| Finished | Sep 01 10:56:24 PM UTC 24 |
| Peak memory | 382772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375730112 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1375730112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.4273571578 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 389301046 ps |
| CPU time | 57.85 seconds |
| Started | Sep 01 10:37:31 PM UTC 24 |
| Finished | Sep 01 10:38:31 PM UTC 24 |
| Peak memory | 329512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273571578 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.4273571578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1802556950 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 7000755203 ps |
| CPU time | 1067.04 seconds |
| Started | Sep 01 10:39:02 PM UTC 24 |
| Finished | Sep 01 10:57:01 PM UTC 24 |
| Peak memory | 393136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180255695 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.1802556950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.869481912 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 630572981 ps |
| CPU time | 152.1 seconds |
| Started | Sep 01 10:38:56 PM UTC 24 |
| Finished | Sep 01 10:41:30 PM UTC 24 |
| Peak memory | 386876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869481912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.869481912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2597348061 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 33973957559 ps |
| CPU time | 288.29 seconds |
| Started | Sep 01 10:37:50 PM UTC 24 |
| Finished | Sep 01 10:42:43 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597348061 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.2597348061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1626886654 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2363648124 ps |
| CPU time | 61.54 seconds |
| Started | Sep 01 10:38:03 PM UTC 24 |
| Finished | Sep 01 10:39:07 PM UTC 24 |
| Peak memory | 339884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1626886654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t hroughput_w_partial_write.1626886654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1946198949 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1616476948 ps |
| CPU time | 252.18 seconds |
| Started | Sep 01 10:40:19 PM UTC 24 |
| Finished | Sep 01 10:44:35 PM UTC 24 |
| Peak memory | 376680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946198949 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during _key_req.1946198949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1506618641 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 12884084 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 10:40:34 PM UTC 24 |
| Finished | Sep 01 10:40:36 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506618641 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1506618641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2945115695 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3570867382 ps |
| CPU time | 33.21 seconds |
| Started | Sep 01 10:39:11 PM UTC 24 |
| Finished | Sep 01 10:39:46 PM UTC 24 |
| Peak memory | 213976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945115695 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.2945115695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.122031264 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 61281889791 ps |
| CPU time | 2030.53 seconds |
| Started | Sep 01 10:40:22 PM UTC 24 |
| Finished | Sep 01 11:14:35 PM UTC 24 |
| Peak memory | 387248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122031264 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.122031264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1521128885 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1846954956 ps |
| CPU time | 3.58 seconds |
| Started | Sep 01 10:40:17 PM UTC 24 |
| Finished | Sep 01 10:40:22 PM UTC 24 |
| Peak memory | 214004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521128885 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.1521128885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3078425964 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 343510620 ps |
| CPU time | 29.91 seconds |
| Started | Sep 01 10:39:47 PM UTC 24 |
| Finished | Sep 01 10:40:18 PM UTC 24 |
| Peak memory | 298860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 078425964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma x_throughput.3078425964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3811349926 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 190173293 ps |
| CPU time | 4.23 seconds |
| Started | Sep 01 10:40:28 PM UTC 24 |
| Finished | Sep 01 10:40:33 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811349926 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.3811349926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1821152179 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 146327722 ps |
| CPU time | 5.2 seconds |
| Started | Sep 01 10:40:28 PM UTC 24 |
| Finished | Sep 01 10:40:34 PM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821152179 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.1821152179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1221357283 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 516391972 ps |
| CPU time | 72.18 seconds |
| Started | Sep 01 10:39:09 PM UTC 24 |
| Finished | Sep 01 10:40:23 PM UTC 24 |
| Peak memory | 335724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221357283 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.1221357283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1296328467 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2060361712 ps |
| CPU time | 24.12 seconds |
| Started | Sep 01 10:39:27 PM UTC 24 |
| Finished | Sep 01 10:39:53 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296328467 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1296328467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3319496203 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 4182536991 ps |
| CPU time | 353.39 seconds |
| Started | Sep 01 10:39:30 PM UTC 24 |
| Finished | Sep 01 10:45:28 PM UTC 24 |
| Peak memory | 213960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319496203 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc ess_b2b.3319496203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3456249883 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 327748103 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 10:40:25 PM UTC 24 |
| Finished | Sep 01 10:40:27 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456249883 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3456249883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2167832218 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 64944629322 ps |
| CPU time | 1196.18 seconds |
| Started | Sep 01 10:40:23 PM UTC 24 |
| Finished | Sep 01 11:00:33 PM UTC 24 |
| Peak memory | 387232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167832218 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2167832218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1177769683 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 137970221 ps |
| CPU time | 10.3 seconds |
| Started | Sep 01 10:39:08 PM UTC 24 |
| Finished | Sep 01 10:39:19 PM UTC 24 |
| Peak memory | 213732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177769683 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1177769683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.611014717 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 17479912682 ps |
| CPU time | 1089.42 seconds |
| Started | Sep 01 10:40:32 PM UTC 24 |
| Finished | Sep 01 10:58:54 PM UTC 24 |
| Peak memory | 387000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611014717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.611014717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3562577756 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 5621864758 ps |
| CPU time | 311.74 seconds |
| Started | Sep 01 10:39:20 PM UTC 24 |
| Finished | Sep 01 10:44:37 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562577756 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.3562577756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3754342870 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 211574763 ps |
| CPU time | 31.43 seconds |
| Started | Sep 01 10:39:54 PM UTC 24 |
| Finished | Sep 01 10:40:27 PM UTC 24 |
| Peak memory | 298856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3754342870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_t hroughput_w_partial_write.3754342870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1924073082 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 8018132185 ps |
| CPU time | 594.22 seconds |
| Started | Sep 01 10:41:29 PM UTC 24 |
| Finished | Sep 01 10:51:31 PM UTC 24 |
| Peak memory | 386980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924073082 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during _key_req.1924073082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.4189463240 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 32560325 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 10:41:54 PM UTC 24 |
| Finished | Sep 01 10:41:56 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189463240 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.4189463240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.3850044451 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1758725791 ps |
| CPU time | 53.13 seconds |
| Started | Sep 01 10:40:46 PM UTC 24 |
| Finished | Sep 01 10:41:41 PM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850044451 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.3850044451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3156477581 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 481913947 ps |
| CPU time | 264.25 seconds |
| Started | Sep 01 10:41:31 PM UTC 24 |
| Finished | Sep 01 10:46:00 PM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156477581 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.3156477581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2713927633 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 698032357 ps |
| CPU time | 16.09 seconds |
| Started | Sep 01 10:41:25 PM UTC 24 |
| Finished | Sep 01 10:41:43 PM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713927633 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.2713927633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.919222841 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 85630146 ps |
| CPU time | 22.01 seconds |
| Started | Sep 01 10:41:07 PM UTC 24 |
| Finished | Sep 01 10:41:30 PM UTC 24 |
| Peak memory | 286584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 19222841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_max _throughput.919222841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.3474493490 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 396199404 ps |
| CPU time | 4.59 seconds |
| Started | Sep 01 10:41:45 PM UTC 24 |
| Finished | Sep 01 10:41:51 PM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474493490 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.3474493490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1977903916 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1443184773 ps |
| CPU time | 11.45 seconds |
| Started | Sep 01 10:41:44 PM UTC 24 |
| Finished | Sep 01 10:41:56 PM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977903916 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.1977903916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2321685088 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3314061576 ps |
| CPU time | 148.42 seconds |
| Started | Sep 01 10:40:37 PM UTC 24 |
| Finished | Sep 01 10:43:09 PM UTC 24 |
| Peak memory | 364368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321685088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.2321685088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.885844493 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 646114936 ps |
| CPU time | 121.5 seconds |
| Started | Sep 01 10:40:50 PM UTC 24 |
| Finished | Sep 01 10:42:54 PM UTC 24 |
| Peak memory | 380732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885844493 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.885844493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2238368239 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 12459340858 ps |
| CPU time | 399.36 seconds |
| Started | Sep 01 10:41:06 PM UTC 24 |
| Finished | Sep 01 10:47:51 PM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238368239 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc ess_b2b.2238368239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3399876592 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 113026881 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 10:41:42 PM UTC 24 |
| Finished | Sep 01 10:41:44 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399876592 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3399876592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.1908160873 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 6709720402 ps |
| CPU time | 781.17 seconds |
| Started | Sep 01 10:41:32 PM UTC 24 |
| Finished | Sep 01 10:54:41 PM UTC 24 |
| Peak memory | 381108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908160873 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1908160873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.501896049 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 719505594 ps |
| CPU time | 8.61 seconds |
| Started | Sep 01 10:40:35 PM UTC 24 |
| Finished | Sep 01 10:40:46 PM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501896049 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.501896049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3756849954 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 281319616189 ps |
| CPU time | 5014.83 seconds |
| Started | Sep 01 10:41:51 PM UTC 24 |
| Finished | Sep 02 12:06:22 AM UTC 24 |
| Peak memory | 388656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375684995 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.3756849954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2125217184 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 266599891 ps |
| CPU time | 10.11 seconds |
| Started | Sep 01 10:41:47 PM UTC 24 |
| Finished | Sep 01 10:41:58 PM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125217184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2125217184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2513739505 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 14225847976 ps |
| CPU time | 399.43 seconds |
| Started | Sep 01 10:40:50 PM UTC 24 |
| Finished | Sep 01 10:47:35 PM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513739505 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.2513739505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3147667209 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 37705650 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 10:41:25 PM UTC 24 |
| Finished | Sep 01 10:41:28 PM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3147667209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t hroughput_w_partial_write.3147667209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.595063127 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 11330674225 ps |
| CPU time | 614.79 seconds |
| Started | Sep 01 10:42:36 PM UTC 24 |
| Finished | Sep 01 10:52:59 PM UTC 24 |
| Peak memory | 374608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595063127 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during_ key_req.595063127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1786911086 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 38437949 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 10:43:09 PM UTC 24 |
| Finished | Sep 01 10:43:11 PM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786911086 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1786911086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.380566657 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 7493842323 ps |
| CPU time | 90.7 seconds |
| Started | Sep 01 10:41:59 PM UTC 24 |
| Finished | Sep 01 10:43:31 PM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380566657 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.380566657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.3734170396 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 8739443428 ps |
| CPU time | 825.56 seconds |
| Started | Sep 01 10:42:39 PM UTC 24 |
| Finished | Sep 01 10:56:33 PM UTC 24 |
| Peak memory | 384960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734170396 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.3734170396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.624138386 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 485525567 ps |
| CPU time | 3.74 seconds |
| Started | Sep 01 10:42:30 PM UTC 24 |
| Finished | Sep 01 10:42:35 PM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624138386 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.624138386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2127372153 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 360157108 ps |
| CPU time | 25.43 seconds |
| Started | Sep 01 10:42:30 PM UTC 24 |
| Finished | Sep 01 10:42:57 PM UTC 24 |
| Peak memory | 305264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 127372153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma x_throughput.2127372153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.343425456 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 195371653 ps |
| CPU time | 4.74 seconds |
| Started | Sep 01 10:42:58 PM UTC 24 |
| Finished | Sep 01 10:43:04 PM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343425456 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.343425456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3966345797 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 96973476 ps |
| CPU time | 7.66 seconds |
| Started | Sep 01 10:42:58 PM UTC 24 |
| Finished | Sep 01 10:43:07 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966345797 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.3966345797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3759412974 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 48762908764 ps |
| CPU time | 1055.61 seconds |
| Started | Sep 01 10:41:58 PM UTC 24 |
| Finished | Sep 01 10:59:45 PM UTC 24 |
| Peak memory | 380804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759412974 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3759412974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1298560910 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 116190681 ps |
| CPU time | 5.29 seconds |
| Started | Sep 01 10:42:18 PM UTC 24 |
| Finished | Sep 01 10:42:24 PM UTC 24 |
| Peak memory | 227132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298560910 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.1298560910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.172235383 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 87555036841 ps |
| CPU time | 591.09 seconds |
| Started | Sep 01 10:42:25 PM UTC 24 |
| Finished | Sep 01 10:52:24 PM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172235383 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acce ss_b2b.172235383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.921621013 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 33855292 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 10:42:55 PM UTC 24 |
| Finished | Sep 01 10:42:57 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921621013 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.921621013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.2188937438 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 13336557884 ps |
| CPU time | 579.91 seconds |
| Started | Sep 01 10:42:44 PM UTC 24 |
| Finished | Sep 01 10:52:31 PM UTC 24 |
| Peak memory | 341868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188937438 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2188937438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.3940658148 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 52842864 ps |
| CPU time | 4.34 seconds |
| Started | Sep 01 10:41:57 PM UTC 24 |
| Finished | Sep 01 10:42:03 PM UTC 24 |
| Peak memory | 229136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940658148 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3940658148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.178582826 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 11086220084 ps |
| CPU time | 2965.2 seconds |
| Started | Sep 01 10:43:07 PM UTC 24 |
| Finished | Sep 01 11:33:04 PM UTC 24 |
| Peak memory | 388788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178582826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.178582826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2771920419 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 802237949 ps |
| CPU time | 10.87 seconds |
| Started | Sep 01 10:43:05 PM UTC 24 |
| Finished | Sep 01 10:43:17 PM UTC 24 |
| Peak memory | 224156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771920419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2771920419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3391357100 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 6889950022 ps |
| CPU time | 204.89 seconds |
| Started | Sep 01 10:42:04 PM UTC 24 |
| Finished | Sep 01 10:45:32 PM UTC 24 |
| Peak memory | 213956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391357100 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.3391357100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1556394994 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 279843896 ps |
| CPU time | 6.16 seconds |
| Started | Sep 01 10:42:30 PM UTC 24 |
| Finished | Sep 01 10:42:38 PM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1556394994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t hroughput_w_partial_write.1556394994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.858152517 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4180007085 ps |
| CPU time | 389.87 seconds |
| Started | Sep 01 10:44:03 PM UTC 24 |
| Finished | Sep 01 10:50:38 PM UTC 24 |
| Peak memory | 350380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858152517 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during_ key_req.858152517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.4051076677 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 25426782 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 10:44:48 PM UTC 24 |
| Finished | Sep 01 10:44:50 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051076677 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.4051076677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.1453595825 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 7567250234 ps |
| CPU time | 33.99 seconds |
| Started | Sep 01 10:43:28 PM UTC 24 |
| Finished | Sep 01 10:44:03 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453595825 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.1453595825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1794625796 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 7255685097 ps |
| CPU time | 645.37 seconds |
| Started | Sep 01 10:44:18 PM UTC 24 |
| Finished | Sep 01 10:55:10 PM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794625796 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.1794625796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1793907515 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1813472999 ps |
| CPU time | 17.2 seconds |
| Started | Sep 01 10:44:02 PM UTC 24 |
| Finished | Sep 01 10:44:21 PM UTC 24 |
| Peak memory | 213832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793907515 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.1793907515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1170280953 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 73238558 ps |
| CPU time | 2.95 seconds |
| Started | Sep 01 10:43:43 PM UTC 24 |
| Finished | Sep 01 10:43:48 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 170280953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ma x_throughput.1170280953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2152451900 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 161850398 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 10:44:39 PM UTC 24 |
| Finished | Sep 01 10:44:44 PM UTC 24 |
| Peak memory | 224296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152451900 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.2152451900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2443231362 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1063404313 ps |
| CPU time | 6.73 seconds |
| Started | Sep 01 10:44:38 PM UTC 24 |
| Finished | Sep 01 10:44:46 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443231362 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.2443231362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1258017955 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 282737364 ps |
| CPU time | 42.79 seconds |
| Started | Sep 01 10:43:33 PM UTC 24 |
| Finished | Sep 01 10:44:17 PM UTC 24 |
| Peak memory | 304936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258017955 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.1258017955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.684341946 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 10773914715 ps |
| CPU time | 432.33 seconds |
| Started | Sep 01 10:43:34 PM UTC 24 |
| Finished | Sep 01 10:50:52 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684341946 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acce ss_b2b.684341946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.176567706 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 28183736 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 10:44:36 PM UTC 24 |
| Finished | Sep 01 10:44:38 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176567706 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.176567706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.2520229619 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 9487471305 ps |
| CPU time | 1382.41 seconds |
| Started | Sep 01 10:44:22 PM UTC 24 |
| Finished | Sep 01 11:07:39 PM UTC 24 |
| Peak memory | 386924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520229619 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2520229619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.1360373877 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 637382904 ps |
| CPU time | 15.52 seconds |
| Started | Sep 01 10:43:12 PM UTC 24 |
| Finished | Sep 01 10:43:29 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360373877 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1360373877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1820116380 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 44924476123 ps |
| CPU time | 1974.16 seconds |
| Started | Sep 01 10:44:46 PM UTC 24 |
| Finished | Sep 01 11:18:03 PM UTC 24 |
| Peak memory | 368812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182011638 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.1820116380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4059418367 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 6089830162 ps |
| CPU time | 338.29 seconds |
| Started | Sep 01 10:44:45 PM UTC 24 |
| Finished | Sep 01 10:50:28 PM UTC 24 |
| Peak memory | 370928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059418367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.4059418367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.207788496 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2486094716 ps |
| CPU time | 299.98 seconds |
| Started | Sep 01 10:43:30 PM UTC 24 |
| Finished | Sep 01 10:48:34 PM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207788496 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.207788496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.4214415060 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 125169545 ps |
| CPU time | 11.17 seconds |
| Started | Sep 01 10:43:49 PM UTC 24 |
| Finished | Sep 01 10:44:02 PM UTC 24 |
| Peak memory | 250032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4214415060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t hroughput_w_partial_write.4214415060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1440740455 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1843086976 ps |
| CPU time | 472.13 seconds |
| Started | Sep 01 10:45:54 PM UTC 24 |
| Finished | Sep 01 10:53:52 PM UTC 24 |
| Peak memory | 382824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440740455 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during _key_req.1440740455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.822378169 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 16406568 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 10:46:25 PM UTC 24 |
| Finished | Sep 01 10:46:27 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822378169 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.822378169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2082343787 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 5834110230 ps |
| CPU time | 65.92 seconds |
| Started | Sep 01 10:45:16 PM UTC 24 |
| Finished | Sep 01 10:46:24 PM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082343787 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.2082343787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3744340627 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 24017058479 ps |
| CPU time | 1277.53 seconds |
| Started | Sep 01 10:46:00 PM UTC 24 |
| Finished | Sep 01 11:07:32 PM UTC 24 |
| Peak memory | 387320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744340627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.3744340627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.585717481 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1461305099 ps |
| CPU time | 7.86 seconds |
| Started | Sep 01 10:45:53 PM UTC 24 |
| Finished | Sep 01 10:46:02 PM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585717481 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.585717481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.596684512 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 87116189 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 10:45:49 PM UTC 24 |
| Finished | Sep 01 10:45:52 PM UTC 24 |
| Peak memory | 212624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 96684512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max _throughput.596684512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1142936657 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 59241922 ps |
| CPU time | 4.51 seconds |
| Started | Sep 01 10:46:08 PM UTC 24 |
| Finished | Sep 01 10:46:14 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142936657 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1142936657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1064087230 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2170574961 ps |
| CPU time | 15.33 seconds |
| Started | Sep 01 10:46:07 PM UTC 24 |
| Finished | Sep 01 10:46:24 PM UTC 24 |
| Peak memory | 224476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064087230 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.1064087230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3020424525 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 7685293214 ps |
| CPU time | 1036.05 seconds |
| Started | Sep 01 10:45:02 PM UTC 24 |
| Finished | Sep 01 11:02:30 PM UTC 24 |
| Peak memory | 385004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020424525 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.3020424525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1021901326 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4217452719 ps |
| CPU time | 28.24 seconds |
| Started | Sep 01 10:45:33 PM UTC 24 |
| Finished | Sep 01 10:46:03 PM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021901326 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.1021901326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1594313929 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 204637832430 ps |
| CPU time | 596.12 seconds |
| Started | Sep 01 10:45:48 PM UTC 24 |
| Finished | Sep 01 10:55:52 PM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594313929 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc ess_b2b.1594313929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2465839286 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 82147377 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 10:46:04 PM UTC 24 |
| Finished | Sep 01 10:46:06 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465839286 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2465839286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.323440876 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 12103503615 ps |
| CPU time | 353.78 seconds |
| Started | Sep 01 10:46:03 PM UTC 24 |
| Finished | Sep 01 10:52:02 PM UTC 24 |
| Peak memory | 381108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323440876 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.323440876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.16715126 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1033090811 ps |
| CPU time | 23.45 seconds |
| Started | Sep 01 10:44:51 PM UTC 24 |
| Finished | Sep 01 10:45:15 PM UTC 24 |
| Peak memory | 272192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16715126 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.16715126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.368690264 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 133944369216 ps |
| CPU time | 4075.31 seconds |
| Started | Sep 01 10:46:15 PM UTC 24 |
| Finished | Sep 01 11:54:55 PM UTC 24 |
| Peak memory | 388660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368690264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.368690264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3546147459 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 6819398999 ps |
| CPU time | 55.14 seconds |
| Started | Sep 01 10:46:08 PM UTC 24 |
| Finished | Sep 01 10:47:05 PM UTC 24 |
| Peak memory | 319396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546147459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3546147459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2430815337 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1065183322 ps |
| CPU time | 145.07 seconds |
| Started | Sep 01 10:45:29 PM UTC 24 |
| Finished | Sep 01 10:47:57 PM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430815337 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2430815337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.2865365931 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 272314817 ps |
| CPU time | 13.44 seconds |
| Started | Sep 01 10:45:53 PM UTC 24 |
| Finished | Sep 01 10:46:08 PM UTC 24 |
| Peak memory | 264168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2865365931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t hroughput_w_partial_write.2865365931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.800823176 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 7559813808 ps |
| CPU time | 1182.06 seconds |
| Started | Sep 01 10:47:18 PM UTC 24 |
| Finished | Sep 01 11:07:14 PM UTC 24 |
| Peak memory | 387200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800823176 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during_ key_req.800823176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3949920941 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 32870248 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 10:48:07 PM UTC 24 |
| Finished | Sep 01 10:48:09 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949920941 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3949920941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.1750915235 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 10102438345 ps |
| CPU time | 35.91 seconds |
| Started | Sep 01 10:46:29 PM UTC 24 |
| Finished | Sep 01 10:47:07 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750915235 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.1750915235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1116830750 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1007289812 ps |
| CPU time | 14.01 seconds |
| Started | Sep 01 10:47:08 PM UTC 24 |
| Finished | Sep 01 10:47:23 PM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116830750 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.1116830750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1599510916 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 658942068 ps |
| CPU time | 60.53 seconds |
| Started | Sep 01 10:46:56 PM UTC 24 |
| Finished | Sep 01 10:47:58 PM UTC 24 |
| Peak memory | 329516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 599510916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ma x_throughput.1599510916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.532224216 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 67351669 ps |
| CPU time | 7.1 seconds |
| Started | Sep 01 10:47:58 PM UTC 24 |
| Finished | Sep 01 10:48:06 PM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532224216 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.532224216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.1243141473 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 231469835 ps |
| CPU time | 8.56 seconds |
| Started | Sep 01 10:47:55 PM UTC 24 |
| Finished | Sep 01 10:48:04 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243141473 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.1243141473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1173415104 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 63152456309 ps |
| CPU time | 1351.17 seconds |
| Started | Sep 01 10:46:28 PM UTC 24 |
| Finished | Sep 01 11:09:14 PM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173415104 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1173415104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.729096953 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1651858145 ps |
| CPU time | 15.6 seconds |
| Started | Sep 01 10:46:38 PM UTC 24 |
| Finished | Sep 01 10:46:55 PM UTC 24 |
| Peak memory | 268156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729096953 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.729096953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2034212180 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 181383830969 ps |
| CPU time | 617.01 seconds |
| Started | Sep 01 10:46:52 PM UTC 24 |
| Finished | Sep 01 10:57:17 PM UTC 24 |
| Peak memory | 214152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034212180 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc ess_b2b.2034212180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2891391817 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 83133479 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 10:47:51 PM UTC 24 |
| Finished | Sep 01 10:47:54 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891391817 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2891391817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1212174919 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 48852728099 ps |
| CPU time | 949.03 seconds |
| Started | Sep 01 10:47:35 PM UTC 24 |
| Finished | Sep 01 11:03:36 PM UTC 24 |
| Peak memory | 378760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212174919 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1212174919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.1459956433 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4235415435 ps |
| CPU time | 24.05 seconds |
| Started | Sep 01 10:46:25 PM UTC 24 |
| Finished | Sep 01 10:46:50 PM UTC 24 |
| Peak memory | 214212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459956433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1459956433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2809478894 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 84421375680 ps |
| CPU time | 1676.34 seconds |
| Started | Sep 01 10:48:05 PM UTC 24 |
| Finished | Sep 01 11:16:19 PM UTC 24 |
| Peak memory | 387248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280947889 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.2809478894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.339258106 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 262539753 ps |
| CPU time | 11.93 seconds |
| Started | Sep 01 10:47:59 PM UTC 24 |
| Finished | Sep 01 10:48:12 PM UTC 24 |
| Peak memory | 224188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339258106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.339258106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.4106856501 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3579635699 ps |
| CPU time | 403.97 seconds |
| Started | Sep 01 10:46:38 PM UTC 24 |
| Finished | Sep 01 10:53:28 PM UTC 24 |
| Peak memory | 214092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106856501 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.4106856501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.715871536 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 438317492 ps |
| CPU time | 76.52 seconds |
| Started | Sep 01 10:47:06 PM UTC 24 |
| Finished | Sep 01 10:48:24 PM UTC 24 |
| Peak memory | 350064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 715871536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_th roughput_w_partial_write.715871536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3723074057 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 49194632492 ps |
| CPU time | 679.35 seconds |
| Started | Sep 01 10:49:05 PM UTC 24 |
| Finished | Sep 01 11:00:33 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723074057 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during _key_req.3723074057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1932288587 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 27447962 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 10:50:00 PM UTC 24 |
| Finished | Sep 01 10:50:02 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932288587 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1932288587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.1510549755 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 791641966 ps |
| CPU time | 60.28 seconds |
| Started | Sep 01 10:48:22 PM UTC 24 |
| Finished | Sep 01 10:49:24 PM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510549755 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.1510549755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2389065801 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 54992589208 ps |
| CPU time | 1220.8 seconds |
| Started | Sep 01 10:49:26 PM UTC 24 |
| Finished | Sep 01 11:10:00 PM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389065801 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.2389065801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.916097093 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 401308184 ps |
| CPU time | 8.14 seconds |
| Started | Sep 01 10:48:55 PM UTC 24 |
| Finished | Sep 01 10:49:05 PM UTC 24 |
| Peak memory | 224108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916097093 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.916097093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3568352252 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 252233690 ps |
| CPU time | 103.76 seconds |
| Started | Sep 01 10:48:35 PM UTC 24 |
| Finished | Sep 01 10:50:21 PM UTC 24 |
| Peak memory | 372596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 568352252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ma x_throughput.3568352252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.206594707 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 48169065 ps |
| CPU time | 4.02 seconds |
| Started | Sep 01 10:49:48 PM UTC 24 |
| Finished | Sep 01 10:49:53 PM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206594707 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.206594707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.2456060380 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 916726570 ps |
| CPU time | 12.97 seconds |
| Started | Sep 01 10:49:47 PM UTC 24 |
| Finished | Sep 01 10:50:01 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456060380 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.2456060380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.3648406526 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 165801642404 ps |
| CPU time | 1138.93 seconds |
| Started | Sep 01 10:48:12 PM UTC 24 |
| Finished | Sep 01 11:07:25 PM UTC 24 |
| Peak memory | 381100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648406526 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.3648406526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1501941378 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 590660624 ps |
| CPU time | 14.77 seconds |
| Started | Sep 01 10:48:25 PM UTC 24 |
| Finished | Sep 01 10:48:41 PM UTC 24 |
| Peak memory | 214044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501941378 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1501941378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.914173507 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 28979037029 ps |
| CPU time | 255.85 seconds |
| Started | Sep 01 10:48:35 PM UTC 24 |
| Finished | Sep 01 10:52:55 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914173507 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acce ss_b2b.914173507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2774412505 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 38796518 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 10:49:44 PM UTC 24 |
| Finished | Sep 01 10:49:46 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774412505 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2774412505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.3646923501 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 23330186763 ps |
| CPU time | 1256.85 seconds |
| Started | Sep 01 10:49:34 PM UTC 24 |
| Finished | Sep 01 11:10:44 PM UTC 24 |
| Peak memory | 386940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646923501 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3646923501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2131604808 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 190351710 ps |
| CPU time | 10.62 seconds |
| Started | Sep 01 10:48:10 PM UTC 24 |
| Finished | Sep 01 10:48:22 PM UTC 24 |
| Peak memory | 214068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131604808 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2131604808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3915278023 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 7715232461 ps |
| CPU time | 2093.09 seconds |
| Started | Sep 01 10:49:59 PM UTC 24 |
| Finished | Sep 01 11:25:16 PM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391527802 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.3915278023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1879246127 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 5984322360 ps |
| CPU time | 328.25 seconds |
| Started | Sep 01 10:48:25 PM UTC 24 |
| Finished | Sep 01 10:53:58 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879246127 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.1879246127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1007624539 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 173611132 ps |
| CPU time | 12.1 seconds |
| Started | Sep 01 10:48:41 PM UTC 24 |
| Finished | Sep 01 10:48:54 PM UTC 24 |
| Peak memory | 257804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1007624539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_t hroughput_w_partial_write.1007624539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.32951505 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6757812399 ps |
| CPU time | 900.06 seconds |
| Started | Sep 01 09:50:44 PM UTC 24 |
| Finished | Sep 01 10:05:56 PM UTC 24 |
| Peak memory | 387112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32951505 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_ke y_req.32951505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2862298374 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 86450597 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 09:51:26 PM UTC 24 |
| Finished | Sep 01 09:51:28 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862298374 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2862298374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2258007035 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 7769250503 ps |
| CPU time | 83.28 seconds |
| Started | Sep 01 09:49:56 PM UTC 24 |
| Finished | Sep 01 09:51:21 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258007035 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.2258007035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.3142642156 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 7610536757 ps |
| CPU time | 575.13 seconds |
| Started | Sep 01 09:50:52 PM UTC 24 |
| Finished | Sep 01 10:00:33 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142642156 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.3142642156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2098777243 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1695646548 ps |
| CPU time | 8.53 seconds |
| Started | Sep 01 09:50:41 PM UTC 24 |
| Finished | Sep 01 09:50:51 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098777243 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2098777243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1262018074 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 330133575 ps |
| CPU time | 41.64 seconds |
| Started | Sep 01 09:50:22 PM UTC 24 |
| Finished | Sep 01 09:51:05 PM UTC 24 |
| Peak memory | 305000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 262018074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max _throughput.1262018074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1317208462 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 555914504 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 09:51:10 PM UTC 24 |
| Finished | Sep 01 09:51:17 PM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317208462 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.1317208462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3041178551 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 100855517 ps |
| CPU time | 7.86 seconds |
| Started | Sep 01 09:51:08 PM UTC 24 |
| Finished | Sep 01 09:51:17 PM UTC 24 |
| Peak memory | 224312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041178551 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.3041178551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3907585873 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2844233470 ps |
| CPU time | 974.98 seconds |
| Started | Sep 01 09:49:55 PM UTC 24 |
| Finished | Sep 01 10:06:21 PM UTC 24 |
| Peak memory | 380844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907585873 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.3907585873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3177017117 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1442196819 ps |
| CPU time | 126.49 seconds |
| Started | Sep 01 09:50:07 PM UTC 24 |
| Finished | Sep 01 09:52:16 PM UTC 24 |
| Peak memory | 380988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177017117 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.3177017117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.1647898131 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 34844156788 ps |
| CPU time | 388.19 seconds |
| Started | Sep 01 09:50:16 PM UTC 24 |
| Finished | Sep 01 09:56:50 PM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647898131 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce ss_b2b.1647898131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.618134248 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 27228901 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:51:07 PM UTC 24 |
| Finished | Sep 01 09:51:09 PM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618134248 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.618134248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.2690627765 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 10848644603 ps |
| CPU time | 1032.61 seconds |
| Started | Sep 01 09:50:59 PM UTC 24 |
| Finished | Sep 01 10:08:22 PM UTC 24 |
| Peak memory | 384956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690627765 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2690627765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3837203802 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 186926444 ps |
| CPU time | 2.83 seconds |
| Started | Sep 01 09:51:21 PM UTC 24 |
| Finished | Sep 01 09:51:25 PM UTC 24 |
| Peak memory | 250200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837203802 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3837203802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.3548583701 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 86354092 ps |
| CPU time | 19.65 seconds |
| Started | Sep 01 09:49:54 PM UTC 24 |
| Finished | Sep 01 09:50:15 PM UTC 24 |
| Peak memory | 292648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548583701 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3548583701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.412707591 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 41873906052 ps |
| CPU time | 4309.31 seconds |
| Started | Sep 01 09:51:18 PM UTC 24 |
| Finished | Sep 01 11:03:52 PM UTC 24 |
| Peak memory | 387004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412707591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.412707591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.466906163 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 905632372 ps |
| CPU time | 30.63 seconds |
| Started | Sep 01 09:51:17 PM UTC 24 |
| Finished | Sep 01 09:51:49 PM UTC 24 |
| Peak memory | 231460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466906163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.466906163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.548359042 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 16266327924 ps |
| CPU time | 285.47 seconds |
| Started | Sep 01 09:49:58 PM UTC 24 |
| Finished | Sep 01 09:54:48 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548359042 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.548359042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.108994019 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 84063283 ps |
| CPU time | 3.21 seconds |
| Started | Sep 01 09:50:36 PM UTC 24 |
| Finished | Sep 01 09:50:41 PM UTC 24 |
| Peak memory | 230200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 108994019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_thr oughput_w_partial_write.108994019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3550452847 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 3693572449 ps |
| CPU time | 1216.68 seconds |
| Started | Sep 01 10:51:00 PM UTC 24 |
| Finished | Sep 01 11:11:30 PM UTC 24 |
| Peak memory | 384860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550452847 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during _key_req.3550452847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3091755869 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 38859558 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 10:51:33 PM UTC 24 |
| Finished | Sep 01 10:51:35 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091755869 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3091755869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1656503192 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2475705546 ps |
| CPU time | 45.53 seconds |
| Started | Sep 01 10:50:22 PM UTC 24 |
| Finished | Sep 01 10:51:09 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656503192 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.1656503192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3031127396 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1678187992 ps |
| CPU time | 232.68 seconds |
| Started | Sep 01 10:51:01 PM UTC 24 |
| Finished | Sep 01 10:54:57 PM UTC 24 |
| Peak memory | 372524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031127396 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.3031127396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1893332084 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 270427816 ps |
| CPU time | 4.96 seconds |
| Started | Sep 01 10:50:53 PM UTC 24 |
| Finished | Sep 01 10:50:59 PM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893332084 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.1893332084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.717515746 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 58117138 ps |
| CPU time | 9.45 seconds |
| Started | Sep 01 10:50:41 PM UTC 24 |
| Finished | Sep 01 10:50:52 PM UTC 24 |
| Peak memory | 249648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 17515746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max _throughput.717515746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.4179023202 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 68700464 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 10:51:23 PM UTC 24 |
| Finished | Sep 01 10:51:30 PM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179023202 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.4179023202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.4011030233 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 295676397 ps |
| CPU time | 8 seconds |
| Started | Sep 01 10:51:13 PM UTC 24 |
| Finished | Sep 01 10:51:22 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011030233 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.4011030233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2590726275 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 15091044683 ps |
| CPU time | 646.45 seconds |
| Started | Sep 01 10:50:04 PM UTC 24 |
| Finished | Sep 01 11:00:58 PM UTC 24 |
| Peak memory | 384864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590726275 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.2590726275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3832128320 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 965997710 ps |
| CPU time | 28.48 seconds |
| Started | Sep 01 10:50:29 PM UTC 24 |
| Finished | Sep 01 10:50:59 PM UTC 24 |
| Peak memory | 213832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832128320 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.3832128320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2932907313 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 34030501927 ps |
| CPU time | 276.99 seconds |
| Started | Sep 01 10:50:39 PM UTC 24 |
| Finished | Sep 01 10:55:20 PM UTC 24 |
| Peak memory | 214092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932907313 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc ess_b2b.2932907313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3506558026 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 29347918 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 10:51:10 PM UTC 24 |
| Finished | Sep 01 10:51:12 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506558026 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3506558026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1457078781 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1513566733 ps |
| CPU time | 339.65 seconds |
| Started | Sep 01 10:51:08 PM UTC 24 |
| Finished | Sep 01 10:56:52 PM UTC 24 |
| Peak memory | 362288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457078781 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1457078781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.4042259595 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1469651736 ps |
| CPU time | 24.52 seconds |
| Started | Sep 01 10:50:01 PM UTC 24 |
| Finished | Sep 01 10:50:27 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042259595 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.4042259595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.314972485 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2041442024 ps |
| CPU time | 140.75 seconds |
| Started | Sep 01 10:51:31 PM UTC 24 |
| Finished | Sep 01 10:53:55 PM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314972485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.314972485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1837809997 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 6519675731 ps |
| CPU time | 585.62 seconds |
| Started | Sep 01 10:51:31 PM UTC 24 |
| Finished | Sep 01 11:01:24 PM UTC 24 |
| Peak memory | 389360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837809997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1837809997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.3761324865 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 7497406303 ps |
| CPU time | 184.93 seconds |
| Started | Sep 01 10:50:28 PM UTC 24 |
| Finished | Sep 01 10:53:36 PM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761324865 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.3761324865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.898886755 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 142826558 ps |
| CPU time | 13.37 seconds |
| Started | Sep 01 10:50:52 PM UTC 24 |
| Finished | Sep 01 10:51:07 PM UTC 24 |
| Peak memory | 264300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 898886755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_th roughput_w_partial_write.898886755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1952012288 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 8759285250 ps |
| CPU time | 1250.25 seconds |
| Started | Sep 01 10:53:00 PM UTC 24 |
| Finished | Sep 01 11:14:05 PM UTC 24 |
| Peak memory | 377076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952012288 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during _key_req.1952012288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.107602055 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 17547841 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 10:53:45 PM UTC 24 |
| Finished | Sep 01 10:53:47 PM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107602055 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.107602055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.2371185284 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 14961855137 ps |
| CPU time | 48.71 seconds |
| Started | Sep 01 10:52:02 PM UTC 24 |
| Finished | Sep 01 10:52:53 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371185284 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.2371185284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.264668009 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 16712156385 ps |
| CPU time | 1534.98 seconds |
| Started | Sep 01 10:53:15 PM UTC 24 |
| Finished | Sep 01 11:19:07 PM UTC 24 |
| Peak memory | 384944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264668009 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.264668009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.225626216 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2658778157 ps |
| CPU time | 17 seconds |
| Started | Sep 01 10:52:56 PM UTC 24 |
| Finished | Sep 01 10:53:14 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225626216 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.225626216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.654577699 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 474011007 ps |
| CPU time | 60.15 seconds |
| Started | Sep 01 10:52:42 PM UTC 24 |
| Finished | Sep 01 10:53:43 PM UTC 24 |
| Peak memory | 339756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 54577699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_max _throughput.654577699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.1043587588 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 173062503 ps |
| CPU time | 5.64 seconds |
| Started | Sep 01 10:53:38 PM UTC 24 |
| Finished | Sep 01 10:53:44 PM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043587588 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.1043587588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2229204187 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2476571333 ps |
| CPU time | 7.71 seconds |
| Started | Sep 01 10:53:31 PM UTC 24 |
| Finished | Sep 01 10:53:40 PM UTC 24 |
| Peak memory | 224128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229204187 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.2229204187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1448336921 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 12222687209 ps |
| CPU time | 1510.53 seconds |
| Started | Sep 01 10:51:53 PM UTC 24 |
| Finished | Sep 01 11:17:20 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448336921 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.1448336921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2093588992 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 138031487 ps |
| CPU time | 5.82 seconds |
| Started | Sep 01 10:52:31 PM UTC 24 |
| Finished | Sep 01 10:52:38 PM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093588992 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.2093588992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3983084977 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 24942250294 ps |
| CPU time | 415.44 seconds |
| Started | Sep 01 10:52:40 PM UTC 24 |
| Finished | Sep 01 10:59:41 PM UTC 24 |
| Peak memory | 213936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983084977 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc ess_b2b.3983084977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1664022549 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 36135456 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 10:53:28 PM UTC 24 |
| Finished | Sep 01 10:53:30 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664022549 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1664022549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.2726894981 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4222945387 ps |
| CPU time | 186.85 seconds |
| Started | Sep 01 10:53:21 PM UTC 24 |
| Finished | Sep 01 10:56:31 PM UTC 24 |
| Peak memory | 364468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726894981 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2726894981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2859031116 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2638669441 ps |
| CPU time | 134.01 seconds |
| Started | Sep 01 10:51:36 PM UTC 24 |
| Finished | Sep 01 10:53:52 PM UTC 24 |
| Peak memory | 376956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859031116 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2859031116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2209809831 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 12579222142 ps |
| CPU time | 1056.62 seconds |
| Started | Sep 01 10:53:44 PM UTC 24 |
| Finished | Sep 01 11:11:32 PM UTC 24 |
| Peak memory | 380740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220980983 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.2209809831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.4218482617 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1303706405 ps |
| CPU time | 189.72 seconds |
| Started | Sep 01 10:53:42 PM UTC 24 |
| Finished | Sep 01 10:56:55 PM UTC 24 |
| Peak memory | 395108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218482617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.4218482617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3628587680 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3894091277 ps |
| CPU time | 197.49 seconds |
| Started | Sep 01 10:52:24 PM UTC 24 |
| Finished | Sep 01 10:55:45 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628587680 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.3628587680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.132614566 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 613432512 ps |
| CPU time | 119.16 seconds |
| Started | Sep 01 10:52:54 PM UTC 24 |
| Finished | Sep 01 10:54:55 PM UTC 24 |
| Peak memory | 381036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 132614566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_th roughput_w_partial_write.132614566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2755061238 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1428954548 ps |
| CPU time | 489.89 seconds |
| Started | Sep 01 10:54:42 PM UTC 24 |
| Finished | Sep 01 11:02:58 PM UTC 24 |
| Peak memory | 387216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755061238 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during _key_req.2755061238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.939688772 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 37001968 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 10:55:08 PM UTC 24 |
| Finished | Sep 01 10:55:10 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939688772 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.939688772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3721252675 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3545301025 ps |
| CPU time | 97.28 seconds |
| Started | Sep 01 10:53:53 PM UTC 24 |
| Finished | Sep 01 10:55:33 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721252675 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.3721252675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3719668094 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 10129344368 ps |
| CPU time | 726.27 seconds |
| Started | Sep 01 10:54:44 PM UTC 24 |
| Finished | Sep 01 11:06:59 PM UTC 24 |
| Peak memory | 385208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719668094 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.3719668094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2258302464 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 987269324 ps |
| CPU time | 7.98 seconds |
| Started | Sep 01 10:54:34 PM UTC 24 |
| Finished | Sep 01 10:54:43 PM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258302464 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.2258302464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.285141181 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 210213078 ps |
| CPU time | 10.86 seconds |
| Started | Sep 01 10:54:12 PM UTC 24 |
| Finished | Sep 01 10:54:24 PM UTC 24 |
| Peak memory | 249716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 85141181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_max _throughput.285141181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.125889424 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 601312972 ps |
| CPU time | 7.23 seconds |
| Started | Sep 01 10:54:59 PM UTC 24 |
| Finished | Sep 01 10:55:07 PM UTC 24 |
| Peak memory | 224004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125889424 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.125889424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.616519037 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 831719402 ps |
| CPU time | 14.2 seconds |
| Started | Sep 01 10:54:58 PM UTC 24 |
| Finished | Sep 01 10:55:13 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616519037 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.616519037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1922414824 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 13749846506 ps |
| CPU time | 1014.99 seconds |
| Started | Sep 01 10:53:53 PM UTC 24 |
| Finished | Sep 01 11:11:00 PM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922414824 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.1922414824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1421189518 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 676521063 ps |
| CPU time | 57.79 seconds |
| Started | Sep 01 10:53:58 PM UTC 24 |
| Finished | Sep 01 10:54:58 PM UTC 24 |
| Peak memory | 329592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421189518 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.1421189518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.863827114 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 17504002448 ps |
| CPU time | 647.8 seconds |
| Started | Sep 01 10:54:04 PM UTC 24 |
| Finished | Sep 01 11:05:00 PM UTC 24 |
| Peak memory | 213960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863827114 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acce ss_b2b.863827114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1851513593 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 90255123 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 10:54:58 PM UTC 24 |
| Finished | Sep 01 10:55:00 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851513593 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1851513593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.1744769511 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 12423167108 ps |
| CPU time | 269.77 seconds |
| Started | Sep 01 10:54:56 PM UTC 24 |
| Finished | Sep 01 10:59:30 PM UTC 24 |
| Peak memory | 362420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744769511 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1744769511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.233803257 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 534917133 ps |
| CPU time | 43.21 seconds |
| Started | Sep 01 10:53:48 PM UTC 24 |
| Finished | Sep 01 10:54:33 PM UTC 24 |
| Peak memory | 327468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233803257 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.233803257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.763618927 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 154462155289 ps |
| CPU time | 3992.39 seconds |
| Started | Sep 01 10:55:01 PM UTC 24 |
| Finished | Sep 02 12:02:19 AM UTC 24 |
| Peak memory | 396976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763618927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.763618927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.19325543 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1220793382 ps |
| CPU time | 563.77 seconds |
| Started | Sep 01 10:54:59 PM UTC 24 |
| Finished | Sep 01 11:04:30 PM UTC 24 |
| Peak memory | 378808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19325543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.19325543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2027349679 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 10452784243 ps |
| CPU time | 326.18 seconds |
| Started | Sep 01 10:53:56 PM UTC 24 |
| Finished | Sep 01 10:59:27 PM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027349679 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.2027349679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3857476569 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 281573681 ps |
| CPU time | 47.54 seconds |
| Started | Sep 01 10:54:25 PM UTC 24 |
| Finished | Sep 01 10:55:14 PM UTC 24 |
| Peak memory | 337776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3857476569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.3857476569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3317183819 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 10015399376 ps |
| CPU time | 478.35 seconds |
| Started | Sep 01 10:55:42 PM UTC 24 |
| Finished | Sep 01 11:03:47 PM UTC 24 |
| Peak memory | 325432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317183819 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during _key_req.3317183819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3944038377 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 108291037 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 10:56:32 PM UTC 24 |
| Finished | Sep 01 10:56:34 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944038377 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3944038377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.781571444 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 2605847736 ps |
| CPU time | 56.36 seconds |
| Started | Sep 01 10:55:12 PM UTC 24 |
| Finished | Sep 01 10:56:11 PM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781571444 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.781571444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.4005418455 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3569194428 ps |
| CPU time | 128.74 seconds |
| Started | Sep 01 10:55:46 PM UTC 24 |
| Finished | Sep 01 10:57:57 PM UTC 24 |
| Peak memory | 321456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005418455 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.4005418455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2805466247 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 481054243 ps |
| CPU time | 3.8 seconds |
| Started | Sep 01 10:55:36 PM UTC 24 |
| Finished | Sep 01 10:55:41 PM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805466247 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.2805466247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.867410333 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 128649743 ps |
| CPU time | 66.91 seconds |
| Started | Sep 01 10:55:23 PM UTC 24 |
| Finished | Sep 01 10:56:32 PM UTC 24 |
| Peak memory | 356216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 67410333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_max _throughput.867410333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.298821088 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 312306596 ps |
| CPU time | 6.82 seconds |
| Started | Sep 01 10:56:25 PM UTC 24 |
| Finished | Sep 01 10:56:33 PM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298821088 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.298821088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3132906680 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 898310324 ps |
| CPU time | 13.77 seconds |
| Started | Sep 01 10:56:15 PM UTC 24 |
| Finished | Sep 01 10:56:30 PM UTC 24 |
| Peak memory | 224412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132906680 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3132906680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.4230147084 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 88163347151 ps |
| CPU time | 1321.42 seconds |
| Started | Sep 01 10:55:11 PM UTC 24 |
| Finished | Sep 01 11:17:29 PM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230147084 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.4230147084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2615952261 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 122379961 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 10:55:15 PM UTC 24 |
| Finished | Sep 01 10:55:22 PM UTC 24 |
| Peak memory | 227124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615952261 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.2615952261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3192404630 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 9908350342 ps |
| CPU time | 390.18 seconds |
| Started | Sep 01 10:55:22 PM UTC 24 |
| Finished | Sep 01 11:01:57 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192404630 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc ess_b2b.3192404630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.471437912 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 81775406 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 10:56:12 PM UTC 24 |
| Finished | Sep 01 10:56:14 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471437912 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.471437912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3163612137 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 51889725336 ps |
| CPU time | 273.98 seconds |
| Started | Sep 01 10:55:53 PM UTC 24 |
| Finished | Sep 01 11:00:32 PM UTC 24 |
| Peak memory | 354232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163612137 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3163612137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.533709014 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5483162190 ps |
| CPU time | 22.19 seconds |
| Started | Sep 01 10:55:11 PM UTC 24 |
| Finished | Sep 01 10:55:35 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533709014 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.533709014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3286062602 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 64383923310 ps |
| CPU time | 4662.69 seconds |
| Started | Sep 01 10:56:32 PM UTC 24 |
| Finished | Sep 02 12:15:07 AM UTC 24 |
| Peak memory | 388784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328606260 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.3286062602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1787343406 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 5580564269 ps |
| CPU time | 94.62 seconds |
| Started | Sep 01 10:56:31 PM UTC 24 |
| Finished | Sep 01 10:58:08 PM UTC 24 |
| Peak memory | 350324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787343406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1787343406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.922176233 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 7675196923 ps |
| CPU time | 220.61 seconds |
| Started | Sep 01 10:55:15 PM UTC 24 |
| Finished | Sep 01 10:58:59 PM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922176233 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.922176233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1041553197 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 872907330 ps |
| CPU time | 118.99 seconds |
| Started | Sep 01 10:55:33 PM UTC 24 |
| Finished | Sep 01 10:57:34 PM UTC 24 |
| Peak memory | 381036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1041553197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_t hroughput_w_partial_write.1041553197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.3465264555 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 8541248412 ps |
| CPU time | 799.05 seconds |
| Started | Sep 01 10:57:35 PM UTC 24 |
| Finished | Sep 01 11:11:05 PM UTC 24 |
| Peak memory | 366428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465264555 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during _key_req.3465264555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2570194498 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 23541936 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 10:58:10 PM UTC 24 |
| Finished | Sep 01 10:58:12 PM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570194498 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2570194498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.600358786 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3748169639 ps |
| CPU time | 75.43 seconds |
| Started | Sep 01 10:56:36 PM UTC 24 |
| Finished | Sep 01 10:57:53 PM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600358786 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.600358786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.3425565105 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1496314981 ps |
| CPU time | 421.94 seconds |
| Started | Sep 01 10:57:44 PM UTC 24 |
| Finished | Sep 01 11:04:51 PM UTC 24 |
| Peak memory | 385120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425565105 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.3425565105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.513137460 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 585949690 ps |
| CPU time | 7.6 seconds |
| Started | Sep 01 10:57:34 PM UTC 24 |
| Finished | Sep 01 10:57:43 PM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513137460 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.513137460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2509157531 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 737407874 ps |
| CPU time | 73.36 seconds |
| Started | Sep 01 10:57:02 PM UTC 24 |
| Finished | Sep 01 10:58:17 PM UTC 24 |
| Peak memory | 347896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 509157531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ma x_throughput.2509157531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3608984730 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 141740104 ps |
| CPU time | 6.78 seconds |
| Started | Sep 01 10:58:01 PM UTC 24 |
| Finished | Sep 01 10:58:09 PM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608984730 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.3608984730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.121720762 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1937002950 ps |
| CPU time | 9.25 seconds |
| Started | Sep 01 10:57:59 PM UTC 24 |
| Finished | Sep 01 10:58:09 PM UTC 24 |
| Peak memory | 224260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121720762 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.121720762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.589510348 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 27618386264 ps |
| CPU time | 559.77 seconds |
| Started | Sep 01 10:56:34 PM UTC 24 |
| Finished | Sep 01 11:06:01 PM UTC 24 |
| Peak memory | 380852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589510348 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.589510348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.958126461 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 645336411 ps |
| CPU time | 135.28 seconds |
| Started | Sep 01 10:56:53 PM UTC 24 |
| Finished | Sep 01 10:59:11 PM UTC 24 |
| Peak memory | 378628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958126461 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.958126461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3719740757 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 92862176954 ps |
| CPU time | 408.94 seconds |
| Started | Sep 01 10:56:56 PM UTC 24 |
| Finished | Sep 01 11:03:51 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719740757 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc ess_b2b.3719740757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3204709882 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 27637248 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 10:57:58 PM UTC 24 |
| Finished | Sep 01 10:58:00 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204709882 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3204709882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.2594301841 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 31395869043 ps |
| CPU time | 305.55 seconds |
| Started | Sep 01 10:57:54 PM UTC 24 |
| Finished | Sep 01 11:03:04 PM UTC 24 |
| Peak memory | 374968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594301841 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2594301841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.2161071566 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 558533420 ps |
| CPU time | 15.79 seconds |
| Started | Sep 01 10:56:33 PM UTC 24 |
| Finished | Sep 01 10:56:50 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161071566 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2161071566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1710054490 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 45267524395 ps |
| CPU time | 3089.28 seconds |
| Started | Sep 01 10:58:09 PM UTC 24 |
| Finished | Sep 01 11:50:13 PM UTC 24 |
| Peak memory | 388660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171005449 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.1710054490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.425647876 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1662262232 ps |
| CPU time | 926.74 seconds |
| Started | Sep 01 10:58:08 PM UTC 24 |
| Finished | Sep 01 11:13:45 PM UTC 24 |
| Peak memory | 389296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425647876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.425647876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2685196273 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2596974435 ps |
| CPU time | 358.02 seconds |
| Started | Sep 01 10:56:52 PM UTC 24 |
| Finished | Sep 01 11:02:55 PM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685196273 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.2685196273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1761289340 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 130001419 ps |
| CPU time | 39.24 seconds |
| Started | Sep 01 10:57:17 PM UTC 24 |
| Finished | Sep 01 10:57:58 PM UTC 24 |
| Peak memory | 309416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1761289340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t hroughput_w_partial_write.1761289340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.295439953 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 61354915594 ps |
| CPU time | 863.9 seconds |
| Started | Sep 01 10:59:31 PM UTC 24 |
| Finished | Sep 01 11:14:05 PM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295439953 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during_ key_req.295439953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1867355697 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 17624856 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 11:00:15 PM UTC 24 |
| Finished | Sep 01 11:00:17 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867355697 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1867355697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3253309705 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1457148764 ps |
| CPU time | 32.7 seconds |
| Started | Sep 01 10:58:29 PM UTC 24 |
| Finished | Sep 01 10:59:03 PM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253309705 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.3253309705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3901014869 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 17933121079 ps |
| CPU time | 1193.29 seconds |
| Started | Sep 01 10:59:40 PM UTC 24 |
| Finished | Sep 01 11:19:47 PM UTC 24 |
| Peak memory | 382904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901014869 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3901014869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.407039271 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4298521757 ps |
| CPU time | 9.8 seconds |
| Started | Sep 01 10:59:28 PM UTC 24 |
| Finished | Sep 01 10:59:39 PM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407039271 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.407039271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3461010385 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 112255453 ps |
| CPU time | 60.35 seconds |
| Started | Sep 01 10:59:11 PM UTC 24 |
| Finished | Sep 01 11:00:13 PM UTC 24 |
| Peak memory | 329904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 461010385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ma x_throughput.3461010385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.792179418 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 310130282 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 10:59:59 PM UTC 24 |
| Finished | Sep 01 11:00:05 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792179418 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.792179418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1897502042 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1830056676 ps |
| CPU time | 12.87 seconds |
| Started | Sep 01 10:59:49 PM UTC 24 |
| Finished | Sep 01 11:00:03 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897502042 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.1897502042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3932270622 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 5494844729 ps |
| CPU time | 439.37 seconds |
| Started | Sep 01 10:58:18 PM UTC 24 |
| Finished | Sep 01 11:05:42 PM UTC 24 |
| Peak memory | 372656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932270622 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.3932270622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2339147725 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 272012737 ps |
| CPU time | 16.92 seconds |
| Started | Sep 01 10:59:00 PM UTC 24 |
| Finished | Sep 01 10:59:18 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339147725 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.2339147725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.3708220733 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2605121715 ps |
| CPU time | 258.85 seconds |
| Started | Sep 01 10:59:04 PM UTC 24 |
| Finished | Sep 01 11:03:27 PM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708220733 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acc ess_b2b.3708220733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.570116707 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 79786242 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 10:59:46 PM UTC 24 |
| Finished | Sep 01 10:59:48 PM UTC 24 |
| Peak memory | 212572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570116707 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.570116707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3313181732 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1808627785 ps |
| CPU time | 195.09 seconds |
| Started | Sep 01 10:59:42 PM UTC 24 |
| Finished | Sep 01 11:03:00 PM UTC 24 |
| Peak memory | 358208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313181732 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3313181732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3402060667 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 134495849 ps |
| CPU time | 124.79 seconds |
| Started | Sep 01 10:58:14 PM UTC 24 |
| Finished | Sep 01 11:00:21 PM UTC 24 |
| Peak memory | 381052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402060667 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3402060667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2888820458 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 41732733692 ps |
| CPU time | 1705.78 seconds |
| Started | Sep 01 11:00:07 PM UTC 24 |
| Finished | Sep 01 11:28:52 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288882045 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.2888820458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3763164330 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 5788150878 ps |
| CPU time | 131.82 seconds |
| Started | Sep 01 11:00:07 PM UTC 24 |
| Finished | Sep 01 11:02:21 PM UTC 24 |
| Peak memory | 354212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763164330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3763164330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1146163853 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 3274756649 ps |
| CPU time | 393.69 seconds |
| Started | Sep 01 10:58:55 PM UTC 24 |
| Finished | Sep 01 11:05:35 PM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146163853 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1146163853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.636318043 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 421689509 ps |
| CPU time | 37.35 seconds |
| Started | Sep 01 10:59:20 PM UTC 24 |
| Finished | Sep 01 10:59:58 PM UTC 24 |
| Peak memory | 303280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 636318043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_th roughput_w_partial_write.636318043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.4057792998 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1115449317 ps |
| CPU time | 184.34 seconds |
| Started | Sep 01 11:01:34 PM UTC 24 |
| Finished | Sep 01 11:04:42 PM UTC 24 |
| Peak memory | 374632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057792998 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during _key_req.4057792998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.707900744 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 15603346 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 11:02:21 PM UTC 24 |
| Finished | Sep 01 11:02:23 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707900744 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.707900744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.4055216705 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 8051185922 ps |
| CPU time | 92.38 seconds |
| Started | Sep 01 11:00:32 PM UTC 24 |
| Finished | Sep 01 11:02:07 PM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055216705 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.4055216705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.773697616 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1061107196 ps |
| CPU time | 84.54 seconds |
| Started | Sep 01 11:01:51 PM UTC 24 |
| Finished | Sep 01 11:03:18 PM UTC 24 |
| Peak memory | 323436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773697616 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.773697616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.4082281389 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 252471639 ps |
| CPU time | 6.77 seconds |
| Started | Sep 01 11:01:25 PM UTC 24 |
| Finished | Sep 01 11:01:33 PM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082281389 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.4082281389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.956947441 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 87557496 ps |
| CPU time | 21.66 seconds |
| Started | Sep 01 11:01:00 PM UTC 24 |
| Finished | Sep 01 11:01:23 PM UTC 24 |
| Peak memory | 288560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 56947441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_max _throughput.956947441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.4281160295 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 645533546 ps |
| CPU time | 8.35 seconds |
| Started | Sep 01 11:02:08 PM UTC 24 |
| Finished | Sep 01 11:02:17 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281160295 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.4281160295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3262763831 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 281775347 ps |
| CPU time | 7.87 seconds |
| Started | Sep 01 11:02:02 PM UTC 24 |
| Finished | Sep 01 11:02:11 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262763831 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.3262763831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.4017247507 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 85497765272 ps |
| CPU time | 614.96 seconds |
| Started | Sep 01 11:00:22 PM UTC 24 |
| Finished | Sep 01 11:10:45 PM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017247507 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.4017247507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3368419706 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 847032391 ps |
| CPU time | 82.77 seconds |
| Started | Sep 01 11:00:33 PM UTC 24 |
| Finished | Sep 01 11:01:58 PM UTC 24 |
| Peak memory | 380792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368419706 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.3368419706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1233050718 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 12758620521 ps |
| CPU time | 325.41 seconds |
| Started | Sep 01 11:00:59 PM UTC 24 |
| Finished | Sep 01 11:06:29 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233050718 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc ess_b2b.1233050718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.444759047 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 95389231 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 11:01:59 PM UTC 24 |
| Finished | Sep 01 11:02:01 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444759047 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.444759047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.4112588140 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1575893741 ps |
| CPU time | 858.43 seconds |
| Started | Sep 01 11:01:59 PM UTC 24 |
| Finished | Sep 01 11:16:27 PM UTC 24 |
| Peak memory | 384888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112588140 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.4112588140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.735505233 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 5942444490 ps |
| CPU time | 39.64 seconds |
| Started | Sep 01 11:00:18 PM UTC 24 |
| Finished | Sep 01 11:00:59 PM UTC 24 |
| Peak memory | 321332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735505233 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.735505233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1975474643 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 172028552919 ps |
| CPU time | 4527.66 seconds |
| Started | Sep 01 11:02:18 PM UTC 24 |
| Finished | Sep 02 12:18:38 AM UTC 24 |
| Peak memory | 399032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197547464 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.1975474643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.444818156 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 6877661843 ps |
| CPU time | 90.59 seconds |
| Started | Sep 01 11:02:12 PM UTC 24 |
| Finished | Sep 01 11:03:45 PM UTC 24 |
| Peak memory | 224184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444818156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.444818156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.1300317433 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4126902596 ps |
| CPU time | 153.79 seconds |
| Started | Sep 01 11:00:33 PM UTC 24 |
| Finished | Sep 01 11:03:10 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300317433 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.1300317433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2611514942 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 157189355 ps |
| CPU time | 25.2 seconds |
| Started | Sep 01 11:01:24 PM UTC 24 |
| Finished | Sep 01 11:01:50 PM UTC 24 |
| Peak memory | 290668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2611514942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t hroughput_w_partial_write.2611514942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3845328029 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3194610212 ps |
| CPU time | 245.1 seconds |
| Started | Sep 01 11:03:19 PM UTC 24 |
| Finished | Sep 01 11:07:28 PM UTC 24 |
| Peak memory | 376616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845328029 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during _key_req.3845328029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1494091815 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 42486681 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 11:03:47 PM UTC 24 |
| Finished | Sep 01 11:03:49 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494091815 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1494091815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.231437483 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 16466056495 ps |
| CPU time | 90.11 seconds |
| Started | Sep 01 11:02:53 PM UTC 24 |
| Finished | Sep 01 11:04:25 PM UTC 24 |
| Peak memory | 213936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231437483 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.231437483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.3446075052 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 3939814090 ps |
| CPU time | 1354.27 seconds |
| Started | Sep 01 11:03:21 PM UTC 24 |
| Finished | Sep 01 11:26:10 PM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446075052 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.3446075052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1290819511 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 402184407 ps |
| CPU time | 4.74 seconds |
| Started | Sep 01 11:03:13 PM UTC 24 |
| Finished | Sep 01 11:03:19 PM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290819511 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.1290819511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4241195354 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 98711002 ps |
| CPU time | 35.03 seconds |
| Started | Sep 01 11:03:05 PM UTC 24 |
| Finished | Sep 01 11:03:42 PM UTC 24 |
| Peak memory | 298788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 241195354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ma x_throughput.4241195354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3237881200 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 473442249 ps |
| CPU time | 6.64 seconds |
| Started | Sep 01 11:03:36 PM UTC 24 |
| Finished | Sep 01 11:03:44 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237881200 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.3237881200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1813916747 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5457905542 ps |
| CPU time | 17.52 seconds |
| Started | Sep 01 11:03:34 PM UTC 24 |
| Finished | Sep 01 11:03:53 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813916747 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.1813916747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2898366994 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2284101530 ps |
| CPU time | 488.46 seconds |
| Started | Sep 01 11:02:30 PM UTC 24 |
| Finished | Sep 01 11:10:45 PM UTC 24 |
| Peak memory | 378800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898366994 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.2898366994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3778798076 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 651101610 ps |
| CPU time | 11.9 seconds |
| Started | Sep 01 11:02:59 PM UTC 24 |
| Finished | Sep 01 11:03:12 PM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778798076 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.3778798076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1969450849 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 4541715352 ps |
| CPU time | 408.33 seconds |
| Started | Sep 01 11:03:01 PM UTC 24 |
| Finished | Sep 01 11:09:55 PM UTC 24 |
| Peak memory | 213996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969450849 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc ess_b2b.1969450849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1644302273 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 120727826 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 11:03:31 PM UTC 24 |
| Finished | Sep 01 11:03:33 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644302273 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1644302273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.757844745 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 3929752919 ps |
| CPU time | 1006.99 seconds |
| Started | Sep 01 11:03:28 PM UTC 24 |
| Finished | Sep 01 11:20:26 PM UTC 24 |
| Peak memory | 385208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757844745 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.757844745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3036889366 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1360199935 ps |
| CPU time | 25.87 seconds |
| Started | Sep 01 11:02:24 PM UTC 24 |
| Finished | Sep 01 11:02:51 PM UTC 24 |
| Peak memory | 282740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036889366 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3036889366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3835307964 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 274858778232 ps |
| CPU time | 3138.24 seconds |
| Started | Sep 01 11:03:45 PM UTC 24 |
| Finished | Sep 01 11:56:39 PM UTC 24 |
| Peak memory | 384640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383530796 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.3835307964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4098174580 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 769811786 ps |
| CPU time | 20.04 seconds |
| Started | Sep 01 11:03:45 PM UTC 24 |
| Finished | Sep 01 11:04:06 PM UTC 24 |
| Peak memory | 223932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098174580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.4098174580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2534550397 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 11419731589 ps |
| CPU time | 305.86 seconds |
| Started | Sep 01 11:02:56 PM UTC 24 |
| Finished | Sep 01 11:08:07 PM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534550397 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.2534550397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.4184178325 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 85296421 ps |
| CPU time | 17.46 seconds |
| Started | Sep 01 11:03:11 PM UTC 24 |
| Finished | Sep 01 11:03:30 PM UTC 24 |
| Peak memory | 272236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4184178325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t hroughput_w_partial_write.4184178325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.425678090 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 303775179 ps |
| CPU time | 83.81 seconds |
| Started | Sep 01 11:04:08 PM UTC 24 |
| Finished | Sep 01 11:05:34 PM UTC 24 |
| Peak memory | 313448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425678090 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during_ key_req.425678090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3877916289 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 84612164 ps |
| CPU time | 1 seconds |
| Started | Sep 01 11:04:38 PM UTC 24 |
| Finished | Sep 01 11:04:40 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877916289 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3877916289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1578381155 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1824697672 ps |
| CPU time | 19.64 seconds |
| Started | Sep 01 11:03:53 PM UTC 24 |
| Finished | Sep 01 11:04:14 PM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578381155 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1578381155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1859411946 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1526234806 ps |
| CPU time | 79.96 seconds |
| Started | Sep 01 11:04:15 PM UTC 24 |
| Finished | Sep 01 11:05:37 PM UTC 24 |
| Peak memory | 325752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859411946 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1859411946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3701154666 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2290654010 ps |
| CPU time | 10.65 seconds |
| Started | Sep 01 11:04:08 PM UTC 24 |
| Finished | Sep 01 11:04:20 PM UTC 24 |
| Peak memory | 224232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701154666 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.3701154666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.4106307214 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 40993745 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 11:04:04 PM UTC 24 |
| Finished | Sep 01 11:04:07 PM UTC 24 |
| Peak memory | 222868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 106307214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ma x_throughput.4106307214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3681893428 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 105390304 ps |
| CPU time | 4.32 seconds |
| Started | Sep 01 11:04:25 PM UTC 24 |
| Finished | Sep 01 11:04:31 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681893428 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.3681893428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.644885272 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 525491491 ps |
| CPU time | 9.73 seconds |
| Started | Sep 01 11:04:25 PM UTC 24 |
| Finished | Sep 01 11:04:37 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644885272 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.644885272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3749783969 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2959642276 ps |
| CPU time | 550.37 seconds |
| Started | Sep 01 11:03:51 PM UTC 24 |
| Finished | Sep 01 11:13:08 PM UTC 24 |
| Peak memory | 374632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749783969 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.3749783969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.385475731 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 555715062 ps |
| CPU time | 5.2 seconds |
| Started | Sep 01 11:03:55 PM UTC 24 |
| Finished | Sep 01 11:04:02 PM UTC 24 |
| Peak memory | 223100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385475731 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.385475731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3167861290 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 16676092629 ps |
| CPU time | 485.53 seconds |
| Started | Sep 01 11:03:55 PM UTC 24 |
| Finished | Sep 01 11:12:08 PM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167861290 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc ess_b2b.3167861290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2078038929 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 45249703 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:04:22 PM UTC 24 |
| Finished | Sep 01 11:04:24 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078038929 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2078038929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3763220441 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 2183339853 ps |
| CPU time | 777.16 seconds |
| Started | Sep 01 11:04:21 PM UTC 24 |
| Finished | Sep 01 11:17:27 PM UTC 24 |
| Peak memory | 376684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763220441 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3763220441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.337395233 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1430566071 ps |
| CPU time | 30.78 seconds |
| Started | Sep 01 11:03:49 PM UTC 24 |
| Finished | Sep 01 11:04:21 PM UTC 24 |
| Peak memory | 284532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337395233 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.337395233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.569439490 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 30729888558 ps |
| CPU time | 1935.33 seconds |
| Started | Sep 01 11:04:32 PM UTC 24 |
| Finished | Sep 01 11:37:10 PM UTC 24 |
| Peak memory | 382848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569439490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.569439490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3004524685 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 3507875657 ps |
| CPU time | 348.19 seconds |
| Started | Sep 01 11:04:31 PM UTC 24 |
| Finished | Sep 01 11:10:24 PM UTC 24 |
| Peak memory | 391404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004524685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3004524685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2432519544 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 4151796689 ps |
| CPU time | 499.75 seconds |
| Started | Sep 01 11:03:53 PM UTC 24 |
| Finished | Sep 01 11:12:20 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432519544 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.2432519544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3543325438 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 114074614 ps |
| CPU time | 43.01 seconds |
| Started | Sep 01 11:04:07 PM UTC 24 |
| Finished | Sep 01 11:04:51 PM UTC 24 |
| Peak memory | 317288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3543325438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t hroughput_w_partial_write.3543325438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3912963776 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 20835257287 ps |
| CPU time | 643.19 seconds |
| Started | Sep 01 11:05:34 PM UTC 24 |
| Finished | Sep 01 11:16:25 PM UTC 24 |
| Peak memory | 386960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912963776 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during _key_req.3912963776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.1308002160 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 26095633 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 11:05:49 PM UTC 24 |
| Finished | Sep 01 11:05:51 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308002160 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.1308002160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2539587829 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 405842212 ps |
| CPU time | 36.23 seconds |
| Started | Sep 01 11:04:52 PM UTC 24 |
| Finished | Sep 01 11:05:30 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539587829 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2539587829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.931465184 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 4808588744 ps |
| CPU time | 1439.96 seconds |
| Started | Sep 01 11:05:35 PM UTC 24 |
| Finished | Sep 01 11:29:51 PM UTC 24 |
| Peak memory | 383152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931465184 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.931465184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.92003668 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 7586094369 ps |
| CPU time | 18.68 seconds |
| Started | Sep 01 11:05:34 PM UTC 24 |
| Finished | Sep 01 11:05:54 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92003668 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.92003668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3693055898 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 96184034 ps |
| CPU time | 30.73 seconds |
| Started | Sep 01 11:05:01 PM UTC 24 |
| Finished | Sep 01 11:05:33 PM UTC 24 |
| Peak memory | 305200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 693055898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma x_throughput.3693055898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2123847171 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 47512535 ps |
| CPU time | 3.67 seconds |
| Started | Sep 01 11:05:43 PM UTC 24 |
| Finished | Sep 01 11:05:48 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123847171 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.2123847171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.890165452 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 149618255 ps |
| CPU time | 5.07 seconds |
| Started | Sep 01 11:05:40 PM UTC 24 |
| Finished | Sep 01 11:05:47 PM UTC 24 |
| Peak memory | 224156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890165452 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.890165452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3050860185 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 8765743689 ps |
| CPU time | 582.96 seconds |
| Started | Sep 01 11:04:43 PM UTC 24 |
| Finished | Sep 01 11:14:33 PM UTC 24 |
| Peak memory | 380728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050860185 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.3050860185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3063076891 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3137349313 ps |
| CPU time | 45.81 seconds |
| Started | Sep 01 11:04:54 PM UTC 24 |
| Finished | Sep 01 11:05:42 PM UTC 24 |
| Peak memory | 309180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063076891 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.3063076891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2144545800 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 15250288464 ps |
| CPU time | 249.41 seconds |
| Started | Sep 01 11:04:59 PM UTC 24 |
| Finished | Sep 01 11:09:12 PM UTC 24 |
| Peak memory | 213996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144545800 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc ess_b2b.2144545800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.971129371 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 28431133 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 11:05:37 PM UTC 24 |
| Finished | Sep 01 11:05:40 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971129371 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.971129371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.819979775 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 6864536484 ps |
| CPU time | 646.03 seconds |
| Started | Sep 01 11:05:36 PM UTC 24 |
| Finished | Sep 01 11:16:30 PM UTC 24 |
| Peak memory | 380784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819979775 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.819979775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.2452309563 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 742903009 ps |
| CPU time | 15.85 seconds |
| Started | Sep 01 11:04:41 PM UTC 24 |
| Finished | Sep 01 11:04:58 PM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452309563 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2452309563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.522756743 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 9218195147 ps |
| CPU time | 3743.89 seconds |
| Started | Sep 01 11:05:48 PM UTC 24 |
| Finished | Sep 02 12:08:55 AM UTC 24 |
| Peak memory | 388688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522756743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.522756743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.829258830 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1594688386 ps |
| CPU time | 393.51 seconds |
| Started | Sep 01 11:05:44 PM UTC 24 |
| Finished | Sep 01 11:12:23 PM UTC 24 |
| Peak memory | 389040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829258830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.829258830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2458788045 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 11654919446 ps |
| CPU time | 332.87 seconds |
| Started | Sep 01 11:04:52 PM UTC 24 |
| Finished | Sep 01 11:10:30 PM UTC 24 |
| Peak memory | 213976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458788045 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2458788045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3871034133 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 453073144 ps |
| CPU time | 3.89 seconds |
| Started | Sep 01 11:05:31 PM UTC 24 |
| Finished | Sep 01 11:05:36 PM UTC 24 |
| Peak memory | 231204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3871034133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t hroughput_w_partial_write.3871034133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.202327074 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 20764172272 ps |
| CPU time | 1510.26 seconds |
| Started | Sep 01 09:52:47 PM UTC 24 |
| Finished | Sep 01 10:18:15 PM UTC 24 |
| Peak memory | 387180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202327074 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_k ey_req.202327074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1784100154 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 13032133 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 09:54:06 PM UTC 24 |
| Finished | Sep 01 09:54:08 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784100154 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.1784100154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2596829550 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 8443879412 ps |
| CPU time | 84.37 seconds |
| Started | Sep 01 09:51:49 PM UTC 24 |
| Finished | Sep 01 09:53:15 PM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596829550 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2596829550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3181054866 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2068503001 ps |
| CPU time | 12.63 seconds |
| Started | Sep 01 09:52:43 PM UTC 24 |
| Finished | Sep 01 09:52:56 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181054866 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.3181054866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2961178308 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 123171431 ps |
| CPU time | 96.35 seconds |
| Started | Sep 01 09:52:33 PM UTC 24 |
| Finished | Sep 01 09:54:12 PM UTC 24 |
| Peak memory | 364316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 961178308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max _throughput.2961178308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.562339812 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 103478713 ps |
| CPU time | 5.47 seconds |
| Started | Sep 01 09:53:35 PM UTC 24 |
| Finished | Sep 01 09:53:42 PM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562339812 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.562339812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.842508364 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3253116113 ps |
| CPU time | 14.71 seconds |
| Started | Sep 01 09:53:19 PM UTC 24 |
| Finished | Sep 01 09:53:35 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842508364 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.842508364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3074865629 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 29133045383 ps |
| CPU time | 1353.55 seconds |
| Started | Sep 01 09:51:47 PM UTC 24 |
| Finished | Sep 01 10:14:36 PM UTC 24 |
| Peak memory | 387200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074865629 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.3074865629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.4232403892 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 548175563 ps |
| CPU time | 74.87 seconds |
| Started | Sep 01 09:52:17 PM UTC 24 |
| Finished | Sep 01 09:53:34 PM UTC 24 |
| Peak memory | 339820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232403892 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.4232403892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2002509353 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 11349077852 ps |
| CPU time | 345.83 seconds |
| Started | Sep 01 09:52:18 PM UTC 24 |
| Finished | Sep 01 09:58:09 PM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002509353 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce ss_b2b.2002509353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.383010734 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 31278406 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:53:16 PM UTC 24 |
| Finished | Sep 01 09:53:18 PM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383010734 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.383010734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.956341429 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 59216033701 ps |
| CPU time | 1058.94 seconds |
| Started | Sep 01 09:53:04 PM UTC 24 |
| Finished | Sep 01 10:10:54 PM UTC 24 |
| Peak memory | 380864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956341429 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.956341429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.2441785416 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 622465380 ps |
| CPU time | 16.54 seconds |
| Started | Sep 01 09:51:29 PM UTC 24 |
| Finished | Sep 01 09:51:48 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441785416 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2441785416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2690021217 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 35349024124 ps |
| CPU time | 2033.23 seconds |
| Started | Sep 01 09:53:42 PM UTC 24 |
| Finished | Sep 01 10:27:58 PM UTC 24 |
| Peak memory | 386952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269002121 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.2690021217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1741431009 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2668440659 ps |
| CPU time | 27.52 seconds |
| Started | Sep 01 09:53:36 PM UTC 24 |
| Finished | Sep 01 09:54:05 PM UTC 24 |
| Peak memory | 266176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741431009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1741431009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3044578883 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 23405124445 ps |
| CPU time | 356.41 seconds |
| Started | Sep 01 09:51:50 PM UTC 24 |
| Finished | Sep 01 09:57:51 PM UTC 24 |
| Peak memory | 214276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044578883 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.3044578883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1679195717 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 164256094 ps |
| CPU time | 123.05 seconds |
| Started | Sep 01 09:52:34 PM UTC 24 |
| Finished | Sep 01 09:54:40 PM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1679195717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th roughput_w_partial_write.1679195717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3704426662 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2564278736 ps |
| CPU time | 730.37 seconds |
| Started | Sep 01 09:55:26 PM UTC 24 |
| Finished | Sep 01 10:07:45 PM UTC 24 |
| Peak memory | 384888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704426662 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_ key_req.3704426662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1259057723 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 21241602 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 09:56:32 PM UTC 24 |
| Finished | Sep 01 09:56:33 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259057723 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1259057723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.881115535 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 25282561310 ps |
| CPU time | 110.02 seconds |
| Started | Sep 01 09:54:21 PM UTC 24 |
| Finished | Sep 01 09:56:14 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881115535 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.881115535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.179531141 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 14543853856 ps |
| CPU time | 487.07 seconds |
| Started | Sep 01 09:55:26 PM UTC 24 |
| Finished | Sep 01 10:03:39 PM UTC 24 |
| Peak memory | 376752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179531141 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.179531141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1654202939 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2757225891 ps |
| CPU time | 8.01 seconds |
| Started | Sep 01 09:55:15 PM UTC 24 |
| Finished | Sep 01 09:55:25 PM UTC 24 |
| Peak memory | 214280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654202939 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.1654202939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.110863911 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 68462902 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:55:06 PM UTC 24 |
| Finished | Sep 01 09:55:09 PM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 10863911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_ throughput.110863911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2492896217 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 629119902 ps |
| CPU time | 7.72 seconds |
| Started | Sep 01 09:56:15 PM UTC 24 |
| Finished | Sep 01 09:56:24 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492896217 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.2492896217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.898451940 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1340273088 ps |
| CPU time | 16.65 seconds |
| Started | Sep 01 09:56:13 PM UTC 24 |
| Finished | Sep 01 09:56:31 PM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898451940 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.898451940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.4004783290 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2404453478 ps |
| CPU time | 1189.49 seconds |
| Started | Sep 01 09:54:13 PM UTC 24 |
| Finished | Sep 01 10:14:16 PM UTC 24 |
| Peak memory | 376692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004783290 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.4004783290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.177147100 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1249292271 ps |
| CPU time | 22.83 seconds |
| Started | Sep 01 09:54:41 PM UTC 24 |
| Finished | Sep 01 09:55:05 PM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177147100 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.177147100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.4150937511 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8784737407 ps |
| CPU time | 237.2 seconds |
| Started | Sep 01 09:54:48 PM UTC 24 |
| Finished | Sep 01 09:58:49 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150937511 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce ss_b2b.4150937511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1917810854 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 84860114 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 09:56:10 PM UTC 24 |
| Finished | Sep 01 09:56:12 PM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917810854 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1917810854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.590129208 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6190363182 ps |
| CPU time | 377.62 seconds |
| Started | Sep 01 09:56:04 PM UTC 24 |
| Finished | Sep 01 10:02:27 PM UTC 24 |
| Peak memory | 384956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590129208 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.590129208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.4215255140 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 100404175 ps |
| CPU time | 8.79 seconds |
| Started | Sep 01 09:54:10 PM UTC 24 |
| Finished | Sep 01 09:54:19 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215255140 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.4215255140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2411539744 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1227119034 ps |
| CPU time | 438.89 seconds |
| Started | Sep 01 09:56:23 PM UTC 24 |
| Finished | Sep 01 10:03:48 PM UTC 24 |
| Peak memory | 364468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411539744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2411539744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4254781215 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2974679301 ps |
| CPU time | 191.68 seconds |
| Started | Sep 01 09:54:26 PM UTC 24 |
| Finished | Sep 01 09:57:41 PM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254781215 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.4254781215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1087847767 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 627852544 ps |
| CPU time | 56.64 seconds |
| Started | Sep 01 09:55:10 PM UTC 24 |
| Finished | Sep 01 09:56:09 PM UTC 24 |
| Peak memory | 317292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1087847767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th roughput_w_partial_write.1087847767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.246917422 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 19713388458 ps |
| CPU time | 1302.6 seconds |
| Started | Sep 01 09:57:53 PM UTC 24 |
| Finished | Sep 01 10:19:49 PM UTC 24 |
| Peak memory | 386988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246917422 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_k ey_req.246917422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.4102565388 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 90902818 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 09:58:29 PM UTC 24 |
| Finished | Sep 01 09:58:31 PM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102565388 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.4102565388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.3043035741 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 6784120877 ps |
| CPU time | 81.69 seconds |
| Started | Sep 01 09:57:01 PM UTC 24 |
| Finished | Sep 01 09:58:25 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043035741 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.3043035741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.402422956 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 14124674207 ps |
| CPU time | 462.25 seconds |
| Started | Sep 01 09:57:53 PM UTC 24 |
| Finished | Sep 01 10:05:41 PM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402422956 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.402422956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3071853060 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 255925673 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 09:57:50 PM UTC 24 |
| Finished | Sep 01 09:57:54 PM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071853060 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3071853060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3068081975 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 202381069 ps |
| CPU time | 8.23 seconds |
| Started | Sep 01 09:57:42 PM UTC 24 |
| Finished | Sep 01 09:57:52 PM UTC 24 |
| Peak memory | 247912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 068081975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max _throughput.3068081975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.293737282 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 378934808 ps |
| CPU time | 4.6 seconds |
| Started | Sep 01 09:58:19 PM UTC 24 |
| Finished | Sep 01 09:58:25 PM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293737282 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.293737282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1098574876 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 601779218 ps |
| CPU time | 14.15 seconds |
| Started | Sep 01 09:58:13 PM UTC 24 |
| Finished | Sep 01 09:58:28 PM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098574876 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.1098574876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.80948108 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 25078993763 ps |
| CPU time | 1166 seconds |
| Started | Sep 01 09:56:51 PM UTC 24 |
| Finished | Sep 01 10:16:30 PM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80948108 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.80948108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1241147457 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 821775358 ps |
| CPU time | 16.98 seconds |
| Started | Sep 01 09:57:27 PM UTC 24 |
| Finished | Sep 01 09:57:46 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241147457 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.1241147457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1398584228 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4141863233 ps |
| CPU time | 166.67 seconds |
| Started | Sep 01 09:57:34 PM UTC 24 |
| Finished | Sep 01 10:00:24 PM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398584228 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acce ss_b2b.1398584228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.79730607 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 35628623 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 09:58:10 PM UTC 24 |
| Finished | Sep 01 09:58:12 PM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79730607 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.79730607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1809551146 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 13158301746 ps |
| CPU time | 659.53 seconds |
| Started | Sep 01 09:57:55 PM UTC 24 |
| Finished | Sep 01 10:09:03 PM UTC 24 |
| Peak memory | 380800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809551146 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1809551146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2851120689 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 149957038 ps |
| CPU time | 101.58 seconds |
| Started | Sep 01 09:56:35 PM UTC 24 |
| Finished | Sep 01 09:58:18 PM UTC 24 |
| Peak memory | 370756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851120689 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2851120689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.223854811 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 26483556794 ps |
| CPU time | 387.15 seconds |
| Started | Sep 01 09:57:23 PM UTC 24 |
| Finished | Sep 01 10:03:56 PM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223854811 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.223854811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2975015242 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 118712696 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:57:46 PM UTC 24 |
| Finished | Sep 01 09:57:49 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2975015242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th roughput_w_partial_write.2975015242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.339585732 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 12816321529 ps |
| CPU time | 924.81 seconds |
| Started | Sep 01 09:59:52 PM UTC 24 |
| Finished | Sep 01 10:15:27 PM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339585732 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_k ey_req.339585732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3113830672 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 19228248 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 10:00:35 PM UTC 24 |
| Finished | Sep 01 10:00:37 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113830672 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3113830672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3353324161 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5032901624 ps |
| CPU time | 98.14 seconds |
| Started | Sep 01 09:58:48 PM UTC 24 |
| Finished | Sep 01 10:00:28 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353324161 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.3353324161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3268495077 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 4471515347 ps |
| CPU time | 441.62 seconds |
| Started | Sep 01 09:59:57 PM UTC 24 |
| Finished | Sep 01 10:07:24 PM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268495077 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3268495077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.726242838 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1624407532 ps |
| CPU time | 11.2 seconds |
| Started | Sep 01 09:59:44 PM UTC 24 |
| Finished | Sep 01 09:59:56 PM UTC 24 |
| Peak memory | 214016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726242838 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.726242838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1747661889 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 130201294 ps |
| CPU time | 90.4 seconds |
| Started | Sep 01 09:59:34 PM UTC 24 |
| Finished | Sep 01 10:01:07 PM UTC 24 |
| Peak memory | 370536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 747661889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max _throughput.1747661889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1755008697 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 58332044 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 10:00:29 PM UTC 24 |
| Finished | Sep 01 10:00:34 PM UTC 24 |
| Peak memory | 224412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755008697 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.1755008697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3845611364 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 777401603 ps |
| CPU time | 5.63 seconds |
| Started | Sep 01 10:00:28 PM UTC 24 |
| Finished | Sep 01 10:00:35 PM UTC 24 |
| Peak memory | 214072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845611364 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3845611364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3821157159 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 26934968752 ps |
| CPU time | 1018.28 seconds |
| Started | Sep 01 09:58:46 PM UTC 24 |
| Finished | Sep 01 10:15:55 PM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821157159 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.3821157159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3855656720 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 264208167 ps |
| CPU time | 16.15 seconds |
| Started | Sep 01 09:59:16 PM UTC 24 |
| Finished | Sep 01 09:59:33 PM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855656720 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3855656720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3149688856 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 201201386923 ps |
| CPU time | 733.96 seconds |
| Started | Sep 01 09:59:31 PM UTC 24 |
| Finished | Sep 01 10:11:55 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149688856 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce ss_b2b.3149688856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1447730347 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 26396248 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 10:00:25 PM UTC 24 |
| Finished | Sep 01 10:00:27 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447730347 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1447730347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1858209977 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4496433760 ps |
| CPU time | 350.82 seconds |
| Started | Sep 01 10:00:00 PM UTC 24 |
| Finished | Sep 01 10:05:56 PM UTC 24 |
| Peak memory | 350136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858209977 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1858209977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1899620673 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 800313682 ps |
| CPU time | 12.76 seconds |
| Started | Sep 01 09:58:33 PM UTC 24 |
| Finished | Sep 01 09:58:47 PM UTC 24 |
| Peak memory | 213832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899620673 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1899620673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3271345323 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 30383133895 ps |
| CPU time | 2558.46 seconds |
| Started | Sep 01 10:00:35 PM UTC 24 |
| Finished | Sep 01 10:43:42 PM UTC 24 |
| Peak memory | 384896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327134532 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.3271345323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.285561671 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4645285721 ps |
| CPU time | 472.23 seconds |
| Started | Sep 01 09:58:50 PM UTC 24 |
| Finished | Sep 01 10:06:48 PM UTC 24 |
| Peak memory | 213996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285561671 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.285561671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2631226865 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 446697241 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 09:59:36 PM UTC 24 |
| Finished | Sep 01 09:59:43 PM UTC 24 |
| Peak memory | 233248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2631226865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th roughput_w_partial_write.2631226865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2476556850 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4367613156 ps |
| CPU time | 996.6 seconds |
| Started | Sep 01 10:02:04 PM UTC 24 |
| Finished | Sep 01 10:18:51 PM UTC 24 |
| Peak memory | 384852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476556850 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_ key_req.2476556850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.4010779336 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 42734754 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 10:02:29 PM UTC 24 |
| Finished | Sep 01 10:02:31 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010779336 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.4010779336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2929865421 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 15315003034 ps |
| CPU time | 85.89 seconds |
| Started | Sep 01 10:01:01 PM UTC 24 |
| Finished | Sep 01 10:02:29 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929865421 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.2929865421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2487647602 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 13815485670 ps |
| CPU time | 484.51 seconds |
| Started | Sep 01 10:02:07 PM UTC 24 |
| Finished | Sep 01 10:10:17 PM UTC 24 |
| Peak memory | 386912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487647602 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.2487647602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1675037652 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 118398043 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 10:02:04 PM UTC 24 |
| Finished | Sep 01 10:02:07 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675037652 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.1675037652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.292327938 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 625696235 ps |
| CPU time | 53.36 seconds |
| Started | Sep 01 10:01:34 PM UTC 24 |
| Finished | Sep 01 10:02:30 PM UTC 24 |
| Peak memory | 321384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 92327938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max_ throughput.292327938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2026168265 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 46535859 ps |
| CPU time | 4.07 seconds |
| Started | Sep 01 10:02:26 PM UTC 24 |
| Finished | Sep 01 10:02:31 PM UTC 24 |
| Peak memory | 224384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026168265 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.2026168265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1993347180 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 352196886 ps |
| CPU time | 10.1 seconds |
| Started | Sep 01 10:02:14 PM UTC 24 |
| Finished | Sep 01 10:02:25 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993347180 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1993347180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.541741559 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 41632069911 ps |
| CPU time | 660.35 seconds |
| Started | Sep 01 10:00:49 PM UTC 24 |
| Finished | Sep 01 10:11:57 PM UTC 24 |
| Peak memory | 378732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541741559 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.541741559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.36397410 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 521698799 ps |
| CPU time | 56.39 seconds |
| Started | Sep 01 10:01:08 PM UTC 24 |
| Finished | Sep 01 10:02:06 PM UTC 24 |
| Peak memory | 321396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36397410 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.36397410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1884931635 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 11460846001 ps |
| CPU time | 286.03 seconds |
| Started | Sep 01 10:01:24 PM UTC 24 |
| Finished | Sep 01 10:06:14 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884931635 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acce ss_b2b.1884931635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1294550198 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 30062498 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 10:02:11 PM UTC 24 |
| Finished | Sep 01 10:02:13 PM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294550198 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1294550198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2202648433 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 28042323666 ps |
| CPU time | 1341.94 seconds |
| Started | Sep 01 10:02:08 PM UTC 24 |
| Finished | Sep 01 10:24:45 PM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202648433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2202648433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.654379386 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 906828731 ps |
| CPU time | 24.37 seconds |
| Started | Sep 01 10:00:39 PM UTC 24 |
| Finished | Sep 01 10:01:04 PM UTC 24 |
| Peak memory | 213976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654379386 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.654379386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1072453971 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 587980958827 ps |
| CPU time | 4710.77 seconds |
| Started | Sep 01 10:02:28 PM UTC 24 |
| Finished | Sep 01 11:21:48 PM UTC 24 |
| Peak memory | 388792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107245397 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.1072453971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2442734698 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 10495403792 ps |
| CPU time | 323.39 seconds |
| Started | Sep 01 10:01:05 PM UTC 24 |
| Finished | Sep 01 10:06:33 PM UTC 24 |
| Peak memory | 214284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442734698 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.2442734698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2778635388 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 364934159 ps |
| CPU time | 9.35 seconds |
| Started | Sep 01 10:01:59 PM UTC 24 |
| Finished | Sep 01 10:02:10 PM UTC 24 |
| Peak memory | 263976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2778635388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th roughput_w_partial_write.2778635388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
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