| T551 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2323642577 |
|
|
Sep 01 10:37:11 PM UTC 24 |
Sep 01 10:37:24 PM UTC 24 |
597535861 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2691100039 |
|
|
Sep 01 10:37:22 PM UTC 24 |
Sep 01 10:37:24 PM UTC 24 |
341197080 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.857733844 |
|
|
Sep 01 10:35:34 PM UTC 24 |
Sep 01 10:37:26 PM UTC 24 |
669210666 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3344088114 |
|
|
Sep 01 10:29:47 PM UTC 24 |
Sep 01 10:37:26 PM UTC 24 |
6382373621 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1957554222 |
|
|
Sep 01 10:37:04 PM UTC 24 |
Sep 01 10:37:27 PM UTC 24 |
93844563 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2628229918 |
|
|
Sep 01 10:37:28 PM UTC 24 |
Sep 01 10:37:30 PM UTC 24 |
52057491 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1500761660 |
|
|
Sep 01 10:37:25 PM UTC 24 |
Sep 01 10:37:34 PM UTC 24 |
366339657 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1683288992 |
|
|
Sep 01 10:37:25 PM UTC 24 |
Sep 01 10:37:38 PM UTC 24 |
136507092 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3135592144 |
|
|
Sep 01 10:32:50 PM UTC 24 |
Sep 01 10:37:49 PM UTC 24 |
2800588195 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.233508457 |
|
|
Sep 01 10:13:58 PM UTC 24 |
Sep 01 10:37:54 PM UTC 24 |
6542191967 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3796547242 |
|
|
Sep 01 10:26:28 PM UTC 24 |
Sep 01 10:37:59 PM UTC 24 |
8174000081 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.480471712 |
|
|
Sep 01 10:36:54 PM UTC 24 |
Sep 01 10:38:02 PM UTC 24 |
1210199973 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1104912578 |
|
|
Sep 01 10:36:42 PM UTC 24 |
Sep 01 10:38:02 PM UTC 24 |
706410308 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3013570061 |
|
|
Sep 01 10:31:21 PM UTC 24 |
Sep 01 10:38:04 PM UTC 24 |
14027449441 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2569908952 |
|
|
Sep 01 10:37:55 PM UTC 24 |
Sep 01 10:38:04 PM UTC 24 |
279943600 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2763253275 |
|
|
Sep 01 10:38:05 PM UTC 24 |
Sep 01 10:38:12 PM UTC 24 |
317207294 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1776862236 |
|
|
Sep 01 10:38:02 PM UTC 24 |
Sep 01 10:38:27 PM UTC 24 |
301229880 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.4273571578 |
|
|
Sep 01 10:37:31 PM UTC 24 |
Sep 01 10:38:31 PM UTC 24 |
389301046 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2660841886 |
|
|
Sep 01 10:38:32 PM UTC 24 |
Sep 01 10:38:34 PM UTC 24 |
71870468 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.93410544 |
|
|
Sep 01 10:38:35 PM UTC 24 |
Sep 01 10:38:51 PM UTC 24 |
1467973954 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.1303062005 |
|
|
Sep 01 10:36:45 PM UTC 24 |
Sep 01 10:38:55 PM UTC 24 |
3246793820 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1386761219 |
|
|
Sep 01 10:38:51 PM UTC 24 |
Sep 01 10:39:00 PM UTC 24 |
1306404521 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1648551470 |
|
|
Sep 01 10:37:39 PM UTC 24 |
Sep 01 10:39:05 PM UTC 24 |
9623152205 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1626886654 |
|
|
Sep 01 10:38:03 PM UTC 24 |
Sep 01 10:39:07 PM UTC 24 |
2363648124 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.989229298 |
|
|
Sep 01 10:39:06 PM UTC 24 |
Sep 01 10:39:08 PM UTC 24 |
81904197 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3034586038 |
|
|
Sep 01 10:13:37 PM UTC 24 |
Sep 01 10:39:10 PM UTC 24 |
7016925183 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1177769683 |
|
|
Sep 01 10:39:08 PM UTC 24 |
Sep 01 10:39:19 PM UTC 24 |
137970221 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2803841440 |
|
|
Sep 01 10:25:12 PM UTC 24 |
Sep 01 10:39:26 PM UTC 24 |
13367955295 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.2068087097 |
|
|
Sep 01 10:14:53 PM UTC 24 |
Sep 01 10:39:29 PM UTC 24 |
21091731132 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2945115695 |
|
|
Sep 01 10:39:11 PM UTC 24 |
Sep 01 10:39:46 PM UTC 24 |
3570867382 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1296328467 |
|
|
Sep 01 10:39:27 PM UTC 24 |
Sep 01 10:39:53 PM UTC 24 |
2060361712 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3797240708 |
|
|
Sep 01 10:37:26 PM UTC 24 |
Sep 01 10:40:16 PM UTC 24 |
5083082117 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3078425964 |
|
|
Sep 01 10:39:47 PM UTC 24 |
Sep 01 10:40:18 PM UTC 24 |
343510620 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1521128885 |
|
|
Sep 01 10:40:17 PM UTC 24 |
Sep 01 10:40:22 PM UTC 24 |
1846954956 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1221357283 |
|
|
Sep 01 10:39:09 PM UTC 24 |
Sep 01 10:40:23 PM UTC 24 |
516391972 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.92896108 |
|
|
Sep 01 10:22:25 PM UTC 24 |
Sep 01 10:40:24 PM UTC 24 |
4692751472 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1419715878 |
|
|
Sep 01 10:34:37 PM UTC 24 |
Sep 01 10:40:27 PM UTC 24 |
12744213636 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3754342870 |
|
|
Sep 01 10:39:54 PM UTC 24 |
Sep 01 10:40:27 PM UTC 24 |
211574763 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3456249883 |
|
|
Sep 01 10:40:25 PM UTC 24 |
Sep 01 10:40:27 PM UTC 24 |
327748103 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3577070704 |
|
|
Sep 01 10:22:17 PM UTC 24 |
Sep 01 10:40:31 PM UTC 24 |
6673353984 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3811349926 |
|
|
Sep 01 10:40:28 PM UTC 24 |
Sep 01 10:40:33 PM UTC 24 |
190173293 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1821152179 |
|
|
Sep 01 10:40:28 PM UTC 24 |
Sep 01 10:40:34 PM UTC 24 |
146327722 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1506618641 |
|
|
Sep 01 10:40:34 PM UTC 24 |
Sep 01 10:40:36 PM UTC 24 |
12884084 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.501896049 |
|
|
Sep 01 10:40:35 PM UTC 24 |
Sep 01 10:40:46 PM UTC 24 |
719505594 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.4051223644 |
|
|
Sep 01 10:27:24 PM UTC 24 |
Sep 01 10:40:49 PM UTC 24 |
46169993038 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3282507099 |
|
|
Sep 01 10:17:54 PM UTC 24 |
Sep 01 10:40:49 PM UTC 24 |
3614459670 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1781512999 |
|
|
Sep 01 10:37:01 PM UTC 24 |
Sep 01 10:41:05 PM UTC 24 |
2842203560 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3585746293 |
|
|
Sep 01 10:28:19 PM UTC 24 |
Sep 01 10:41:06 PM UTC 24 |
7864980765 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3998680583 |
|
|
Sep 01 10:35:03 PM UTC 24 |
Sep 01 10:46:07 PM UTC 24 |
2526499517 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.445567698 |
|
|
Sep 01 10:35:45 PM UTC 24 |
Sep 01 10:41:25 PM UTC 24 |
8966415616 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3147667209 |
|
|
Sep 01 10:41:25 PM UTC 24 |
Sep 01 10:41:28 PM UTC 24 |
37705650 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.919222841 |
|
|
Sep 01 10:41:07 PM UTC 24 |
Sep 01 10:41:30 PM UTC 24 |
85630146 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.869481912 |
|
|
Sep 01 10:38:56 PM UTC 24 |
Sep 01 10:41:30 PM UTC 24 |
630572981 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.3850044451 |
|
|
Sep 01 10:40:46 PM UTC 24 |
Sep 01 10:41:41 PM UTC 24 |
1758725791 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2713927633 |
|
|
Sep 01 10:41:25 PM UTC 24 |
Sep 01 10:41:43 PM UTC 24 |
698032357 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3399876592 |
|
|
Sep 01 10:41:42 PM UTC 24 |
Sep 01 10:41:44 PM UTC 24 |
113026881 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1532888476 |
|
|
Sep 01 10:24:15 PM UTC 24 |
Sep 01 10:41:46 PM UTC 24 |
6169590479 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.3474493490 |
|
|
Sep 01 10:41:45 PM UTC 24 |
Sep 01 10:41:51 PM UTC 24 |
396199404 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.552326429 |
|
|
Sep 01 10:24:25 PM UTC 24 |
Sep 01 10:41:53 PM UTC 24 |
17618040487 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.4189463240 |
|
|
Sep 01 10:41:54 PM UTC 24 |
Sep 01 10:41:56 PM UTC 24 |
32560325 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1977903916 |
|
|
Sep 01 10:41:44 PM UTC 24 |
Sep 01 10:41:56 PM UTC 24 |
1443184773 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2125217184 |
|
|
Sep 01 10:41:47 PM UTC 24 |
Sep 01 10:41:58 PM UTC 24 |
266599891 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.3940658148 |
|
|
Sep 01 10:41:57 PM UTC 24 |
Sep 01 10:42:03 PM UTC 24 |
52842864 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.4139434646 |
|
|
Sep 01 10:35:50 PM UTC 24 |
Sep 01 10:42:17 PM UTC 24 |
61891596654 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1298560910 |
|
|
Sep 01 10:42:18 PM UTC 24 |
Sep 01 10:42:24 PM UTC 24 |
116190681 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.4005955406 |
|
|
Sep 01 10:33:05 PM UTC 24 |
Sep 01 10:42:29 PM UTC 24 |
16965804235 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2465839286 |
|
|
Sep 01 10:46:04 PM UTC 24 |
Sep 01 10:46:06 PM UTC 24 |
82147377 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.4200759618 |
|
|
Sep 01 10:28:38 PM UTC 24 |
Sep 01 10:42:29 PM UTC 24 |
5444107310 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.624138386 |
|
|
Sep 01 10:42:30 PM UTC 24 |
Sep 01 10:42:35 PM UTC 24 |
485525567 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1556394994 |
|
|
Sep 01 10:42:30 PM UTC 24 |
Sep 01 10:42:38 PM UTC 24 |
279843896 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2597348061 |
|
|
Sep 01 10:37:50 PM UTC 24 |
Sep 01 10:42:43 PM UTC 24 |
33973957559 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.885844493 |
|
|
Sep 01 10:40:50 PM UTC 24 |
Sep 01 10:42:54 PM UTC 24 |
646114936 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.921621013 |
|
|
Sep 01 10:42:55 PM UTC 24 |
Sep 01 10:42:57 PM UTC 24 |
33855292 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2127372153 |
|
|
Sep 01 10:42:30 PM UTC 24 |
Sep 01 10:42:57 PM UTC 24 |
360157108 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.343425456 |
|
|
Sep 01 10:42:58 PM UTC 24 |
Sep 01 10:43:04 PM UTC 24 |
195371653 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3966345797 |
|
|
Sep 01 10:42:58 PM UTC 24 |
Sep 01 10:43:07 PM UTC 24 |
96973476 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2321685088 |
|
|
Sep 01 10:40:37 PM UTC 24 |
Sep 01 10:43:09 PM UTC 24 |
3314061576 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1786911086 |
|
|
Sep 01 10:43:09 PM UTC 24 |
Sep 01 10:43:11 PM UTC 24 |
38437949 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2771920419 |
|
|
Sep 01 10:43:05 PM UTC 24 |
Sep 01 10:43:17 PM UTC 24 |
802237949 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.710500453 |
|
|
Sep 01 10:36:56 PM UTC 24 |
Sep 01 10:43:27 PM UTC 24 |
11991291372 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.1360373877 |
|
|
Sep 01 10:43:12 PM UTC 24 |
Sep 01 10:43:29 PM UTC 24 |
637382904 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.380566657 |
|
|
Sep 01 10:41:59 PM UTC 24 |
Sep 01 10:43:31 PM UTC 24 |
7493842323 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1524710973 |
|
|
Sep 01 10:34:39 PM UTC 24 |
Sep 01 10:43:33 PM UTC 24 |
71431574810 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3271345323 |
|
|
Sep 01 10:00:35 PM UTC 24 |
Sep 01 10:43:42 PM UTC 24 |
30383133895 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1170280953 |
|
|
Sep 01 10:43:43 PM UTC 24 |
Sep 01 10:43:48 PM UTC 24 |
73238558 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.4214415060 |
|
|
Sep 01 10:43:49 PM UTC 24 |
Sep 01 10:44:02 PM UTC 24 |
125169545 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.1453595825 |
|
|
Sep 01 10:43:28 PM UTC 24 |
Sep 01 10:44:03 PM UTC 24 |
7567250234 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1258017955 |
|
|
Sep 01 10:43:33 PM UTC 24 |
Sep 01 10:44:17 PM UTC 24 |
282737364 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1793907515 |
|
|
Sep 01 10:44:02 PM UTC 24 |
Sep 01 10:44:21 PM UTC 24 |
1813472999 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1946198949 |
|
|
Sep 01 10:40:19 PM UTC 24 |
Sep 01 10:44:35 PM UTC 24 |
1616476948 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3562577756 |
|
|
Sep 01 10:39:20 PM UTC 24 |
Sep 01 10:44:37 PM UTC 24 |
5621864758 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.176567706 |
|
|
Sep 01 10:44:36 PM UTC 24 |
Sep 01 10:44:38 PM UTC 24 |
28183736 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2152451900 |
|
|
Sep 01 10:44:39 PM UTC 24 |
Sep 01 10:44:44 PM UTC 24 |
161850398 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2443231362 |
|
|
Sep 01 10:44:38 PM UTC 24 |
Sep 01 10:44:46 PM UTC 24 |
1063404313 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2432169635 |
|
|
Sep 01 10:38:05 PM UTC 24 |
Sep 01 10:44:46 PM UTC 24 |
4658818237 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.4051076677 |
|
|
Sep 01 10:44:48 PM UTC 24 |
Sep 01 10:44:50 PM UTC 24 |
25426782 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1601450612 |
|
|
Sep 01 10:37:27 PM UTC 24 |
Sep 01 10:45:01 PM UTC 24 |
5971629815 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.16715126 |
|
|
Sep 01 10:44:51 PM UTC 24 |
Sep 01 10:45:15 PM UTC 24 |
1033090811 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3319496203 |
|
|
Sep 01 10:39:30 PM UTC 24 |
Sep 01 10:45:28 PM UTC 24 |
4182536991 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3391357100 |
|
|
Sep 01 10:42:04 PM UTC 24 |
Sep 01 10:45:32 PM UTC 24 |
6889950022 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.4115566481 |
|
|
Sep 01 10:31:42 PM UTC 24 |
Sep 01 10:45:47 PM UTC 24 |
9076030642 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3223117517 |
|
|
Sep 01 10:31:41 PM UTC 24 |
Sep 01 10:45:48 PM UTC 24 |
10897520348 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3074520620 |
|
|
Sep 01 10:06:34 PM UTC 24 |
Sep 01 10:45:52 PM UTC 24 |
7834394292 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.596684512 |
|
|
Sep 01 10:45:49 PM UTC 24 |
Sep 01 10:45:52 PM UTC 24 |
87116189 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.2005082453 |
|
|
Sep 01 10:19:34 PM UTC 24 |
Sep 01 10:45:53 PM UTC 24 |
44299024777 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3156477581 |
|
|
Sep 01 10:41:31 PM UTC 24 |
Sep 01 10:46:00 PM UTC 24 |
481913947 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.585717481 |
|
|
Sep 01 10:45:53 PM UTC 24 |
Sep 01 10:46:02 PM UTC 24 |
1461305099 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1021901326 |
|
|
Sep 01 10:45:33 PM UTC 24 |
Sep 01 10:46:03 PM UTC 24 |
4217452719 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.2865365931 |
|
|
Sep 01 10:45:53 PM UTC 24 |
Sep 01 10:46:08 PM UTC 24 |
272314817 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1142936657 |
|
|
Sep 01 10:46:08 PM UTC 24 |
Sep 01 10:46:14 PM UTC 24 |
59241922 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2082343787 |
|
|
Sep 01 10:45:16 PM UTC 24 |
Sep 01 10:46:24 PM UTC 24 |
5834110230 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1064087230 |
|
|
Sep 01 10:46:07 PM UTC 24 |
Sep 01 10:46:24 PM UTC 24 |
2170574961 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.822378169 |
|
|
Sep 01 10:46:25 PM UTC 24 |
Sep 01 10:46:27 PM UTC 24 |
16406568 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2888156936 |
|
|
Sep 01 10:33:27 PM UTC 24 |
Sep 01 10:46:28 PM UTC 24 |
2589268406 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.39291915 |
|
|
Sep 01 10:18:37 PM UTC 24 |
Sep 01 10:46:37 PM UTC 24 |
87159250350 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.866039285 |
|
|
Sep 01 10:31:54 PM UTC 24 |
Sep 01 10:46:38 PM UTC 24 |
3363226483 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.1459956433 |
|
|
Sep 01 10:46:25 PM UTC 24 |
Sep 01 10:46:50 PM UTC 24 |
4235415435 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.729096953 |
|
|
Sep 01 10:46:38 PM UTC 24 |
Sep 01 10:46:55 PM UTC 24 |
1651858145 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3546147459 |
|
|
Sep 01 10:46:08 PM UTC 24 |
Sep 01 10:47:05 PM UTC 24 |
6819398999 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.1750915235 |
|
|
Sep 01 10:46:29 PM UTC 24 |
Sep 01 10:47:07 PM UTC 24 |
10102438345 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.42444594 |
|
|
Sep 01 10:36:45 PM UTC 24 |
Sep 01 10:47:17 PM UTC 24 |
11552707890 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1116830750 |
|
|
Sep 01 10:47:08 PM UTC 24 |
Sep 01 10:47:23 PM UTC 24 |
1007289812 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2513739505 |
|
|
Sep 01 10:40:50 PM UTC 24 |
Sep 01 10:47:35 PM UTC 24 |
14225847976 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2238368239 |
|
|
Sep 01 10:41:06 PM UTC 24 |
Sep 01 10:47:51 PM UTC 24 |
12459340858 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2891391817 |
|
|
Sep 01 10:47:51 PM UTC 24 |
Sep 01 10:47:54 PM UTC 24 |
83133479 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2430815337 |
|
|
Sep 01 10:45:29 PM UTC 24 |
Sep 01 10:47:57 PM UTC 24 |
1065183322 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1599510916 |
|
|
Sep 01 10:46:56 PM UTC 24 |
Sep 01 10:47:58 PM UTC 24 |
658942068 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.1243141473 |
|
|
Sep 01 10:47:55 PM UTC 24 |
Sep 01 10:48:04 PM UTC 24 |
231469835 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.532224216 |
|
|
Sep 01 10:47:58 PM UTC 24 |
Sep 01 10:48:06 PM UTC 24 |
67351669 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3949920941 |
|
|
Sep 01 10:48:07 PM UTC 24 |
Sep 01 10:48:09 PM UTC 24 |
32870248 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.339258106 |
|
|
Sep 01 10:47:59 PM UTC 24 |
Sep 01 10:48:12 PM UTC 24 |
262539753 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2131604808 |
|
|
Sep 01 10:48:10 PM UTC 24 |
Sep 01 10:48:22 PM UTC 24 |
190351710 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.735505233 |
|
|
Sep 01 11:00:18 PM UTC 24 |
Sep 01 11:00:59 PM UTC 24 |
5942444490 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.715871536 |
|
|
Sep 01 10:47:06 PM UTC 24 |
Sep 01 10:48:24 PM UTC 24 |
438317492 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.207788496 |
|
|
Sep 01 10:43:30 PM UTC 24 |
Sep 01 10:48:34 PM UTC 24 |
2486094716 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.30293291 |
|
|
Sep 01 10:12:17 PM UTC 24 |
Sep 01 10:48:34 PM UTC 24 |
26801586923 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1501941378 |
|
|
Sep 01 10:48:25 PM UTC 24 |
Sep 01 10:48:41 PM UTC 24 |
590660624 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1007624539 |
|
|
Sep 01 10:48:41 PM UTC 24 |
Sep 01 10:48:54 PM UTC 24 |
173611132 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.916097093 |
|
|
Sep 01 10:48:55 PM UTC 24 |
Sep 01 10:49:05 PM UTC 24 |
401308184 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.1510549755 |
|
|
Sep 01 10:48:22 PM UTC 24 |
Sep 01 10:49:24 PM UTC 24 |
791641966 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3324860854 |
|
|
Sep 01 10:38:00 PM UTC 24 |
Sep 01 10:49:33 PM UTC 24 |
29143637003 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.1450422547 |
|
|
Sep 01 10:33:31 PM UTC 24 |
Sep 01 10:49:43 PM UTC 24 |
11789867382 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2774412505 |
|
|
Sep 01 10:49:44 PM UTC 24 |
Sep 01 10:49:46 PM UTC 24 |
38796518 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3382806216 |
|
|
Sep 01 10:04:32 PM UTC 24 |
Sep 01 10:49:48 PM UTC 24 |
6547975706 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.206594707 |
|
|
Sep 01 10:49:48 PM UTC 24 |
Sep 01 10:49:53 PM UTC 24 |
48169065 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.650501116 |
|
|
Sep 01 10:37:35 PM UTC 24 |
Sep 01 10:49:59 PM UTC 24 |
2258855758 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.2456060380 |
|
|
Sep 01 10:49:47 PM UTC 24 |
Sep 01 10:50:01 PM UTC 24 |
916726570 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1932288587 |
|
|
Sep 01 10:50:00 PM UTC 24 |
Sep 01 10:50:02 PM UTC 24 |
27447962 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3568352252 |
|
|
Sep 01 10:48:35 PM UTC 24 |
Sep 01 10:50:21 PM UTC 24 |
252233690 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.4042259595 |
|
|
Sep 01 10:50:01 PM UTC 24 |
Sep 01 10:50:27 PM UTC 24 |
1469651736 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4059418367 |
|
|
Sep 01 10:44:45 PM UTC 24 |
Sep 01 10:50:28 PM UTC 24 |
6089830162 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.858152517 |
|
|
Sep 01 10:44:03 PM UTC 24 |
Sep 01 10:50:38 PM UTC 24 |
4180007085 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3799415367 |
|
|
Sep 01 10:34:54 PM UTC 24 |
Sep 01 10:50:40 PM UTC 24 |
4068437823 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.717515746 |
|
|
Sep 01 10:50:41 PM UTC 24 |
Sep 01 10:50:52 PM UTC 24 |
58117138 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.684341946 |
|
|
Sep 01 10:43:34 PM UTC 24 |
Sep 01 10:50:52 PM UTC 24 |
10773914715 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3832128320 |
|
|
Sep 01 10:50:29 PM UTC 24 |
Sep 01 10:50:59 PM UTC 24 |
965997710 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1893332084 |
|
|
Sep 01 10:50:53 PM UTC 24 |
Sep 01 10:50:59 PM UTC 24 |
270427816 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.898886755 |
|
|
Sep 01 10:50:52 PM UTC 24 |
Sep 01 10:51:07 PM UTC 24 |
142826558 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1656503192 |
|
|
Sep 01 10:50:22 PM UTC 24 |
Sep 01 10:51:09 PM UTC 24 |
2475705546 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3506558026 |
|
|
Sep 01 10:51:10 PM UTC 24 |
Sep 01 10:51:12 PM UTC 24 |
29347918 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.4011030233 |
|
|
Sep 01 10:51:13 PM UTC 24 |
Sep 01 10:51:22 PM UTC 24 |
295676397 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.4179023202 |
|
|
Sep 01 10:51:23 PM UTC 24 |
Sep 01 10:51:30 PM UTC 24 |
68700464 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1924073082 |
|
|
Sep 01 10:41:29 PM UTC 24 |
Sep 01 10:51:31 PM UTC 24 |
8018132185 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2572937603 |
|
|
Sep 01 10:36:54 PM UTC 24 |
Sep 01 10:51:32 PM UTC 24 |
2737959382 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3091755869 |
|
|
Sep 01 10:51:33 PM UTC 24 |
Sep 01 10:51:35 PM UTC 24 |
38859558 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2478370619 |
|
|
Sep 01 10:35:34 PM UTC 24 |
Sep 01 10:51:52 PM UTC 24 |
10265486365 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.323440876 |
|
|
Sep 01 10:46:03 PM UTC 24 |
Sep 01 10:52:02 PM UTC 24 |
12103503615 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.172235383 |
|
|
Sep 01 10:42:25 PM UTC 24 |
Sep 01 10:52:24 PM UTC 24 |
87555036841 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.2188937438 |
|
|
Sep 01 10:42:44 PM UTC 24 |
Sep 01 10:52:31 PM UTC 24 |
13336557884 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2093588992 |
|
|
Sep 01 10:52:31 PM UTC 24 |
Sep 01 10:52:38 PM UTC 24 |
138031487 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3184371380 |
|
|
Sep 01 10:29:36 PM UTC 24 |
Sep 01 10:52:41 PM UTC 24 |
2972369883 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.2371185284 |
|
|
Sep 01 10:52:02 PM UTC 24 |
Sep 01 10:52:53 PM UTC 24 |
14961855137 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.914173507 |
|
|
Sep 01 10:48:35 PM UTC 24 |
Sep 01 10:52:55 PM UTC 24 |
28979037029 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.595063127 |
|
|
Sep 01 10:42:36 PM UTC 24 |
Sep 01 10:52:59 PM UTC 24 |
11330674225 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.225626216 |
|
|
Sep 01 10:52:56 PM UTC 24 |
Sep 01 10:53:14 PM UTC 24 |
2658778157 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.3601540905 |
|
|
Sep 01 10:37:20 PM UTC 24 |
Sep 01 10:53:20 PM UTC 24 |
12290217827 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.4106856501 |
|
|
Sep 01 10:46:38 PM UTC 24 |
Sep 01 10:53:28 PM UTC 24 |
3579635699 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1664022549 |
|
|
Sep 01 10:53:28 PM UTC 24 |
Sep 01 10:53:30 PM UTC 24 |
36135456 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.3761324865 |
|
|
Sep 01 10:50:28 PM UTC 24 |
Sep 01 10:53:36 PM UTC 24 |
7497406303 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2229204187 |
|
|
Sep 01 10:53:31 PM UTC 24 |
Sep 01 10:53:40 PM UTC 24 |
2476571333 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.654577699 |
|
|
Sep 01 10:52:42 PM UTC 24 |
Sep 01 10:53:43 PM UTC 24 |
474011007 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.1043587588 |
|
|
Sep 01 10:53:38 PM UTC 24 |
Sep 01 10:53:44 PM UTC 24 |
173062503 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.107602055 |
|
|
Sep 01 10:53:45 PM UTC 24 |
Sep 01 10:53:47 PM UTC 24 |
17547841 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1440740455 |
|
|
Sep 01 10:45:54 PM UTC 24 |
Sep 01 10:53:52 PM UTC 24 |
1843086976 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2859031116 |
|
|
Sep 01 10:51:36 PM UTC 24 |
Sep 01 10:53:52 PM UTC 24 |
2638669441 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.314972485 |
|
|
Sep 01 10:51:31 PM UTC 24 |
Sep 01 10:53:55 PM UTC 24 |
2041442024 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1879246127 |
|
|
Sep 01 10:48:25 PM UTC 24 |
Sep 01 10:53:58 PM UTC 24 |
5984322360 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2542324039 |
|
|
Sep 01 10:31:01 PM UTC 24 |
Sep 01 10:54:03 PM UTC 24 |
57419215446 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2281336934 |
|
|
Sep 01 10:29:27 PM UTC 24 |
Sep 01 10:54:11 PM UTC 24 |
20061825455 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.285141181 |
|
|
Sep 01 10:54:12 PM UTC 24 |
Sep 01 10:54:24 PM UTC 24 |
210213078 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.233803257 |
|
|
Sep 01 10:53:48 PM UTC 24 |
Sep 01 10:54:33 PM UTC 24 |
534917133 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.1908160873 |
|
|
Sep 01 10:41:32 PM UTC 24 |
Sep 01 10:54:41 PM UTC 24 |
6709720402 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2258302464 |
|
|
Sep 01 10:54:34 PM UTC 24 |
Sep 01 10:54:43 PM UTC 24 |
987269324 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.132614566 |
|
|
Sep 01 10:52:54 PM UTC 24 |
Sep 01 10:54:55 PM UTC 24 |
613432512 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3714593595 |
|
|
Sep 01 10:27:04 PM UTC 24 |
Sep 01 10:54:56 PM UTC 24 |
85888574325 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3031127396 |
|
|
Sep 01 10:51:01 PM UTC 24 |
Sep 01 10:54:57 PM UTC 24 |
1678187992 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3106847309 |
|
|
Sep 01 10:38:13 PM UTC 24 |
Sep 01 10:54:57 PM UTC 24 |
70205782951 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1421189518 |
|
|
Sep 01 10:53:58 PM UTC 24 |
Sep 01 10:54:58 PM UTC 24 |
676521063 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1851513593 |
|
|
Sep 01 10:54:58 PM UTC 24 |
Sep 01 10:55:00 PM UTC 24 |
90255123 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.125889424 |
|
|
Sep 01 10:54:59 PM UTC 24 |
Sep 01 10:55:07 PM UTC 24 |
601312972 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.939688772 |
|
|
Sep 01 10:55:08 PM UTC 24 |
Sep 01 10:55:10 PM UTC 24 |
37001968 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1794625796 |
|
|
Sep 01 10:44:18 PM UTC 24 |
Sep 01 10:55:10 PM UTC 24 |
7255685097 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.616519037 |
|
|
Sep 01 10:54:58 PM UTC 24 |
Sep 01 10:55:13 PM UTC 24 |
831719402 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3857476569 |
|
|
Sep 01 10:54:25 PM UTC 24 |
Sep 01 10:55:14 PM UTC 24 |
281573681 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2932907313 |
|
|
Sep 01 10:50:39 PM UTC 24 |
Sep 01 10:55:20 PM UTC 24 |
34030501927 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2615952261 |
|
|
Sep 01 10:55:15 PM UTC 24 |
Sep 01 10:55:22 PM UTC 24 |
122379961 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3721252675 |
|
|
Sep 01 10:53:53 PM UTC 24 |
Sep 01 10:55:33 PM UTC 24 |
3545301025 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.533709014 |
|
|
Sep 01 10:55:11 PM UTC 24 |
Sep 01 10:55:35 PM UTC 24 |
5483162190 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2805466247 |
|
|
Sep 01 10:55:36 PM UTC 24 |
Sep 01 10:55:41 PM UTC 24 |
481054243 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3628587680 |
|
|
Sep 01 10:52:24 PM UTC 24 |
Sep 01 10:55:45 PM UTC 24 |
3894091277 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1594313929 |
|
|
Sep 01 10:45:48 PM UTC 24 |
Sep 01 10:55:52 PM UTC 24 |
204637832430 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.781571444 |
|
|
Sep 01 10:55:12 PM UTC 24 |
Sep 01 10:56:11 PM UTC 24 |
2605847736 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.471437912 |
|
|
Sep 01 10:56:12 PM UTC 24 |
Sep 01 10:56:14 PM UTC 24 |
81775406 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.1375730112 |
|
|
Sep 01 10:38:28 PM UTC 24 |
Sep 01 10:56:24 PM UTC 24 |
20305226294 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3132906680 |
|
|
Sep 01 10:56:15 PM UTC 24 |
Sep 01 10:56:30 PM UTC 24 |
898310324 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.2726894981 |
|
|
Sep 01 10:53:21 PM UTC 24 |
Sep 01 10:56:31 PM UTC 24 |
4222945387 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.867410333 |
|
|
Sep 01 10:55:23 PM UTC 24 |
Sep 01 10:56:32 PM UTC 24 |
128649743 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.298821088 |
|
|
Sep 01 10:56:25 PM UTC 24 |
Sep 01 10:56:33 PM UTC 24 |
312306596 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.3734170396 |
|
|
Sep 01 10:42:39 PM UTC 24 |
Sep 01 10:56:33 PM UTC 24 |
8739443428 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3944038377 |
|
|
Sep 01 10:56:32 PM UTC 24 |
Sep 01 10:56:34 PM UTC 24 |
108291037 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.2161071566 |
|
|
Sep 01 10:56:33 PM UTC 24 |
Sep 01 10:56:50 PM UTC 24 |
558533420 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1457078781 |
|
|
Sep 01 10:51:08 PM UTC 24 |
Sep 01 10:56:52 PM UTC 24 |
1513566733 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.4218482617 |
|
|
Sep 01 10:53:42 PM UTC 24 |
Sep 01 10:56:55 PM UTC 24 |
1303706405 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1802556950 |
|
|
Sep 01 10:39:02 PM UTC 24 |
Sep 01 10:57:01 PM UTC 24 |
7000755203 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2034212180 |
|
|
Sep 01 10:46:52 PM UTC 24 |
Sep 01 10:57:17 PM UTC 24 |
181383830969 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1490385898 |
|
|
Sep 01 10:32:33 PM UTC 24 |
Sep 01 10:57:34 PM UTC 24 |
15115973879 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1041553197 |
|
|
Sep 01 10:55:33 PM UTC 24 |
Sep 01 10:57:34 PM UTC 24 |
872907330 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.513137460 |
|
|
Sep 01 10:57:34 PM UTC 24 |
Sep 01 10:57:43 PM UTC 24 |
585949690 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.600358786 |
|
|
Sep 01 10:56:36 PM UTC 24 |
Sep 01 10:57:53 PM UTC 24 |
3748169639 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.4005418455 |
|
|
Sep 01 10:55:46 PM UTC 24 |
Sep 01 10:57:57 PM UTC 24 |
3569194428 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1761289340 |
|
|
Sep 01 10:57:17 PM UTC 24 |
Sep 01 10:57:58 PM UTC 24 |
130001419 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3204709882 |
|
|
Sep 01 10:57:58 PM UTC 24 |
Sep 01 10:58:00 PM UTC 24 |
27637248 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1787343406 |
|
|
Sep 01 10:56:31 PM UTC 24 |
Sep 01 10:58:08 PM UTC 24 |
5580564269 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3608984730 |
|
|
Sep 01 10:58:01 PM UTC 24 |
Sep 01 10:58:09 PM UTC 24 |
141740104 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.121720762 |
|
|
Sep 01 10:57:59 PM UTC 24 |
Sep 01 10:58:09 PM UTC 24 |
1937002950 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2570194498 |
|
|
Sep 01 10:58:10 PM UTC 24 |
Sep 01 10:58:12 PM UTC 24 |
23541936 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2509157531 |
|
|
Sep 01 10:57:02 PM UTC 24 |
Sep 01 10:58:17 PM UTC 24 |
737407874 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.11960997 |
|
|
Sep 01 10:37:16 PM UTC 24 |
Sep 01 10:58:28 PM UTC 24 |
9847379926 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.611014717 |
|
|
Sep 01 10:40:32 PM UTC 24 |
Sep 01 10:58:54 PM UTC 24 |
17479912682 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.922176233 |
|
|
Sep 01 10:55:15 PM UTC 24 |
Sep 01 10:58:59 PM UTC 24 |
7675196923 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3253309705 |
|
|
Sep 01 10:58:29 PM UTC 24 |
Sep 01 10:59:03 PM UTC 24 |
1457148764 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.958126461 |
|
|
Sep 01 10:56:53 PM UTC 24 |
Sep 01 10:59:11 PM UTC 24 |
645336411 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2339147725 |
|
|
Sep 01 10:59:00 PM UTC 24 |
Sep 01 10:59:18 PM UTC 24 |
272012737 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2027349679 |
|
|
Sep 01 10:53:56 PM UTC 24 |
Sep 01 10:59:27 PM UTC 24 |
10452784243 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.1744769511 |
|
|
Sep 01 10:54:56 PM UTC 24 |
Sep 01 10:59:30 PM UTC 24 |
12423167108 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.407039271 |
|
|
Sep 01 10:59:28 PM UTC 24 |
Sep 01 10:59:39 PM UTC 24 |
4298521757 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3983084977 |
|
|
Sep 01 10:52:40 PM UTC 24 |
Sep 01 10:59:41 PM UTC 24 |
24942250294 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3759412974 |
|
|
Sep 01 10:41:58 PM UTC 24 |
Sep 01 10:59:45 PM UTC 24 |
48762908764 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.570116707 |
|
|
Sep 01 10:59:46 PM UTC 24 |
Sep 01 10:59:48 PM UTC 24 |
79786242 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.636318043 |
|
|
Sep 01 10:59:20 PM UTC 24 |
Sep 01 10:59:58 PM UTC 24 |
421689509 ps |