| T305 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1513697476 |
|
|
Sep 04 03:55:28 PM UTC 24 |
Sep 04 03:55:35 PM UTC 24 |
356031732 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.155022162 |
|
|
Sep 04 03:43:47 PM UTC 24 |
Sep 04 03:55:35 PM UTC 24 |
49597831266 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2821315031 |
|
|
Sep 04 03:54:15 PM UTC 24 |
Sep 04 03:55:43 PM UTC 24 |
2131743960 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.4113507631 |
|
|
Sep 04 03:55:27 PM UTC 24 |
Sep 04 03:55:46 PM UTC 24 |
2744417985 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2630059847 |
|
|
Sep 04 03:55:44 PM UTC 24 |
Sep 04 03:55:46 PM UTC 24 |
41699935 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.4226470467 |
|
|
Sep 04 03:51:57 PM UTC 24 |
Sep 04 03:55:48 PM UTC 24 |
10268567152 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.2516816711 |
|
|
Sep 04 03:38:02 PM UTC 24 |
Sep 04 03:55:51 PM UTC 24 |
31299656353 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2594244888 |
|
|
Sep 04 03:47:24 PM UTC 24 |
Sep 04 03:55:51 PM UTC 24 |
10783575164 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2617335747 |
|
|
Sep 04 03:54:36 PM UTC 24 |
Sep 04 03:56:05 PM UTC 24 |
268030105 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3284684856 |
|
|
Sep 04 03:47:59 PM UTC 24 |
Sep 04 03:56:08 PM UTC 24 |
38041701088 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1732467695 |
|
|
Sep 04 03:55:52 PM UTC 24 |
Sep 04 03:56:36 PM UTC 24 |
840214132 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1620530520 |
|
|
Sep 04 03:56:36 PM UTC 24 |
Sep 04 03:56:39 PM UTC 24 |
230093863 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3657614385 |
|
|
Sep 04 03:40:57 PM UTC 24 |
Sep 04 03:56:39 PM UTC 24 |
4350905786 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.1347778512 |
|
|
Sep 04 03:55:47 PM UTC 24 |
Sep 04 03:56:39 PM UTC 24 |
402378925 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1977555682 |
|
|
Sep 04 03:56:40 PM UTC 24 |
Sep 04 03:56:51 PM UTC 24 |
1940568933 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.772717427 |
|
|
Sep 04 03:55:48 PM UTC 24 |
Sep 04 03:56:59 PM UTC 24 |
3551032082 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3602929815 |
|
|
Sep 04 03:57:00 PM UTC 24 |
Sep 04 03:57:02 PM UTC 24 |
51835941 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3534511276 |
|
|
Sep 04 03:57:03 PM UTC 24 |
Sep 04 03:57:12 PM UTC 24 |
347534978 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.4248997807 |
|
|
Sep 04 03:57:13 PM UTC 24 |
Sep 04 03:57:18 PM UTC 24 |
182834521 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2048770239 |
|
|
Sep 04 03:48:30 PM UTC 24 |
Sep 04 03:57:28 PM UTC 24 |
18239246535 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3500357442 |
|
|
Sep 04 03:57:29 PM UTC 24 |
Sep 04 03:57:31 PM UTC 24 |
26272036 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.4144752535 |
|
|
Sep 04 03:54:28 PM UTC 24 |
Sep 04 03:57:32 PM UTC 24 |
6360559640 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.907035562 |
|
|
Sep 04 03:55:21 PM UTC 24 |
Sep 04 03:57:37 PM UTC 24 |
13526606447 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2354232257 |
|
|
Sep 04 03:56:09 PM UTC 24 |
Sep 04 03:57:50 PM UTC 24 |
262699830 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.87860349 |
|
|
Sep 04 03:57:32 PM UTC 24 |
Sep 04 03:57:53 PM UTC 24 |
251248486 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3264254007 |
|
|
Sep 04 03:43:18 PM UTC 24 |
Sep 04 03:58:12 PM UTC 24 |
15958588561 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.934761625 |
|
|
Sep 04 03:49:06 PM UTC 24 |
Sep 04 03:58:19 PM UTC 24 |
108539644905 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1465031746 |
|
|
Sep 04 03:58:14 PM UTC 24 |
Sep 04 03:58:19 PM UTC 24 |
48231305 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.4109341569 |
|
|
Sep 04 03:54:30 PM UTC 24 |
Sep 04 03:58:25 PM UTC 24 |
10253626822 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.291106976 |
|
|
Sep 04 03:58:20 PM UTC 24 |
Sep 04 03:58:28 PM UTC 24 |
1019603762 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3460748197 |
|
|
Sep 04 03:39:50 PM UTC 24 |
Sep 04 03:58:32 PM UTC 24 |
3401343753 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3451906063 |
|
|
Sep 04 03:55:47 PM UTC 24 |
Sep 04 03:58:33 PM UTC 24 |
2229321458 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.3232401177 |
|
|
Sep 04 03:45:40 PM UTC 24 |
Sep 04 03:58:33 PM UTC 24 |
2600305051 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.771092969 |
|
|
Sep 04 03:57:53 PM UTC 24 |
Sep 04 03:58:34 PM UTC 24 |
142909054 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.310576378 |
|
|
Sep 04 03:57:38 PM UTC 24 |
Sep 04 03:58:36 PM UTC 24 |
9086070738 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2364667663 |
|
|
Sep 04 03:58:34 PM UTC 24 |
Sep 04 03:58:37 PM UTC 24 |
45149783 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3868260996 |
|
|
Sep 04 03:58:36 PM UTC 24 |
Sep 04 03:58:43 PM UTC 24 |
149427002 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3906674768 |
|
|
Sep 04 03:58:44 PM UTC 24 |
Sep 04 03:58:46 PM UTC 24 |
36208478 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2963206165 |
|
|
Sep 04 03:57:19 PM UTC 24 |
Sep 04 03:58:50 PM UTC 24 |
2539278539 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3281952368 |
|
|
Sep 04 03:58:34 PM UTC 24 |
Sep 04 03:58:52 PM UTC 24 |
899704528 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2194938369 |
|
|
Sep 04 03:50:29 PM UTC 24 |
Sep 04 03:59:04 PM UTC 24 |
52608556581 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.56453132 |
|
|
Sep 04 03:38:55 PM UTC 24 |
Sep 04 03:59:13 PM UTC 24 |
41878917706 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.4038504667 |
|
|
Sep 04 03:52:02 PM UTC 24 |
Sep 04 03:59:18 PM UTC 24 |
59265920025 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1137000514 |
|
|
Sep 04 03:58:20 PM UTC 24 |
Sep 04 03:59:18 PM UTC 24 |
116699531 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3145288092 |
|
|
Sep 04 03:59:19 PM UTC 24 |
Sep 04 03:59:29 PM UTC 24 |
163626860 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2332351110 |
|
|
Sep 04 03:58:47 PM UTC 24 |
Sep 04 03:59:35 PM UTC 24 |
104078314 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.516076678 |
|
|
Sep 04 03:53:09 PM UTC 24 |
Sep 04 03:59:37 PM UTC 24 |
14224124100 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3586270682 |
|
|
Sep 04 03:47:05 PM UTC 24 |
Sep 04 03:59:39 PM UTC 24 |
3574182435 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1126319938 |
|
|
Sep 04 03:59:30 PM UTC 24 |
Sep 04 03:59:40 PM UTC 24 |
3149028460 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1887437859 |
|
|
Sep 04 03:59:41 PM UTC 24 |
Sep 04 03:59:43 PM UTC 24 |
92701206 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3734686351 |
|
|
Sep 04 03:59:45 PM UTC 24 |
Sep 04 03:59:50 PM UTC 24 |
70008173 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.581209877 |
|
|
Sep 04 03:59:44 PM UTC 24 |
Sep 04 03:59:52 PM UTC 24 |
355520076 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.967974241 |
|
|
Sep 04 03:59:25 PM UTC 24 |
Sep 04 04:00:15 PM UTC 24 |
118497693 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.664553405 |
|
|
Sep 04 03:52:55 PM UTC 24 |
Sep 04 04:00:15 PM UTC 24 |
73121343829 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2092762875 |
|
|
Sep 04 04:00:16 PM UTC 24 |
Sep 04 04:00:18 PM UTC 24 |
58161267 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.272136770 |
|
|
Sep 04 04:00:16 PM UTC 24 |
Sep 04 04:00:25 PM UTC 24 |
1425029703 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.3555519313 |
|
|
Sep 04 03:53:55 PM UTC 24 |
Sep 04 04:00:28 PM UTC 24 |
6794353210 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1553111444 |
|
|
Sep 04 03:55:52 PM UTC 24 |
Sep 04 04:00:31 PM UTC 24 |
9339706469 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2373163891 |
|
|
Sep 04 03:46:23 PM UTC 24 |
Sep 04 04:00:42 PM UTC 24 |
17882232710 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3562964788 |
|
|
Sep 04 03:59:13 PM UTC 24 |
Sep 04 04:00:44 PM UTC 24 |
819823213 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.2873923435 |
|
|
Sep 04 04:00:25 PM UTC 24 |
Sep 04 04:00:46 PM UTC 24 |
1391585891 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1229468980 |
|
|
Sep 04 03:58:53 PM UTC 24 |
Sep 04 04:00:47 PM UTC 24 |
45732468296 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.240994719 |
|
|
Sep 04 03:40:57 PM UTC 24 |
Sep 04 04:00:50 PM UTC 24 |
65223066475 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.552372530 |
|
|
Sep 04 04:00:47 PM UTC 24 |
Sep 04 04:00:55 PM UTC 24 |
58988754 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2479012258 |
|
|
Sep 04 04:00:48 PM UTC 24 |
Sep 04 04:01:07 PM UTC 24 |
3296484927 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2479484465 |
|
|
Sep 04 04:00:31 PM UTC 24 |
Sep 04 04:01:25 PM UTC 24 |
242399797 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2467943300 |
|
|
Sep 04 04:01:25 PM UTC 24 |
Sep 04 04:01:28 PM UTC 24 |
215048501 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.748041283 |
|
|
Sep 04 03:52:35 PM UTC 24 |
Sep 04 04:01:38 PM UTC 24 |
4477394583 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2234462612 |
|
|
Sep 04 04:01:28 PM UTC 24 |
Sep 04 04:01:42 PM UTC 24 |
642664721 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.2589519596 |
|
|
Sep 04 04:01:39 PM UTC 24 |
Sep 04 04:01:46 PM UTC 24 |
490978973 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.517914375 |
|
|
Sep 04 03:59:39 PM UTC 24 |
Sep 04 04:01:48 PM UTC 24 |
7326891823 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1047537715 |
|
|
Sep 04 04:01:49 PM UTC 24 |
Sep 04 04:01:51 PM UTC 24 |
15733113 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3565596177 |
|
|
Sep 04 03:53:16 PM UTC 24 |
Sep 04 04:02:00 PM UTC 24 |
16489656767 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1001110993 |
|
|
Sep 04 03:57:52 PM UTC 24 |
Sep 04 04:02:02 PM UTC 24 |
2150095994 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1340385316 |
|
|
Sep 04 03:48:55 PM UTC 24 |
Sep 04 04:02:12 PM UTC 24 |
3452580207 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.755815809 |
|
|
Sep 04 03:50:55 PM UTC 24 |
Sep 04 04:02:13 PM UTC 24 |
11766855887 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.1747851117 |
|
|
Sep 04 04:01:52 PM UTC 24 |
Sep 04 04:02:13 PM UTC 24 |
76157946 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.663165686 |
|
|
Sep 04 04:00:45 PM UTC 24 |
Sep 04 04:02:24 PM UTC 24 |
289121086 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.500738466 |
|
|
Sep 04 04:02:25 PM UTC 24 |
Sep 04 04:02:31 PM UTC 24 |
192052382 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2007728995 |
|
|
Sep 04 04:02:13 PM UTC 24 |
Sep 04 04:02:39 PM UTC 24 |
883270982 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1564961462 |
|
|
Sep 04 04:00:19 PM UTC 24 |
Sep 04 04:02:44 PM UTC 24 |
8261890737 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1855168112 |
|
|
Sep 04 03:56:07 PM UTC 24 |
Sep 04 04:02:45 PM UTC 24 |
22215539212 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.203737367 |
|
|
Sep 04 04:02:40 PM UTC 24 |
Sep 04 04:02:50 PM UTC 24 |
565642299 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.4077246436 |
|
|
Sep 04 03:58:32 PM UTC 24 |
Sep 04 04:02:55 PM UTC 24 |
6334152050 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.672290555 |
|
|
Sep 04 04:02:02 PM UTC 24 |
Sep 04 04:02:59 PM UTC 24 |
2876068604 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1782100709 |
|
|
Sep 04 04:02:57 PM UTC 24 |
Sep 04 04:02:59 PM UTC 24 |
74768459 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3242007170 |
|
|
Sep 04 04:03:00 PM UTC 24 |
Sep 04 04:03:05 PM UTC 24 |
175423292 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2433111483 |
|
|
Sep 04 03:59:04 PM UTC 24 |
Sep 04 04:03:13 PM UTC 24 |
4786739783 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2621989166 |
|
|
Sep 04 04:03:00 PM UTC 24 |
Sep 04 04:03:17 PM UTC 24 |
1818067660 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.24788284 |
|
|
Sep 04 04:02:32 PM UTC 24 |
Sep 04 04:03:18 PM UTC 24 |
141869772 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.4195758057 |
|
|
Sep 04 04:03:18 PM UTC 24 |
Sep 04 04:03:20 PM UTC 24 |
80847229 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3900654356 |
|
|
Sep 04 03:54:25 PM UTC 24 |
Sep 04 04:03:21 PM UTC 24 |
19713417897 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.1734078687 |
|
|
Sep 04 03:45:38 PM UTC 24 |
Sep 04 04:03:23 PM UTC 24 |
18530789392 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.379566027 |
|
|
Sep 04 03:59:52 PM UTC 24 |
Sep 04 04:03:28 PM UTC 24 |
3960704563 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1292220848 |
|
|
Sep 04 03:51:48 PM UTC 24 |
Sep 04 04:03:29 PM UTC 24 |
10557723523 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.913921473 |
|
|
Sep 04 03:57:54 PM UTC 24 |
Sep 04 04:03:32 PM UTC 24 |
41292248600 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2732674549 |
|
|
Sep 04 03:50:47 PM UTC 24 |
Sep 04 04:03:44 PM UTC 24 |
2636846973 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3043434575 |
|
|
Sep 04 04:03:44 PM UTC 24 |
Sep 04 04:03:54 PM UTC 24 |
79789905 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3394714112 |
|
|
Sep 04 04:01:43 PM UTC 24 |
Sep 04 04:04:00 PM UTC 24 |
3380823605 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3753660079 |
|
|
Sep 04 04:03:55 PM UTC 24 |
Sep 04 04:04:02 PM UTC 24 |
297741198 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3090234571 |
|
|
Sep 04 03:34:17 PM UTC 24 |
Sep 04 04:04:07 PM UTC 24 |
46719440726 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1178053054 |
|
|
Sep 04 04:03:33 PM UTC 24 |
Sep 04 04:04:11 PM UTC 24 |
175206200 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.994761741 |
|
|
Sep 04 04:04:13 PM UTC 24 |
Sep 04 04:04:15 PM UTC 24 |
25545089 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.633725105 |
|
|
Sep 04 04:04:16 PM UTC 24 |
Sep 04 04:04:24 PM UTC 24 |
927841721 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1397418052 |
|
|
Sep 04 04:04:25 PM UTC 24 |
Sep 04 04:04:33 PM UTC 24 |
352947566 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.2324344426 |
|
|
Sep 04 04:03:22 PM UTC 24 |
Sep 04 04:04:34 PM UTC 24 |
8290906527 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.492439497 |
|
|
Sep 04 04:02:01 PM UTC 24 |
Sep 04 04:04:36 PM UTC 24 |
1825668796 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.3973115102 |
|
|
Sep 04 04:04:36 PM UTC 24 |
Sep 04 04:04:38 PM UTC 24 |
14105068 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.583197217 |
|
|
Sep 04 04:03:29 PM UTC 24 |
Sep 04 04:04:40 PM UTC 24 |
227290266 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.2798788157 |
|
|
Sep 04 04:04:37 PM UTC 24 |
Sep 04 04:04:54 PM UTC 24 |
820865879 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.2421573315 |
|
|
Sep 04 04:03:19 PM UTC 24 |
Sep 04 04:05:16 PM UTC 24 |
5774402171 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1690568525 |
|
|
Sep 04 04:05:18 PM UTC 24 |
Sep 04 04:05:34 PM UTC 24 |
602210424 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.4149072676 |
|
|
Sep 04 04:04:41 PM UTC 24 |
Sep 04 04:05:38 PM UTC 24 |
1803805954 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3323868483 |
|
|
Sep 04 03:57:32 PM UTC 24 |
Sep 04 04:05:39 PM UTC 24 |
2624955206 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3602948035 |
|
|
Sep 04 04:00:29 PM UTC 24 |
Sep 04 04:05:44 PM UTC 24 |
2981958802 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2698867981 |
|
|
Sep 04 03:53:49 PM UTC 24 |
Sep 04 04:05:46 PM UTC 24 |
2610317755 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2169905334 |
|
|
Sep 04 04:05:40 PM UTC 24 |
Sep 04 04:05:50 PM UTC 24 |
1747737854 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3438499300 |
|
|
Sep 04 04:05:40 PM UTC 24 |
Sep 04 04:05:51 PM UTC 24 |
468993022 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.1336710092 |
|
|
Sep 04 04:05:52 PM UTC 24 |
Sep 04 04:05:54 PM UTC 24 |
29593547 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.774068697 |
|
|
Sep 04 03:53:36 PM UTC 24 |
Sep 04 04:05:59 PM UTC 24 |
3643465128 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1588581997 |
|
|
Sep 04 03:55:18 PM UTC 24 |
Sep 04 04:06:00 PM UTC 24 |
2413131598 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3125007449 |
|
|
Sep 04 04:06:00 PM UTC 24 |
Sep 04 04:06:06 PM UTC 24 |
95288362 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3453237858 |
|
|
Sep 04 04:05:55 PM UTC 24 |
Sep 04 04:06:08 PM UTC 24 |
544824317 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.1900952443 |
|
|
Sep 04 03:40:57 PM UTC 24 |
Sep 04 04:06:08 PM UTC 24 |
18773040203 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2790756980 |
|
|
Sep 04 04:06:08 PM UTC 24 |
Sep 04 04:06:10 PM UTC 24 |
17454285 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.846865949 |
|
|
Sep 04 04:05:39 PM UTC 24 |
Sep 04 04:06:20 PM UTC 24 |
298238206 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3536054160 |
|
|
Sep 04 04:06:10 PM UTC 24 |
Sep 04 04:06:28 PM UTC 24 |
2520497073 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.117255383 |
|
|
Sep 04 04:02:13 PM UTC 24 |
Sep 04 04:06:32 PM UTC 24 |
9181920989 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.997992248 |
|
|
Sep 04 03:47:12 PM UTC 24 |
Sep 04 04:06:37 PM UTC 24 |
16448602359 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.872819425 |
|
|
Sep 04 04:06:33 PM UTC 24 |
Sep 04 04:06:49 PM UTC 24 |
374158808 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1526584479 |
|
|
Sep 04 03:59:19 PM UTC 24 |
Sep 04 04:06:54 PM UTC 24 |
16139839047 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3533698129 |
|
|
Sep 04 03:59:36 PM UTC 24 |
Sep 04 04:07:00 PM UTC 24 |
12069408857 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3883757199 |
|
|
Sep 04 04:06:01 PM UTC 24 |
Sep 04 04:07:11 PM UTC 24 |
2375597726 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3558298666 |
|
|
Sep 04 04:06:21 PM UTC 24 |
Sep 04 04:07:15 PM UTC 24 |
3133876371 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1827558752 |
|
|
Sep 04 04:07:00 PM UTC 24 |
Sep 04 04:07:17 PM UTC 24 |
2694687392 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2596205087 |
|
|
Sep 04 03:53:07 PM UTC 24 |
Sep 04 04:07:18 PM UTC 24 |
3238308788 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.244930380 |
|
|
Sep 04 04:03:24 PM UTC 24 |
Sep 04 04:07:19 PM UTC 24 |
2254345299 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.313251560 |
|
|
Sep 04 04:04:35 PM UTC 24 |
Sep 04 04:07:20 PM UTC 24 |
3908876345 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.641042324 |
|
|
Sep 04 04:07:19 PM UTC 24 |
Sep 04 04:07:21 PM UTC 24 |
34843266 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2854051056 |
|
|
Sep 04 04:02:15 PM UTC 24 |
Sep 04 04:07:24 PM UTC 24 |
7661469449 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1174460907 |
|
|
Sep 04 03:52:54 PM UTC 24 |
Sep 04 04:07:26 PM UTC 24 |
3575137187 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2384748348 |
|
|
Sep 04 04:07:21 PM UTC 24 |
Sep 04 04:07:29 PM UTC 24 |
1175692779 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.519975273 |
|
|
Sep 04 04:07:27 PM UTC 24 |
Sep 04 04:07:30 PM UTC 24 |
40262483 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.152332942 |
|
|
Sep 04 04:07:20 PM UTC 24 |
Sep 04 04:07:36 PM UTC 24 |
2854786238 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2883869290 |
|
|
Sep 04 04:07:29 PM UTC 24 |
Sep 04 04:07:43 PM UTC 24 |
142470715 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1371697961 |
|
|
Sep 04 04:06:54 PM UTC 24 |
Sep 04 04:07:44 PM UTC 24 |
124728827 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.65172686 |
|
|
Sep 04 04:06:49 PM UTC 24 |
Sep 04 04:07:48 PM UTC 24 |
140248065 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2376350643 |
|
|
Sep 04 04:07:45 PM UTC 24 |
Sep 04 04:08:07 PM UTC 24 |
4358109694 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3041961412 |
|
|
Sep 04 03:55:16 PM UTC 24 |
Sep 04 04:08:16 PM UTC 24 |
3025963446 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.592824982 |
|
|
Sep 04 03:56:40 PM UTC 24 |
Sep 04 04:08:17 PM UTC 24 |
2722647892 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3597770808 |
|
|
Sep 04 04:13:59 PM UTC 24 |
Sep 04 04:14:53 PM UTC 24 |
431452253 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.185609733 |
|
|
Sep 04 04:07:18 PM UTC 24 |
Sep 04 04:08:18 PM UTC 24 |
4017379242 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4045728400 |
|
|
Sep 04 04:08:08 PM UTC 24 |
Sep 04 04:08:22 PM UTC 24 |
184066861 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.126744155 |
|
|
Sep 04 04:08:18 PM UTC 24 |
Sep 04 04:08:23 PM UTC 24 |
819808704 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.496312760 |
|
|
Sep 04 04:04:55 PM UTC 24 |
Sep 04 04:08:34 PM UTC 24 |
3991282831 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.960242112 |
|
|
Sep 04 04:08:35 PM UTC 24 |
Sep 04 04:08:37 PM UTC 24 |
74002109 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1982107381 |
|
|
Sep 04 04:00:42 PM UTC 24 |
Sep 04 04:08:44 PM UTC 24 |
7548801512 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1363401759 |
|
|
Sep 04 04:08:45 PM UTC 24 |
Sep 04 04:08:50 PM UTC 24 |
1047815838 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3995468723 |
|
|
Sep 04 04:08:38 PM UTC 24 |
Sep 04 04:08:51 PM UTC 24 |
2720575816 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1110085293 |
|
|
Sep 04 03:58:51 PM UTC 24 |
Sep 04 04:08:57 PM UTC 24 |
1635922785 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.4136231270 |
|
|
Sep 04 04:08:58 PM UTC 24 |
Sep 04 04:09:00 PM UTC 24 |
17040838 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2958377361 |
|
|
Sep 04 04:07:37 PM UTC 24 |
Sep 04 04:09:02 PM UTC 24 |
1023723130 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.2628970766 |
|
|
Sep 04 04:09:01 PM UTC 24 |
Sep 04 04:09:06 PM UTC 24 |
60567137 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.797313691 |
|
|
Sep 04 04:08:51 PM UTC 24 |
Sep 04 04:09:37 PM UTC 24 |
1478634277 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1037969882 |
|
|
Sep 04 04:08:16 PM UTC 24 |
Sep 04 04:09:39 PM UTC 24 |
299201758 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.594421963 |
|
|
Sep 04 04:09:40 PM UTC 24 |
Sep 04 04:10:10 PM UTC 24 |
1009140167 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.4267087644 |
|
|
Sep 04 04:06:29 PM UTC 24 |
Sep 04 04:10:18 PM UTC 24 |
12850525103 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2767624058 |
|
|
Sep 04 03:58:37 PM UTC 24 |
Sep 04 04:10:29 PM UTC 24 |
2678463800 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2816000004 |
|
|
Sep 04 04:00:51 PM UTC 24 |
Sep 04 04:10:45 PM UTC 24 |
6358347427 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.2243194663 |
|
|
Sep 04 04:09:06 PM UTC 24 |
Sep 04 04:10:52 PM UTC 24 |
17353198618 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2077725841 |
|
|
Sep 04 04:10:45 PM UTC 24 |
Sep 04 04:10:55 PM UTC 24 |
1077973693 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1673197004 |
|
|
Sep 04 04:10:30 PM UTC 24 |
Sep 04 04:10:59 PM UTC 24 |
104364991 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2862293292 |
|
|
Sep 04 04:03:06 PM UTC 24 |
Sep 04 04:11:12 PM UTC 24 |
6138552174 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1190869199 |
|
|
Sep 04 04:11:13 PM UTC 24 |
Sep 04 04:11:15 PM UTC 24 |
48518498 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.523501751 |
|
|
Sep 04 04:03:30 PM UTC 24 |
Sep 04 04:11:19 PM UTC 24 |
18905452293 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1897484047 |
|
|
Sep 04 04:11:19 PM UTC 24 |
Sep 04 04:11:28 PM UTC 24 |
159943973 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1906092326 |
|
|
Sep 04 04:11:16 PM UTC 24 |
Sep 04 04:11:31 PM UTC 24 |
666254317 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.1472107259 |
|
|
Sep 04 04:07:44 PM UTC 24 |
Sep 04 04:11:39 PM UTC 24 |
1880431307 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2158729126 |
|
|
Sep 04 04:11:40 PM UTC 24 |
Sep 04 04:11:41 PM UTC 24 |
13062282 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3531668307 |
|
|
Sep 04 03:38:46 PM UTC 24 |
Sep 04 04:11:50 PM UTC 24 |
9805277496 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.3661411867 |
|
|
Sep 04 04:11:43 PM UTC 24 |
Sep 04 04:12:06 PM UTC 24 |
3506049001 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2579700590 |
|
|
Sep 04 04:10:18 PM UTC 24 |
Sep 04 04:12:08 PM UTC 24 |
136518762 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.386332978 |
|
|
Sep 04 04:07:49 PM UTC 24 |
Sep 04 04:12:21 PM UTC 24 |
3110081105 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1942718654 |
|
|
Sep 04 04:08:25 PM UTC 24 |
Sep 04 04:12:35 PM UTC 24 |
12415617997 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3458471510 |
|
|
Sep 04 03:56:51 PM UTC 24 |
Sep 04 04:12:38 PM UTC 24 |
52863445494 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2623126451 |
|
|
Sep 04 04:12:22 PM UTC 24 |
Sep 04 04:12:40 PM UTC 24 |
999007856 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1897740141 |
|
|
Sep 04 04:12:38 PM UTC 24 |
Sep 04 04:12:45 PM UTC 24 |
49864518 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2383118030 |
|
|
Sep 04 03:53:01 PM UTC 24 |
Sep 04 04:12:46 PM UTC 24 |
20102049795 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2095943561 |
|
|
Sep 04 04:07:22 PM UTC 24 |
Sep 04 04:12:50 PM UTC 24 |
8407923764 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3804043992 |
|
|
Sep 04 04:12:46 PM UTC 24 |
Sep 04 04:12:55 PM UTC 24 |
398967707 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.2721403684 |
|
|
Sep 04 04:01:07 PM UTC 24 |
Sep 04 04:12:55 PM UTC 24 |
52282435529 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.548916632 |
|
|
Sep 04 04:12:56 PM UTC 24 |
Sep 04 04:12:58 PM UTC 24 |
54382431 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.594354621 |
|
|
Sep 04 04:12:42 PM UTC 24 |
Sep 04 04:13:04 PM UTC 24 |
116520685 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.862995915 |
|
|
Sep 04 04:05:36 PM UTC 24 |
Sep 04 04:13:08 PM UTC 24 |
5965391545 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4294066549 |
|
|
Sep 04 04:13:04 PM UTC 24 |
Sep 04 04:13:11 PM UTC 24 |
203095473 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3901817702 |
|
|
Sep 04 04:12:07 PM UTC 24 |
Sep 04 04:13:13 PM UTC 24 |
4729334923 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1920349089 |
|
|
Sep 04 04:13:14 PM UTC 24 |
Sep 04 04:13:16 PM UTC 24 |
16121001 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2402404667 |
|
|
Sep 04 04:12:59 PM UTC 24 |
Sep 04 04:13:17 PM UTC 24 |
2731820125 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3898108904 |
|
|
Sep 04 03:49:48 PM UTC 24 |
Sep 04 04:13:30 PM UTC 24 |
88719815330 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.4085321516 |
|
|
Sep 04 04:13:17 PM UTC 24 |
Sep 04 04:13:35 PM UTC 24 |
6235293589 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1144328558 |
|
|
Sep 04 04:11:28 PM UTC 24 |
Sep 04 04:13:58 PM UTC 24 |
5349305274 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.479299391 |
|
|
Sep 04 03:56:40 PM UTC 24 |
Sep 04 04:14:02 PM UTC 24 |
62460668670 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1652363959 |
|
|
Sep 04 04:04:08 PM UTC 24 |
Sep 04 04:14:38 PM UTC 24 |
48669760219 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3620932970 |
|
|
Sep 04 04:14:43 PM UTC 24 |
Sep 04 04:14:48 PM UTC 24 |
195031012 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.431552695 |
|
|
Sep 04 03:59:38 PM UTC 24 |
Sep 04 04:14:51 PM UTC 24 |
119927229363 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2901536920 |
|
|
Sep 04 04:14:49 PM UTC 24 |
Sep 04 04:14:53 PM UTC 24 |
258035142 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.990713795 |
|
|
Sep 04 04:06:12 PM UTC 24 |
Sep 04 04:14:59 PM UTC 24 |
3419159651 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3930025429 |
|
|
Sep 04 04:15:00 PM UTC 24 |
Sep 04 04:15:02 PM UTC 24 |
29680165 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.374563289 |
|
|
Sep 04 04:15:03 PM UTC 24 |
Sep 04 04:15:10 PM UTC 24 |
380858566 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.3582720171 |
|
|
Sep 04 04:13:30 PM UTC 24 |
Sep 04 04:15:13 PM UTC 24 |
5276800742 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2704414685 |
|
|
Sep 04 04:15:12 PM UTC 24 |
Sep 04 04:15:20 PM UTC 24 |
174460739 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.942209452 |
|
|
Sep 04 04:15:22 PM UTC 24 |
Sep 04 04:15:24 PM UTC 24 |
24292118 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.26083499 |
|
|
Sep 04 04:09:38 PM UTC 24 |
Sep 04 04:15:34 PM UTC 24 |
6569210706 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.3619361057 |
|
|
Sep 04 04:15:25 PM UTC 24 |
Sep 04 04:15:38 PM UTC 24 |
212638774 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2275999609 |
|
|
Sep 04 04:06:38 PM UTC 24 |
Sep 04 04:16:01 PM UTC 24 |
68001896113 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1154497568 |
|
|
Sep 04 04:13:12 PM UTC 24 |
Sep 04 04:16:01 PM UTC 24 |
9065544338 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2138543667 |
|
|
Sep 04 04:12:09 PM UTC 24 |
Sep 04 04:16:05 PM UTC 24 |
4562401119 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.4185923392 |
|
|
Sep 04 04:15:38 PM UTC 24 |
Sep 04 04:16:20 PM UTC 24 |
614321652 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.795992265 |
|
|
Sep 04 04:00:55 PM UTC 24 |
Sep 04 04:16:28 PM UTC 24 |
13468879302 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.4050736673 |
|
|
Sep 04 04:14:39 PM UTC 24 |
Sep 04 04:16:29 PM UTC 24 |
460878597 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1154320107 |
|
|
Sep 04 04:05:47 PM UTC 24 |
Sep 04 04:16:33 PM UTC 24 |
13523465657 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3491758486 |
|
|
Sep 04 04:16:21 PM UTC 24 |
Sep 04 04:16:37 PM UTC 24 |
1133623163 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1389033632 |
|
|
Sep 04 04:13:35 PM UTC 24 |
Sep 04 04:16:39 PM UTC 24 |
1823726532 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2211561042 |
|
|
Sep 04 04:16:30 PM UTC 24 |
Sep 04 04:16:43 PM UTC 24 |
963713900 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3286023636 |
|
|
Sep 04 04:16:29 PM UTC 24 |
Sep 04 04:16:44 PM UTC 24 |
151196303 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1824042830 |
|
|
Sep 04 04:16:44 PM UTC 24 |
Sep 04 04:16:46 PM UTC 24 |
35796753 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2404132179 |
|
|
Sep 04 04:20:41 PM UTC 24 |
Sep 04 04:20:55 PM UTC 24 |
455483250 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.1452777025 |
|
|
Sep 04 04:04:02 PM UTC 24 |
Sep 04 04:16:47 PM UTC 24 |
34694557616 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.3854734670 |
|
|
Sep 04 04:16:47 PM UTC 24 |
Sep 04 04:16:52 PM UTC 24 |
179516060 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2320026176 |
|
|
Sep 04 04:16:45 PM UTC 24 |
Sep 04 04:16:59 PM UTC 24 |
783419719 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3941865335 |
|
|
Sep 04 04:17:01 PM UTC 24 |
Sep 04 04:17:03 PM UTC 24 |
16520613 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3937165712 |
|
|
Sep 04 04:11:00 PM UTC 24 |
Sep 04 04:17:06 PM UTC 24 |
11500894088 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3856270165 |
|
|
Sep 04 04:16:02 PM UTC 24 |
Sep 04 04:17:07 PM UTC 24 |
596480520 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.3274546770 |
|
|
Sep 04 04:08:18 PM UTC 24 |
Sep 04 04:17:10 PM UTC 24 |
13115927948 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3434392577 |
|
|
Sep 04 04:17:04 PM UTC 24 |
Sep 04 04:17:10 PM UTC 24 |
125473862 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.360202019 |
|
|
Sep 04 04:17:11 PM UTC 24 |
Sep 04 04:17:17 PM UTC 24 |
108753142 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3076773589 |
|
|
Sep 04 04:07:16 PM UTC 24 |
Sep 04 04:17:29 PM UTC 24 |
30415384145 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2272404927 |
|
|
Sep 04 04:10:11 PM UTC 24 |
Sep 04 04:17:40 PM UTC 24 |
177888753939 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3209933166 |
|
|
Sep 04 04:05:51 PM UTC 24 |
Sep 04 04:17:41 PM UTC 24 |
38930628107 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.660852937 |
|
|
Sep 04 04:15:14 PM UTC 24 |
Sep 04 04:17:54 PM UTC 24 |
5049919921 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.4185710701 |
|
|
Sep 04 04:17:42 PM UTC 24 |
Sep 04 04:17:55 PM UTC 24 |
907101645 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.3878088294 |
|
|
Sep 04 04:17:08 PM UTC 24 |
Sep 04 04:18:04 PM UTC 24 |
9034270268 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.147400165 |
|
|
Sep 04 04:12:56 PM UTC 24 |
Sep 04 04:18:13 PM UTC 24 |
6386976106 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2970479347 |
|
|
Sep 04 04:17:40 PM UTC 24 |
Sep 04 04:18:15 PM UTC 24 |
201364838 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3630037266 |
|
|
Sep 04 04:18:14 PM UTC 24 |
Sep 04 04:18:16 PM UTC 24 |
33033401 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1022611683 |
|
|
Sep 04 04:18:15 PM UTC 24 |
Sep 04 04:18:22 PM UTC 24 |
297888550 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.740192099 |
|
|
Sep 04 04:18:17 PM UTC 24 |
Sep 04 04:18:24 PM UTC 24 |
104811825 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3547334393 |
|
|
Sep 04 03:33:02 PM UTC 24 |
Sep 04 04:18:37 PM UTC 24 |
15276263804 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3347819726 |
|
|
Sep 04 04:18:39 PM UTC 24 |
Sep 04 04:18:41 PM UTC 24 |
17108878 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1957849312 |
|
|
Sep 04 04:17:30 PM UTC 24 |
Sep 04 04:18:47 PM UTC 24 |
134837167 ps |