Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1029
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1002 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.933477754 Sep 04 03:31:04 PM UTC 24 Sep 04 03:31:06 PM UTC 24 53614751 ps
T1003 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4009523546 Sep 04 03:31:02 PM UTC 24 Sep 04 03:31:07 PM UTC 24 44263094 ps
T1004 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1622886031 Sep 04 03:31:05 PM UTC 24 Sep 04 03:31:07 PM UTC 24 18877827 ps
T1005 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3740281877 Sep 04 03:31:03 PM UTC 24 Sep 04 03:31:07 PM UTC 24 743685893 ps
T1006 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1062227551 Sep 04 03:31:05 PM UTC 24 Sep 04 03:31:07 PM UTC 24 19512226 ps
T1007 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2492073231 Sep 04 03:31:04 PM UTC 24 Sep 04 03:31:08 PM UTC 24 840400021 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1454346305 Sep 04 03:31:05 PM UTC 24 Sep 04 03:31:09 PM UTC 24 156538326 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2564470649 Sep 04 03:31:02 PM UTC 24 Sep 04 03:31:09 PM UTC 24 530284202 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4177717675 Sep 04 03:31:04 PM UTC 24 Sep 04 03:31:09 PM UTC 24 213243918 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3445819477 Sep 04 03:31:07 PM UTC 24 Sep 04 03:31:09 PM UTC 24 33122329 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1991425080 Sep 04 03:31:07 PM UTC 24 Sep 04 03:31:10 PM UTC 24 49215091 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2020312316 Sep 04 03:31:07 PM UTC 24 Sep 04 03:31:10 PM UTC 24 85438228 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.132123109 Sep 04 03:31:06 PM UTC 24 Sep 04 03:31:10 PM UTC 24 116641881 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.897174062 Sep 04 03:31:09 PM UTC 24 Sep 04 03:31:11 PM UTC 24 104709883 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2508842108 Sep 04 03:31:02 PM UTC 24 Sep 04 03:31:11 PM UTC 24 1212234851 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3004682210 Sep 04 03:31:07 PM UTC 24 Sep 04 03:31:12 PM UTC 24 1098665684 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1095210861 Sep 04 03:31:10 PM UTC 24 Sep 04 03:31:12 PM UTC 24 12898857 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.391435726 Sep 04 03:31:07 PM UTC 24 Sep 04 03:31:13 PM UTC 24 382557839 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.481309422 Sep 04 03:31:11 PM UTC 24 Sep 04 03:31:13 PM UTC 24 28968984 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2371885850 Sep 04 03:31:11 PM UTC 24 Sep 04 03:31:13 PM UTC 24 29310971 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.115982392 Sep 04 03:31:10 PM UTC 24 Sep 04 03:31:13 PM UTC 24 219574786 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1635395211 Sep 04 03:31:10 PM UTC 24 Sep 04 03:31:14 PM UTC 24 202236172 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.876428394 Sep 04 03:31:12 PM UTC 24 Sep 04 03:31:14 PM UTC 24 80361404 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1189076665 Sep 04 03:31:12 PM UTC 24 Sep 04 03:31:14 PM UTC 24 24391398 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3046827031 Sep 04 03:31:10 PM UTC 24 Sep 04 03:31:15 PM UTC 24 26751911 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1592211277 Sep 04 03:31:12 PM UTC 24 Sep 04 03:31:15 PM UTC 24 34721597 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3775197556 Sep 04 03:31:11 PM UTC 24 Sep 04 03:31:17 PM UTC 24 131172767 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2166959321 Sep 04 03:31:12 PM UTC 24 Sep 04 03:31:17 PM UTC 24 1606259113 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.278353352 Sep 04 03:31:11 PM UTC 24 Sep 04 03:31:18 PM UTC 24 418467587 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3914724833
Short name T4
Test name
Test status
Simulation time 426765499 ps
CPU time 4.95 seconds
Started Sep 04 03:31:21 PM UTC 24
Finished Sep 04 03:31:27 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914724833 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.3914724833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1771757496
Short name T22
Test name
Test status
Simulation time 1028427149 ps
CPU time 58.92 seconds
Started Sep 04 03:31:22 PM UTC 24
Finished Sep 04 03:32:23 PM UTC 24
Peak memory 278448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771757496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1771757496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.6237682
Short name T29
Test name
Test status
Simulation time 417064734 ps
CPU time 6.28 seconds
Started Sep 04 03:37:12 PM UTC 24
Finished Sep 04 03:37:19 PM UTC 24
Peak memory 250196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6237682 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.6237682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3551735302
Short name T131
Test name
Test status
Simulation time 31995206080 ps
CPU time 523.33 seconds
Started Sep 04 03:36:17 PM UTC 24
Finished Sep 04 03:45:07 PM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355173530
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3551735302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1929433528
Short name T119
Test name
Test status
Simulation time 521893595 ps
CPU time 3.14 seconds
Started Sep 04 03:30:30 PM UTC 24
Finished Sep 04 03:30:34 PM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19294
33528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in
tg_err.1929433528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1148353616
Short name T133
Test name
Test status
Simulation time 9772684157 ps
CPU time 658.3 seconds
Started Sep 04 03:31:17 PM UTC 24
Finished Sep 04 03:42:24 PM UTC 24
Peak memory 382888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148353616 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.1148353616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4125328966
Short name T5
Test name
Test status
Simulation time 767737718 ps
CPU time 11.1 seconds
Started Sep 04 03:31:16 PM UTC 24
Finished Sep 04 03:31:29 PM UTC 24
Peak memory 213748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125328966 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.4125328966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2070894652
Short name T61
Test name
Test status
Simulation time 263969542 ps
CPU time 3.53 seconds
Started Sep 04 03:30:12 PM UTC 24
Finished Sep 04 03:30:17 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20
70894652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pa
ssthru_mem_tl_intg_err.2070894652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3634984706
Short name T99
Test name
Test status
Simulation time 15422065917 ps
CPU time 452.96 seconds
Started Sep 04 03:33:29 PM UTC 24
Finished Sep 04 03:41:08 PM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634984706 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce
ss_b2b.3634984706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2941165671
Short name T2
Test name
Test status
Simulation time 91581780 ps
CPU time 1.14 seconds
Started Sep 04 03:31:18 PM UTC 24
Finished Sep 04 03:31:21 PM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941165671 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2941165671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1212230819
Short name T86
Test name
Test status
Simulation time 12059984042 ps
CPU time 298.08 seconds
Started Sep 04 03:31:15 PM UTC 24
Finished Sep 04 03:36:17 PM UTC 24
Peak memory 213780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212230819 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.1212230819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1917329050
Short name T136
Test name
Test status
Simulation time 10828488715 ps
CPU time 736.2 seconds
Started Sep 04 03:38:04 PM UTC 24
Finished Sep 04 03:50:28 PM UTC 24
Peak memory 384884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917329050 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1917329050
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1144328558
Short name T106
Test name
Test status
Simulation time 5349305274 ps
CPU time 147.09 seconds
Started Sep 04 04:11:28 PM UTC 24
Finished Sep 04 04:13:58 PM UTC 24
Peak memory 366500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144328558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1144328558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.278869264
Short name T13
Test name
Test status
Simulation time 29765620 ps
CPU time 0.98 seconds
Started Sep 04 03:33:06 PM UTC 24
Finished Sep 04 03:33:09 PM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278869264 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.278869264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1091839646
Short name T142
Test name
Test status
Simulation time 31320076997 ps
CPU time 955.48 seconds
Started Sep 04 03:36:48 PM UTC 24
Finished Sep 04 03:52:54 PM UTC 24
Peak memory 378736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091839646 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.1091839646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.804700341
Short name T127
Test name
Test status
Simulation time 186030747 ps
CPU time 3.19 seconds
Started Sep 04 03:30:57 PM UTC 24
Finished Sep 04 03:31:01 PM UTC 24
Peak memory 221616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80470
0341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_in
tg_err.804700341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3936907000
Short name T151
Test name
Test status
Simulation time 99465200033 ps
CPU time 142.5 seconds
Started Sep 04 03:31:15 PM UTC 24
Finished Sep 04 03:33:40 PM UTC 24
Peak memory 214016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936907000 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.3936907000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.234610180
Short name T128
Test name
Test status
Simulation time 208520651 ps
CPU time 2.91 seconds
Started Sep 04 03:30:49 PM UTC 24
Finished Sep 04 03:30:53 PM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23461
0180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_in
tg_err.234610180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4117398374
Short name T115
Test name
Test status
Simulation time 627344406 ps
CPU time 2.56 seconds
Started Sep 04 03:30:53 PM UTC 24
Finished Sep 04 03:30:57 PM UTC 24
Peak memory 221720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41173
98374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_i
ntg_err.4117398374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1370017908
Short name T124
Test name
Test status
Simulation time 175951913 ps
CPU time 2.14 seconds
Started Sep 04 03:30:40 PM UTC 24
Finished Sep 04 03:30:44 PM UTC 24
Peak memory 221672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13700
17908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in
tg_err.1370017908
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.873577146
Short name T24
Test name
Test status
Simulation time 311126928 ps
CPU time 29.03 seconds
Started Sep 04 03:32:58 PM UTC 24
Finished Sep 04 03:33:28 PM UTC 24
Peak memory 245568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873577146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.873577146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3522951481
Short name T52
Test name
Test status
Simulation time 208045168 ps
CPU time 3.34 seconds
Started Sep 04 03:30:05 PM UTC 24
Finished Sep 04 03:30:10 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35
22951481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa
ssthru_mem_tl_intg_err.3522951481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3679596461
Short name T59
Test name
Test status
Simulation time 34608283 ps
CPU time 1 seconds
Started Sep 04 03:30:11 PM UTC 24
Finished Sep 04 03:30:13 PM UTC 24
Peak memory 210656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36795964
61 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alia
sing.3679596461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1983507455
Short name T102
Test name
Test status
Simulation time 125849041 ps
CPU time 3.17 seconds
Started Sep 04 03:30:10 PM UTC 24
Finished Sep 04 03:30:15 PM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19835074
55 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_
bash.1983507455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3479560424
Short name T53
Test name
Test status
Simulation time 44956711 ps
CPU time 1.05 seconds
Started Sep 04 03:30:09 PM UTC 24
Finished Sep 04 03:30:11 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34795604
24 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_r
eset.3479560424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1731955228
Short name T946
Test name
Test status
Simulation time 64926885 ps
CPU time 2.71 seconds
Started Sep 04 03:30:12 PM UTC 24
Finished Sep 04 03:30:16 PM UTC 24
Peak memory 221740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1731955228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1731955228
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3386664042
Short name T58
Test name
Test status
Simulation time 14814965 ps
CPU time 0.98 seconds
Started Sep 04 03:30:10 PM UTC 24
Finished Sep 04 03:30:12 PM UTC 24
Peak memory 210720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386664042 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.3386664042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3499025986
Short name T60
Test name
Test status
Simulation time 15667999 ps
CPU time 1.09 seconds
Started Sep 04 03:30:12 PM UTC 24
Finished Sep 04 03:30:14 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3499025986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c
trl_same_csr_outstanding.3499025986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2330384112
Short name T109
Test name
Test status
Simulation time 1669278580 ps
CPU time 4.64 seconds
Started Sep 04 03:30:05 PM UTC 24
Finished Sep 04 03:30:11 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330384112 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.2330384112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.141032776
Short name T46
Test name
Test status
Simulation time 350156643 ps
CPU time 2.73 seconds
Started Sep 04 03:30:07 PM UTC 24
Finished Sep 04 03:30:11 PM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14103
2776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_int
g_err.141032776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3363894670
Short name T64
Test name
Test status
Simulation time 49529559 ps
CPU time 1.03 seconds
Started Sep 04 03:30:18 PM UTC 24
Finished Sep 04 03:30:20 PM UTC 24
Peak memory 210452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33638946
70 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alia
sing.3363894670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3315516802
Short name T63
Test name
Test status
Simulation time 50885332 ps
CPU time 1.89 seconds
Started Sep 04 03:30:17 PM UTC 24
Finished Sep 04 03:30:20 PM UTC 24
Peak memory 210312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33155168
02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_
bash.3315516802
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3539892068
Short name T103
Test name
Test status
Simulation time 25455396 ps
CPU time 1.06 seconds
Started Sep 04 03:30:16 PM UTC 24
Finished Sep 04 03:30:18 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35398920
68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r
eset.3539892068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1069674023
Short name T949
Test name
Test status
Simulation time 498049400 ps
CPU time 2.91 seconds
Started Sep 04 03:30:19 PM UTC 24
Finished Sep 04 03:30:23 PM UTC 24
Peak memory 221772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1069674023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1069674023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4267629516
Short name T62
Test name
Test status
Simulation time 14837053 ps
CPU time 0.99 seconds
Started Sep 04 03:30:16 PM UTC 24
Finished Sep 04 03:30:18 PM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267629516 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.4267629516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2171742968
Short name T65
Test name
Test status
Simulation time 26163920 ps
CPU time 1.24 seconds
Started Sep 04 03:30:18 PM UTC 24
Finished Sep 04 03:30:20 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2171742968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c
trl_same_csr_outstanding.2171742968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1632923161
Short name T947
Test name
Test status
Simulation time 120390486 ps
CPU time 3.03 seconds
Started Sep 04 03:30:14 PM UTC 24
Finished Sep 04 03:30:18 PM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632923161 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.1632923161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.994076523
Short name T47
Test name
Test status
Simulation time 88438375 ps
CPU time 2.25 seconds
Started Sep 04 03:30:15 PM UTC 24
Finished Sep 04 03:30:18 PM UTC 24
Peak memory 221620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99407
6523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_int
g_err.994076523
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1750176073
Short name T982
Test name
Test status
Simulation time 452146075 ps
CPU time 1.32 seconds
Started Sep 04 03:30:50 PM UTC 24
Finished Sep 04 03:30:52 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1750176073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1750176073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2053224628
Short name T978
Test name
Test status
Simulation time 96180884 ps
CPU time 0.96 seconds
Started Sep 04 03:30:49 PM UTC 24
Finished Sep 04 03:30:51 PM UTC 24
Peak memory 209596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053224628 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2053224628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.424268459
Short name T85
Test name
Test status
Simulation time 2892541058 ps
CPU time 3.58 seconds
Started Sep 04 03:30:48 PM UTC 24
Finished Sep 04 03:30:52 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
4268459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_pa
ssthru_mem_tl_intg_err.424268459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3227048089
Short name T980
Test name
Test status
Simulation time 51992688 ps
CPU time 1.1 seconds
Started Sep 04 03:30:50 PM UTC 24
Finished Sep 04 03:30:52 PM UTC 24
Peak memory 210384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3227048089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_
ctrl_same_csr_outstanding.3227048089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.501457012
Short name T983
Test name
Test status
Simulation time 23915420 ps
CPU time 3.31 seconds
Started Sep 04 03:30:49 PM UTC 24
Finished Sep 04 03:30:53 PM UTC 24
Peak memory 221656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501457012 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.501457012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1069540756
Short name T984
Test name
Test status
Simulation time 16207478 ps
CPU time 1 seconds
Started Sep 04 03:30:54 PM UTC 24
Finished Sep 04 03:30:56 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069540756 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.1069540756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1794947527
Short name T988
Test name
Test status
Simulation time 286175765 ps
CPU time 3.28 seconds
Started Sep 04 03:30:53 PM UTC 24
Finished Sep 04 03:30:57 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17
94947527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p
assthru_mem_tl_intg_err.1794947527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2728094347
Short name T986
Test name
Test status
Simulation time 47876262 ps
CPU time 1.21 seconds
Started Sep 04 03:30:54 PM UTC 24
Finished Sep 04 03:30:56 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2728094347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_
ctrl_same_csr_outstanding.2728094347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3100294663
Short name T993
Test name
Test status
Simulation time 158770376 ps
CPU time 6.41 seconds
Started Sep 04 03:30:53 PM UTC 24
Finished Sep 04 03:31:00 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100294663 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.3100294663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1069825223
Short name T989
Test name
Test status
Simulation time 27699808 ps
CPU time 1.49 seconds
Started Sep 04 03:30:57 PM UTC 24
Finished Sep 04 03:30:59 PM UTC 24
Peak memory 220020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1069825223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1069825223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3569822611
Short name T985
Test name
Test status
Simulation time 22265800 ps
CPU time 0.97 seconds
Started Sep 04 03:30:54 PM UTC 24
Finished Sep 04 03:30:56 PM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569822611 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.3569822611
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.92605022
Short name T992
Test name
Test status
Simulation time 1050101363 ps
CPU time 4.95 seconds
Started Sep 04 03:30:54 PM UTC 24
Finished Sep 04 03:31:00 PM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92
605022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_pas
sthru_mem_tl_intg_err.92605022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1228057711
Short name T987
Test name
Test status
Simulation time 26089789 ps
CPU time 1.19 seconds
Started Sep 04 03:30:54 PM UTC 24
Finished Sep 04 03:30:57 PM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1228057711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_
ctrl_same_csr_outstanding.1228057711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1400966874
Short name T994
Test name
Test status
Simulation time 45566654 ps
CPU time 6.62 seconds
Started Sep 04 03:30:54 PM UTC 24
Finished Sep 04 03:31:02 PM UTC 24
Peak memory 221824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400966874 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.1400966874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1590096388
Short name T125
Test name
Test status
Simulation time 208116010 ps
CPU time 4.06 seconds
Started Sep 04 03:30:54 PM UTC 24
Finished Sep 04 03:30:59 PM UTC 24
Peak memory 221800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15900
96388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i
ntg_err.1590096388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.761638672
Short name T990
Test name
Test status
Simulation time 13130598 ps
CPU time 0.99 seconds
Started Sep 04 03:30:58 PM UTC 24
Finished Sep 04 03:31:00 PM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761638672 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.761638672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2536675949
Short name T996
Test name
Test status
Simulation time 409862675 ps
CPU time 5.21 seconds
Started Sep 04 03:30:57 PM UTC 24
Finished Sep 04 03:31:03 PM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25
36675949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p
assthru_mem_tl_intg_err.2536675949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.708950809
Short name T991
Test name
Test status
Simulation time 21901304 ps
CPU time 1.17 seconds
Started Sep 04 03:30:58 PM UTC 24
Finished Sep 04 03:31:00 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=708950809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_c
trl_same_csr_outstanding.708950809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2632899768
Short name T1000
Test name
Test status
Simulation time 238335934 ps
CPU time 6.83 seconds
Started Sep 04 03:30:57 PM UTC 24
Finished Sep 04 03:31:05 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632899768 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.2632899768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4009523546
Short name T1003
Test name
Test status
Simulation time 44263094 ps
CPU time 4.49 seconds
Started Sep 04 03:31:02 PM UTC 24
Finished Sep 04 03:31:07 PM UTC 24
Peak memory 221864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=4009523546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.4009523546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1711879607
Short name T997
Test name
Test status
Simulation time 30132291 ps
CPU time 0.96 seconds
Started Sep 04 03:31:01 PM UTC 24
Finished Sep 04 03:31:03 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711879607 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.1711879607
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.929780693
Short name T995
Test name
Test status
Simulation time 229374472 ps
CPU time 3.37 seconds
Started Sep 04 03:30:58 PM UTC 24
Finished Sep 04 03:31:03 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92
9780693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_pa
ssthru_mem_tl_intg_err.929780693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3056080663
Short name T998
Test name
Test status
Simulation time 288387649 ps
CPU time 1.22 seconds
Started Sep 04 03:31:01 PM UTC 24
Finished Sep 04 03:31:04 PM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3056080663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_
ctrl_same_csr_outstanding.3056080663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.354992948
Short name T117
Test name
Test status
Simulation time 57777331 ps
CPU time 3.55 seconds
Started Sep 04 03:31:00 PM UTC 24
Finished Sep 04 03:31:05 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354992948 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.354992948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.227148955
Short name T120
Test name
Test status
Simulation time 78253788 ps
CPU time 2.14 seconds
Started Sep 04 03:31:00 PM UTC 24
Finished Sep 04 03:31:03 PM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22714
8955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_in
tg_err.227148955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.933477754
Short name T1002
Test name
Test status
Simulation time 53614751 ps
CPU time 1.46 seconds
Started Sep 04 03:31:04 PM UTC 24
Finished Sep 04 03:31:06 PM UTC 24
Peak memory 220248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=933477754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.933477754
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1647853894
Short name T999
Test name
Test status
Simulation time 20887844 ps
CPU time 0.96 seconds
Started Sep 04 03:31:03 PM UTC 24
Finished Sep 04 03:31:05 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647853894 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.1647853894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2564470649
Short name T1009
Test name
Test status
Simulation time 530284202 ps
CPU time 6.09 seconds
Started Sep 04 03:31:02 PM UTC 24
Finished Sep 04 03:31:09 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25
64470649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p
assthru_mem_tl_intg_err.2564470649
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3500468288
Short name T1001
Test name
Test status
Simulation time 76444782 ps
CPU time 1.12 seconds
Started Sep 04 03:31:04 PM UTC 24
Finished Sep 04 03:31:06 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3500468288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_
ctrl_same_csr_outstanding.3500468288
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2508842108
Short name T1016
Test name
Test status
Simulation time 1212234851 ps
CPU time 8.21 seconds
Started Sep 04 03:31:02 PM UTC 24
Finished Sep 04 03:31:11 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508842108 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.2508842108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3740281877
Short name T1005
Test name
Test status
Simulation time 743685893 ps
CPU time 3.28 seconds
Started Sep 04 03:31:03 PM UTC 24
Finished Sep 04 03:31:07 PM UTC 24
Peak memory 221616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37402
81877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i
ntg_err.3740281877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.132123109
Short name T1014
Test name
Test status
Simulation time 116641881 ps
CPU time 2.88 seconds
Started Sep 04 03:31:06 PM UTC 24
Finished Sep 04 03:31:10 PM UTC 24
Peak memory 221792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=132123109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.132123109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1622886031
Short name T1004
Test name
Test status
Simulation time 18877827 ps
CPU time 0.9 seconds
Started Sep 04 03:31:05 PM UTC 24
Finished Sep 04 03:31:07 PM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622886031 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1622886031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2492073231
Short name T1007
Test name
Test status
Simulation time 840400021 ps
CPU time 3.41 seconds
Started Sep 04 03:31:04 PM UTC 24
Finished Sep 04 03:31:08 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24
92073231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p
assthru_mem_tl_intg_err.2492073231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1062227551
Short name T1006
Test name
Test status
Simulation time 19512226 ps
CPU time 1.03 seconds
Started Sep 04 03:31:05 PM UTC 24
Finished Sep 04 03:31:07 PM UTC 24
Peak memory 210384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1062227551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_
ctrl_same_csr_outstanding.1062227551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4177717675
Short name T1010
Test name
Test status
Simulation time 213243918 ps
CPU time 4.01 seconds
Started Sep 04 03:31:04 PM UTC 24
Finished Sep 04 03:31:09 PM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177717675 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.4177717675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1454346305
Short name T1008
Test name
Test status
Simulation time 156538326 ps
CPU time 2.41 seconds
Started Sep 04 03:31:05 PM UTC 24
Finished Sep 04 03:31:09 PM UTC 24
Peak memory 221664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14543
46305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i
ntg_err.1454346305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.897174062
Short name T1015
Test name
Test status
Simulation time 104709883 ps
CPU time 1.3 seconds
Started Sep 04 03:31:09 PM UTC 24
Finished Sep 04 03:31:11 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=897174062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.897174062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3445819477
Short name T1011
Test name
Test status
Simulation time 33122329 ps
CPU time 0.97 seconds
Started Sep 04 03:31:07 PM UTC 24
Finished Sep 04 03:31:09 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445819477 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.3445819477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3004682210
Short name T1017
Test name
Test status
Simulation time 1098665684 ps
CPU time 3.34 seconds
Started Sep 04 03:31:07 PM UTC 24
Finished Sep 04 03:31:12 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30
04682210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_p
assthru_mem_tl_intg_err.3004682210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1991425080
Short name T1012
Test name
Test status
Simulation time 49215091 ps
CPU time 1.06 seconds
Started Sep 04 03:31:07 PM UTC 24
Finished Sep 04 03:31:10 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1991425080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_
ctrl_same_csr_outstanding.1991425080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.391435726
Short name T1019
Test name
Test status
Simulation time 382557839 ps
CPU time 4.11 seconds
Started Sep 04 03:31:07 PM UTC 24
Finished Sep 04 03:31:13 PM UTC 24
Peak memory 221692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391435726 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.391435726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2020312316
Short name T1013
Test name
Test status
Simulation time 85438228 ps
CPU time 1.65 seconds
Started Sep 04 03:31:07 PM UTC 24
Finished Sep 04 03:31:10 PM UTC 24
Peak memory 220484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20203
12316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i
ntg_err.2020312316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2371885850
Short name T1021
Test name
Test status
Simulation time 29310971 ps
CPU time 1.28 seconds
Started Sep 04 03:31:11 PM UTC 24
Finished Sep 04 03:31:13 PM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2371885850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2371885850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1095210861
Short name T1018
Test name
Test status
Simulation time 12898857 ps
CPU time 0.99 seconds
Started Sep 04 03:31:10 PM UTC 24
Finished Sep 04 03:31:12 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095210861 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1095210861
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1635395211
Short name T1023
Test name
Test status
Simulation time 202236172 ps
CPU time 3.15 seconds
Started Sep 04 03:31:10 PM UTC 24
Finished Sep 04 03:31:14 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16
35395211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p
assthru_mem_tl_intg_err.1635395211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.481309422
Short name T1020
Test name
Test status
Simulation time 28968984 ps
CPU time 1.15 seconds
Started Sep 04 03:31:11 PM UTC 24
Finished Sep 04 03:31:13 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=481309422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_c
trl_same_csr_outstanding.481309422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3046827031
Short name T1026
Test name
Test status
Simulation time 26751911 ps
CPU time 3.9 seconds
Started Sep 04 03:31:10 PM UTC 24
Finished Sep 04 03:31:15 PM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046827031 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.3046827031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.115982392
Short name T1022
Test name
Test status
Simulation time 219574786 ps
CPU time 2.52 seconds
Started Sep 04 03:31:10 PM UTC 24
Finished Sep 04 03:31:13 PM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11598
2392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_in
tg_err.115982392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1592211277
Short name T1027
Test name
Test status
Simulation time 34721597 ps
CPU time 1.82 seconds
Started Sep 04 03:31:12 PM UTC 24
Finished Sep 04 03:31:15 PM UTC 24
Peak memory 220612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1592211277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1592211277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.876428394
Short name T1024
Test name
Test status
Simulation time 80361404 ps
CPU time 0.97 seconds
Started Sep 04 03:31:12 PM UTC 24
Finished Sep 04 03:31:14 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876428394 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.876428394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.278353352
Short name T1029
Test name
Test status
Simulation time 418467587 ps
CPU time 5.35 seconds
Started Sep 04 03:31:11 PM UTC 24
Finished Sep 04 03:31:18 PM UTC 24
Peak memory 211632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27
8353352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_pa
ssthru_mem_tl_intg_err.278353352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1189076665
Short name T1025
Test name
Test status
Simulation time 24391398 ps
CPU time 1.12 seconds
Started Sep 04 03:31:12 PM UTC 24
Finished Sep 04 03:31:14 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1189076665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_
ctrl_same_csr_outstanding.1189076665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3775197556
Short name T1028
Test name
Test status
Simulation time 131172767 ps
CPU time 4.35 seconds
Started Sep 04 03:31:11 PM UTC 24
Finished Sep 04 03:31:17 PM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775197556 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.3775197556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2166959321
Short name T121
Test name
Test status
Simulation time 1606259113 ps
CPU time 3.91 seconds
Started Sep 04 03:31:12 PM UTC 24
Finished Sep 04 03:31:17 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21669
59321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i
ntg_err.2166959321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2997815986
Short name T69
Test name
Test status
Simulation time 18451842 ps
CPU time 1.05 seconds
Started Sep 04 03:30:22 PM UTC 24
Finished Sep 04 03:30:24 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29978159
86 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alia
sing.2997815986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1512643113
Short name T950
Test name
Test status
Simulation time 218389277 ps
CPU time 2.8 seconds
Started Sep 04 03:30:22 PM UTC 24
Finished Sep 04 03:30:26 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15126431
13 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_
bash.1512643113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3535495320
Short name T948
Test name
Test status
Simulation time 59416462 ps
CPU time 1.06 seconds
Started Sep 04 03:30:21 PM UTC 24
Finished Sep 04 03:30:23 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35354953
20 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r
eset.3535495320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1804700310
Short name T951
Test name
Test status
Simulation time 149506285 ps
CPU time 1.72 seconds
Started Sep 04 03:30:23 PM UTC 24
Finished Sep 04 03:30:26 PM UTC 24
Peak memory 220280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1804700310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1804700310
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2037362356
Short name T66
Test name
Test status
Simulation time 36246502 ps
CPU time 1 seconds
Started Sep 04 03:30:21 PM UTC 24
Finished Sep 04 03:30:23 PM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037362356 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.2037362356
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2711611066
Short name T70
Test name
Test status
Simulation time 380650459 ps
CPU time 4.94 seconds
Started Sep 04 03:30:19 PM UTC 24
Finished Sep 04 03:30:25 PM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27
11611066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa
ssthru_mem_tl_intg_err.2711611066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1233179156
Short name T91
Test name
Test status
Simulation time 54488330 ps
CPU time 1.11 seconds
Started Sep 04 03:30:23 PM UTC 24
Finished Sep 04 03:30:25 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1233179156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c
trl_same_csr_outstanding.1233179156
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3058192232
Short name T952
Test name
Test status
Simulation time 95288990 ps
CPU time 6.61 seconds
Started Sep 04 03:30:19 PM UTC 24
Finished Sep 04 03:30:27 PM UTC 24
Peak memory 221864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058192232 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.3058192232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.265765959
Short name T48
Test name
Test status
Simulation time 106562033 ps
CPU time 2.55 seconds
Started Sep 04 03:30:20 PM UTC 24
Finished Sep 04 03:30:24 PM UTC 24
Peak memory 221604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26576
5959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_int
g_err.265765959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3268602935
Short name T954
Test name
Test status
Simulation time 13085312 ps
CPU time 1.06 seconds
Started Sep 04 03:30:26 PM UTC 24
Finished Sep 04 03:30:28 PM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32686029
35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia
sing.3268602935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1843389228
Short name T78
Test name
Test status
Simulation time 170264157 ps
CPU time 3.46 seconds
Started Sep 04 03:30:26 PM UTC 24
Finished Sep 04 03:30:31 PM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18433892
28 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_
bash.1843389228
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.755143912
Short name T953
Test name
Test status
Simulation time 42903478 ps
CPU time 1.01 seconds
Started Sep 04 03:30:26 PM UTC 24
Finished Sep 04 03:30:28 PM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75514391
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_re
set.755143912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1516764255
Short name T71
Test name
Test status
Simulation time 41393560 ps
CPU time 0.99 seconds
Started Sep 04 03:30:26 PM UTC 24
Finished Sep 04 03:30:28 PM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516764255 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.1516764255
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.722433718
Short name T72
Test name
Test status
Simulation time 584210060 ps
CPU time 3.25 seconds
Started Sep 04 03:30:24 PM UTC 24
Finished Sep 04 03:30:28 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72
2433718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pas
sthru_mem_tl_intg_err.722433718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4096568950
Short name T92
Test name
Test status
Simulation time 83369087 ps
CPU time 1.04 seconds
Started Sep 04 03:30:29 PM UTC 24
Finished Sep 04 03:30:31 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4096568950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c
trl_same_csr_outstanding.4096568950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3176589419
Short name T955
Test name
Test status
Simulation time 171403174 ps
CPU time 2.94 seconds
Started Sep 04 03:30:25 PM UTC 24
Finished Sep 04 03:30:29 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176589419 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.3176589419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.605790248
Short name T113
Test name
Test status
Simulation time 188098633 ps
CPU time 2.36 seconds
Started Sep 04 03:30:25 PM UTC 24
Finished Sep 04 03:30:29 PM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60579
0248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_int
g_err.605790248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2956802403
Short name T957
Test name
Test status
Simulation time 18819898 ps
CPU time 1.11 seconds
Started Sep 04 03:30:31 PM UTC 24
Finished Sep 04 03:30:33 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29568024
03 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia
sing.2956802403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3149980202
Short name T958
Test name
Test status
Simulation time 83025246 ps
CPU time 2.88 seconds
Started Sep 04 03:30:30 PM UTC 24
Finished Sep 04 03:30:34 PM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31499802
02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_
bash.3149980202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.482157082
Short name T73
Test name
Test status
Simulation time 14676436 ps
CPU time 0.99 seconds
Started Sep 04 03:30:30 PM UTC 24
Finished Sep 04 03:30:32 PM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48215708
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_re
set.482157082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2665184460
Short name T960
Test name
Test status
Simulation time 76831204 ps
CPU time 2.41 seconds
Started Sep 04 03:30:32 PM UTC 24
Finished Sep 04 03:30:36 PM UTC 24
Peak memory 223964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2665184460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2665184460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1262876433
Short name T956
Test name
Test status
Simulation time 12111360 ps
CPU time 0.96 seconds
Started Sep 04 03:30:30 PM UTC 24
Finished Sep 04 03:30:32 PM UTC 24
Peak memory 210424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262876433 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.1262876433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3578048272
Short name T79
Test name
Test status
Simulation time 1579232079 ps
CPU time 5.38 seconds
Started Sep 04 03:30:30 PM UTC 24
Finished Sep 04 03:30:36 PM UTC 24
Peak memory 211856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35
78048272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pa
ssthru_mem_tl_intg_err.3578048272
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3077480346
Short name T93
Test name
Test status
Simulation time 43283385 ps
CPU time 1.1 seconds
Started Sep 04 03:30:32 PM UTC 24
Finished Sep 04 03:30:34 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3077480346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c
trl_same_csr_outstanding.3077480346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4210344894
Short name T959
Test name
Test status
Simulation time 26681727 ps
CPU time 3.36 seconds
Started Sep 04 03:30:30 PM UTC 24
Finished Sep 04 03:30:34 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210344894 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.4210344894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3793406220
Short name T964
Test name
Test status
Simulation time 106162628 ps
CPU time 2.16 seconds
Started Sep 04 03:30:36 PM UTC 24
Finished Sep 04 03:30:39 PM UTC 24
Peak memory 224020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3793406220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3793406220
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2690922685
Short name T961
Test name
Test status
Simulation time 16051141 ps
CPU time 0.97 seconds
Started Sep 04 03:30:35 PM UTC 24
Finished Sep 04 03:30:37 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690922685 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.2690922685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1207961939
Short name T80
Test name
Test status
Simulation time 860646051 ps
CPU time 3.4 seconds
Started Sep 04 03:30:33 PM UTC 24
Finished Sep 04 03:30:38 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12
07961939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa
ssthru_mem_tl_intg_err.1207961939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.40965862
Short name T962
Test name
Test status
Simulation time 45158112 ps
CPU time 1.1 seconds
Started Sep 04 03:30:36 PM UTC 24
Finished Sep 04 03:30:38 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=40965862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctr
l_same_csr_outstanding.40965862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4277169407
Short name T963
Test name
Test status
Simulation time 81091648 ps
CPU time 3.98 seconds
Started Sep 04 03:30:33 PM UTC 24
Finished Sep 04 03:30:39 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277169407 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.4277169407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.383505163
Short name T123
Test name
Test status
Simulation time 617202127 ps
CPU time 3.71 seconds
Started Sep 04 03:30:35 PM UTC 24
Finished Sep 04 03:30:39 PM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38350
5163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_int
g_err.383505163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.948835852
Short name T968
Test name
Test status
Simulation time 82384073 ps
CPU time 2.04 seconds
Started Sep 04 03:30:39 PM UTC 24
Finished Sep 04 03:30:42 PM UTC 24
Peak memory 221524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=948835852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.948835852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2636849503
Short name T965
Test name
Test status
Simulation time 12579127 ps
CPU time 0.96 seconds
Started Sep 04 03:30:38 PM UTC 24
Finished Sep 04 03:30:40 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636849503 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.2636849503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2790156741
Short name T82
Test name
Test status
Simulation time 209489149 ps
CPU time 3.15 seconds
Started Sep 04 03:30:36 PM UTC 24
Finished Sep 04 03:30:40 PM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27
90156741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa
ssthru_mem_tl_intg_err.2790156741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.63863827
Short name T966
Test name
Test status
Simulation time 49606327 ps
CPU time 1.13 seconds
Started Sep 04 03:30:39 PM UTC 24
Finished Sep 04 03:30:41 PM UTC 24
Peak memory 210452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=63863827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctr
l_same_csr_outstanding.63863827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3451904312
Short name T967
Test name
Test status
Simulation time 103917105 ps
CPU time 3.8 seconds
Started Sep 04 03:30:37 PM UTC 24
Finished Sep 04 03:30:42 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451904312 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3451904312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3456176575
Short name T116
Test name
Test status
Simulation time 883735070 ps
CPU time 3.08 seconds
Started Sep 04 03:30:37 PM UTC 24
Finished Sep 04 03:30:41 PM UTC 24
Peak memory 221540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34561
76575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in
tg_err.3456176575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2652792081
Short name T971
Test name
Test status
Simulation time 32267274 ps
CPU time 1.46 seconds
Started Sep 04 03:30:42 PM UTC 24
Finished Sep 04 03:30:44 PM UTC 24
Peak memory 220608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2652792081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2652792081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.902362997
Short name T969
Test name
Test status
Simulation time 27882272 ps
CPU time 0.99 seconds
Started Sep 04 03:30:40 PM UTC 24
Finished Sep 04 03:30:42 PM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902362997 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.902362997
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1834204534
Short name T83
Test name
Test status
Simulation time 202282570 ps
CPU time 2.83 seconds
Started Sep 04 03:30:39 PM UTC 24
Finished Sep 04 03:30:43 PM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18
34204534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pa
ssthru_mem_tl_intg_err.1834204534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1900242812
Short name T970
Test name
Test status
Simulation time 22304993 ps
CPU time 0.97 seconds
Started Sep 04 03:30:42 PM UTC 24
Finished Sep 04 03:30:43 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1900242812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_c
trl_same_csr_outstanding.1900242812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1645215467
Short name T975
Test name
Test status
Simulation time 152204660 ps
CPU time 6.58 seconds
Started Sep 04 03:30:40 PM UTC 24
Finished Sep 04 03:30:48 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645215467 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.1645215467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1358691325
Short name T976
Test name
Test status
Simulation time 60790218 ps
CPU time 2.74 seconds
Started Sep 04 03:30:44 PM UTC 24
Finished Sep 04 03:30:48 PM UTC 24
Peak memory 222040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1358691325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1358691325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.844189838
Short name T972
Test name
Test status
Simulation time 23414133 ps
CPU time 0.99 seconds
Started Sep 04 03:30:43 PM UTC 24
Finished Sep 04 03:30:45 PM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844189838 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.844189838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2875409363
Short name T81
Test name
Test status
Simulation time 493478932 ps
CPU time 3.54 seconds
Started Sep 04 03:30:42 PM UTC 24
Finished Sep 04 03:30:46 PM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28
75409363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa
ssthru_mem_tl_intg_err.2875409363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3200992141
Short name T973
Test name
Test status
Simulation time 12394173 ps
CPU time 1.01 seconds
Started Sep 04 03:30:43 PM UTC 24
Finished Sep 04 03:30:45 PM UTC 24
Peak memory 210928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3200992141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c
trl_same_csr_outstanding.3200992141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.511847711
Short name T114
Test name
Test status
Simulation time 145426135 ps
CPU time 7.15 seconds
Started Sep 04 03:30:43 PM UTC 24
Finished Sep 04 03:30:51 PM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511847711 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.511847711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.170474881
Short name T122
Test name
Test status
Simulation time 96611572 ps
CPU time 2.55 seconds
Started Sep 04 03:30:43 PM UTC 24
Finished Sep 04 03:30:47 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17047
4881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_int
g_err.170474881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2704074111
Short name T981
Test name
Test status
Simulation time 76777950 ps
CPU time 4.4 seconds
Started Sep 04 03:30:47 PM UTC 24
Finished Sep 04 03:30:52 PM UTC 24
Peak memory 221716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2704074111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2704074111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1051646212
Short name T974
Test name
Test status
Simulation time 37211143 ps
CPU time 1 seconds
Started Sep 04 03:30:45 PM UTC 24
Finished Sep 04 03:30:47 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051646212 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.1051646212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1646695230
Short name T84
Test name
Test status
Simulation time 1269236976 ps
CPU time 3.44 seconds
Started Sep 04 03:30:44 PM UTC 24
Finished Sep 04 03:30:49 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16
46695230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa
ssthru_mem_tl_intg_err.1646695230
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3030509337
Short name T977
Test name
Test status
Simulation time 149772624 ps
CPU time 1.15 seconds
Started Sep 04 03:30:46 PM UTC 24
Finished Sep 04 03:30:49 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3030509337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c
trl_same_csr_outstanding.3030509337
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.703633953
Short name T979
Test name
Test status
Simulation time 530948760 ps
CPU time 6.51 seconds
Started Sep 04 03:30:44 PM UTC 24
Finished Sep 04 03:30:52 PM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703633953 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.703633953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4188987220
Short name T126
Test name
Test status
Simulation time 673735639 ps
CPU time 3.45 seconds
Started Sep 04 03:30:45 PM UTC 24
Finished Sep 04 03:30:50 PM UTC 24
Peak memory 221844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41889
87220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_in
tg_err.4188987220
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1480080700
Short name T225
Test name
Test status
Simulation time 3231560581 ps
CPU time 906.15 seconds
Started Sep 04 03:31:16 PM UTC 24
Finished Sep 04 03:46:34 PM UTC 24
Peak memory 386988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480080700 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_
key_req.1480080700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.499170593
Short name T10
Test name
Test status
Simulation time 14327029 ps
CPU time 0.99 seconds
Started Sep 04 03:31:30 PM UTC 24
Finished Sep 04 03:31:32 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499170593 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.499170593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2036193729
Short name T1
Test name
Test status
Simulation time 44470088 ps
CPU time 2.59 seconds
Started Sep 04 03:31:16 PM UTC 24
Finished Sep 04 03:31:20 PM UTC 24
Peak memory 224196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
036193729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max
_throughput.2036193729
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.739931756
Short name T9
Test name
Test status
Simulation time 873578854 ps
CPU time 10.15 seconds
Started Sep 04 03:31:20 PM UTC 24
Finished Sep 04 03:31:31 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739931756 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.739931756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2027119724
Short name T186
Test name
Test status
Simulation time 7850762143 ps
CPU time 603.4 seconds
Started Sep 04 03:31:15 PM UTC 24
Finished Sep 04 03:41:26 PM UTC 24
Peak memory 386916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027119724 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.2027119724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2143142064
Short name T3
Test name
Test status
Simulation time 389519992 ps
CPU time 10.09 seconds
Started Sep 04 03:31:15 PM UTC 24
Finished Sep 04 03:31:26 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143142064 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.2143142064
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1072661631
Short name T97
Test name
Test status
Simulation time 42302841723 ps
CPU time 505.22 seconds
Started Sep 04 03:31:15 PM UTC 24
Finished Sep 04 03:39:47 PM UTC 24
Peak memory 213644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072661631 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce
ss_b2b.1072661631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2155466904
Short name T18
Test name
Test status
Simulation time 7727563695 ps
CPU time 343.71 seconds
Started Sep 04 03:31:18 PM UTC 24
Finished Sep 04 03:37:07 PM UTC 24
Peak memory 362428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155466904 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2155466904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1266227469
Short name T6
Test name
Test status
Simulation time 1386761492 ps
CPU time 5.08 seconds
Started Sep 04 03:31:28 PM UTC 24
Finished Sep 04 03:31:34 PM UTC 24
Peak memory 257276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266227469 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1266227469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.650901350
Short name T31
Test name
Test status
Simulation time 107273729 ps
CPU time 53.79 seconds
Started Sep 04 03:31:13 PM UTC 24
Finished Sep 04 03:32:09 PM UTC 24
Peak memory 323452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650901350 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.650901350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1420320419
Short name T614
Test name
Test status
Simulation time 166702183521 ps
CPU time 3092.91 seconds
Started Sep 04 03:31:27 PM UTC 24
Finished Sep 04 04:23:33 PM UTC 24
Peak memory 388708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142032041
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.1420320419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3378467123
Short name T11
Test name
Test status
Simulation time 263423197 ps
CPU time 14.8 seconds
Started Sep 04 03:31:16 PM UTC 24
Finished Sep 04 03:31:32 PM UTC 24
Peak memory 264300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3378467123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th
roughput_w_partial_write.3378467123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1483437078
Short name T35
Test name
Test status
Simulation time 3238824052 ps
CPU time 488.97 seconds
Started Sep 04 03:32:15 PM UTC 24
Finished Sep 04 03:40:30 PM UTC 24
Peak memory 380820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483437078 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_
key_req.1483437078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.1573140613
Short name T17
Test name
Test status
Simulation time 25485983888 ps
CPU time 82.47 seconds
Started Sep 04 03:31:33 PM UTC 24
Finished Sep 04 03:32:58 PM UTC 24
Peak memory 213992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573140613 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.1573140613
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1390854272
Short name T132
Test name
Test status
Simulation time 15772406890 ps
CPU time 388.94 seconds
Started Sep 04 03:32:24 PM UTC 24
Finished Sep 04 03:38:58 PM UTC 24
Peak memory 378792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390854272 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.1390854272
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1544258434
Short name T7
Test name
Test status
Simulation time 701159601 ps
CPU time 11.68 seconds
Started Sep 04 03:32:10 PM UTC 24
Finished Sep 04 03:32:23 PM UTC 24
Peak memory 214108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544258434 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.1544258434
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.4274974421
Short name T50
Test name
Test status
Simulation time 322264462 ps
CPU time 83.61 seconds
Started Sep 04 03:31:58 PM UTC 24
Finished Sep 04 03:33:23 PM UTC 24
Peak memory 370792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
274974421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max
_throughput.4274974421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3693734884
Short name T23
Test name
Test status
Simulation time 146910673 ps
CPU time 7.72 seconds
Started Sep 04 03:32:57 PM UTC 24
Finished Sep 04 03:33:06 PM UTC 24
Peak memory 224172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693734884 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.3693734884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2233035741
Short name T33
Test name
Test status
Simulation time 356357970 ps
CPU time 9.95 seconds
Started Sep 04 03:32:51 PM UTC 24
Finished Sep 04 03:33:02 PM UTC 24
Peak memory 214056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233035741 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2233035741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1673927098
Short name T170
Test name
Test status
Simulation time 30401438479 ps
CPU time 446.6 seconds
Started Sep 04 03:31:33 PM UTC 24
Finished Sep 04 03:39:06 PM UTC 24
Peak memory 384864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673927098 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.1673927098
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3463665086
Short name T30
Test name
Test status
Simulation time 989425338 ps
CPU time 28.52 seconds
Started Sep 04 03:31:38 PM UTC 24
Finished Sep 04 03:32:08 PM UTC 24
Peak memory 214076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463665086 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.3463665086
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1236412592
Short name T101
Test name
Test status
Simulation time 22379886311 ps
CPU time 610.31 seconds
Started Sep 04 03:31:44 PM UTC 24
Finished Sep 04 03:42:02 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236412592 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce
ss_b2b.1236412592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1233464505
Short name T26
Test name
Test status
Simulation time 51520145 ps
CPU time 1.18 seconds
Started Sep 04 03:32:48 PM UTC 24
Finished Sep 04 03:32:50 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233464505 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1233464505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1879534430
Short name T135
Test name
Test status
Simulation time 21965950074 ps
CPU time 869.97 seconds
Started Sep 04 03:32:24 PM UTC 24
Finished Sep 04 03:47:05 PM UTC 24
Peak memory 382896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879534430 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1879534430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1885076644
Short name T15
Test name
Test status
Simulation time 255753527 ps
CPU time 3.59 seconds
Started Sep 04 03:33:03 PM UTC 24
Finished Sep 04 03:33:08 PM UTC 24
Peak memory 250136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885076644 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1885076644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.1459217530
Short name T12
Test name
Test status
Simulation time 91645369 ps
CPU time 4.08 seconds
Started Sep 04 03:31:32 PM UTC 24
Finished Sep 04 03:31:37 PM UTC 24
Peak memory 220340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459217530 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1459217530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3547334393
Short name T549
Test name
Test status
Simulation time 15276263804 ps
CPU time 2707.86 seconds
Started Sep 04 03:33:02 PM UTC 24
Finished Sep 04 04:18:37 PM UTC 24
Peak memory 397304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354733439
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.3547334393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3934982072
Short name T94
Test name
Test status
Simulation time 2944802088 ps
CPU time 349.23 seconds
Started Sep 04 03:31:35 PM UTC 24
Finished Sep 04 03:37:30 PM UTC 24
Peak memory 213880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934982072 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.3934982072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3649357654
Short name T32
Test name
Test status
Simulation time 221652293 ps
CPU time 45.65 seconds
Started Sep 04 03:32:09 PM UTC 24
Finished Sep 04 03:32:56 PM UTC 24
Peak memory 313448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3649357654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th
roughput_w_partial_write.3649357654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.1734078687
Short name T396
Test name
Test status
Simulation time 18530789392 ps
CPU time 1053.12 seconds
Started Sep 04 03:45:38 PM UTC 24
Finished Sep 04 04:03:23 PM UTC 24
Peak memory 384932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734078687 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during
_key_req.1734078687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.4004931191
Short name T222
Test name
Test status
Simulation time 110933292 ps
CPU time 1.06 seconds
Started Sep 04 03:46:19 PM UTC 24
Finished Sep 04 03:46:21 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004931191 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.4004931191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.3376976724
Short name T218
Test name
Test status
Simulation time 6306541649 ps
CPU time 48.65 seconds
Started Sep 04 03:45:07 PM UTC 24
Finished Sep 04 03:45:57 PM UTC 24
Peak memory 213944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376976724 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.3376976724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.3232401177
Short name T336
Test name
Test status
Simulation time 2600305051 ps
CPU time 764.36 seconds
Started Sep 04 03:45:40 PM UTC 24
Finished Sep 04 03:58:33 PM UTC 24
Peak memory 362312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232401177 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.3232401177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1742845309
Short name T216
Test name
Test status
Simulation time 140172472 ps
CPU time 3.9 seconds
Started Sep 04 03:45:34 PM UTC 24
Finished Sep 04 03:45:39 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742845309 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.1742845309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3030742498
Short name T213
Test name
Test status
Simulation time 367385718 ps
CPU time 7.6 seconds
Started Sep 04 03:45:20 PM UTC 24
Finished Sep 04 03:45:29 PM UTC 24
Peak memory 247788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
030742498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma
x_throughput.3030742498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1360004449
Short name T223
Test name
Test status
Simulation time 628509036 ps
CPU time 7.8 seconds
Started Sep 04 03:46:14 PM UTC 24
Finished Sep 04 03:46:23 PM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360004449 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.1360004449
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3252630017
Short name T220
Test name
Test status
Simulation time 2788243147 ps
CPU time 10.9 seconds
Started Sep 04 03:46:01 PM UTC 24
Finished Sep 04 03:46:13 PM UTC 24
Peak memory 214216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252630017 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.3252630017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.555326173
Short name T295
Test name
Test status
Simulation time 41953646458 ps
CPU time 572.42 seconds
Started Sep 04 03:44:48 PM UTC 24
Finished Sep 04 03:54:27 PM UTC 24
Peak memory 385080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555326173 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.555326173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1104763421
Short name T214
Test name
Test status
Simulation time 609928595 ps
CPU time 22.24 seconds
Started Sep 04 03:45:09 PM UTC 24
Finished Sep 04 03:45:33 PM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104763421 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.1104763421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.627902209
Short name T297
Test name
Test status
Simulation time 74024467550 ps
CPU time 546.29 seconds
Started Sep 04 03:45:16 PM UTC 24
Finished Sep 04 03:54:29 PM UTC 24
Peak memory 214064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627902209 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acce
ss_b2b.627902209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1920707689
Short name T219
Test name
Test status
Simulation time 80420945 ps
CPU time 1.11 seconds
Started Sep 04 03:45:58 PM UTC 24
Finished Sep 04 03:46:00 PM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920707689 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1920707689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.4288258846
Short name T137
Test name
Test status
Simulation time 6251491527 ps
CPU time 367.75 seconds
Started Sep 04 03:45:41 PM UTC 24
Finished Sep 04 03:51:53 PM UTC 24
Peak memory 378808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288258846 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.4288258846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2007027028
Short name T210
Test name
Test status
Simulation time 2965921442 ps
CPU time 23.53 seconds
Started Sep 04 03:44:43 PM UTC 24
Finished Sep 04 03:45:08 PM UTC 24
Peak memory 214296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007027028 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2007027028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3795307329
Short name T236
Test name
Test status
Simulation time 3476903236 ps
CPU time 99.21 seconds
Started Sep 04 03:46:19 PM UTC 24
Finished Sep 04 03:48:01 PM UTC 24
Peak memory 228248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379530732
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.3795307329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1742345341
Short name T41
Test name
Test status
Simulation time 940062506 ps
CPU time 8.89 seconds
Started Sep 04 03:46:19 PM UTC 24
Finished Sep 04 03:46:29 PM UTC 24
Peak memory 224408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742345341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1742345341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.207940993
Short name T231
Test name
Test status
Simulation time 1491647444 ps
CPU time 156.09 seconds
Started Sep 04 03:45:08 PM UTC 24
Finished Sep 04 03:47:47 PM UTC 24
Peak memory 214116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207940993 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.207940993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.157177756
Short name T217
Test name
Test status
Simulation time 66280730 ps
CPU time 9.28 seconds
Started Sep 04 03:45:29 PM UTC 24
Finished Sep 04 03:45:40 PM UTC 24
Peak memory 247656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
157177756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_th
roughput_w_partial_write.157177756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3586270682
Short name T351
Test name
Test status
Simulation time 3574182435 ps
CPU time 744.7 seconds
Started Sep 04 03:47:05 PM UTC 24
Finished Sep 04 03:59:39 PM UTC 24
Peak memory 379112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586270682 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during
_key_req.3586270682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3476645913
Short name T234
Test name
Test status
Simulation time 33160068 ps
CPU time 0.95 seconds
Started Sep 04 03:47:54 PM UTC 24
Finished Sep 04 03:47:56 PM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476645913 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3476645913
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2483202012
Short name T229
Test name
Test status
Simulation time 717607547 ps
CPU time 51.19 seconds
Started Sep 04 03:46:30 PM UTC 24
Finished Sep 04 03:47:23 PM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483202012 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.2483202012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.997992248
Short name T432
Test name
Test status
Simulation time 16448602359 ps
CPU time 1152.26 seconds
Started Sep 04 03:47:12 PM UTC 24
Finished Sep 04 04:06:37 PM UTC 24
Peak memory 370796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997992248 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.997992248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.4290401535
Short name T228
Test name
Test status
Simulation time 872664393 ps
CPU time 6.96 seconds
Started Sep 04 03:47:03 PM UTC 24
Finished Sep 04 03:47:11 PM UTC 24
Peak memory 213748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290401535 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.4290401535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.680048193
Short name T227
Test name
Test status
Simulation time 45886899 ps
CPU time 2.82 seconds
Started Sep 04 03:46:51 PM UTC 24
Finished Sep 04 03:46:55 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
80048193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_max
_throughput.680048193
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3733817529
Short name T232
Test name
Test status
Simulation time 375395622 ps
CPU time 4.36 seconds
Started Sep 04 03:47:46 PM UTC 24
Finished Sep 04 03:47:51 PM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733817529 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.3733817529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2985119859
Short name T235
Test name
Test status
Simulation time 521687618 ps
CPU time 11.28 seconds
Started Sep 04 03:47:46 PM UTC 24
Finished Sep 04 03:47:58 PM UTC 24
Peak memory 224004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985119859 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.2985119859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2373163891
Short name T362
Test name
Test status
Simulation time 17882232710 ps
CPU time 848.2 seconds
Started Sep 04 03:46:23 PM UTC 24
Finished Sep 04 04:00:42 PM UTC 24
Peak memory 381100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373163891 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.2373163891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2951031078
Short name T226
Test name
Test status
Simulation time 451221185 ps
CPU time 14.76 seconds
Started Sep 04 03:46:34 PM UTC 24
Finished Sep 04 03:46:50 PM UTC 24
Peak memory 213844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951031078 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.2951031078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1164201776
Short name T253
Test name
Test status
Simulation time 7272482240 ps
CPU time 239.95 seconds
Started Sep 04 03:46:35 PM UTC 24
Finished Sep 04 03:50:38 PM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164201776 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc
ess_b2b.1164201776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3848795424
Short name T230
Test name
Test status
Simulation time 47725946 ps
CPU time 1.21 seconds
Started Sep 04 03:47:41 PM UTC 24
Finished Sep 04 03:47:44 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848795424 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3848795424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2594244888
Short name T311
Test name
Test status
Simulation time 10783575164 ps
CPU time 501.86 seconds
Started Sep 04 03:47:24 PM UTC 24
Finished Sep 04 03:55:51 PM UTC 24
Peak memory 372616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594244888 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2594244888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.562654788
Short name T224
Test name
Test status
Simulation time 372200130 ps
CPU time 9.07 seconds
Started Sep 04 03:46:22 PM UTC 24
Finished Sep 04 03:46:33 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562654788 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.562654788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1622881362
Short name T801
Test name
Test status
Simulation time 42413025974 ps
CPU time 3096.82 seconds
Started Sep 04 03:47:52 PM UTC 24
Finished Sep 04 04:40:00 PM UTC 24
Peak memory 396912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162288136
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.1622881362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.548176229
Short name T271
Test name
Test status
Simulation time 3501567866 ps
CPU time 300.13 seconds
Started Sep 04 03:47:48 PM UTC 24
Finished Sep 04 03:52:52 PM UTC 24
Peak memory 384952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548176229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.548176229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3162839027
Short name T274
Test name
Test status
Simulation time 6196267892 ps
CPU time 379.85 seconds
Started Sep 04 03:46:33 PM UTC 24
Finished Sep 04 03:52:58 PM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162839027 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.3162839027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3993791314
Short name T233
Test name
Test status
Simulation time 138511565 ps
CPU time 55.68 seconds
Started Sep 04 03:46:56 PM UTC 24
Finished Sep 04 03:47:53 PM UTC 24
Peak memory 352108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3993791314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t
hroughput_w_partial_write.3993791314
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1340385316
Short name T378
Test name
Test status
Simulation time 3452580207 ps
CPU time 787.72 seconds
Started Sep 04 03:48:55 PM UTC 24
Finished Sep 04 04:02:12 PM UTC 24
Peak memory 387032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340385316 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during
_key_req.1340385316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.4023476279
Short name T250
Test name
Test status
Simulation time 43031089 ps
CPU time 0.8 seconds
Started Sep 04 03:49:44 PM UTC 24
Finished Sep 04 03:49:46 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023476279 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.4023476279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.479818960
Short name T244
Test name
Test status
Simulation time 931514943 ps
CPU time 64.58 seconds
Started Sep 04 03:48:01 PM UTC 24
Finished Sep 04 03:49:08 PM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479818960 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.479818960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.2872443656
Short name T300
Test name
Test status
Simulation time 38663703497 ps
CPU time 371.77 seconds
Started Sep 04 03:48:58 PM UTC 24
Finished Sep 04 03:55:15 PM UTC 24
Peak memory 348004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872443656 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.2872443656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.84043327
Short name T242
Test name
Test status
Simulation time 927795894 ps
CPU time 2.54 seconds
Started Sep 04 03:48:54 PM UTC 24
Finished Sep 04 03:48:58 PM UTC 24
Peak memory 213832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84043327 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.84043327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3353836878
Short name T251
Test name
Test status
Simulation time 499701111 ps
CPU time 78.29 seconds
Started Sep 04 03:48:40 PM UTC 24
Finished Sep 04 03:50:00 PM UTC 24
Peak memory 368428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
353836878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma
x_throughput.3353836878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2700257749
Short name T247
Test name
Test status
Simulation time 155915111 ps
CPU time 7.49 seconds
Started Sep 04 03:49:26 PM UTC 24
Finished Sep 04 03:49:35 PM UTC 24
Peak memory 223968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700257749 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2700257749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.623515440
Short name T246
Test name
Test status
Simulation time 147325387 ps
CPU time 11.79 seconds
Started Sep 04 03:49:12 PM UTC 24
Finished Sep 04 03:49:25 PM UTC 24
Peak memory 224412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623515440 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.623515440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3284684856
Short name T313
Test name
Test status
Simulation time 38041701088 ps
CPU time 482.66 seconds
Started Sep 04 03:47:59 PM UTC 24
Finished Sep 04 03:56:08 PM UTC 24
Peak memory 368500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284684856 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.3284684856
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1963941657
Short name T252
Test name
Test status
Simulation time 454999944 ps
CPU time 113.44 seconds
Started Sep 04 03:48:13 PM UTC 24
Finished Sep 04 03:50:09 PM UTC 24
Peak memory 378744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963941657 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.1963941657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2048770239
Short name T323
Test name
Test status
Simulation time 18239246535 ps
CPU time 531.11 seconds
Started Sep 04 03:48:30 PM UTC 24
Finished Sep 04 03:57:28 PM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048770239 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acc
ess_b2b.2048770239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2590523924
Short name T245
Test name
Test status
Simulation time 81785807 ps
CPU time 1.17 seconds
Started Sep 04 03:49:09 PM UTC 24
Finished Sep 04 03:49:11 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590523924 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2590523924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.934761625
Short name T330
Test name
Test status
Simulation time 108539644905 ps
CPU time 546.65 seconds
Started Sep 04 03:49:06 PM UTC 24
Finished Sep 04 03:58:19 PM UTC 24
Peak memory 380780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934761625 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.934761625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.1556618468
Short name T238
Test name
Test status
Simulation time 527681480 ps
CPU time 13.63 seconds
Started Sep 04 03:47:57 PM UTC 24
Finished Sep 04 03:48:12 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556618468 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1556618468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1933582857
Short name T627
Test name
Test status
Simulation time 27043093379 ps
CPU time 2079.63 seconds
Started Sep 04 03:49:42 PM UTC 24
Finished Sep 04 04:24:43 PM UTC 24
Peak memory 384616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193358285
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.1933582857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1593326202
Short name T267
Test name
Test status
Simulation time 615851452 ps
CPU time 141.52 seconds
Started Sep 04 03:49:36 PM UTC 24
Finished Sep 04 03:52:01 PM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593326202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1593326202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1361419641
Short name T291
Test name
Test status
Simulation time 6333676098 ps
CPU time 366.62 seconds
Started Sep 04 03:48:03 PM UTC 24
Finished Sep 04 03:54:15 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361419641 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.1361419641
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3216741831
Short name T249
Test name
Test status
Simulation time 168493908 ps
CPU time 57.58 seconds
Started Sep 04 03:48:45 PM UTC 24
Finished Sep 04 03:49:44 PM UTC 24
Peak memory 348272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3216741831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t
hroughput_w_partial_write.3216741831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2732674549
Short name T400
Test name
Test status
Simulation time 2636846973 ps
CPU time 767.85 seconds
Started Sep 04 03:50:47 PM UTC 24
Finished Sep 04 04:03:44 PM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732674549 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during
_key_req.2732674549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3668473423
Short name T263
Test name
Test status
Simulation time 145252206 ps
CPU time 0.93 seconds
Started Sep 04 03:51:44 PM UTC 24
Finished Sep 04 03:51:46 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668473423 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3668473423
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.967804113
Short name T264
Test name
Test status
Simulation time 21690917340 ps
CPU time 103.91 seconds
Started Sep 04 03:50:01 PM UTC 24
Finished Sep 04 03:51:47 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967804113 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.967804113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.755815809
Short name T379
Test name
Test status
Simulation time 11766855887 ps
CPU time 669.99 seconds
Started Sep 04 03:50:55 PM UTC 24
Finished Sep 04 04:02:13 PM UTC 24
Peak memory 362552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755815809 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.755815809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2457231529
Short name T255
Test name
Test status
Simulation time 204884358 ps
CPU time 3.6 seconds
Started Sep 04 03:50:41 PM UTC 24
Finished Sep 04 03:50:46 PM UTC 24
Peak memory 214128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457231529 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.2457231529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.825392540
Short name T268
Test name
Test status
Simulation time 586488696 ps
CPU time 100.59 seconds
Started Sep 04 03:50:39 PM UTC 24
Finished Sep 04 03:52:22 PM UTC 24
Peak memory 382840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8
25392540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_max
_throughput.825392540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2269836711
Short name T260
Test name
Test status
Simulation time 572095416 ps
CPU time 5 seconds
Started Sep 04 03:51:27 PM UTC 24
Finished Sep 04 03:51:33 PM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269836711 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2269836711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3832072873
Short name T261
Test name
Test status
Simulation time 467320259 ps
CPU time 14.26 seconds
Started Sep 04 03:51:25 PM UTC 24
Finished Sep 04 03:51:41 PM UTC 24
Peak memory 224036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832072873 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3832072873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3898108904
Short name T501
Test name
Test status
Simulation time 88719815330 ps
CPU time 1407.59 seconds
Started Sep 04 03:49:48 PM UTC 24
Finished Sep 04 04:13:30 PM UTC 24
Peak memory 386920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898108904 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.3898108904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3726526481
Short name T256
Test name
Test status
Simulation time 2750708420 ps
CPU time 28.45 seconds
Started Sep 04 03:50:24 PM UTC 24
Finished Sep 04 03:50:54 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726526481 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.3726526481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2194938369
Short name T344
Test name
Test status
Simulation time 52608556581 ps
CPU time 507.92 seconds
Started Sep 04 03:50:29 PM UTC 24
Finished Sep 04 03:59:04 PM UTC 24
Peak memory 213972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194938369 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc
ess_b2b.2194938369
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.1123458686
Short name T258
Test name
Test status
Simulation time 89033644 ps
CPU time 1.06 seconds
Started Sep 04 03:51:22 PM UTC 24
Finished Sep 04 03:51:24 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123458686 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1123458686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2793806417
Short name T277
Test name
Test status
Simulation time 1220410490 ps
CPU time 109.58 seconds
Started Sep 04 03:51:13 PM UTC 24
Finished Sep 04 03:53:05 PM UTC 24
Peak memory 372916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793806417 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2793806417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3663655260
Short name T259
Test name
Test status
Simulation time 143477975 ps
CPU time 99.04 seconds
Started Sep 04 03:49:45 PM UTC 24
Finished Sep 04 03:51:27 PM UTC 24
Peak memory 378748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663655260 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3663655260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.653413866
Short name T773
Test name
Test status
Simulation time 40249732192 ps
CPU time 2741.77 seconds
Started Sep 04 03:51:41 PM UTC 24
Finished Sep 04 04:37:53 PM UTC 24
Peak memory 388784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653413866
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.653413866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1222760624
Short name T262
Test name
Test status
Simulation time 177555137 ps
CPU time 8.53 seconds
Started Sep 04 03:51:34 PM UTC 24
Finished Sep 04 03:51:44 PM UTC 24
Peak memory 224160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222760624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1222760624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2202497516
Short name T283
Test name
Test status
Simulation time 1631731460 ps
CPU time 201.24 seconds
Started Sep 04 03:50:10 PM UTC 24
Finished Sep 04 03:53:34 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202497516 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2202497516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.615777270
Short name T265
Test name
Test status
Simulation time 855293716 ps
CPU time 72.32 seconds
Started Sep 04 03:50:41 PM UTC 24
Finished Sep 04 03:51:56 PM UTC 24
Peak memory 360244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
615777270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_th
roughput_w_partial_write.615777270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.748041283
Short name T371
Test name
Test status
Simulation time 4477394583 ps
CPU time 536.17 seconds
Started Sep 04 03:52:35 PM UTC 24
Finished Sep 04 04:01:38 PM UTC 24
Peak memory 378728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748041283 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during_
key_req.748041283
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3462682543
Short name T279
Test name
Test status
Simulation time 29592581 ps
CPU time 0.97 seconds
Started Sep 04 03:53:05 PM UTC 24
Finished Sep 04 03:53:07 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462682543 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3462682543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.536268867
Short name T289
Test name
Test status
Simulation time 55278108829 ps
CPU time 132.77 seconds
Started Sep 04 03:51:55 PM UTC 24
Finished Sep 04 03:54:10 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536268867 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.536268867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1174460907
Short name T443
Test name
Test status
Simulation time 3575137187 ps
CPU time 862.54 seconds
Started Sep 04 03:52:54 PM UTC 24
Finished Sep 04 04:07:26 PM UTC 24
Peak memory 385272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174460907 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.1174460907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1086783066
Short name T270
Test name
Test status
Simulation time 1262565222 ps
CPU time 8.24 seconds
Started Sep 04 03:52:25 PM UTC 24
Finished Sep 04 03:52:34 PM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086783066 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.1086783066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4036826919
Short name T287
Test name
Test status
Simulation time 155118600 ps
CPU time 89.54 seconds
Started Sep 04 03:52:22 PM UTC 24
Finished Sep 04 03:53:54 PM UTC 24
Peak memory 378736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
036826919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma
x_throughput.4036826919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2375949238
Short name T276
Test name
Test status
Simulation time 66726063 ps
CPU time 5.14 seconds
Started Sep 04 03:52:58 PM UTC 24
Finished Sep 04 03:53:04 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375949238 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2375949238
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.950547531
Short name T278
Test name
Test status
Simulation time 136500410 ps
CPU time 9.85 seconds
Started Sep 04 03:52:56 PM UTC 24
Finished Sep 04 03:53:07 PM UTC 24
Peak memory 224156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950547531 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.950547531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1292220848
Short name T398
Test name
Test status
Simulation time 10557723523 ps
CPU time 693.96 seconds
Started Sep 04 03:51:48 PM UTC 24
Finished Sep 04 04:03:29 PM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292220848 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.1292220848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1495078475
Short name T269
Test name
Test status
Simulation time 3785501735 ps
CPU time 24.23 seconds
Started Sep 04 03:51:58 PM UTC 24
Finished Sep 04 03:52:23 PM UTC 24
Peak memory 213996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495078475 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1495078475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.4038504667
Short name T346
Test name
Test status
Simulation time 59265920025 ps
CPU time 430.09 seconds
Started Sep 04 03:52:02 PM UTC 24
Finished Sep 04 03:59:18 PM UTC 24
Peak memory 213812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038504667 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acc
ess_b2b.4038504667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2046884518
Short name T273
Test name
Test status
Simulation time 30196614 ps
CPU time 0.98 seconds
Started Sep 04 03:52:55 PM UTC 24
Finished Sep 04 03:52:57 PM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046884518 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2046884518
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.664553405
Short name T357
Test name
Test status
Simulation time 73121343829 ps
CPU time 435.17 seconds
Started Sep 04 03:52:55 PM UTC 24
Finished Sep 04 04:00:15 PM UTC 24
Peak memory 379060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664553405 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.664553405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.204946597
Short name T266
Test name
Test status
Simulation time 708039266 ps
CPU time 8.78 seconds
Started Sep 04 03:51:48 PM UTC 24
Finished Sep 04 03:51:57 PM UTC 24
Peak memory 239736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204946597 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.204946597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2383118030
Short name T490
Test name
Test status
Simulation time 20102049795 ps
CPU time 1172.77 seconds
Started Sep 04 03:53:01 PM UTC 24
Finished Sep 04 04:12:46 PM UTC 24
Peak memory 364408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238311803
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.2383118030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2117724617
Short name T104
Test name
Test status
Simulation time 7200184878 ps
CPU time 145.32 seconds
Started Sep 04 03:52:59 PM UTC 24
Finished Sep 04 03:55:27 PM UTC 24
Peak memory 333728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117724617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2117724617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.4226470467
Short name T309
Test name
Test status
Simulation time 10268567152 ps
CPU time 227.24 seconds
Started Sep 04 03:51:57 PM UTC 24
Finished Sep 04 03:55:48 PM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226470467 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.4226470467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2395588751
Short name T275
Test name
Test status
Simulation time 415157874 ps
CPU time 35.37 seconds
Started Sep 04 03:52:23 PM UTC 24
Finished Sep 04 03:53:00 PM UTC 24
Peak memory 311148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2395588751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_t
hroughput_w_partial_write.2395588751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.774068697
Short name T423
Test name
Test status
Simulation time 3643465128 ps
CPU time 735.18 seconds
Started Sep 04 03:53:36 PM UTC 24
Finished Sep 04 04:05:59 PM UTC 24
Peak memory 383024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774068697 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during_
key_req.774068697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.936713076
Short name T294
Test name
Test status
Simulation time 45061827 ps
CPU time 0.81 seconds
Started Sep 04 03:54:20 PM UTC 24
Finished Sep 04 03:54:22 PM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936713076 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.936713076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.2965792916
Short name T286
Test name
Test status
Simulation time 2880177565 ps
CPU time 54.14 seconds
Started Sep 04 03:53:08 PM UTC 24
Finished Sep 04 03:54:03 PM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965792916 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.2965792916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2698867981
Short name T419
Test name
Test status
Simulation time 2610317755 ps
CPU time 709.32 seconds
Started Sep 04 03:53:49 PM UTC 24
Finished Sep 04 04:05:46 PM UTC 24
Peak memory 387000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698867981 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.2698867981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.839745525
Short name T285
Test name
Test status
Simulation time 504274978 ps
CPU time 11.14 seconds
Started Sep 04 03:53:35 PM UTC 24
Finished Sep 04 03:53:48 PM UTC 24
Peak memory 213880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839745525 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.839745525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1540268181
Short name T282
Test name
Test status
Simulation time 121719100 ps
CPU time 1.41 seconds
Started Sep 04 03:53:27 PM UTC 24
Finished Sep 04 03:53:30 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
540268181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma
x_throughput.1540268181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3891358925
Short name T292
Test name
Test status
Simulation time 88998663 ps
CPU time 7.44 seconds
Started Sep 04 03:54:11 PM UTC 24
Finished Sep 04 03:54:20 PM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891358925 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.3891358925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1347500201
Short name T290
Test name
Test status
Simulation time 296304430 ps
CPU time 5.98 seconds
Started Sep 04 03:54:07 PM UTC 24
Finished Sep 04 03:54:14 PM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347500201 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.1347500201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2596205087
Short name T439
Test name
Test status
Simulation time 3238308788 ps
CPU time 841.8 seconds
Started Sep 04 03:53:07 PM UTC 24
Finished Sep 04 04:07:18 PM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596205087 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.2596205087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2614088817
Short name T293
Test name
Test status
Simulation time 3421316104 ps
CPU time 70.67 seconds
Started Sep 04 03:53:10 PM UTC 24
Finished Sep 04 03:54:22 PM UTC 24
Peak memory 370544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614088817 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.2614088817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3565596177
Short name T376
Test name
Test status
Simulation time 16489656767 ps
CPU time 517.38 seconds
Started Sep 04 03:53:16 PM UTC 24
Finished Sep 04 04:02:00 PM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565596177 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acc
ess_b2b.3565596177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1059651451
Short name T288
Test name
Test status
Simulation time 29556690 ps
CPU time 1.13 seconds
Started Sep 04 03:54:04 PM UTC 24
Finished Sep 04 03:54:06 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059651451 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1059651451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.3555519313
Short name T360
Test name
Test status
Simulation time 6794353210 ps
CPU time 388.34 seconds
Started Sep 04 03:53:55 PM UTC 24
Finished Sep 04 04:00:28 PM UTC 24
Peak memory 384876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555519313 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3555519313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2346317374
Short name T280
Test name
Test status
Simulation time 141637663 ps
CPU time 1.4 seconds
Started Sep 04 03:53:06 PM UTC 24
Finished Sep 04 03:53:09 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346317374 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2346317374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3071607968
Short name T936
Test name
Test status
Simulation time 507006435927 ps
CPU time 4521.45 seconds
Started Sep 04 03:54:15 PM UTC 24
Finished Sep 04 05:10:25 PM UTC 24
Peak memory 388712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307160796
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.3071607968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2821315031
Short name T306
Test name
Test status
Simulation time 2131743960 ps
CPU time 85.83 seconds
Started Sep 04 03:54:15 PM UTC 24
Finished Sep 04 03:55:43 PM UTC 24
Peak memory 317616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821315031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2821315031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.516076678
Short name T350
Test name
Test status
Simulation time 14224124100 ps
CPU time 382.94 seconds
Started Sep 04 03:53:09 PM UTC 24
Finished Sep 04 03:59:37 PM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516076678 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.516076678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3167866030
Short name T296
Test name
Test status
Simulation time 135439017 ps
CPU time 57.01 seconds
Started Sep 04 03:53:30 PM UTC 24
Finished Sep 04 03:54:29 PM UTC 24
Peak memory 350316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3167866030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t
hroughput_w_partial_write.3167866030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3041961412
Short name T451
Test name
Test status
Simulation time 3025963446 ps
CPU time 769.96 seconds
Started Sep 04 03:55:16 PM UTC 24
Finished Sep 04 04:08:16 PM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041961412 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during
_key_req.3041961412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2630059847
Short name T308
Test name
Test status
Simulation time 41699935 ps
CPU time 0.87 seconds
Started Sep 04 03:55:44 PM UTC 24
Finished Sep 04 03:55:46 PM UTC 24
Peak memory 212576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630059847 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2630059847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.2214564209
Short name T303
Test name
Test status
Simulation time 5515083918 ps
CPU time 55.99 seconds
Started Sep 04 03:54:25 PM UTC 24
Finished Sep 04 03:55:22 PM UTC 24
Peak memory 213992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214564209 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.2214564209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1588581997
Short name T424
Test name
Test status
Simulation time 2413131598 ps
CPU time 634.74 seconds
Started Sep 04 03:55:18 PM UTC 24
Finished Sep 04 04:06:00 PM UTC 24
Peak memory 379076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588581997 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.1588581997
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1357702934
Short name T301
Test name
Test status
Simulation time 647391661 ps
CPU time 11.38 seconds
Started Sep 04 03:55:05 PM UTC 24
Finished Sep 04 03:55:18 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357702934 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1357702934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2617335747
Short name T312
Test name
Test status
Simulation time 268030105 ps
CPU time 86.99 seconds
Started Sep 04 03:54:36 PM UTC 24
Finished Sep 04 03:56:05 PM UTC 24
Peak memory 380712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
617335747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ma
x_throughput.2617335747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1513697476
Short name T305
Test name
Test status
Simulation time 356031732 ps
CPU time 5.45 seconds
Started Sep 04 03:55:28 PM UTC 24
Finished Sep 04 03:55:35 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513697476 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.1513697476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.4113507631
Short name T307
Test name
Test status
Simulation time 2744417985 ps
CPU time 18.01 seconds
Started Sep 04 03:55:27 PM UTC 24
Finished Sep 04 03:55:46 PM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113507631 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.4113507631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3900654356
Short name T395
Test name
Test status
Simulation time 19713417897 ps
CPU time 529.57 seconds
Started Sep 04 03:54:25 PM UTC 24
Finished Sep 04 04:03:21 PM UTC 24
Peak memory 354484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900654356 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3900654356
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3331362865
Short name T299
Test name
Test status
Simulation time 1299039068 ps
CPU time 32.6 seconds
Started Sep 04 03:54:30 PM UTC 24
Finished Sep 04 03:55:04 PM UTC 24
Peak memory 298820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331362865 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.3331362865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.4109341569
Short name T332
Test name
Test status
Simulation time 10253626822 ps
CPU time 231.27 seconds
Started Sep 04 03:54:30 PM UTC 24
Finished Sep 04 03:58:25 PM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109341569 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acc
ess_b2b.4109341569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2024729568
Short name T304
Test name
Test status
Simulation time 77151061 ps
CPU time 1.17 seconds
Started Sep 04 03:55:24 PM UTC 24
Finished Sep 04 03:55:26 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024729568 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2024729568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.907035562
Short name T326
Test name
Test status
Simulation time 13526606447 ps
CPU time 134.48 seconds
Started Sep 04 03:55:21 PM UTC 24
Finished Sep 04 03:57:37 PM UTC 24
Peak memory 370828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907035562 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.907035562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3354160765
Short name T298
Test name
Test status
Simulation time 1295727117 ps
CPU time 10.82 seconds
Started Sep 04 03:54:24 PM UTC 24
Finished Sep 04 03:54:36 PM UTC 24
Peak memory 245820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354160765 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3354160765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.62389494
Short name T907
Test name
Test status
Simulation time 35717996517 ps
CPU time 3385.7 seconds
Started Sep 04 03:55:36 PM UTC 24
Finished Sep 04 04:52:36 PM UTC 24
Peak memory 388696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62389494
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.62389494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.4144752535
Short name T325
Test name
Test status
Simulation time 6360559640 ps
CPU time 181.2 seconds
Started Sep 04 03:54:28 PM UTC 24
Finished Sep 04 03:57:32 PM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144752535 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.4144752535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3797897409
Short name T302
Test name
Test status
Simulation time 105517634 ps
CPU time 35.82 seconds
Started Sep 04 03:54:42 PM UTC 24
Finished Sep 04 03:55:19 PM UTC 24
Peak memory 313196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3797897409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t
hroughput_w_partial_write.3797897409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.592824982
Short name T452
Test name
Test status
Simulation time 2722647892 ps
CPU time 689.16 seconds
Started Sep 04 03:56:40 PM UTC 24
Finished Sep 04 04:08:17 PM UTC 24
Peak memory 380836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592824982 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_
key_req.592824982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3500357442
Short name T324
Test name
Test status
Simulation time 26272036 ps
CPU time 0.95 seconds
Started Sep 04 03:57:29 PM UTC 24
Finished Sep 04 03:57:31 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500357442 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3500357442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.772717427
Short name T319
Test name
Test status
Simulation time 3551032082 ps
CPU time 68.46 seconds
Started Sep 04 03:55:48 PM UTC 24
Finished Sep 04 03:56:59 PM UTC 24
Peak memory 213992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772717427 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.772717427
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.479299391
Short name T503
Test name
Test status
Simulation time 62460668670 ps
CPU time 1030.51 seconds
Started Sep 04 03:56:40 PM UTC 24
Finished Sep 04 04:14:02 PM UTC 24
Peak memory 384876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479299391 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.479299391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1977555682
Short name T318
Test name
Test status
Simulation time 1940568933 ps
CPU time 9.49 seconds
Started Sep 04 03:56:40 PM UTC 24
Finished Sep 04 03:56:51 PM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977555682 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.1977555682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2354232257
Short name T327
Test name
Test status
Simulation time 262699830 ps
CPU time 99.19 seconds
Started Sep 04 03:56:09 PM UTC 24
Finished Sep 04 03:57:50 PM UTC 24
Peak memory 380980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
354232257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma
x_throughput.2354232257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.4248997807
Short name T322
Test name
Test status
Simulation time 182834521 ps
CPU time 4.54 seconds
Started Sep 04 03:57:13 PM UTC 24
Finished Sep 04 03:57:18 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248997807 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.4248997807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3534511276
Short name T321
Test name
Test status
Simulation time 347534978 ps
CPU time 8.01 seconds
Started Sep 04 03:57:03 PM UTC 24
Finished Sep 04 03:57:12 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534511276 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.3534511276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3451906063
Short name T335
Test name
Test status
Simulation time 2229321458 ps
CPU time 162.29 seconds
Started Sep 04 03:55:47 PM UTC 24
Finished Sep 04 03:58:33 PM UTC 24
Peak memory 382896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451906063 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.3451906063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1732467695
Short name T314
Test name
Test status
Simulation time 840214132 ps
CPU time 42.25 seconds
Started Sep 04 03:55:52 PM UTC 24
Finished Sep 04 03:56:36 PM UTC 24
Peak memory 303288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732467695 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1732467695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1855168112
Short name T385
Test name
Test status
Simulation time 22215539212 ps
CPU time 392.96 seconds
Started Sep 04 03:56:07 PM UTC 24
Finished Sep 04 04:02:45 PM UTC 24
Peak memory 213948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855168112 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acc
ess_b2b.1855168112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3602929815
Short name T320
Test name
Test status
Simulation time 51835941 ps
CPU time 1.04 seconds
Started Sep 04 03:57:00 PM UTC 24
Finished Sep 04 03:57:02 PM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602929815 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3602929815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3458471510
Short name T487
Test name
Test status
Simulation time 52863445494 ps
CPU time 936.73 seconds
Started Sep 04 03:56:51 PM UTC 24
Finished Sep 04 04:12:38 PM UTC 24
Peak memory 384952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458471510 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3458471510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.1347778512
Short name T317
Test name
Test status
Simulation time 402378925 ps
CPU time 50.25 seconds
Started Sep 04 03:55:47 PM UTC 24
Finished Sep 04 03:56:39 PM UTC 24
Peak memory 311164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347778512 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1347778512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.414935054
Short name T849
Test name
Test status
Simulation time 161762435998 ps
CPU time 2790.08 seconds
Started Sep 04 03:57:23 PM UTC 24
Finished Sep 04 04:44:22 PM UTC 24
Peak memory 388676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414935054
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.414935054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2963206165
Short name T342
Test name
Test status
Simulation time 2539278539 ps
CPU time 89.16 seconds
Started Sep 04 03:57:19 PM UTC 24
Finished Sep 04 03:58:50 PM UTC 24
Peak memory 348080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963206165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2963206165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1553111444
Short name T361
Test name
Test status
Simulation time 9339706469 ps
CPU time 274.69 seconds
Started Sep 04 03:55:52 PM UTC 24
Finished Sep 04 04:00:31 PM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553111444 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.1553111444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1620530520
Short name T315
Test name
Test status
Simulation time 230093863 ps
CPU time 2.04 seconds
Started Sep 04 03:56:36 PM UTC 24
Finished Sep 04 03:56:39 PM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1620530520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_t
hroughput_w_partial_write.1620530520
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.680096319
Short name T570
Test name
Test status
Simulation time 17685395292 ps
CPU time 1287.34 seconds
Started Sep 04 03:58:26 PM UTC 24
Finished Sep 04 04:20:07 PM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680096319 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during_
key_req.680096319
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3906674768
Short name T341
Test name
Test status
Simulation time 36208478 ps
CPU time 0.85 seconds
Started Sep 04 03:58:44 PM UTC 24
Finished Sep 04 03:58:46 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906674768 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3906674768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.310576378
Short name T338
Test name
Test status
Simulation time 9086070738 ps
CPU time 55.85 seconds
Started Sep 04 03:57:38 PM UTC 24
Finished Sep 04 03:58:36 PM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310576378 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.310576378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.255805450
Short name T559
Test name
Test status
Simulation time 72286015676 ps
CPU time 1244.73 seconds
Started Sep 04 03:58:29 PM UTC 24
Finished Sep 04 04:19:27 PM UTC 24
Peak memory 386988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255805450 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.255805450
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.291106976
Short name T333
Test name
Test status
Simulation time 1019603762 ps
CPU time 6.95 seconds
Started Sep 04 03:58:20 PM UTC 24
Finished Sep 04 03:58:28 PM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291106976 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.291106976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1465031746
Short name T331
Test name
Test status
Simulation time 48231305 ps
CPU time 4.66 seconds
Started Sep 04 03:58:14 PM UTC 24
Finished Sep 04 03:58:19 PM UTC 24
Peak memory 235376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
465031746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ma
x_throughput.1465031746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3868260996
Short name T340
Test name
Test status
Simulation time 149427002 ps
CPU time 5.21 seconds
Started Sep 04 03:58:36 PM UTC 24
Finished Sep 04 03:58:43 PM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868260996 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.3868260996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3281952368
Short name T343
Test name
Test status
Simulation time 899704528 ps
CPU time 16.35 seconds
Started Sep 04 03:58:34 PM UTC 24
Finished Sep 04 03:58:52 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281952368 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.3281952368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3323868483
Short name T417
Test name
Test status
Simulation time 2624955206 ps
CPU time 480.92 seconds
Started Sep 04 03:57:32 PM UTC 24
Finished Sep 04 04:05:39 PM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323868483 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.3323868483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.771092969
Short name T337
Test name
Test status
Simulation time 142909054 ps
CPU time 39.61 seconds
Started Sep 04 03:57:53 PM UTC 24
Finished Sep 04 03:58:34 PM UTC 24
Peak memory 313156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771092969 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.771092969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.913921473
Short name T399
Test name
Test status
Simulation time 41292248600 ps
CPU time 334.22 seconds
Started Sep 04 03:57:54 PM UTC 24
Finished Sep 04 04:03:32 PM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913921473 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acce
ss_b2b.913921473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2364667663
Short name T339
Test name
Test status
Simulation time 45149783 ps
CPU time 1.25 seconds
Started Sep 04 03:58:34 PM UTC 24
Finished Sep 04 03:58:37 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364667663 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2364667663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.4077246436
Short name T387
Test name
Test status
Simulation time 6334152050 ps
CPU time 258.96 seconds
Started Sep 04 03:58:32 PM UTC 24
Finished Sep 04 04:02:55 PM UTC 24
Peak memory 380856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077246436 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.4077246436
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.87860349
Short name T328
Test name
Test status
Simulation time 251248486 ps
CPU time 19.54 seconds
Started Sep 04 03:57:32 PM UTC 24
Finished Sep 04 03:57:53 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87860349 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.87860349
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.420335518
Short name T647
Test name
Test status
Simulation time 27742404547 ps
CPU time 1662.25 seconds
Started Sep 04 03:58:38 PM UTC 24
Finished Sep 04 04:26:38 PM UTC 24
Peak memory 395072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420335518
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.420335518
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2767624058
Short name T470
Test name
Test status
Simulation time 2678463800 ps
CPU time 703.82 seconds
Started Sep 04 03:58:37 PM UTC 24
Finished Sep 04 04:10:29 PM UTC 24
Peak memory 385004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767624058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2767624058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1001110993
Short name T377
Test name
Test status
Simulation time 2150095994 ps
CPU time 245.76 seconds
Started Sep 04 03:57:52 PM UTC 24
Finished Sep 04 04:02:02 PM UTC 24
Peak memory 214276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001110993 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.1001110993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1137000514
Short name T347
Test name
Test status
Simulation time 116699531 ps
CPU time 56.39 seconds
Started Sep 04 03:58:20 PM UTC 24
Finished Sep 04 03:59:18 PM UTC 24
Peak memory 329508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1137000514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t
hroughput_w_partial_write.1137000514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3533698129
Short name T435
Test name
Test status
Simulation time 12069408857 ps
CPU time 438.35 seconds
Started Sep 04 03:59:36 PM UTC 24
Finished Sep 04 04:07:00 PM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533698129 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during
_key_req.3533698129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2092762875
Short name T358
Test name
Test status
Simulation time 58161267 ps
CPU time 0.96 seconds
Started Sep 04 04:00:16 PM UTC 24
Finished Sep 04 04:00:18 PM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092762875 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2092762875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1229468980
Short name T365
Test name
Test status
Simulation time 45732468296 ps
CPU time 111.43 seconds
Started Sep 04 03:58:53 PM UTC 24
Finished Sep 04 04:00:47 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229468980 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1229468980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.431552695
Short name T506
Test name
Test status
Simulation time 119927229363 ps
CPU time 903.19 seconds
Started Sep 04 03:59:38 PM UTC 24
Finished Sep 04 04:14:51 PM UTC 24
Peak memory 386992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431552695 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.431552695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1126319938
Short name T352
Test name
Test status
Simulation time 3149028460 ps
CPU time 9.72 seconds
Started Sep 04 03:59:30 PM UTC 24
Finished Sep 04 03:59:40 PM UTC 24
Peak memory 214200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126319938 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.1126319938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3145288092
Short name T348
Test name
Test status
Simulation time 163626860 ps
CPU time 8.85 seconds
Started Sep 04 03:59:19 PM UTC 24
Finished Sep 04 03:59:29 PM UTC 24
Peak memory 249712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
145288092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma
x_throughput.3145288092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3734686351
Short name T354
Test name
Test status
Simulation time 70008173 ps
CPU time 3.78 seconds
Started Sep 04 03:59:45 PM UTC 24
Finished Sep 04 03:59:50 PM UTC 24
Peak memory 223984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734686351 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.3734686351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.581209877
Short name T355
Test name
Test status
Simulation time 355520076 ps
CPU time 7.03 seconds
Started Sep 04 03:59:44 PM UTC 24
Finished Sep 04 03:59:52 PM UTC 24
Peak memory 224204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581209877 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.581209877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1110085293
Short name T462
Test name
Test status
Simulation time 1635922785 ps
CPU time 598.74 seconds
Started Sep 04 03:58:51 PM UTC 24
Finished Sep 04 04:08:57 PM UTC 24
Peak memory 382764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110085293 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1110085293
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3562964788
Short name T363
Test name
Test status
Simulation time 819823213 ps
CPU time 88.44 seconds
Started Sep 04 03:59:13 PM UTC 24
Finished Sep 04 04:00:44 PM UTC 24
Peak memory 372600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562964788 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.3562964788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1526584479
Short name T434
Test name
Test status
Simulation time 16139839047 ps
CPU time 449.57 seconds
Started Sep 04 03:59:19 PM UTC 24
Finished Sep 04 04:06:54 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526584479 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc
ess_b2b.1526584479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1887437859
Short name T353
Test name
Test status
Simulation time 92701206 ps
CPU time 1.24 seconds
Started Sep 04 03:59:41 PM UTC 24
Finished Sep 04 03:59:43 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887437859 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1887437859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.517914375
Short name T374
Test name
Test status
Simulation time 7326891823 ps
CPU time 126.98 seconds
Started Sep 04 03:59:39 PM UTC 24
Finished Sep 04 04:01:48 PM UTC 24
Peak memory 339972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517914375 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.517914375
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2332351110
Short name T349
Test name
Test status
Simulation time 104078314 ps
CPU time 46.39 seconds
Started Sep 04 03:58:47 PM UTC 24
Finished Sep 04 03:59:35 PM UTC 24
Peak memory 321404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332351110 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2332351110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.226013957
Short name T800
Test name
Test status
Simulation time 42767248689 ps
CPU time 2377.66 seconds
Started Sep 04 03:59:54 PM UTC 24
Finished Sep 04 04:39:57 PM UTC 24
Peak memory 397048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226013957
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.226013957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.379566027
Short name T397
Test name
Test status
Simulation time 3960704563 ps
CPU time 213.18 seconds
Started Sep 04 03:59:52 PM UTC 24
Finished Sep 04 04:03:28 PM UTC 24
Peak memory 366500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379566027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.379566027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2433111483
Short name T391
Test name
Test status
Simulation time 4786739783 ps
CPU time 245.01 seconds
Started Sep 04 03:59:04 PM UTC 24
Finished Sep 04 04:03:13 PM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433111483 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.2433111483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.967974241
Short name T356
Test name
Test status
Simulation time 118497693 ps
CPU time 48.8 seconds
Started Sep 04 03:59:25 PM UTC 24
Finished Sep 04 04:00:15 PM UTC 24
Peak memory 321644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
967974241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_th
roughput_w_partial_write.967974241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2788438621
Short name T34
Test name
Test status
Simulation time 1820491169 ps
CPU time 386.01 seconds
Started Sep 04 03:33:47 PM UTC 24
Finished Sep 04 03:40:18 PM UTC 24
Peak memory 360228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788438621 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_
key_req.2788438621
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3063832080
Short name T14
Test name
Test status
Simulation time 14886346 ps
CPU time 0.96 seconds
Started Sep 04 03:34:35 PM UTC 24
Finished Sep 04 03:34:37 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063832080 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3063832080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2057508348
Short name T157
Test name
Test status
Simulation time 21624051586 ps
CPU time 135.98 seconds
Started Sep 04 03:33:10 PM UTC 24
Finished Sep 04 03:35:28 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057508348 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.2057508348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1870311442
Short name T138
Test name
Test status
Simulation time 2985693677 ps
CPU time 881.33 seconds
Started Sep 04 03:33:48 PM UTC 24
Finished Sep 04 03:48:39 PM UTC 24
Peak memory 385256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870311442 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.1870311442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2110475849
Short name T8
Test name
Test status
Simulation time 353253721 ps
CPU time 5.29 seconds
Started Sep 04 03:33:41 PM UTC 24
Finished Sep 04 03:33:47 PM UTC 24
Peak memory 214072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110475849 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.2110475849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3006690716
Short name T153
Test name
Test status
Simulation time 137756921 ps
CPU time 89.19 seconds
Started Sep 04 03:33:32 PM UTC 24
Finished Sep 04 03:35:03 PM UTC 24
Peak memory 381032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
006690716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max
_throughput.3006690716
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1640687266
Short name T38
Test name
Test status
Simulation time 676151738 ps
CPU time 8.55 seconds
Started Sep 04 03:34:07 PM UTC 24
Finished Sep 04 03:34:16 PM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640687266 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.1640687266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1791928058
Short name T129
Test name
Test status
Simulation time 525159395 ps
CPU time 12.76 seconds
Started Sep 04 03:33:58 PM UTC 24
Finished Sep 04 03:34:12 PM UTC 24
Peak memory 223992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791928058 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.1791928058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2709360612
Short name T68
Test name
Test status
Simulation time 8543602213 ps
CPU time 55.74 seconds
Started Sep 04 03:33:08 PM UTC 24
Finished Sep 04 03:34:06 PM UTC 24
Peak memory 224508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709360612 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.2709360612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2691209632
Short name T67
Test name
Test status
Simulation time 296347039 ps
CPU time 8.51 seconds
Started Sep 04 03:33:24 PM UTC 24
Finished Sep 04 03:33:33 PM UTC 24
Peak memory 237420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691209632 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.2691209632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2557571219
Short name T27
Test name
Test status
Simulation time 61662705 ps
CPU time 1.23 seconds
Started Sep 04 03:33:55 PM UTC 24
Finished Sep 04 03:33:57 PM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557571219 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2557571219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.1931462544
Short name T37
Test name
Test status
Simulation time 2992243423 ps
CPU time 79.15 seconds
Started Sep 04 03:33:53 PM UTC 24
Finished Sep 04 03:35:14 PM UTC 24
Peak memory 303012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931462544 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1931462544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3676131859
Short name T16
Test name
Test status
Simulation time 406445207 ps
CPU time 5.23 seconds
Started Sep 04 03:34:27 PM UTC 24
Finished Sep 04 03:34:34 PM UTC 24
Peak memory 250080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676131859 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3676131859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.4265917154
Short name T56
Test name
Test status
Simulation time 535650053 ps
CPU time 13.7 seconds
Started Sep 04 03:33:06 PM UTC 24
Finished Sep 04 03:33:21 PM UTC 24
Peak memory 214064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265917154 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.4265917154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3090234571
Short name T404
Test name
Test status
Simulation time 46719440726 ps
CPU time 1772.41 seconds
Started Sep 04 03:34:17 PM UTC 24
Finished Sep 04 04:04:07 PM UTC 24
Peak memory 388744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309023457
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.3090234571
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4208520943
Short name T25
Test name
Test status
Simulation time 298571730 ps
CPU time 24.64 seconds
Started Sep 04 03:34:13 PM UTC 24
Finished Sep 04 03:34:39 PM UTC 24
Peak memory 247680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208520943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.4208520943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1268065412
Short name T95
Test name
Test status
Simulation time 12601125236 ps
CPU time 298.49 seconds
Started Sep 04 03:33:23 PM UTC 24
Finished Sep 04 03:38:26 PM UTC 24
Peak memory 214144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268065412 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.1268065412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3988213000
Short name T147
Test name
Test status
Simulation time 77690742 ps
CPU time 11.39 seconds
Started Sep 04 03:33:34 PM UTC 24
Finished Sep 04 03:33:46 PM UTC 24
Peak memory 252012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3988213000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th
roughput_w_partial_write.3988213000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2816000004
Short name T471
Test name
Test status
Simulation time 6358347427 ps
CPU time 586.46 seconds
Started Sep 04 04:00:51 PM UTC 24
Finished Sep 04 04:10:45 PM UTC 24
Peak memory 384884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816000004 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during
_key_req.2816000004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1047537715
Short name T375
Test name
Test status
Simulation time 15733113 ps
CPU time 0.97 seconds
Started Sep 04 04:01:49 PM UTC 24
Finished Sep 04 04:01:51 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047537715 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1047537715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.2873923435
Short name T364
Test name
Test status
Simulation time 1391585891 ps
CPU time 19.47 seconds
Started Sep 04 04:00:25 PM UTC 24
Finished Sep 04 04:00:46 PM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873923435 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.2873923435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.795992265
Short name T520
Test name
Test status
Simulation time 13468879302 ps
CPU time 922.57 seconds
Started Sep 04 04:00:55 PM UTC 24
Finished Sep 04 04:16:28 PM UTC 24
Peak memory 380776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795992265 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.795992265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2479012258
Short name T368
Test name
Test status
Simulation time 3296484927 ps
CPU time 17.6 seconds
Started Sep 04 04:00:48 PM UTC 24
Finished Sep 04 04:01:07 PM UTC 24
Peak memory 214004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479012258 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.2479012258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.663165686
Short name T381
Test name
Test status
Simulation time 289121086 ps
CPU time 97.27 seconds
Started Sep 04 04:00:45 PM UTC 24
Finished Sep 04 04:02:24 PM UTC 24
Peak memory 376696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
63165686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max
_throughput.663165686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.2589519596
Short name T373
Test name
Test status
Simulation time 490978973 ps
CPU time 6.46 seconds
Started Sep 04 04:01:39 PM UTC 24
Finished Sep 04 04:01:46 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589519596 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.2589519596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2234462612
Short name T372
Test name
Test status
Simulation time 642664721 ps
CPU time 12.56 seconds
Started Sep 04 04:01:28 PM UTC 24
Finished Sep 04 04:01:42 PM UTC 24
Peak memory 224004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234462612 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.2234462612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1564961462
Short name T384
Test name
Test status
Simulation time 8261890737 ps
CPU time 142.17 seconds
Started Sep 04 04:00:19 PM UTC 24
Finished Sep 04 04:02:44 PM UTC 24
Peak memory 370924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564961462 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.1564961462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2479484465
Short name T369
Test name
Test status
Simulation time 242399797 ps
CPU time 51.74 seconds
Started Sep 04 04:00:31 PM UTC 24
Finished Sep 04 04:01:25 PM UTC 24
Peak memory 354168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479484465 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.2479484465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1982107381
Short name T459
Test name
Test status
Simulation time 7548801512 ps
CPU time 475.11 seconds
Started Sep 04 04:00:42 PM UTC 24
Finished Sep 04 04:08:44 PM UTC 24
Peak memory 214228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982107381 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc
ess_b2b.1982107381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2467943300
Short name T370
Test name
Test status
Simulation time 215048501 ps
CPU time 1.31 seconds
Started Sep 04 04:01:25 PM UTC 24
Finished Sep 04 04:01:28 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467943300 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2467943300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.2721403684
Short name T493
Test name
Test status
Simulation time 52282435529 ps
CPU time 700 seconds
Started Sep 04 04:01:07 PM UTC 24
Finished Sep 04 04:12:55 PM UTC 24
Peak memory 384816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721403684 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2721403684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.272136770
Short name T359
Test name
Test status
Simulation time 1425029703 ps
CPU time 7.47 seconds
Started Sep 04 04:00:16 PM UTC 24
Finished Sep 04 04:00:25 PM UTC 24
Peak memory 213776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272136770 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.272136770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.144206753
Short name T908
Test name
Test status
Simulation time 184261117152 ps
CPU time 3030.48 seconds
Started Sep 04 04:01:48 PM UTC 24
Finished Sep 04 04:52:49 PM UTC 24
Peak memory 388724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144206753
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.144206753
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3394714112
Short name T402
Test name
Test status
Simulation time 3380823605 ps
CPU time 134.29 seconds
Started Sep 04 04:01:43 PM UTC 24
Finished Sep 04 04:04:00 PM UTC 24
Peak memory 366572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394714112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3394714112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3602948035
Short name T418
Test name
Test status
Simulation time 2981958802 ps
CPU time 310.38 seconds
Started Sep 04 04:00:29 PM UTC 24
Finished Sep 04 04:05:44 PM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602948035 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.3602948035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.552372530
Short name T367
Test name
Test status
Simulation time 58988754 ps
CPU time 6.88 seconds
Started Sep 04 04:00:47 PM UTC 24
Finished Sep 04 04:00:55 PM UTC 24
Peak memory 239724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
552372530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_th
roughput_w_partial_write.552372530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1546894962
Short name T557
Test name
Test status
Simulation time 5809891426 ps
CPU time 982.59 seconds
Started Sep 04 04:02:45 PM UTC 24
Finished Sep 04 04:19:18 PM UTC 24
Peak memory 385192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546894962 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during
_key_req.1546894962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.4195758057
Short name T394
Test name
Test status
Simulation time 80847229 ps
CPU time 1.04 seconds
Started Sep 04 04:03:18 PM UTC 24
Finished Sep 04 04:03:20 PM UTC 24
Peak memory 212612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195758057 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.4195758057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.672290555
Short name T388
Test name
Test status
Simulation time 2876068604 ps
CPU time 54.59 seconds
Started Sep 04 04:02:02 PM UTC 24
Finished Sep 04 04:02:59 PM UTC 24
Peak memory 213792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672290555 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.672290555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2622163824
Short name T552
Test name
Test status
Simulation time 8389791963 ps
CPU time 952.67 seconds
Started Sep 04 04:02:46 PM UTC 24
Finished Sep 04 04:18:49 PM UTC 24
Peak memory 382900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622163824 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.2622163824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.203737367
Short name T386
Test name
Test status
Simulation time 565642299 ps
CPU time 9.04 seconds
Started Sep 04 04:02:40 PM UTC 24
Finished Sep 04 04:02:50 PM UTC 24
Peak memory 228540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203737367 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.203737367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.500738466
Short name T382
Test name
Test status
Simulation time 192052382 ps
CPU time 5.57 seconds
Started Sep 04 04:02:25 PM UTC 24
Finished Sep 04 04:02:31 PM UTC 24
Peak memory 231540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5
00738466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_max
_throughput.500738466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3242007170
Short name T390
Test name
Test status
Simulation time 175423292 ps
CPU time 3.84 seconds
Started Sep 04 04:03:00 PM UTC 24
Finished Sep 04 04:03:05 PM UTC 24
Peak memory 223960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242007170 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.3242007170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2621989166
Short name T392
Test name
Test status
Simulation time 1818067660 ps
CPU time 16.24 seconds
Started Sep 04 04:03:00 PM UTC 24
Finished Sep 04 04:03:17 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621989166 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.2621989166
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.492439497
Short name T410
Test name
Test status
Simulation time 1825668796 ps
CPU time 152.27 seconds
Started Sep 04 04:02:01 PM UTC 24
Finished Sep 04 04:04:36 PM UTC 24
Peak memory 384884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492439497 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.492439497
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2007728995
Short name T383
Test name
Test status
Simulation time 883270982 ps
CPU time 24.17 seconds
Started Sep 04 04:02:13 PM UTC 24
Finished Sep 04 04:02:39 PM UTC 24
Peak memory 213764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007728995 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2007728995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2854051056
Short name T442
Test name
Test status
Simulation time 7661469449 ps
CPU time 305.21 seconds
Started Sep 04 04:02:15 PM UTC 24
Finished Sep 04 04:07:24 PM UTC 24
Peak memory 214208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854051056 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc
ess_b2b.2854051056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1782100709
Short name T389
Test name
Test status
Simulation time 74768459 ps
CPU time 1.2 seconds
Started Sep 04 04:02:57 PM UTC 24
Finished Sep 04 04:02:59 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782100709 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1782100709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.3620446683
Short name T625
Test name
Test status
Simulation time 16002754012 ps
CPU time 1293.42 seconds
Started Sep 04 04:02:51 PM UTC 24
Finished Sep 04 04:24:39 PM UTC 24
Peak memory 376704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620446683 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3620446683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.1747851117
Short name T380
Test name
Test status
Simulation time 76157946 ps
CPU time 19.95 seconds
Started Sep 04 04:01:52 PM UTC 24
Finished Sep 04 04:02:13 PM UTC 24
Peak memory 292732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747851117 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1747851117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3604835000
Short name T618
Test name
Test status
Simulation time 36850121477 ps
CPU time 1214.84 seconds
Started Sep 04 04:03:14 PM UTC 24
Finished Sep 04 04:23:43 PM UTC 24
Peak memory 382748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360483500
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.3604835000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2862293292
Short name T475
Test name
Test status
Simulation time 6138552174 ps
CPU time 479.81 seconds
Started Sep 04 04:03:06 PM UTC 24
Finished Sep 04 04:11:12 PM UTC 24
Peak memory 386980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862293292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2862293292
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.117255383
Short name T431
Test name
Test status
Simulation time 9181920989 ps
CPU time 254.84 seconds
Started Sep 04 04:02:13 PM UTC 24
Finished Sep 04 04:06:32 PM UTC 24
Peak memory 214196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117255383 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.117255383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.24788284
Short name T393
Test name
Test status
Simulation time 141869772 ps
CPU time 45.15 seconds
Started Sep 04 04:02:32 PM UTC 24
Finished Sep 04 04:03:18 PM UTC 24
Peak memory 337772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
24788284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_thr
oughput_w_partial_write.24788284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.4045820693
Short name T581
Test name
Test status
Simulation time 4247108844 ps
CPU time 993.71 seconds
Started Sep 04 04:04:01 PM UTC 24
Finished Sep 04 04:20:46 PM UTC 24
Peak memory 382816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045820693 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during
_key_req.4045820693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.3973115102
Short name T411
Test name
Test status
Simulation time 14105068 ps
CPU time 0.79 seconds
Started Sep 04 04:04:36 PM UTC 24
Finished Sep 04 04:04:38 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973115102 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3973115102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.2324344426
Short name T409
Test name
Test status
Simulation time 8290906527 ps
CPU time 69.84 seconds
Started Sep 04 04:03:22 PM UTC 24
Finished Sep 04 04:04:34 PM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324344426 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.2324344426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.1452777025
Short name T529
Test name
Test status
Simulation time 34694557616 ps
CPU time 756.01 seconds
Started Sep 04 04:04:02 PM UTC 24
Finished Sep 04 04:16:47 PM UTC 24
Peak memory 376768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452777025 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.1452777025
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3753660079
Short name T403
Test name
Test status
Simulation time 297741198 ps
CPU time 5.49 seconds
Started Sep 04 04:03:55 PM UTC 24
Finished Sep 04 04:04:02 PM UTC 24
Peak memory 224168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753660079 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.3753660079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1178053054
Short name T405
Test name
Test status
Simulation time 175206200 ps
CPU time 37.12 seconds
Started Sep 04 04:03:33 PM UTC 24
Finished Sep 04 04:04:11 PM UTC 24
Peak memory 303212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
178053054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ma
x_throughput.1178053054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1397418052
Short name T408
Test name
Test status
Simulation time 352947566 ps
CPU time 6.58 seconds
Started Sep 04 04:04:25 PM UTC 24
Finished Sep 04 04:04:33 PM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397418052 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.1397418052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.633725105
Short name T407
Test name
Test status
Simulation time 927841721 ps
CPU time 7.37 seconds
Started Sep 04 04:04:16 PM UTC 24
Finished Sep 04 04:04:24 PM UTC 24
Peak memory 213784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633725105 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.633725105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3633602568
Short name T580
Test name
Test status
Simulation time 3865837902 ps
CPU time 1030.29 seconds
Started Sep 04 04:03:21 PM UTC 24
Finished Sep 04 04:20:44 PM UTC 24
Peak memory 382892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633602568 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.3633602568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.583197217
Short name T412
Test name
Test status
Simulation time 227290266 ps
CPU time 70.05 seconds
Started Sep 04 04:03:29 PM UTC 24
Finished Sep 04 04:04:40 PM UTC 24
Peak memory 378676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583197217 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.583197217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.523501751
Short name T477
Test name
Test status
Simulation time 18905452293 ps
CPU time 462.78 seconds
Started Sep 04 04:03:30 PM UTC 24
Finished Sep 04 04:11:19 PM UTC 24
Peak memory 213960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523501751 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acce
ss_b2b.523501751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.994761741
Short name T406
Test name
Test status
Simulation time 25545089 ps
CPU time 1.02 seconds
Started Sep 04 04:04:13 PM UTC 24
Finished Sep 04 04:04:15 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994761741 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.994761741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1652363959
Short name T504
Test name
Test status
Simulation time 48669760219 ps
CPU time 622.28 seconds
Started Sep 04 04:04:08 PM UTC 24
Finished Sep 04 04:14:38 PM UTC 24
Peak memory 366424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652363959 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1652363959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.2421573315
Short name T414
Test name
Test status
Simulation time 5774402171 ps
CPU time 114.75 seconds
Started Sep 04 04:03:19 PM UTC 24
Finished Sep 04 04:05:16 PM UTC 24
Peak memory 381116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421573315 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2421573315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.652626482
Short name T935
Test name
Test status
Simulation time 330292499826 ps
CPU time 3677.42 seconds
Started Sep 04 04:04:36 PM UTC 24
Finished Sep 04 05:06:30 PM UTC 24
Peak memory 396916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652626482
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.652626482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.313251560
Short name T105
Test name
Test status
Simulation time 3908876345 ps
CPU time 161.79 seconds
Started Sep 04 04:04:35 PM UTC 24
Finished Sep 04 04:07:20 PM UTC 24
Peak memory 382884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313251560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.313251560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.244930380
Short name T440
Test name
Test status
Simulation time 2254345299 ps
CPU time 231.38 seconds
Started Sep 04 04:03:24 PM UTC 24
Finished Sep 04 04:07:19 PM UTC 24
Peak memory 213964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244930380 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.244930380
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3043434575
Short name T401
Test name
Test status
Simulation time 79789905 ps
CPU time 9.13 seconds
Started Sep 04 04:03:44 PM UTC 24
Finished Sep 04 04:03:54 PM UTC 24
Peak memory 251756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3043434575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t
hroughput_w_partial_write.3043434575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.1146619169
Short name T588
Test name
Test status
Simulation time 3261121953 ps
CPU time 938.46 seconds
Started Sep 04 04:05:46 PM UTC 24
Finished Sep 04 04:21:34 PM UTC 24
Peak memory 384944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146619169 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during
_key_req.1146619169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2790756980
Short name T428
Test name
Test status
Simulation time 17454285 ps
CPU time 0.91 seconds
Started Sep 04 04:06:08 PM UTC 24
Finished Sep 04 04:06:10 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790756980 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2790756980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.4149072676
Short name T416
Test name
Test status
Simulation time 1803805954 ps
CPU time 55.39 seconds
Started Sep 04 04:04:41 PM UTC 24
Finished Sep 04 04:05:38 PM UTC 24
Peak memory 213864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149072676 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.4149072676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1154320107
Short name T522
Test name
Test status
Simulation time 13523465657 ps
CPU time 638.65 seconds
Started Sep 04 04:05:47 PM UTC 24
Finished Sep 04 04:16:33 PM UTC 24
Peak memory 384960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154320107 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.1154320107
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2169905334
Short name T420
Test name
Test status
Simulation time 1747737854 ps
CPU time 8.31 seconds
Started Sep 04 04:05:40 PM UTC 24
Finished Sep 04 04:05:50 PM UTC 24
Peak memory 214196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169905334 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2169905334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.846865949
Short name T429
Test name
Test status
Simulation time 298238206 ps
CPU time 39.33 seconds
Started Sep 04 04:05:39 PM UTC 24
Finished Sep 04 04:06:20 PM UTC 24
Peak memory 323372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8
46865949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_max
_throughput.846865949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3125007449
Short name T425
Test name
Test status
Simulation time 95288362 ps
CPU time 4.37 seconds
Started Sep 04 04:06:00 PM UTC 24
Finished Sep 04 04:06:06 PM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125007449 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3125007449
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3453237858
Short name T426
Test name
Test status
Simulation time 544824317 ps
CPU time 10.98 seconds
Started Sep 04 04:05:55 PM UTC 24
Finished Sep 04 04:06:08 PM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453237858 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.3453237858
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2784615729
Short name T555
Test name
Test status
Simulation time 2768372231 ps
CPU time 853.12 seconds
Started Sep 04 04:04:39 PM UTC 24
Finished Sep 04 04:19:03 PM UTC 24
Peak memory 378620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784615729 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2784615729
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1690568525
Short name T415
Test name
Test status
Simulation time 602210424 ps
CPU time 15.84 seconds
Started Sep 04 04:05:18 PM UTC 24
Finished Sep 04 04:05:34 PM UTC 24
Peak memory 214060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690568525 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.1690568525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.862995915
Short name T496
Test name
Test status
Simulation time 5965391545 ps
CPU time 446.88 seconds
Started Sep 04 04:05:36 PM UTC 24
Finished Sep 04 04:13:08 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862995915 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acce
ss_b2b.862995915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.1336710092
Short name T422
Test name
Test status
Simulation time 29593547 ps
CPU time 1.13 seconds
Started Sep 04 04:05:52 PM UTC 24
Finished Sep 04 04:05:54 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336710092 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1336710092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3209933166
Short name T540
Test name
Test status
Simulation time 38930628107 ps
CPU time 702.19 seconds
Started Sep 04 04:05:51 PM UTC 24
Finished Sep 04 04:17:41 PM UTC 24
Peak memory 383156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209933166 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3209933166
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.2798788157
Short name T413
Test name
Test status
Simulation time 820865879 ps
CPU time 15.61 seconds
Started Sep 04 04:04:37 PM UTC 24
Finished Sep 04 04:04:54 PM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798788157 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2798788157
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.4136376756
Short name T814
Test name
Test status
Simulation time 64624075857 ps
CPU time 2068.24 seconds
Started Sep 04 04:06:06 PM UTC 24
Finished Sep 04 04:40:56 PM UTC 24
Peak memory 385008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413637675
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.4136376756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3883757199
Short name T436
Test name
Test status
Simulation time 2375597726 ps
CPU time 67.82 seconds
Started Sep 04 04:06:01 PM UTC 24
Finished Sep 04 04:07:11 PM UTC 24
Peak memory 315372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883757199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3883757199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.496312760
Short name T457
Test name
Test status
Simulation time 3991282831 ps
CPU time 215.72 seconds
Started Sep 04 04:04:55 PM UTC 24
Finished Sep 04 04:08:34 PM UTC 24
Peak memory 214108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496312760 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.496312760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3438499300
Short name T421
Test name
Test status
Simulation time 468993022 ps
CPU time 10.02 seconds
Started Sep 04 04:05:40 PM UTC 24
Finished Sep 04 04:05:51 PM UTC 24
Peak memory 257836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3438499300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_t
hroughput_w_partial_write.3438499300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1627479134
Short name T665
Test name
Test status
Simulation time 24771228205 ps
CPU time 1234.04 seconds
Started Sep 04 04:07:12 PM UTC 24
Finished Sep 04 04:27:59 PM UTC 24
Peak memory 382884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627479134 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during
_key_req.1627479134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.519975273
Short name T445
Test name
Test status
Simulation time 40262483 ps
CPU time 1.01 seconds
Started Sep 04 04:07:27 PM UTC 24
Finished Sep 04 04:07:30 PM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519975273 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.519975273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3558298666
Short name T437
Test name
Test status
Simulation time 3133876371 ps
CPU time 52.8 seconds
Started Sep 04 04:06:21 PM UTC 24
Finished Sep 04 04:07:15 PM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558298666 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3558298666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3076773589
Short name T538
Test name
Test status
Simulation time 30415384145 ps
CPU time 606.82 seconds
Started Sep 04 04:07:16 PM UTC 24
Finished Sep 04 04:17:29 PM UTC 24
Peak memory 384952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076773589 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.3076773589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1827558752
Short name T438
Test name
Test status
Simulation time 2694687392 ps
CPU time 15.01 seconds
Started Sep 04 04:07:00 PM UTC 24
Finished Sep 04 04:07:17 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827558752 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.1827558752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.65172686
Short name T449
Test name
Test status
Simulation time 140248065 ps
CPU time 56.69 seconds
Started Sep 04 04:06:49 PM UTC 24
Finished Sep 04 04:07:48 PM UTC 24
Peak memory 362416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
5172686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_max_
throughput.65172686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2384748348
Short name T444
Test name
Test status
Simulation time 1175692779 ps
CPU time 6.66 seconds
Started Sep 04 04:07:21 PM UTC 24
Finished Sep 04 04:07:29 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384748348 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.2384748348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.152332942
Short name T446
Test name
Test status
Simulation time 2854786238 ps
CPU time 14.42 seconds
Started Sep 04 04:07:20 PM UTC 24
Finished Sep 04 04:07:36 PM UTC 24
Peak memory 224128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152332942 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.152332942
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.990713795
Short name T508
Test name
Test status
Simulation time 3419159651 ps
CPU time 521.04 seconds
Started Sep 04 04:06:12 PM UTC 24
Finished Sep 04 04:14:59 PM UTC 24
Peak memory 387168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990713795 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.990713795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.872819425
Short name T433
Test name
Test status
Simulation time 374158808 ps
CPU time 14.48 seconds
Started Sep 04 04:06:33 PM UTC 24
Finished Sep 04 04:06:49 PM UTC 24
Peak memory 266028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872819425 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.872819425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2275999609
Short name T516
Test name
Test status
Simulation time 68001896113 ps
CPU time 555.22 seconds
Started Sep 04 04:06:38 PM UTC 24
Finished Sep 04 04:16:01 PM UTC 24
Peak memory 213960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275999609 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc
ess_b2b.2275999609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.641042324
Short name T441
Test name
Test status
Simulation time 34843266 ps
CPU time 1.24 seconds
Started Sep 04 04:07:19 PM UTC 24
Finished Sep 04 04:07:21 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641042324 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.641042324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.185609733
Short name T454
Test name
Test status
Simulation time 4017379242 ps
CPU time 58.3 seconds
Started Sep 04 04:07:18 PM UTC 24
Finished Sep 04 04:08:18 PM UTC 24
Peak memory 214016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185609733 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.185609733
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3536054160
Short name T430
Test name
Test status
Simulation time 2520497073 ps
CPU time 17.2 seconds
Started Sep 04 04:06:10 PM UTC 24
Finished Sep 04 04:06:28 PM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536054160 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3536054160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2514961457
Short name T637
Test name
Test status
Simulation time 5083469515 ps
CPU time 1052.93 seconds
Started Sep 04 04:07:25 PM UTC 24
Finished Sep 04 04:25:10 PM UTC 24
Peak memory 387000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251496145
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.2514961457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2095943561
Short name T491
Test name
Test status
Simulation time 8407923764 ps
CPU time 323.4 seconds
Started Sep 04 04:07:22 PM UTC 24
Finished Sep 04 04:12:50 PM UTC 24
Peak memory 387312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095943561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2095943561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.4267087644
Short name T469
Test name
Test status
Simulation time 12850525103 ps
CPU time 225.2 seconds
Started Sep 04 04:06:29 PM UTC 24
Finished Sep 04 04:10:18 PM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267087644 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.4267087644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1371697961
Short name T448
Test name
Test status
Simulation time 124728827 ps
CPU time 47.88 seconds
Started Sep 04 04:06:54 PM UTC 24
Finished Sep 04 04:07:44 PM UTC 24
Peak memory 323692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1371697961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t
hroughput_w_partial_write.1371697961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.3274546770
Short name T535
Test name
Test status
Simulation time 13115927948 ps
CPU time 525.64 seconds
Started Sep 04 04:08:18 PM UTC 24
Finished Sep 04 04:17:10 PM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274546770 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during
_key_req.3274546770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.4136231270
Short name T463
Test name
Test status
Simulation time 17040838 ps
CPU time 0.94 seconds
Started Sep 04 04:08:58 PM UTC 24
Finished Sep 04 04:09:00 PM UTC 24
Peak memory 212748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136231270 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.4136231270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2958377361
Short name T464
Test name
Test status
Simulation time 1023723130 ps
CPU time 83.86 seconds
Started Sep 04 04:07:37 PM UTC 24
Finished Sep 04 04:09:02 PM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958377361 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.2958377361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.1612250049
Short name T553
Test name
Test status
Simulation time 10024177447 ps
CPU time 621.12 seconds
Started Sep 04 04:08:22 PM UTC 24
Finished Sep 04 04:18:51 PM UTC 24
Peak memory 384904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612250049 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.1612250049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.126744155
Short name T456
Test name
Test status
Simulation time 819808704 ps
CPU time 4.03 seconds
Started Sep 04 04:08:18 PM UTC 24
Finished Sep 04 04:08:23 PM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126744155 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.126744155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4045728400
Short name T455
Test name
Test status
Simulation time 184066861 ps
CPU time 12.46 seconds
Started Sep 04 04:08:08 PM UTC 24
Finished Sep 04 04:08:22 PM UTC 24
Peak memory 274288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
045728400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma
x_throughput.4045728400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1363401759
Short name T460
Test name
Test status
Simulation time 1047815838 ps
CPU time 4.52 seconds
Started Sep 04 04:08:45 PM UTC 24
Finished Sep 04 04:08:50 PM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363401759 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.1363401759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3995468723
Short name T461
Test name
Test status
Simulation time 2720575816 ps
CPU time 11.8 seconds
Started Sep 04 04:08:38 PM UTC 24
Finished Sep 04 04:08:51 PM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995468723 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.3995468723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.4241272414
Short name T573
Test name
Test status
Simulation time 6950361407 ps
CPU time 768.73 seconds
Started Sep 04 04:07:31 PM UTC 24
Finished Sep 04 04:20:28 PM UTC 24
Peak memory 372580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241272414 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.4241272414
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2376350643
Short name T450
Test name
Test status
Simulation time 4358109694 ps
CPU time 20.65 seconds
Started Sep 04 04:07:45 PM UTC 24
Finished Sep 04 04:08:07 PM UTC 24
Peak memory 213972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376350643 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.2376350643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.386332978
Short name T485
Test name
Test status
Simulation time 3110081105 ps
CPU time 268.38 seconds
Started Sep 04 04:07:49 PM UTC 24
Finished Sep 04 04:12:21 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386332978 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acce
ss_b2b.386332978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.960242112
Short name T458
Test name
Test status
Simulation time 74002109 ps
CPU time 1.25 seconds
Started Sep 04 04:08:35 PM UTC 24
Finished Sep 04 04:08:37 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960242112 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.960242112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1942718654
Short name T486
Test name
Test status
Simulation time 12415617997 ps
CPU time 246.86 seconds
Started Sep 04 04:08:25 PM UTC 24
Finished Sep 04 04:12:35 PM UTC 24
Peak memory 378736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942718654 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1942718654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2883869290
Short name T447
Test name
Test status
Simulation time 142470715 ps
CPU time 12.19 seconds
Started Sep 04 04:07:29 PM UTC 24
Finished Sep 04 04:07:43 PM UTC 24
Peak memory 213764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883869290 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2883869290
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1537797583
Short name T786
Test name
Test status
Simulation time 12575143872 ps
CPU time 1795.37 seconds
Started Sep 04 04:08:52 PM UTC 24
Finished Sep 04 04:39:06 PM UTC 24
Peak memory 395448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153779758
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.1537797583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.797313691
Short name T466
Test name
Test status
Simulation time 1478634277 ps
CPU time 44.23 seconds
Started Sep 04 04:08:51 PM UTC 24
Finished Sep 04 04:09:37 PM UTC 24
Peak memory 325424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797313691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.797313691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.1472107259
Short name T480
Test name
Test status
Simulation time 1880431307 ps
CPU time 231.23 seconds
Started Sep 04 04:07:44 PM UTC 24
Finished Sep 04 04:11:39 PM UTC 24
Peak memory 214072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472107259 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.1472107259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1037969882
Short name T467
Test name
Test status
Simulation time 299201758 ps
CPU time 80.83 seconds
Started Sep 04 04:08:16 PM UTC 24
Finished Sep 04 04:09:39 PM UTC 24
Peak memory 374892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1037969882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t
hroughput_w_partial_write.1037969882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.5516260
Short name T586
Test name
Test status
Simulation time 43643571445 ps
CPU time 619.68 seconds
Started Sep 04 04:10:53 PM UTC 24
Finished Sep 04 04:21:20 PM UTC 24
Peak memory 382840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5516260 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_ke
y_req.5516260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2158729126
Short name T481
Test name
Test status
Simulation time 13062282 ps
CPU time 0.88 seconds
Started Sep 04 04:11:40 PM UTC 24
Finished Sep 04 04:11:41 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158729126 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2158729126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.2243194663
Short name T472
Test name
Test status
Simulation time 17353198618 ps
CPU time 103.49 seconds
Started Sep 04 04:09:06 PM UTC 24
Finished Sep 04 04:10:52 PM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243194663 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.2243194663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3426399881
Short name T657
Test name
Test status
Simulation time 114867734138 ps
CPU time 970.28 seconds
Started Sep 04 04:10:56 PM UTC 24
Finished Sep 04 04:27:17 PM UTC 24
Peak memory 382840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426399881 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.3426399881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2077725841
Short name T473
Test name
Test status
Simulation time 1077973693 ps
CPU time 8.26 seconds
Started Sep 04 04:10:45 PM UTC 24
Finished Sep 04 04:10:55 PM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077725841 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.2077725841
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2579700590
Short name T484
Test name
Test status
Simulation time 136518762 ps
CPU time 108.1 seconds
Started Sep 04 04:10:18 PM UTC 24
Finished Sep 04 04:12:08 PM UTC 24
Peak memory 380720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
579700590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ma
x_throughput.2579700590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1897484047
Short name T478
Test name
Test status
Simulation time 159943973 ps
CPU time 7.42 seconds
Started Sep 04 04:11:19 PM UTC 24
Finished Sep 04 04:11:28 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897484047 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.1897484047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1906092326
Short name T479
Test name
Test status
Simulation time 666254317 ps
CPU time 13.91 seconds
Started Sep 04 04:11:16 PM UTC 24
Finished Sep 04 04:11:31 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906092326 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.1906092326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3755895922
Short name T568
Test name
Test status
Simulation time 17123007083 ps
CPU time 637.72 seconds
Started Sep 04 04:09:03 PM UTC 24
Finished Sep 04 04:19:48 PM UTC 24
Peak memory 372908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755895922 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3755895922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.594421963
Short name T468
Test name
Test status
Simulation time 1009140167 ps
CPU time 29.22 seconds
Started Sep 04 04:09:40 PM UTC 24
Finished Sep 04 04:10:10 PM UTC 24
Peak memory 214048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594421963 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.594421963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2272404927
Short name T539
Test name
Test status
Simulation time 177888753939 ps
CPU time 442.7 seconds
Started Sep 04 04:10:11 PM UTC 24
Finished Sep 04 04:17:40 PM UTC 24
Peak memory 214252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272404927 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc
ess_b2b.2272404927
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1190869199
Short name T476
Test name
Test status
Simulation time 48518498 ps
CPU time 1.13 seconds
Started Sep 04 04:11:13 PM UTC 24
Finished Sep 04 04:11:15 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190869199 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1190869199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3937165712
Short name T533
Test name
Test status
Simulation time 11500894088 ps
CPU time 361.37 seconds
Started Sep 04 04:11:00 PM UTC 24
Finished Sep 04 04:17:06 PM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937165712 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3937165712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.2628970766
Short name T465
Test name
Test status
Simulation time 60567137 ps
CPU time 3.5 seconds
Started Sep 04 04:09:01 PM UTC 24
Finished Sep 04 04:09:06 PM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628970766 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2628970766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1809600076
Short name T748
Test name
Test status
Simulation time 56780433887 ps
CPU time 1430.09 seconds
Started Sep 04 04:11:32 PM UTC 24
Finished Sep 04 04:35:38 PM UTC 24
Peak memory 384804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180960007
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.1809600076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.26083499
Short name T514
Test name
Test status
Simulation time 6569210706 ps
CPU time 351.28 seconds
Started Sep 04 04:09:38 PM UTC 24
Finished Sep 04 04:15:34 PM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26083499 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.26083499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1673197004
Short name T474
Test name
Test status
Simulation time 104364991 ps
CPU time 27.21 seconds
Started Sep 04 04:10:30 PM UTC 24
Finished Sep 04 04:10:59 PM UTC 24
Peak memory 301164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1673197004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t
hroughput_w_partial_write.1673197004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.342934128
Short name T554
Test name
Test status
Simulation time 2754930611 ps
CPU time 370.93 seconds
Started Sep 04 04:12:47 PM UTC 24
Finished Sep 04 04:19:03 PM UTC 24
Peak memory 364780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342934128 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_
key_req.342934128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1920349089
Short name T499
Test name
Test status
Simulation time 16121001 ps
CPU time 0.99 seconds
Started Sep 04 04:13:14 PM UTC 24
Finished Sep 04 04:13:16 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920349089 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1920349089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3901817702
Short name T498
Test name
Test status
Simulation time 4729334923 ps
CPU time 64.1 seconds
Started Sep 04 04:12:07 PM UTC 24
Finished Sep 04 04:13:13 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901817702 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.3901817702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.2131644951
Short name T602
Test name
Test status
Simulation time 16198496333 ps
CPU time 578.74 seconds
Started Sep 04 04:12:51 PM UTC 24
Finished Sep 04 04:22:37 PM UTC 24
Peak memory 356212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131644951 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.2131644951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3804043992
Short name T492
Test name
Test status
Simulation time 398967707 ps
CPU time 8.2 seconds
Started Sep 04 04:12:46 PM UTC 24
Finished Sep 04 04:12:55 PM UTC 24
Peak memory 214076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804043992 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.3804043992
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1897740141
Short name T489
Test name
Test status
Simulation time 49864518 ps
CPU time 5.45 seconds
Started Sep 04 04:12:38 PM UTC 24
Finished Sep 04 04:12:45 PM UTC 24
Peak memory 235376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
897740141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ma
x_throughput.1897740141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4294066549
Short name T497
Test name
Test status
Simulation time 203095473 ps
CPU time 5.52 seconds
Started Sep 04 04:13:04 PM UTC 24
Finished Sep 04 04:13:11 PM UTC 24
Peak memory 223992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294066549 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.4294066549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2402404667
Short name T500
Test name
Test status
Simulation time 2731820125 ps
CPU time 16.15 seconds
Started Sep 04 04:12:59 PM UTC 24
Finished Sep 04 04:13:17 PM UTC 24
Peak memory 224072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402404667 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.2402404667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2391594719
Short name T623
Test name
Test status
Simulation time 3650435337 ps
CPU time 741.58 seconds
Started Sep 04 04:11:51 PM UTC 24
Finished Sep 04 04:24:21 PM UTC 24
Peak memory 379120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391594719 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2391594719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2623126451
Short name T488
Test name
Test status
Simulation time 999007856 ps
CPU time 16.89 seconds
Started Sep 04 04:12:22 PM UTC 24
Finished Sep 04 04:12:40 PM UTC 24
Peak memory 268408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623126451 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.2623126451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.67626967
Short name T563
Test name
Test status
Simulation time 29521362617 ps
CPU time 414.77 seconds
Started Sep 04 04:12:35 PM UTC 24
Finished Sep 04 04:19:36 PM UTC 24
Peak memory 214016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67626967 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acces
s_b2b.67626967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.548916632
Short name T494
Test name
Test status
Simulation time 54382431 ps
CPU time 1.21 seconds
Started Sep 04 04:12:56 PM UTC 24
Finished Sep 04 04:12:58 PM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548916632 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.548916632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.147400165
Short name T544
Test name
Test status
Simulation time 6386976106 ps
CPU time 313.07 seconds
Started Sep 04 04:12:56 PM UTC 24
Finished Sep 04 04:18:13 PM UTC 24
Peak memory 375028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147400165 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.147400165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.3661411867
Short name T483
Test name
Test status
Simulation time 3506049001 ps
CPU time 22.43 seconds
Started Sep 04 04:11:43 PM UTC 24
Finished Sep 04 04:12:06 PM UTC 24
Peak memory 214260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661411867 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3661411867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1154497568
Short name T517
Test name
Test status
Simulation time 9065544338 ps
CPU time 166.81 seconds
Started Sep 04 04:13:12 PM UTC 24
Finished Sep 04 04:16:01 PM UTC 24
Peak memory 239724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115449756
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.1154497568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2138543667
Short name T518
Test name
Test status
Simulation time 4562401119 ps
CPU time 232.15 seconds
Started Sep 04 04:12:09 PM UTC 24
Finished Sep 04 04:16:05 PM UTC 24
Peak memory 214116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138543667 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2138543667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.594354621
Short name T495
Test name
Test status
Simulation time 116520685 ps
CPU time 20.84 seconds
Started Sep 04 04:12:42 PM UTC 24
Finished Sep 04 04:13:04 PM UTC 24
Peak memory 296732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
594354621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_th
roughput_w_partial_write.594354621
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2329600214
Short name T733
Test name
Test status
Simulation time 4187652954 ps
CPU time 1167.98 seconds
Started Sep 04 04:14:52 PM UTC 24
Finished Sep 04 04:34:33 PM UTC 24
Peak memory 374908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329600214 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during
_key_req.2329600214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.942209452
Short name T513
Test name
Test status
Simulation time 24292118 ps
CPU time 0.87 seconds
Started Sep 04 04:15:22 PM UTC 24
Finished Sep 04 04:15:24 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942209452 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.942209452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.3582720171
Short name T511
Test name
Test status
Simulation time 5276800742 ps
CPU time 100.45 seconds
Started Sep 04 04:13:30 PM UTC 24
Finished Sep 04 04:15:13 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582720171 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.3582720171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.3943633307
Short name T631
Test name
Test status
Simulation time 10154498806 ps
CPU time 595.46 seconds
Started Sep 04 04:14:54 PM UTC 24
Finished Sep 04 04:24:57 PM UTC 24
Peak memory 374708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943633307 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.3943633307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2901536920
Short name T507
Test name
Test status
Simulation time 258035142 ps
CPU time 2.89 seconds
Started Sep 04 04:14:49 PM UTC 24
Finished Sep 04 04:14:53 PM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901536920 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.2901536920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.4050736673
Short name T521
Test name
Test status
Simulation time 460878597 ps
CPU time 108.1 seconds
Started Sep 04 04:14:39 PM UTC 24
Finished Sep 04 04:16:29 PM UTC 24
Peak memory 380784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
050736673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ma
x_throughput.4050736673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2704414685
Short name T512
Test name
Test status
Simulation time 174460739 ps
CPU time 7.33 seconds
Started Sep 04 04:15:12 PM UTC 24
Finished Sep 04 04:15:20 PM UTC 24
Peak memory 224016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704414685 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.2704414685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.374563289
Short name T510
Test name
Test status
Simulation time 380858566 ps
CPU time 6.71 seconds
Started Sep 04 04:15:03 PM UTC 24
Finished Sep 04 04:15:10 PM UTC 24
Peak memory 224072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374563289 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.374563289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2273545070
Short name T564
Test name
Test status
Simulation time 2467682971 ps
CPU time 374.9 seconds
Started Sep 04 04:13:18 PM UTC 24
Finished Sep 04 04:19:37 PM UTC 24
Peak memory 364464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273545070 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.2273545070
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3597770808
Short name T453
Test name
Test status
Simulation time 431452253 ps
CPU time 52.32 seconds
Started Sep 04 04:13:59 PM UTC 24
Finished Sep 04 04:14:53 PM UTC 24
Peak memory 315200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597770808 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.3597770808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1554851538
Short name T577
Test name
Test status
Simulation time 49595023365 ps
CPU time 388.96 seconds
Started Sep 04 04:14:02 PM UTC 24
Finished Sep 04 04:20:36 PM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554851538 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acc
ess_b2b.1554851538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3930025429
Short name T509
Test name
Test status
Simulation time 29680165 ps
CPU time 1.03 seconds
Started Sep 04 04:15:00 PM UTC 24
Finished Sep 04 04:15:02 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930025429 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3930025429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.939853276
Short name T673
Test name
Test status
Simulation time 36207554594 ps
CPU time 835.2 seconds
Started Sep 04 04:14:54 PM UTC 24
Finished Sep 04 04:29:00 PM UTC 24
Peak memory 380780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939853276 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.939853276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.4085321516
Short name T502
Test name
Test status
Simulation time 6235293589 ps
CPU time 16.14 seconds
Started Sep 04 04:13:17 PM UTC 24
Finished Sep 04 04:13:35 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085321516 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.4085321516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2971728568
Short name T779
Test name
Test status
Simulation time 24320194408 ps
CPU time 1387.05 seconds
Started Sep 04 04:15:20 PM UTC 24
Finished Sep 04 04:38:42 PM UTC 24
Peak memory 395188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297172856
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.2971728568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.660852937
Short name T541
Test name
Test status
Simulation time 5049919921 ps
CPU time 156.86 seconds
Started Sep 04 04:15:14 PM UTC 24
Finished Sep 04 04:17:54 PM UTC 24
Peak memory 378788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660852937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.660852937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1389033632
Short name T524
Test name
Test status
Simulation time 1823726532 ps
CPU time 180.67 seconds
Started Sep 04 04:13:35 PM UTC 24
Finished Sep 04 04:16:39 PM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389033632 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.1389033632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3620932970
Short name T505
Test name
Test status
Simulation time 195031012 ps
CPU time 4.41 seconds
Started Sep 04 04:14:43 PM UTC 24
Finished Sep 04 04:14:48 PM UTC 24
Peak memory 231144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3620932970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t
hroughput_w_partial_write.3620932970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2189049596
Short name T608
Test name
Test status
Simulation time 3792169252 ps
CPU time 387.74 seconds
Started Sep 04 04:16:34 PM UTC 24
Finished Sep 04 04:23:07 PM UTC 24
Peak memory 382864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189049596 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during
_key_req.2189049596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3941865335
Short name T532
Test name
Test status
Simulation time 16520613 ps
CPU time 0.89 seconds
Started Sep 04 04:17:01 PM UTC 24
Finished Sep 04 04:17:03 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941865335 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.3941865335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.4185923392
Short name T519
Test name
Test status
Simulation time 614321652 ps
CPU time 40.4 seconds
Started Sep 04 04:15:38 PM UTC 24
Finished Sep 04 04:16:20 PM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185923392 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.4185923392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3390043481
Short name T740
Test name
Test status
Simulation time 2376304460 ps
CPU time 1085.16 seconds
Started Sep 04 04:16:38 PM UTC 24
Finished Sep 04 04:34:55 PM UTC 24
Peak memory 385152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390043481 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3390043481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2211561042
Short name T525
Test name
Test status
Simulation time 963713900 ps
CPU time 12.07 seconds
Started Sep 04 04:16:30 PM UTC 24
Finished Sep 04 04:16:43 PM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211561042 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.2211561042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3491758486
Short name T523
Test name
Test status
Simulation time 1133623163 ps
CPU time 15.18 seconds
Started Sep 04 04:16:21 PM UTC 24
Finished Sep 04 04:16:37 PM UTC 24
Peak memory 276260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
491758486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma
x_throughput.3491758486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.3854734670
Short name T530
Test name
Test status
Simulation time 179516060 ps
CPU time 3.79 seconds
Started Sep 04 04:16:47 PM UTC 24
Finished Sep 04 04:16:52 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854734670 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.3854734670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2320026176
Short name T531
Test name
Test status
Simulation time 783419719 ps
CPU time 13.02 seconds
Started Sep 04 04:16:45 PM UTC 24
Finished Sep 04 04:16:59 PM UTC 24
Peak memory 224012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320026176 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.2320026176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3142087564
Short name T705
Test name
Test status
Simulation time 12219162409 ps
CPU time 952.41 seconds
Started Sep 04 04:15:35 PM UTC 24
Finished Sep 04 04:31:38 PM UTC 24
Peak memory 383148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142087564 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.3142087564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3856270165
Short name T534
Test name
Test status
Simulation time 596480520 ps
CPU time 63.16 seconds
Started Sep 04 04:16:02 PM UTC 24
Finished Sep 04 04:17:07 PM UTC 24
Peak memory 337728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856270165 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.3856270165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2193764294
Short name T574
Test name
Test status
Simulation time 10152158226 ps
CPU time 259.97 seconds
Started Sep 04 04:16:05 PM UTC 24
Finished Sep 04 04:20:29 PM UTC 24
Peak memory 213780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193764294 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc
ess_b2b.2193764294
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1824042830
Short name T527
Test name
Test status
Simulation time 35796753 ps
CPU time 1.27 seconds
Started Sep 04 04:16:44 PM UTC 24
Finished Sep 04 04:16:46 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824042830 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1824042830
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.4117447827
Short name T636
Test name
Test status
Simulation time 19148300164 ps
CPU time 503.19 seconds
Started Sep 04 04:16:40 PM UTC 24
Finished Sep 04 04:25:10 PM UTC 24
Peak memory 383160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117447827 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4117447827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.3619361057
Short name T515
Test name
Test status
Simulation time 212638774 ps
CPU time 11.76 seconds
Started Sep 04 04:15:25 PM UTC 24
Finished Sep 04 04:15:38 PM UTC 24
Peak memory 260196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619361057 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3619361057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.753144257
Short name T911
Test name
Test status
Simulation time 126128287890 ps
CPU time 2231.97 seconds
Started Sep 04 04:16:52 PM UTC 24
Finished Sep 04 04:54:28 PM UTC 24
Peak memory 388916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753144257
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.753144257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2846790124
Short name T107
Test name
Test status
Simulation time 2849777099 ps
CPU time 160.55 seconds
Started Sep 04 04:16:47 PM UTC 24
Finished Sep 04 04:19:31 PM UTC 24
Peak memory 364528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846790124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2846790124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.896209537
Short name T604
Test name
Test status
Simulation time 9523684826 ps
CPU time 394.42 seconds
Started Sep 04 04:16:01 PM UTC 24
Finished Sep 04 04:22:41 PM UTC 24
Peak memory 213832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896209537 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.896209537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3286023636
Short name T526
Test name
Test status
Simulation time 151196303 ps
CPU time 14.2 seconds
Started Sep 04 04:16:29 PM UTC 24
Finished Sep 04 04:16:44 PM UTC 24
Peak memory 272168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3286023636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t
hroughput_w_partial_write.3286023636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.357592817
Short name T36
Test name
Test status
Simulation time 8873948436 ps
CPU time 461.65 seconds
Started Sep 04 03:35:27 PM UTC 24
Finished Sep 04 03:43:14 PM UTC 24
Peak memory 385192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357592817 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_k
ey_req.357592817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2991550187
Short name T87
Test name
Test status
Simulation time 13976193 ps
CPU time 1.03 seconds
Started Sep 04 03:36:24 PM UTC 24
Finished Sep 04 03:36:26 PM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991550187 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2991550187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3007708355
Short name T155
Test name
Test status
Simulation time 1704559056 ps
CPU time 31.05 seconds
Started Sep 04 03:34:41 PM UTC 24
Finished Sep 04 03:35:14 PM UTC 24
Peak memory 213800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007708355 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3007708355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1202950993
Short name T130
Test name
Test status
Simulation time 8911960040 ps
CPU time 321.83 seconds
Started Sep 04 03:35:29 PM UTC 24
Finished Sep 04 03:40:55 PM UTC 24
Peak memory 380768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202950993 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.1202950993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.261294333
Short name T21
Test name
Test status
Simulation time 3225027243 ps
CPU time 18.31 seconds
Started Sep 04 03:35:21 PM UTC 24
Finished Sep 04 03:35:40 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261294333 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.261294333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.250595221
Short name T156
Test name
Test status
Simulation time 56575463 ps
CPU time 4.51 seconds
Started Sep 04 03:35:14 PM UTC 24
Finished Sep 04 03:35:20 PM UTC 24
Peak memory 231496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
50595221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_
throughput.250595221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1354143546
Short name T39
Test name
Test status
Simulation time 167672571 ps
CPU time 8.53 seconds
Started Sep 04 03:36:15 PM UTC 24
Finished Sep 04 03:36:25 PM UTC 24
Peak memory 224128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354143546 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1354143546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1341990914
Short name T43
Test name
Test status
Simulation time 340084501 ps
CPU time 9.27 seconds
Started Sep 04 03:36:13 PM UTC 24
Finished Sep 04 03:36:24 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341990914 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.1341990914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.4055612810
Short name T110
Test name
Test status
Simulation time 3383149509 ps
CPU time 140.42 seconds
Started Sep 04 03:34:41 PM UTC 24
Finished Sep 04 03:37:04 PM UTC 24
Peak memory 383092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055612810 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.4055612810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.4107942244
Short name T154
Test name
Test status
Simulation time 201779279 ps
CPU time 5.62 seconds
Started Sep 04 03:35:04 PM UTC 24
Finished Sep 04 03:35:11 PM UTC 24
Peak memory 213792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107942244 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.4107942244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3424674050
Short name T96
Test name
Test status
Simulation time 11336923957 ps
CPU time 234.85 seconds
Started Sep 04 03:35:11 PM UTC 24
Finished Sep 04 03:39:10 PM UTC 24
Peak memory 213972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424674050 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce
ss_b2b.3424674050
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3194236842
Short name T158
Test name
Test status
Simulation time 34034947 ps
CPU time 1.27 seconds
Started Sep 04 03:36:11 PM UTC 24
Finished Sep 04 03:36:13 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194236842 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3194236842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.951456694
Short name T49
Test name
Test status
Simulation time 5779064927 ps
CPU time 557.73 seconds
Started Sep 04 03:35:41 PM UTC 24
Finished Sep 04 03:45:06 PM UTC 24
Peak memory 382768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951456694 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.951456694
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.226543133
Short name T28
Test name
Test status
Simulation time 1950771006 ps
CPU time 4.21 seconds
Started Sep 04 03:36:23 PM UTC 24
Finished Sep 04 03:36:28 PM UTC 24
Peak memory 250148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226543133 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.226543133
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.2426494296
Short name T144
Test name
Test status
Simulation time 345719315 ps
CPU time 7.39 seconds
Started Sep 04 03:34:38 PM UTC 24
Finished Sep 04 03:34:46 PM UTC 24
Peak memory 237636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426494296 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2426494296
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2685298775
Short name T40
Test name
Test status
Simulation time 2531715056 ps
CPU time 11.87 seconds
Started Sep 04 03:36:15 PM UTC 24
Finished Sep 04 03:36:28 PM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685298775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2685298775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.2226795000
Short name T98
Test name
Test status
Simulation time 5656355704 ps
CPU time 312.95 seconds
Started Sep 04 03:34:47 PM UTC 24
Finished Sep 04 03:40:05 PM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226795000 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.2226795000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.558611513
Short name T88
Test name
Test status
Simulation time 132309239 ps
CPU time 81.18 seconds
Started Sep 04 03:35:15 PM UTC 24
Finished Sep 04 03:36:38 PM UTC 24
Peak memory 352104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
558611513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_thr
oughput_w_partial_write.558611513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3779387742
Short name T683
Test name
Test status
Simulation time 16136270124 ps
CPU time 702.74 seconds
Started Sep 04 04:17:55 PM UTC 24
Finished Sep 04 04:29:46 PM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779387742 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during
_key_req.3779387742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3347819726
Short name T550
Test name
Test status
Simulation time 17108878 ps
CPU time 0.91 seconds
Started Sep 04 04:18:39 PM UTC 24
Finished Sep 04 04:18:41 PM UTC 24
Peak memory 212576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347819726 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3347819726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.3878088294
Short name T543
Test name
Test status
Simulation time 9034270268 ps
CPU time 54.46 seconds
Started Sep 04 04:17:08 PM UTC 24
Finished Sep 04 04:18:04 PM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878088294 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.3878088294
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2338262535
Short name T593
Test name
Test status
Simulation time 7467456135 ps
CPU time 253.29 seconds
Started Sep 04 04:17:56 PM UTC 24
Finished Sep 04 04:22:13 PM UTC 24
Peak memory 374720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338262535 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.2338262535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.4185710701
Short name T542
Test name
Test status
Simulation time 907101645 ps
CPU time 12.19 seconds
Started Sep 04 04:17:42 PM UTC 24
Finished Sep 04 04:17:55 PM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185710701 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.4185710701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1957849312
Short name T551
Test name
Test status
Simulation time 134837167 ps
CPU time 75.26 seconds
Started Sep 04 04:17:30 PM UTC 24
Finished Sep 04 04:18:47 PM UTC 24
Peak memory 380784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
957849312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma
x_throughput.1957849312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.740192099
Short name T548
Test name
Test status
Simulation time 104811825 ps
CPU time 5.7 seconds
Started Sep 04 04:18:17 PM UTC 24
Finished Sep 04 04:18:24 PM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740192099 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.740192099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1022611683
Short name T547
Test name
Test status
Simulation time 297888550 ps
CPU time 5.81 seconds
Started Sep 04 04:18:15 PM UTC 24
Finished Sep 04 04:18:22 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022611683 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.1022611683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1031887117
Short name T660
Test name
Test status
Simulation time 27720949503 ps
CPU time 618.62 seconds
Started Sep 04 04:17:07 PM UTC 24
Finished Sep 04 04:27:32 PM UTC 24
Peak memory 378728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031887117 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.1031887117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.360202019
Short name T537
Test name
Test status
Simulation time 108753142 ps
CPU time 4.72 seconds
Started Sep 04 04:17:11 PM UTC 24
Finished Sep 04 04:17:17 PM UTC 24
Peak memory 222396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360202019 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.360202019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1137916475
Short name T600
Test name
Test status
Simulation time 6637834856 ps
CPU time 311.53 seconds
Started Sep 04 04:17:18 PM UTC 24
Finished Sep 04 04:22:34 PM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137916475 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acc
ess_b2b.1137916475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3630037266
Short name T546
Test name
Test status
Simulation time 33033401 ps
CPU time 1.05 seconds
Started Sep 04 04:18:14 PM UTC 24
Finished Sep 04 04:18:16 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630037266 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3630037266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.285156377
Short name T745
Test name
Test status
Simulation time 31154768130 ps
CPU time 1009.2 seconds
Started Sep 04 04:18:05 PM UTC 24
Finished Sep 04 04:35:05 PM UTC 24
Peak memory 384948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285156377 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.285156377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3434392577
Short name T536
Test name
Test status
Simulation time 125473862 ps
CPU time 5.21 seconds
Started Sep 04 04:17:04 PM UTC 24
Finished Sep 04 04:17:10 PM UTC 24
Peak memory 225140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434392577 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3434392577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1912067564
Short name T715
Test name
Test status
Simulation time 34773913258 ps
CPU time 824.26 seconds
Started Sep 04 04:18:25 PM UTC 24
Finished Sep 04 04:32:18 PM UTC 24
Peak memory 386996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191206756
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.1912067564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1055656768
Short name T592
Test name
Test status
Simulation time 9851039765 ps
CPU time 286.34 seconds
Started Sep 04 04:17:11 PM UTC 24
Finished Sep 04 04:22:02 PM UTC 24
Peak memory 214136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055656768 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.1055656768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2970479347
Short name T545
Test name
Test status
Simulation time 201364838 ps
CPU time 32.93 seconds
Started Sep 04 04:17:40 PM UTC 24
Finished Sep 04 04:18:15 PM UTC 24
Peak memory 302880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2970479347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_t
hroughput_w_partial_write.2970479347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1272427618
Short name T711
Test name
Test status
Simulation time 39784898477 ps
CPU time 748.51 seconds
Started Sep 04 04:19:29 PM UTC 24
Finished Sep 04 04:32:05 PM UTC 24
Peak memory 384932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272427618 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during
_key_req.1272427618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.907949192
Short name T567
Test name
Test status
Simulation time 15230159 ps
CPU time 0.93 seconds
Started Sep 04 04:19:44 PM UTC 24
Finished Sep 04 04:19:45 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907949192 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.907949192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1894412925
Short name T556
Test name
Test status
Simulation time 6846898672 ps
CPU time 21.92 seconds
Started Sep 04 04:18:50 PM UTC 24
Finished Sep 04 04:19:13 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894412925 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.1894412925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.2961559081
Short name T692
Test name
Test status
Simulation time 1777457411 ps
CPU time 658.41 seconds
Started Sep 04 04:19:30 PM UTC 24
Finished Sep 04 04:30:36 PM UTC 24
Peak memory 380800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961559081 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.2961559081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3647435130
Short name T565
Test name
Test status
Simulation time 7863668828 ps
CPU time 12.27 seconds
Started Sep 04 04:19:29 PM UTC 24
Finished Sep 04 04:19:42 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647435130 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.3647435130
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.121171170
Short name T576
Test name
Test status
Simulation time 385883697 ps
CPU time 77.55 seconds
Started Sep 04 04:19:14 PM UTC 24
Finished Sep 04 04:20:34 PM UTC 24
Peak memory 379000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
21171170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_max
_throughput.121171170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3378877388
Short name T566
Test name
Test status
Simulation time 816953662 ps
CPU time 5.09 seconds
Started Sep 04 04:19:36 PM UTC 24
Finished Sep 04 04:19:42 PM UTC 24
Peak memory 224344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378877388 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.3378877388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2244981596
Short name T569
Test name
Test status
Simulation time 571894961 ps
CPU time 14.44 seconds
Started Sep 04 04:19:34 PM UTC 24
Finished Sep 04 04:19:50 PM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244981596 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.2244981596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.4092818951
Short name T628
Test name
Test status
Simulation time 5482927533 ps
CPU time 355 seconds
Started Sep 04 04:18:48 PM UTC 24
Finished Sep 04 04:24:48 PM UTC 24
Peak memory 333744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092818951 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.4092818951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3588113943
Short name T560
Test name
Test status
Simulation time 312654751 ps
CPU time 24.71 seconds
Started Sep 04 04:19:03 PM UTC 24
Finished Sep 04 04:19:29 PM UTC 24
Peak memory 282488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588113943 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.3588113943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3043195845
Short name T634
Test name
Test status
Simulation time 45420302623 ps
CPU time 357.33 seconds
Started Sep 04 04:19:03 PM UTC 24
Finished Sep 04 04:25:06 PM UTC 24
Peak memory 213980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043195845 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc
ess_b2b.3043195845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3674883301
Short name T562
Test name
Test status
Simulation time 35481882 ps
CPU time 1.11 seconds
Started Sep 04 04:19:31 PM UTC 24
Finished Sep 04 04:19:33 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674883301 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3674883301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.1298101744
Short name T766
Test name
Test status
Simulation time 14108981507 ps
CPU time 1063.85 seconds
Started Sep 04 04:19:31 PM UTC 24
Finished Sep 04 04:37:26 PM UTC 24
Peak memory 387000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298101744 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1298101744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.3239122280
Short name T572
Test name
Test status
Simulation time 1194494818 ps
CPU time 91.02 seconds
Started Sep 04 04:18:42 PM UTC 24
Finished Sep 04 04:20:15 PM UTC 24
Peak memory 362364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239122280 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3239122280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.4071628027
Short name T922
Test name
Test status
Simulation time 8666245451 ps
CPU time 2218.01 seconds
Started Sep 04 04:19:44 PM UTC 24
Finished Sep 04 04:57:04 PM UTC 24
Peak memory 386672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407162802
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.4071628027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.993770479
Short name T640
Test name
Test status
Simulation time 4214909539 ps
CPU time 334.7 seconds
Started Sep 04 04:19:38 PM UTC 24
Finished Sep 04 04:25:17 PM UTC 24
Peak memory 375024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993770479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.993770479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.185882981
Short name T615
Test name
Test status
Simulation time 3084428733 ps
CPU time 279.3 seconds
Started Sep 04 04:18:52 PM UTC 24
Finished Sep 04 04:23:35 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185882981 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.185882981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.764878172
Short name T561
Test name
Test status
Simulation time 429363207 ps
CPU time 9.22 seconds
Started Sep 04 04:19:20 PM UTC 24
Finished Sep 04 04:19:30 PM UTC 24
Peak memory 264296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
764878172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_th
roughput_w_partial_write.764878172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3446876333
Short name T601
Test name
Test status
Simulation time 773907148 ps
CPU time 122.92 seconds
Started Sep 04 04:20:31 PM UTC 24
Finished Sep 04 04:22:36 PM UTC 24
Peak memory 333924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446876333 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during
_key_req.3446876333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.817863686
Short name T584
Test name
Test status
Simulation time 40631375 ps
CPU time 0.96 seconds
Started Sep 04 04:20:56 PM UTC 24
Finished Sep 04 04:20:58 PM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817863686 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.817863686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.918237491
Short name T583
Test name
Test status
Simulation time 1673160551 ps
CPU time 64.52 seconds
Started Sep 04 04:19:51 PM UTC 24
Finished Sep 04 04:20:57 PM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918237491 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.918237491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2847572206
Short name T784
Test name
Test status
Simulation time 11330778979 ps
CPU time 1097.19 seconds
Started Sep 04 04:20:35 PM UTC 24
Finished Sep 04 04:39:04 PM UTC 24
Peak memory 384948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847572206 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.2847572206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.367060212
Short name T578
Test name
Test status
Simulation time 586363044 ps
CPU time 6.81 seconds
Started Sep 04 04:20:30 PM UTC 24
Finished Sep 04 04:20:37 PM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367060212 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.367060212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3989444356
Short name T597
Test name
Test status
Simulation time 144938901 ps
CPU time 118.98 seconds
Started Sep 04 04:20:21 PM UTC 24
Finished Sep 04 04:22:23 PM UTC 24
Peak memory 380776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
989444356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma
x_throughput.3989444356
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4009280033
Short name T582
Test name
Test status
Simulation time 194646971 ps
CPU time 7.02 seconds
Started Sep 04 04:20:44 PM UTC 24
Finished Sep 04 04:20:52 PM UTC 24
Peak memory 223984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009280033 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.4009280033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2404132179
Short name T528
Test name
Test status
Simulation time 455483250 ps
CPU time 12.81 seconds
Started Sep 04 04:20:41 PM UTC 24
Finished Sep 04 04:20:55 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404132179 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.2404132179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3205568735
Short name T902
Test name
Test status
Simulation time 3782973027 ps
CPU time 1863.94 seconds
Started Sep 04 04:19:49 PM UTC 24
Finished Sep 04 04:51:13 PM UTC 24
Peak memory 386664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205568735 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.3205568735
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1615849731
Short name T575
Test name
Test status
Simulation time 915220730 ps
CPU time 21.34 seconds
Started Sep 04 04:20:07 PM UTC 24
Finished Sep 04 04:20:30 PM UTC 24
Peak memory 213808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615849731 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1615849731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.389546528
Short name T644
Test name
Test status
Simulation time 34041466177 ps
CPU time 315.15 seconds
Started Sep 04 04:20:16 PM UTC 24
Finished Sep 04 04:25:36 PM UTC 24
Peak memory 213968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389546528 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acce
ss_b2b.389546528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3796853058
Short name T579
Test name
Test status
Simulation time 35689398 ps
CPU time 1.2 seconds
Started Sep 04 04:20:38 PM UTC 24
Finished Sep 04 04:20:40 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796853058 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3796853058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.215495170
Short name T728
Test name
Test status
Simulation time 39700198308 ps
CPU time 763.96 seconds
Started Sep 04 04:20:38 PM UTC 24
Finished Sep 04 04:33:30 PM UTC 24
Peak memory 386996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215495170 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.215495170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.3755321845
Short name T571
Test name
Test status
Simulation time 158850679 ps
CPU time 18.75 seconds
Started Sep 04 04:19:47 PM UTC 24
Finished Sep 04 04:20:07 PM UTC 24
Peak memory 284456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755321845 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3755321845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2963675912
Short name T879
Test name
Test status
Simulation time 5764155415 ps
CPU time 1514.24 seconds
Started Sep 04 04:20:54 PM UTC 24
Finished Sep 04 04:46:25 PM UTC 24
Peak memory 387248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296367591
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.2963675912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2878654026
Short name T587
Test name
Test status
Simulation time 803984972 ps
CPU time 34.28 seconds
Started Sep 04 04:20:46 PM UTC 24
Finished Sep 04 04:21:22 PM UTC 24
Peak memory 240548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878654026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2878654026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3076836778
Short name T656
Test name
Test status
Simulation time 7069126806 ps
CPU time 402.31 seconds
Started Sep 04 04:20:07 PM UTC 24
Finished Sep 04 04:26:55 PM UTC 24
Peak memory 213808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076836778 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.3076836778
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3415168324
Short name T595
Test name
Test status
Simulation time 598114183 ps
CPU time 103.53 seconds
Started Sep 04 04:20:29 PM UTC 24
Finished Sep 04 04:22:14 PM UTC 24
Peak memory 374568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3415168324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t
hroughput_w_partial_write.3415168324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.65531888
Short name T678
Test name
Test status
Simulation time 1901528388 ps
CPU time 444.72 seconds
Started Sep 04 04:22:03 PM UTC 24
Finished Sep 04 04:29:34 PM UTC 24
Peak memory 376912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65531888 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during_k
ey_req.65531888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2215151077
Short name T603
Test name
Test status
Simulation time 36500960 ps
CPU time 0.87 seconds
Started Sep 04 04:22:36 PM UTC 24
Finished Sep 04 04:22:38 PM UTC 24
Peak memory 212808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215151077 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2215151077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.3661145457
Short name T589
Test name
Test status
Simulation time 2046312903 ps
CPU time 37.77 seconds
Started Sep 04 04:21:04 PM UTC 24
Finished Sep 04 04:21:43 PM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661145457 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.3661145457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3823395008
Short name T726
Test name
Test status
Simulation time 2009795632 ps
CPU time 664.13 seconds
Started Sep 04 04:22:13 PM UTC 24
Finished Sep 04 04:33:25 PM UTC 24
Peak memory 376704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823395008 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3823395008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3783414461
Short name T594
Test name
Test status
Simulation time 775688940 ps
CPU time 11.22 seconds
Started Sep 04 04:22:01 PM UTC 24
Finished Sep 04 04:22:13 PM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783414461 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.3783414461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.4059432674
Short name T590
Test name
Test status
Simulation time 56752202 ps
CPU time 1.22 seconds
Started Sep 04 04:21:45 PM UTC 24
Finished Sep 04 04:21:48 PM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
059432674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma
x_throughput.4059432674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2861125006
Short name T598
Test name
Test status
Simulation time 847763715 ps
CPU time 6 seconds
Started Sep 04 04:22:24 PM UTC 24
Finished Sep 04 04:22:31 PM UTC 24
Peak memory 224416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861125006 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.2861125006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1788246580
Short name T599
Test name
Test status
Simulation time 147258709 ps
CPU time 10.2 seconds
Started Sep 04 04:22:20 PM UTC 24
Finished Sep 04 04:22:31 PM UTC 24
Peak memory 213948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788246580 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.1788246580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3861118669
Short name T617
Test name
Test status
Simulation time 3885808517 ps
CPU time 159.94 seconds
Started Sep 04 04:20:59 PM UTC 24
Finished Sep 04 04:23:41 PM UTC 24
Peak memory 376748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861118669 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.3861118669
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1494725446
Short name T591
Test name
Test status
Simulation time 121467724 ps
CPU time 30.15 seconds
Started Sep 04 04:21:29 PM UTC 24
Finished Sep 04 04:22:01 PM UTC 24
Peak memory 292660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494725446 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1494725446
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1209054570
Short name T638
Test name
Test status
Simulation time 7701867328 ps
CPU time 213.63 seconds
Started Sep 04 04:21:35 PM UTC 24
Finished Sep 04 04:25:12 PM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209054570 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc
ess_b2b.1209054570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2011831132
Short name T596
Test name
Test status
Simulation time 150326370 ps
CPU time 1.12 seconds
Started Sep 04 04:22:16 PM UTC 24
Finished Sep 04 04:22:18 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011831132 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2011831132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.45536124
Short name T677
Test name
Test status
Simulation time 1630146477 ps
CPU time 416.54 seconds
Started Sep 04 04:22:15 PM UTC 24
Finished Sep 04 04:29:18 PM UTC 24
Peak memory 366772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45536124 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.45536124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.2520069301
Short name T585
Test name
Test status
Simulation time 191282030 ps
CPU time 4.61 seconds
Started Sep 04 04:20:58 PM UTC 24
Finished Sep 04 04:21:03 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520069301 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2520069301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.226943558
Short name T944
Test name
Test status
Simulation time 347385719955 ps
CPU time 5892.69 seconds
Started Sep 04 04:22:32 PM UTC 24
Finished Sep 04 06:01:47 PM UTC 24
Peak memory 388716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226943558
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.226943558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2567003515
Short name T609
Test name
Test status
Simulation time 3586165631 ps
CPU time 34.24 seconds
Started Sep 04 04:22:32 PM UTC 24
Finished Sep 04 04:23:08 PM UTC 24
Peak memory 231380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567003515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2567003515
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3795368124
Short name T666
Test name
Test status
Simulation time 18777082381 ps
CPU time 395.44 seconds
Started Sep 04 04:21:20 PM UTC 24
Finished Sep 04 04:28:01 PM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795368124 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.3795368124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1982938102
Short name T606
Test name
Test status
Simulation time 132392449 ps
CPU time 63.26 seconds
Started Sep 04 04:21:49 PM UTC 24
Finished Sep 04 04:22:54 PM UTC 24
Peak memory 345968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1982938102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_t
hroughput_w_partial_write.1982938102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3001226106
Short name T730
Test name
Test status
Simulation time 2892006090 ps
CPU time 629 seconds
Started Sep 04 04:23:09 PM UTC 24
Finished Sep 04 04:33:46 PM UTC 24
Peak memory 385144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001226106 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during
_key_req.3001226106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.961722651
Short name T619
Test name
Test status
Simulation time 15330885 ps
CPU time 0.87 seconds
Started Sep 04 04:23:42 PM UTC 24
Finished Sep 04 04:23:44 PM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961722651 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.961722651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.3972053931
Short name T621
Test name
Test status
Simulation time 3688562783 ps
CPU time 76.5 seconds
Started Sep 04 04:22:40 PM UTC 24
Finished Sep 04 04:23:59 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972053931 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.3972053931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.2197756752
Short name T664
Test name
Test status
Simulation time 17332981317 ps
CPU time 281.59 seconds
Started Sep 04 04:23:13 PM UTC 24
Finished Sep 04 04:27:58 PM UTC 24
Peak memory 376756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197756752 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.2197756752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.4094793556
Short name T610
Test name
Test status
Simulation time 147006528 ps
CPU time 3.28 seconds
Started Sep 04 04:23:08 PM UTC 24
Finished Sep 04 04:23:12 PM UTC 24
Peak memory 213872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094793556 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.4094793556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.521080422
Short name T611
Test name
Test status
Simulation time 207947280 ps
CPU time 23.14 seconds
Started Sep 04 04:22:55 PM UTC 24
Finished Sep 04 04:23:20 PM UTC 24
Peak memory 290872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5
21080422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_max
_throughput.521080422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1409832968
Short name T77
Test name
Test status
Simulation time 193652835 ps
CPU time 8.34 seconds
Started Sep 04 04:23:34 PM UTC 24
Finished Sep 04 04:23:43 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409832968 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.1409832968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2156792698
Short name T616
Test name
Test status
Simulation time 1563663502 ps
CPU time 12.07 seconds
Started Sep 04 04:23:25 PM UTC 24
Finished Sep 04 04:23:39 PM UTC 24
Peak memory 224340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156792698 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.2156792698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1384540686
Short name T743
Test name
Test status
Simulation time 14171788550 ps
CPU time 735.23 seconds
Started Sep 04 04:22:38 PM UTC 24
Finished Sep 04 04:35:02 PM UTC 24
Peak memory 386920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384540686 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.1384540686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2098923387
Short name T607
Test name
Test status
Simulation time 432701641 ps
CPU time 11.75 seconds
Started Sep 04 04:22:48 PM UTC 24
Finished Sep 04 04:23:00 PM UTC 24
Peak memory 251712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098923387 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.2098923387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2221911189
Short name T695
Test name
Test status
Simulation time 14875623804 ps
CPU time 471.49 seconds
Started Sep 04 04:22:55 PM UTC 24
Finished Sep 04 04:30:53 PM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221911189 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc
ess_b2b.2221911189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.4078691040
Short name T613
Test name
Test status
Simulation time 27949306 ps
CPU time 1.06 seconds
Started Sep 04 04:23:22 PM UTC 24
Finished Sep 04 04:23:24 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078691040 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.4078691040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2088247507
Short name T708
Test name
Test status
Simulation time 6509489503 ps
CPU time 513.36 seconds
Started Sep 04 04:23:20 PM UTC 24
Finished Sep 04 04:32:00 PM UTC 24
Peak memory 376760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088247507 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2088247507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.1758836287
Short name T605
Test name
Test status
Simulation time 270162941 ps
CPU time 7.05 seconds
Started Sep 04 04:22:38 PM UTC 24
Finished Sep 04 04:22:46 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758836287 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1758836287
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.972605186
Short name T655
Test name
Test status
Simulation time 3284280383 ps
CPU time 178.11 seconds
Started Sep 04 04:23:36 PM UTC 24
Finished Sep 04 04:26:37 PM UTC 24
Peak memory 389364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972605186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.972605186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2577870640
Short name T661
Test name
Test status
Simulation time 10652170006 ps
CPU time 286.61 seconds
Started Sep 04 04:22:43 PM UTC 24
Finished Sep 04 04:27:34 PM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577870640 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.2577870640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.826279934
Short name T624
Test name
Test status
Simulation time 151484445 ps
CPU time 81.37 seconds
Started Sep 04 04:23:01 PM UTC 24
Finished Sep 04 04:24:24 PM UTC 24
Peak memory 374632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
826279934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_th
roughput_w_partial_write.826279934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.925731498
Short name T780
Test name
Test status
Simulation time 16065160835 ps
CPU time 838.04 seconds
Started Sep 04 04:24:43 PM UTC 24
Finished Sep 04 04:38:50 PM UTC 24
Peak memory 383216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925731498 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during_
key_req.925731498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1365626984
Short name T635
Test name
Test status
Simulation time 38420714 ps
CPU time 0.91 seconds
Started Sep 04 04:25:06 PM UTC 24
Finished Sep 04 04:25:08 PM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365626984 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1365626984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.1021845090
Short name T639
Test name
Test status
Simulation time 6806720569 ps
CPU time 89.58 seconds
Started Sep 04 04:23:45 PM UTC 24
Finished Sep 04 04:25:17 PM UTC 24
Peak memory 214164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021845090 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.1021845090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.3270429629
Short name T693
Test name
Test status
Simulation time 1290033382 ps
CPU time 354.56 seconds
Started Sep 04 04:24:44 PM UTC 24
Finished Sep 04 04:30:43 PM UTC 24
Peak memory 384896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270429629 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.3270429629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2295150617
Short name T629
Test name
Test status
Simulation time 625984906 ps
CPU time 7.55 seconds
Started Sep 04 04:24:40 PM UTC 24
Finished Sep 04 04:24:49 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295150617 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.2295150617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1397426241
Short name T626
Test name
Test status
Simulation time 198670384 ps
CPU time 17.94 seconds
Started Sep 04 04:24:22 PM UTC 24
Finished Sep 04 04:24:42 PM UTC 24
Peak memory 290664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
397426241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma
x_throughput.1397426241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.2551635264
Short name T632
Test name
Test status
Simulation time 207844785 ps
CPU time 5.16 seconds
Started Sep 04 04:24:58 PM UTC 24
Finished Sep 04 04:25:04 PM UTC 24
Peak memory 224296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551635264 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.2551635264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3305828951
Short name T633
Test name
Test status
Simulation time 544887822 ps
CPU time 10.64 seconds
Started Sep 04 04:24:53 PM UTC 24
Finished Sep 04 04:25:05 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305828951 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.3305828951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.2078883557
Short name T738
Test name
Test status
Simulation time 42522030320 ps
CPU time 656.13 seconds
Started Sep 04 04:23:45 PM UTC 24
Finished Sep 04 04:34:49 PM UTC 24
Peak memory 386532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078883557 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.2078883557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3518151045
Short name T622
Test name
Test status
Simulation time 523710454 ps
CPU time 12.81 seconds
Started Sep 04 04:24:00 PM UTC 24
Finished Sep 04 04:24:13 PM UTC 24
Peak memory 213752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518151045 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.3518151045
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1051384541
Short name T697
Test name
Test status
Simulation time 103546681284 ps
CPU time 399.16 seconds
Started Sep 04 04:24:15 PM UTC 24
Finished Sep 04 04:31:00 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051384541 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acc
ess_b2b.1051384541
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2993757675
Short name T630
Test name
Test status
Simulation time 30783802 ps
CPU time 1.13 seconds
Started Sep 04 04:24:50 PM UTC 24
Finished Sep 04 04:24:52 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993757675 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2993757675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.573690602
Short name T714
Test name
Test status
Simulation time 1626035956 ps
CPU time 443.02 seconds
Started Sep 04 04:24:49 PM UTC 24
Finished Sep 04 04:32:18 PM UTC 24
Peak memory 378740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573690602 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.573690602
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.318290395
Short name T620
Test name
Test status
Simulation time 489579011 ps
CPU time 2.18 seconds
Started Sep 04 04:23:43 PM UTC 24
Finished Sep 04 04:23:47 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318290395 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.318290395
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.200290628
Short name T929
Test name
Test status
Simulation time 34975784870 ps
CPU time 2141.67 seconds
Started Sep 04 04:25:06 PM UTC 24
Finished Sep 04 05:01:10 PM UTC 24
Peak memory 397044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200290628
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.200290628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1482931533
Short name T108
Test name
Test status
Simulation time 20676943070 ps
CPU time 40.81 seconds
Started Sep 04 04:25:05 PM UTC 24
Finished Sep 04 04:25:47 PM UTC 24
Peak memory 224192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482931533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1482931533
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.597271466
Short name T663
Test name
Test status
Simulation time 2671825567 ps
CPU time 237.09 seconds
Started Sep 04 04:23:47 PM UTC 24
Finished Sep 04 04:27:48 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597271466 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.597271466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3250721265
Short name T641
Test name
Test status
Simulation time 478499562 ps
CPU time 55.21 seconds
Started Sep 04 04:24:25 PM UTC 24
Finished Sep 04 04:25:21 PM UTC 24
Peak memory 350056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3250721265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t
hroughput_w_partial_write.3250721265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2219482274
Short name T759
Test name
Test status
Simulation time 12115017581 ps
CPU time 644.77 seconds
Started Sep 04 04:25:37 PM UTC 24
Finished Sep 04 04:36:29 PM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219482274 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during
_key_req.2219482274
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.641085351
Short name T653
Test name
Test status
Simulation time 12638452 ps
CPU time 1.02 seconds
Started Sep 04 04:26:11 PM UTC 24
Finished Sep 04 04:26:14 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641085351 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.641085351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.71033227
Short name T648
Test name
Test status
Simulation time 483712416 ps
CPU time 36.9 seconds
Started Sep 04 04:25:12 PM UTC 24
Finished Sep 04 04:25:51 PM UTC 24
Peak memory 213784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71033227 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.71033227
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3984909287
Short name T872
Test name
Test status
Simulation time 56900678061 ps
CPU time 1209.2 seconds
Started Sep 04 04:25:40 PM UTC 24
Finished Sep 04 04:46:02 PM UTC 24
Peak memory 384948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984909287 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.3984909287
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.347927838
Short name T646
Test name
Test status
Simulation time 2491083603 ps
CPU time 11.48 seconds
Started Sep 04 04:25:31 PM UTC 24
Finished Sep 04 04:25:44 PM UTC 24
Peak memory 213988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347927838 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.347927838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3681319017
Short name T645
Test name
Test status
Simulation time 75261907 ps
CPU time 15.92 seconds
Started Sep 04 04:25:22 PM UTC 24
Finished Sep 04 04:25:39 PM UTC 24
Peak memory 282412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
681319017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ma
x_throughput.3681319017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.968368427
Short name T651
Test name
Test status
Simulation time 170066781 ps
CPU time 7.37 seconds
Started Sep 04 04:25:53 PM UTC 24
Finished Sep 04 04:26:02 PM UTC 24
Peak memory 224020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968368427 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.968368427
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3920023536
Short name T652
Test name
Test status
Simulation time 2094102828 ps
CPU time 16.14 seconds
Started Sep 04 04:25:53 PM UTC 24
Finished Sep 04 04:26:10 PM UTC 24
Peak memory 224396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920023536 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.3920023536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.2853764436
Short name T785
Test name
Test status
Simulation time 12841581752 ps
CPU time 824.64 seconds
Started Sep 04 04:25:11 PM UTC 24
Finished Sep 04 04:39:05 PM UTC 24
Peak memory 379056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853764436 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.2853764436
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.2293943682
Short name T643
Test name
Test status
Simulation time 1759474679 ps
CPU time 11.67 seconds
Started Sep 04 04:25:18 PM UTC 24
Finished Sep 04 04:25:30 PM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293943682 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.2293943682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.56957590
Short name T775
Test name
Test status
Simulation time 49622973378 ps
CPU time 756.05 seconds
Started Sep 04 04:25:19 PM UTC 24
Finished Sep 04 04:38:04 PM UTC 24
Peak memory 213940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56957590 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acces
s_b2b.56957590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.664721971
Short name T649
Test name
Test status
Simulation time 151778349 ps
CPU time 1.11 seconds
Started Sep 04 04:25:49 PM UTC 24
Finished Sep 04 04:25:51 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664721971 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.664721971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.2531134534
Short name T828
Test name
Test status
Simulation time 2774684950 ps
CPU time 1009.03 seconds
Started Sep 04 04:25:45 PM UTC 24
Finished Sep 04 04:42:46 PM UTC 24
Peak memory 382900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531134534 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2531134534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.3764069248
Short name T642
Test name
Test status
Simulation time 920774052 ps
CPU time 16.17 seconds
Started Sep 04 04:25:09 PM UTC 24
Finished Sep 04 04:25:27 PM UTC 24
Peak memory 262268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764069248 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3764069248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.502557115
Short name T889
Test name
Test status
Simulation time 19448000433 ps
CPU time 1302.46 seconds
Started Sep 04 04:26:02 PM UTC 24
Finished Sep 04 04:47:59 PM UTC 24
Peak memory 387000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502557115
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.502557115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2645394750
Short name T691
Test name
Test status
Simulation time 4444399449 ps
CPU time 276.37 seconds
Started Sep 04 04:25:53 PM UTC 24
Finished Sep 04 04:30:33 PM UTC 24
Peak memory 372720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645394750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2645394750
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3834690391
Short name T675
Test name
Test status
Simulation time 10073545707 ps
CPU time 226.35 seconds
Started Sep 04 04:25:12 PM UTC 24
Finished Sep 04 04:29:02 PM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834690391 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.3834690391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3994698162
Short name T650
Test name
Test status
Simulation time 340557719 ps
CPU time 21.23 seconds
Started Sep 04 04:25:28 PM UTC 24
Finished Sep 04 04:25:51 PM UTC 24
Peak memory 290664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3994698162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t
hroughput_w_partial_write.3994698162
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1570648160
Short name T698
Test name
Test status
Simulation time 2743734006 ps
CPU time 203.22 seconds
Started Sep 04 04:27:35 PM UTC 24
Finished Sep 04 04:31:01 PM UTC 24
Peak memory 382892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570648160 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during
_key_req.1570648160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1410671512
Short name T670
Test name
Test status
Simulation time 61365872 ps
CPU time 0.98 seconds
Started Sep 04 04:28:14 PM UTC 24
Finished Sep 04 04:28:16 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410671512 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1410671512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2127886979
Short name T659
Test name
Test status
Simulation time 2014598483 ps
CPU time 41.45 seconds
Started Sep 04 04:26:38 PM UTC 24
Finished Sep 04 04:27:21 PM UTC 24
Peak memory 214056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127886979 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.2127886979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.1291951102
Short name T834
Test name
Test status
Simulation time 16473323946 ps
CPU time 930.31 seconds
Started Sep 04 04:27:43 PM UTC 24
Finished Sep 04 04:43:24 PM UTC 24
Peak memory 376668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291951102 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.1291951102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3198220055
Short name T662
Test name
Test status
Simulation time 3174611453 ps
CPU time 7.57 seconds
Started Sep 04 04:27:34 PM UTC 24
Finished Sep 04 04:27:43 PM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198220055 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.3198220055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.592347654
Short name T676
Test name
Test status
Simulation time 281935963 ps
CPU time 109.01 seconds
Started Sep 04 04:27:22 PM UTC 24
Finished Sep 04 04:29:14 PM UTC 24
Peak memory 380792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5
92347654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max
_throughput.592347654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1016657384
Short name T668
Test name
Test status
Simulation time 91704987 ps
CPU time 6.4 seconds
Started Sep 04 04:28:02 PM UTC 24
Finished Sep 04 04:28:10 PM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016657384 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1016657384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2925026247
Short name T669
Test name
Test status
Simulation time 229164179 ps
CPU time 11.89 seconds
Started Sep 04 04:28:00 PM UTC 24
Finished Sep 04 04:28:13 PM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925026247 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.2925026247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.1901989653
Short name T731
Test name
Test status
Simulation time 18587157293 ps
CPU time 474.7 seconds
Started Sep 04 04:26:26 PM UTC 24
Finished Sep 04 04:34:26 PM UTC 24
Peak memory 384916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901989653 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.1901989653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.277856843
Short name T658
Test name
Test status
Simulation time 5989671981 ps
CPU time 23.94 seconds
Started Sep 04 04:26:56 PM UTC 24
Finished Sep 04 04:27:21 PM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277856843 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.277856843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1057710816
Short name T735
Test name
Test status
Simulation time 4421407049 ps
CPU time 437.62 seconds
Started Sep 04 04:27:18 PM UTC 24
Finished Sep 04 04:34:42 PM UTC 24
Peak memory 214216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057710816 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc
ess_b2b.1057710816
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.665041034
Short name T667
Test name
Test status
Simulation time 89804906 ps
CPU time 1.03 seconds
Started Sep 04 04:28:00 PM UTC 24
Finished Sep 04 04:28:02 PM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665041034 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.665041034
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.1479275768
Short name T810
Test name
Test status
Simulation time 13060332588 ps
CPU time 762.89 seconds
Started Sep 04 04:27:48 PM UTC 24
Finished Sep 04 04:40:40 PM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479275768 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1479275768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.835249509
Short name T654
Test name
Test status
Simulation time 318156086 ps
CPU time 9.33 seconds
Started Sep 04 04:26:15 PM UTC 24
Finished Sep 04 04:26:25 PM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835249509 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.835249509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1346993545
Short name T905
Test name
Test status
Simulation time 20180878970 ps
CPU time 1417.95 seconds
Started Sep 04 04:28:11 PM UTC 24
Finished Sep 04 04:52:04 PM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134699354
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.1346993545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3564681287
Short name T682
Test name
Test status
Simulation time 951006268 ps
CPU time 99.25 seconds
Started Sep 04 04:28:02 PM UTC 24
Finished Sep 04 04:29:44 PM UTC 24
Peak memory 290736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564681287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3564681287
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2852368043
Short name T690
Test name
Test status
Simulation time 3710258408 ps
CPU time 229.22 seconds
Started Sep 04 04:26:38 PM UTC 24
Finished Sep 04 04:30:31 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852368043 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2852368043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3830479050
Short name T672
Test name
Test status
Simulation time 669132958 ps
CPU time 91.47 seconds
Started Sep 04 04:27:23 PM UTC 24
Finished Sep 04 04:28:56 PM UTC 24
Peak memory 380708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3830479050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t
hroughput_w_partial_write.3830479050
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1136379889
Short name T853
Test name
Test status
Simulation time 15659316915 ps
CPU time 901.92 seconds
Started Sep 04 04:29:41 PM UTC 24
Finished Sep 04 04:44:53 PM UTC 24
Peak memory 383132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136379889 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during
_key_req.1136379889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1567364492
Short name T689
Test name
Test status
Simulation time 128244998 ps
CPU time 0.96 seconds
Started Sep 04 04:30:17 PM UTC 24
Finished Sep 04 04:30:19 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567364492 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1567364492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.493606900
Short name T687
Test name
Test status
Simulation time 14513428460 ps
CPU time 69.41 seconds
Started Sep 04 04:28:57 PM UTC 24
Finished Sep 04 04:30:09 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493606900 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.493606900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1191577970
Short name T820
Test name
Test status
Simulation time 8493606008 ps
CPU time 711.86 seconds
Started Sep 04 04:29:44 PM UTC 24
Finished Sep 04 04:41:44 PM UTC 24
Peak memory 379060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191577970 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.1191577970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3595153051
Short name T680
Test name
Test status
Simulation time 653257446 ps
CPU time 2.67 seconds
Started Sep 04 04:29:36 PM UTC 24
Finished Sep 04 04:29:39 PM UTC 24
Peak memory 224020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595153051 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.3595153051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.185009858
Short name T688
Test name
Test status
Simulation time 115029026 ps
CPU time 55.75 seconds
Started Sep 04 04:29:18 PM UTC 24
Finished Sep 04 04:30:15 PM UTC 24
Peak memory 337708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
85009858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_max
_throughput.185009858
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.79793031
Short name T686
Test name
Test status
Simulation time 125948985 ps
CPU time 4.18 seconds
Started Sep 04 04:29:59 PM UTC 24
Finished Sep 04 04:30:04 PM UTC 24
Peak memory 224180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79793031 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.79793031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.246558911
Short name T685
Test name
Test status
Simulation time 195292343 ps
CPU time 7.29 seconds
Started Sep 04 04:29:49 PM UTC 24
Finished Sep 04 04:29:58 PM UTC 24
Peak memory 223996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246558911 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.246558911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1571502740
Short name T925
Test name
Test status
Simulation time 269980051153 ps
CPU time 1749.11 seconds
Started Sep 04 04:28:32 PM UTC 24
Finished Sep 04 04:58:00 PM UTC 24
Peak memory 388780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571502740 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1571502740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1375510288
Short name T679
Test name
Test status
Simulation time 336544754 ps
CPU time 30.95 seconds
Started Sep 04 04:29:03 PM UTC 24
Finished Sep 04 04:29:35 PM UTC 24
Peak memory 290936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375510288 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.1375510288
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.556408994
Short name T750
Test name
Test status
Simulation time 15375744933 ps
CPU time 383.79 seconds
Started Sep 04 04:29:15 PM UTC 24
Finished Sep 04 04:35:44 PM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556408994 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acce
ss_b2b.556408994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.347500468
Short name T684
Test name
Test status
Simulation time 63781160 ps
CPU time 1.07 seconds
Started Sep 04 04:29:46 PM UTC 24
Finished Sep 04 04:29:48 PM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347500468 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.347500468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2276200367
Short name T671
Test name
Test status
Simulation time 175615531 ps
CPU time 12.66 seconds
Started Sep 04 04:28:17 PM UTC 24
Finished Sep 04 04:28:31 PM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276200367 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2276200367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1762513465
Short name T941
Test name
Test status
Simulation time 89413349648 ps
CPU time 3271.73 seconds
Started Sep 04 04:30:09 PM UTC 24
Finished Sep 04 05:25:17 PM UTC 24
Peak memory 398888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176251346
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.1762513465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1122165358
Short name T696
Test name
Test status
Simulation time 1327085902 ps
CPU time 50.43 seconds
Started Sep 04 04:30:05 PM UTC 24
Finished Sep 04 04:30:57 PM UTC 24
Peak memory 302944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122165358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1122165358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.1629816819
Short name T729
Test name
Test status
Simulation time 2333562161 ps
CPU time 268.75 seconds
Started Sep 04 04:29:00 PM UTC 24
Finished Sep 04 04:33:33 PM UTC 24
Peak memory 213936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629816819 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.1629816819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2980367046
Short name T681
Test name
Test status
Simulation time 95998644 ps
CPU time 7.37 seconds
Started Sep 04 04:29:34 PM UTC 24
Finished Sep 04 04:29:43 PM UTC 24
Peak memory 247660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2980367046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t
hroughput_w_partial_write.2980367046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.258128764
Short name T753
Test name
Test status
Simulation time 1448056299 ps
CPU time 305.09 seconds
Started Sep 04 04:31:03 PM UTC 24
Finished Sep 04 04:36:12 PM UTC 24
Peak memory 364652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258128764 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during_
key_req.258128764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1365251333
Short name T706
Test name
Test status
Simulation time 24772883 ps
CPU time 0.98 seconds
Started Sep 04 04:31:39 PM UTC 24
Finished Sep 04 04:31:41 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365251333 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1365251333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.4252173144
Short name T699
Test name
Test status
Simulation time 1067528705 ps
CPU time 27.5 seconds
Started Sep 04 04:30:34 PM UTC 24
Finished Sep 04 04:31:03 PM UTC 24
Peak memory 213736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252173144 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.4252173144
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3223679975
Short name T854
Test name
Test status
Simulation time 43286671212 ps
CPU time 818.72 seconds
Started Sep 04 04:31:05 PM UTC 24
Finished Sep 04 04:44:53 PM UTC 24
Peak memory 384956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223679975 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.3223679975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.540717884
Short name T700
Test name
Test status
Simulation time 862612018 ps
CPU time 10.96 seconds
Started Sep 04 04:31:00 PM UTC 24
Finished Sep 04 04:31:13 PM UTC 24
Peak memory 214136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540717884 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.540717884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.497580214
Short name T709
Test name
Test status
Simulation time 108102708 ps
CPU time 64.58 seconds
Started Sep 04 04:30:54 PM UTC 24
Finished Sep 04 04:32:00 PM UTC 24
Peak memory 335664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
97580214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_max
_throughput.497580214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1613445019
Short name T704
Test name
Test status
Simulation time 974338258 ps
CPU time 7.59 seconds
Started Sep 04 04:31:19 PM UTC 24
Finished Sep 04 04:31:28 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613445019 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.1613445019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1378395908
Short name T703
Test name
Test status
Simulation time 465066888 ps
CPU time 7.52 seconds
Started Sep 04 04:31:17 PM UTC 24
Finished Sep 04 04:31:25 PM UTC 24
Peak memory 224008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378395908 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.1378395908
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.897193501
Short name T852
Test name
Test status
Simulation time 70585338170 ps
CPU time 847.09 seconds
Started Sep 04 04:30:32 PM UTC 24
Finished Sep 04 04:44:49 PM UTC 24
Peak memory 386992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897193501 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.897193501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1249224797
Short name T707
Test name
Test status
Simulation time 545019823 ps
CPU time 67.14 seconds
Started Sep 04 04:30:45 PM UTC 24
Finished Sep 04 04:31:54 PM UTC 24
Peak memory 349992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249224797 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1249224797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2486359205
Short name T732
Test name
Test status
Simulation time 9071184558 ps
CPU time 211.8 seconds
Started Sep 04 04:30:53 PM UTC 24
Finished Sep 04 04:34:28 PM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486359205 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acc
ess_b2b.2486359205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3079573783
Short name T701
Test name
Test status
Simulation time 29714533 ps
CPU time 1.13 seconds
Started Sep 04 04:31:13 PM UTC 24
Finished Sep 04 04:31:15 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079573783 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3079573783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.424675127
Short name T833
Test name
Test status
Simulation time 3194701885 ps
CPU time 723.6 seconds
Started Sep 04 04:31:09 PM UTC 24
Finished Sep 04 04:43:21 PM UTC 24
Peak memory 381128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424675127 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.424675127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1039804258
Short name T694
Test name
Test status
Simulation time 589768483 ps
CPU time 30.83 seconds
Started Sep 04 04:30:20 PM UTC 24
Finished Sep 04 04:30:52 PM UTC 24
Peak memory 303124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039804258 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1039804258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.4168095606
Short name T928
Test name
Test status
Simulation time 13382725481 ps
CPU time 1719.63 seconds
Started Sep 04 04:31:29 PM UTC 24
Finished Sep 04 05:00:26 PM UTC 24
Peak memory 385036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416809560
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.4168095606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2795351676
Short name T713
Test name
Test status
Simulation time 2102057922 ps
CPU time 48.64 seconds
Started Sep 04 04:31:26 PM UTC 24
Finished Sep 04 04:32:16 PM UTC 24
Peak memory 306996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795351676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2795351676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1396820747
Short name T755
Test name
Test status
Simulation time 3120779063 ps
CPU time 334.55 seconds
Started Sep 04 04:30:37 PM UTC 24
Finished Sep 04 04:36:16 PM UTC 24
Peak memory 213976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396820747 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.1396820747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.3867503749
Short name T712
Test name
Test status
Simulation time 257807752 ps
CPU time 75.44 seconds
Started Sep 04 04:30:58 PM UTC 24
Finished Sep 04 04:32:15 PM UTC 24
Peak memory 362348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3867503749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_t
hroughput_w_partial_write.3867503749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1069697056
Short name T243
Test name
Test status
Simulation time 3198472229 ps
CPU time 731.39 seconds
Started Sep 04 03:36:45 PM UTC 24
Finished Sep 04 03:49:05 PM UTC 24
Peak memory 384864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069697056 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_
key_req.1069697056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.4097187772
Short name T159
Test name
Test status
Simulation time 45927190 ps
CPU time 0.91 seconds
Started Sep 04 03:37:15 PM UTC 24
Finished Sep 04 03:37:17 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097187772 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.4097187772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2255393822
Short name T111
Test name
Test status
Simulation time 2157516719 ps
CPU time 35.16 seconds
Started Sep 04 03:36:30 PM UTC 24
Finished Sep 04 03:37:07 PM UTC 24
Peak memory 214116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255393822 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.2255393822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2058774716
Short name T57
Test name
Test status
Simulation time 820271414 ps
CPU time 10.58 seconds
Started Sep 04 03:36:41 PM UTC 24
Finished Sep 04 03:36:53 PM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058774716 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2058774716
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2305407873
Short name T161
Test name
Test status
Simulation time 375552932 ps
CPU time 53.28 seconds
Started Sep 04 03:36:39 PM UTC 24
Finished Sep 04 03:37:33 PM UTC 24
Peak memory 333672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
305407873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max
_throughput.2305407873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3081284383
Short name T44
Test name
Test status
Simulation time 194494538 ps
CPU time 4.7 seconds
Started Sep 04 03:37:06 PM UTC 24
Finished Sep 04 03:37:12 PM UTC 24
Peak memory 224408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081284383 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.3081284383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3304671811
Short name T112
Test name
Test status
Simulation time 1845146128 ps
CPU time 10.3 seconds
Started Sep 04 03:37:03 PM UTC 24
Finished Sep 04 03:37:14 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304671811 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.3304671811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3639803212
Short name T215
Test name
Test status
Simulation time 1580933045 ps
CPU time 542.77 seconds
Started Sep 04 03:36:27 PM UTC 24
Finished Sep 04 03:45:37 PM UTC 24
Peak memory 376612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639803212 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.3639803212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3687256341
Short name T149
Test name
Test status
Simulation time 754502026 ps
CPU time 73.33 seconds
Started Sep 04 03:36:30 PM UTC 24
Finished Sep 04 03:37:45 PM UTC 24
Peak memory 360300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687256341 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.3687256341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3444621482
Short name T248
Test name
Test status
Simulation time 176550153994 ps
CPU time 775.54 seconds
Started Sep 04 03:36:39 PM UTC 24
Finished Sep 04 03:49:44 PM UTC 24
Peak memory 213788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444621482 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce
ss_b2b.3444621482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3208412041
Short name T90
Test name
Test status
Simulation time 48885606 ps
CPU time 1.16 seconds
Started Sep 04 03:37:00 PM UTC 24
Finished Sep 04 03:37:02 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208412041 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3208412041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3443206165
Short name T257
Test name
Test status
Simulation time 9638403533 ps
CPU time 848.72 seconds
Started Sep 04 03:36:53 PM UTC 24
Finished Sep 04 03:51:12 PM UTC 24
Peak memory 378964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443206165 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3443206165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.3782597116
Short name T89
Test name
Test status
Simulation time 549515171 ps
CPU time 12.89 seconds
Started Sep 04 03:36:26 PM UTC 24
Finished Sep 04 03:36:40 PM UTC 24
Peak memory 214196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782597116 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3782597116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1231255914
Short name T139
Test name
Test status
Simulation time 53341306870 ps
CPU time 672.75 seconds
Started Sep 04 03:37:08 PM UTC 24
Finished Sep 04 03:48:29 PM UTC 24
Peak memory 384820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123125591
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.1231255914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1516495738
Short name T51
Test name
Test status
Simulation time 5320785430 ps
CPU time 94.09 seconds
Started Sep 04 03:37:08 PM UTC 24
Finished Sep 04 03:38:44 PM UTC 24
Peak memory 366524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516495738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1516495738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2553981967
Short name T100
Test name
Test status
Simulation time 13083488488 ps
CPU time 317.26 seconds
Started Sep 04 03:36:30 PM UTC 24
Finished Sep 04 03:41:52 PM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553981967 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.2553981967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1776644382
Short name T164
Test name
Test status
Simulation time 136808332 ps
CPU time 77.6 seconds
Started Sep 04 03:36:41 PM UTC 24
Finished Sep 04 03:38:01 PM UTC 24
Peak memory 355928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1776644382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th
roughput_w_partial_write.1776644382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2818660576
Short name T825
Test name
Test status
Simulation time 2200917530 ps
CPU time 610.05 seconds
Started Sep 04 04:32:19 PM UTC 24
Finished Sep 04 04:42:36 PM UTC 24
Peak memory 383208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818660576 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during
_key_req.2818660576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1733666347
Short name T724
Test name
Test status
Simulation time 22904990 ps
CPU time 0.87 seconds
Started Sep 04 04:33:07 PM UTC 24
Finished Sep 04 04:33:09 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733666347 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1733666347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.184797118
Short name T722
Test name
Test status
Simulation time 2395137333 ps
CPU time 46.21 seconds
Started Sep 04 04:32:00 PM UTC 24
Finished Sep 04 04:32:48 PM UTC 24
Peak memory 213984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184797118 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.184797118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.921251505
Short name T725
Test name
Test status
Simulation time 2095888115 ps
CPU time 51.53 seconds
Started Sep 04 04:32:24 PM UTC 24
Finished Sep 04 04:33:17 PM UTC 24
Peak memory 213748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921251505 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.921251505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1235345948
Short name T718
Test name
Test status
Simulation time 788147873 ps
CPU time 7.9 seconds
Started Sep 04 04:32:19 PM UTC 24
Finished Sep 04 04:32:28 PM UTC 24
Peak memory 214156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235345948 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.1235345948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3925835311
Short name T716
Test name
Test status
Simulation time 63101202 ps
CPU time 5.79 seconds
Started Sep 04 04:32:16 PM UTC 24
Finished Sep 04 04:32:23 PM UTC 24
Peak memory 237356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
925835311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ma
x_throughput.3925835311
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.435053483
Short name T721
Test name
Test status
Simulation time 335719365 ps
CPU time 4.17 seconds
Started Sep 04 04:32:43 PM UTC 24
Finished Sep 04 04:32:48 PM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435053483 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.435053483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2945275789
Short name T720
Test name
Test status
Simulation time 603192246 ps
CPU time 9.45 seconds
Started Sep 04 04:32:31 PM UTC 24
Finished Sep 04 04:32:42 PM UTC 24
Peak memory 214124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945275789 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2945275789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2513844202
Short name T840
Test name
Test status
Simulation time 18889585645 ps
CPU time 705.44 seconds
Started Sep 04 04:31:54 PM UTC 24
Finished Sep 04 04:43:48 PM UTC 24
Peak memory 382896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513844202 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.2513844202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2394288742
Short name T717
Test name
Test status
Simulation time 614275635 ps
CPU time 18.39 seconds
Started Sep 04 04:32:04 PM UTC 24
Finished Sep 04 04:32:23 PM UTC 24
Peak memory 213812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394288742 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.2394288742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2624778827
Short name T821
Test name
Test status
Simulation time 24668727718 ps
CPU time 587.78 seconds
Started Sep 04 04:32:07 PM UTC 24
Finished Sep 04 04:42:02 PM UTC 24
Peak memory 213972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624778827 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc
ess_b2b.2624778827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.4161648371
Short name T719
Test name
Test status
Simulation time 75389879 ps
CPU time 1.26 seconds
Started Sep 04 04:32:28 PM UTC 24
Finished Sep 04 04:32:30 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161648371 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.4161648371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.577186279
Short name T906
Test name
Test status
Simulation time 62961862115 ps
CPU time 1183.27 seconds
Started Sep 04 04:32:24 PM UTC 24
Finished Sep 04 04:52:20 PM UTC 24
Peak memory 386948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577186279 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.577186279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3070791030
Short name T710
Test name
Test status
Simulation time 235721350 ps
CPU time 19.26 seconds
Started Sep 04 04:31:42 PM UTC 24
Finished Sep 04 04:32:02 PM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070791030 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3070791030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2561671
Short name T913
Test name
Test status
Simulation time 51118171577 ps
CPU time 1299.5 seconds
Started Sep 04 04:32:49 PM UTC 24
Finished Sep 04 04:54:43 PM UTC 24
Peak memory 387240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561671 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.2561671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1914594393
Short name T761
Test name
Test status
Simulation time 4218009899 ps
CPU time 218.38 seconds
Started Sep 04 04:32:49 PM UTC 24
Finished Sep 04 04:36:31 PM UTC 24
Peak memory 389028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914594393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1914594393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1646947755
Short name T765
Test name
Test status
Simulation time 12473177203 ps
CPU time 318.29 seconds
Started Sep 04 04:32:02 PM UTC 24
Finished Sep 04 04:37:24 PM UTC 24
Peak memory 213952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646947755 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.1646947755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1393266853
Short name T723
Test name
Test status
Simulation time 118392952 ps
CPU time 47.5 seconds
Started Sep 04 04:32:17 PM UTC 24
Finished Sep 04 04:33:06 PM UTC 24
Peak memory 319344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1393266853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_t
hroughput_w_partial_write.1393266853
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1202529579
Short name T912
Test name
Test status
Simulation time 18756263979 ps
CPU time 1187.42 seconds
Started Sep 04 04:34:28 PM UTC 24
Finished Sep 04 04:54:29 PM UTC 24
Peak memory 386912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202529579 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during
_key_req.1202529579
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.2908833076
Short name T742
Test name
Test status
Simulation time 15611332 ps
CPU time 0.96 seconds
Started Sep 04 04:34:57 PM UTC 24
Finished Sep 04 04:34:59 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908833076 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2908833076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3611791953
Short name T736
Test name
Test status
Simulation time 23075618567 ps
CPU time 73.96 seconds
Started Sep 04 04:33:26 PM UTC 24
Finished Sep 04 04:34:42 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611791953 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.3611791953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2283470978
Short name T917
Test name
Test status
Simulation time 35528372592 ps
CPU time 1258.73 seconds
Started Sep 04 04:34:35 PM UTC 24
Finished Sep 04 04:55:48 PM UTC 24
Peak memory 379076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283470978 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.2283470978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1793326172
Short name T734
Test name
Test status
Simulation time 1743873438 ps
CPU time 6.59 seconds
Started Sep 04 04:34:27 PM UTC 24
Finished Sep 04 04:34:35 PM UTC 24
Peak memory 213800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793326172 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.1793326172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.4132317134
Short name T744
Test name
Test status
Simulation time 508427753 ps
CPU time 73.05 seconds
Started Sep 04 04:33:48 PM UTC 24
Finished Sep 04 04:35:02 PM UTC 24
Peak memory 358260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
132317134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma
x_throughput.4132317134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.1122184956
Short name T741
Test name
Test status
Simulation time 164513333 ps
CPU time 8.2 seconds
Started Sep 04 04:34:46 PM UTC 24
Finished Sep 04 04:34:56 PM UTC 24
Peak memory 224424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122184956 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.1122184956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1857251757
Short name T739
Test name
Test status
Simulation time 281173998 ps
CPU time 5.83 seconds
Started Sep 04 04:34:43 PM UTC 24
Finished Sep 04 04:34:50 PM UTC 24
Peak memory 224148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857251757 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.1857251757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2336906589
Short name T885
Test name
Test status
Simulation time 74130476675 ps
CPU time 807.08 seconds
Started Sep 04 04:33:18 PM UTC 24
Finished Sep 04 04:46:54 PM UTC 24
Peak memory 382892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336906589 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2336906589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1175282621
Short name T674
Test name
Test status
Simulation time 1898954274 ps
CPU time 14.64 seconds
Started Sep 04 04:33:32 PM UTC 24
Finished Sep 04 04:33:48 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175282621 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.1175282621
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.706587389
Short name T791
Test name
Test status
Simulation time 13091910197 ps
CPU time 346.92 seconds
Started Sep 04 04:33:34 PM UTC 24
Finished Sep 04 04:39:26 PM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706587389 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acce
ss_b2b.706587389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4027881169
Short name T737
Test name
Test status
Simulation time 28509604 ps
CPU time 1.17 seconds
Started Sep 04 04:34:43 PM UTC 24
Finished Sep 04 04:34:45 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027881169 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4027881169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.980454072
Short name T899
Test name
Test status
Simulation time 13081126242 ps
CPU time 959.84 seconds
Started Sep 04 04:34:36 PM UTC 24
Finished Sep 04 04:50:46 PM UTC 24
Peak memory 378724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980454072 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.980454072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2436699087
Short name T727
Test name
Test status
Simulation time 362578325 ps
CPU time 14.04 seconds
Started Sep 04 04:33:11 PM UTC 24
Finished Sep 04 04:33:26 PM UTC 24
Peak memory 213752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436699087 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2436699087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2158024742
Short name T938
Test name
Test status
Simulation time 33139176319 ps
CPU time 2484.8 seconds
Started Sep 04 04:34:51 PM UTC 24
Finished Sep 04 05:16:43 PM UTC 24
Peak memory 388720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215802474
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.2158024742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3650295240
Short name T768
Test name
Test status
Simulation time 2166089436 ps
CPU time 240.82 seconds
Started Sep 04 04:33:27 PM UTC 24
Finished Sep 04 04:37:32 PM UTC 24
Peak memory 213788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650295240 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.3650295240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4192708206
Short name T747
Test name
Test status
Simulation time 1210891040 ps
CPU time 102.96 seconds
Started Sep 04 04:33:49 PM UTC 24
Finished Sep 04 04:35:34 PM UTC 24
Peak memory 380708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4192708206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t
hroughput_w_partial_write.4192708206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.4280540546
Short name T832
Test name
Test status
Simulation time 4416793661 ps
CPU time 448.82 seconds
Started Sep 04 04:35:45 PM UTC 24
Finished Sep 04 04:43:19 PM UTC 24
Peak memory 376756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280540546 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during
_key_req.4280540546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.358288823
Short name T760
Test name
Test status
Simulation time 41359219 ps
CPU time 0.87 seconds
Started Sep 04 04:36:28 PM UTC 24
Finished Sep 04 04:36:30 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358288823 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.358288823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3721048372
Short name T763
Test name
Test status
Simulation time 49576117548 ps
CPU time 117.16 seconds
Started Sep 04 04:35:03 PM UTC 24
Finished Sep 04 04:37:03 PM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721048372 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.3721048372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3642072393
Short name T846
Test name
Test status
Simulation time 40548410112 ps
CPU time 489.01 seconds
Started Sep 04 04:35:56 PM UTC 24
Finished Sep 04 04:44:11 PM UTC 24
Peak memory 382824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642072393 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.3642072393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2503289955
Short name T751
Test name
Test status
Simulation time 412853623 ps
CPU time 9.58 seconds
Started Sep 04 04:35:45 PM UTC 24
Finished Sep 04 04:35:56 PM UTC 24
Peak memory 214132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503289955 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.2503289955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2264817358
Short name T749
Test name
Test status
Simulation time 73403381 ps
CPU time 7.29 seconds
Started Sep 04 04:35:35 PM UTC 24
Finished Sep 04 04:35:43 PM UTC 24
Peak memory 247732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
264817358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma
x_throughput.2264817358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.908033727
Short name T756
Test name
Test status
Simulation time 459083313 ps
CPU time 4.4 seconds
Started Sep 04 04:36:17 PM UTC 24
Finished Sep 04 04:36:23 PM UTC 24
Peak memory 224092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908033727 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.908033727
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.455689785
Short name T758
Test name
Test status
Simulation time 499627729 ps
CPU time 9.36 seconds
Started Sep 04 04:36:16 PM UTC 24
Finished Sep 04 04:36:27 PM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455689785 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.455689785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3284407306
Short name T813
Test name
Test status
Simulation time 3766263227 ps
CPU time 343.03 seconds
Started Sep 04 04:35:00 PM UTC 24
Finished Sep 04 04:40:48 PM UTC 24
Peak memory 378724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284407306 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.3284407306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3596470114
Short name T757
Test name
Test status
Simulation time 4299182035 ps
CPU time 76.41 seconds
Started Sep 04 04:35:07 PM UTC 24
Finished Sep 04 04:36:25 PM UTC 24
Peak memory 348344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596470114 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.3596470114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.927576889
Short name T796
Test name
Test status
Simulation time 7349805382 ps
CPU time 267.04 seconds
Started Sep 04 04:35:10 PM UTC 24
Finished Sep 04 04:39:41 PM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927576889 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acce
ss_b2b.927576889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2784727004
Short name T754
Test name
Test status
Simulation time 84662704 ps
CPU time 1.1 seconds
Started Sep 04 04:36:13 PM UTC 24
Finished Sep 04 04:36:15 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784727004 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2784727004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.1720917058
Short name T916
Test name
Test status
Simulation time 3543997835 ps
CPU time 1152.34 seconds
Started Sep 04 04:36:11 PM UTC 24
Finished Sep 04 04:55:35 PM UTC 24
Peak memory 380732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720917058 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1720917058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.4064010380
Short name T746
Test name
Test status
Simulation time 965118398 ps
CPU time 11.13 seconds
Started Sep 04 04:34:57 PM UTC 24
Finished Sep 04 04:35:09 PM UTC 24
Peak memory 268148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064010380 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4064010380
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1541989486
Short name T920
Test name
Test status
Simulation time 17547290003 ps
CPU time 1198.77 seconds
Started Sep 04 04:36:26 PM UTC 24
Finished Sep 04 04:56:38 PM UTC 24
Peak memory 386936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154198948
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.1541989486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1555310835
Short name T805
Test name
Test status
Simulation time 1442140044 ps
CPU time 232.46 seconds
Started Sep 04 04:36:24 PM UTC 24
Finished Sep 04 04:40:19 PM UTC 24
Peak memory 393056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555310835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1555310835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.3409478390
Short name T781
Test name
Test status
Simulation time 2306508951 ps
CPU time 231.16 seconds
Started Sep 04 04:35:03 PM UTC 24
Finished Sep 04 04:38:58 PM UTC 24
Peak memory 213980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409478390 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.3409478390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3193134642
Short name T752
Test name
Test status
Simulation time 410231545 ps
CPU time 28.75 seconds
Started Sep 04 04:35:39 PM UTC 24
Finished Sep 04 04:36:09 PM UTC 24
Peak memory 313516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3193134642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t
hroughput_w_partial_write.3193134642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1677904138
Short name T915
Test name
Test status
Simulation time 14992717768 ps
CPU time 1067.29 seconds
Started Sep 04 04:37:30 PM UTC 24
Finished Sep 04 04:55:29 PM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677904138 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during
_key_req.1677904138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.464286507
Short name T776
Test name
Test status
Simulation time 44828313 ps
CPU time 0.86 seconds
Started Sep 04 04:38:04 PM UTC 24
Finished Sep 04 04:38:06 PM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464286507 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.464286507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.2656712379
Short name T770
Test name
Test status
Simulation time 2915910154 ps
CPU time 64.32 seconds
Started Sep 04 04:36:31 PM UTC 24
Finished Sep 04 04:37:38 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656712379 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.2656712379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2161051672
Short name T914
Test name
Test status
Simulation time 38622353042 ps
CPU time 1031.28 seconds
Started Sep 04 04:37:33 PM UTC 24
Finished Sep 04 04:54:55 PM UTC 24
Peak memory 384900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161051672 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.2161051672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4239733185
Short name T769
Test name
Test status
Simulation time 528246415 ps
CPU time 6.83 seconds
Started Sep 04 04:37:28 PM UTC 24
Finished Sep 04 04:37:36 PM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239733185 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.4239733185
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3808376482
Short name T778
Test name
Test status
Simulation time 134827457 ps
CPU time 77.05 seconds
Started Sep 04 04:37:08 PM UTC 24
Finished Sep 04 04:38:27 PM UTC 24
Peak memory 378664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
808376482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma
x_throughput.3808376482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2235067923
Short name T774
Test name
Test status
Simulation time 663165019 ps
CPU time 7.28 seconds
Started Sep 04 04:37:51 PM UTC 24
Finished Sep 04 04:37:59 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235067923 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.2235067923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.497100641
Short name T772
Test name
Test status
Simulation time 530577593 ps
CPU time 6.36 seconds
Started Sep 04 04:37:42 PM UTC 24
Finished Sep 04 04:37:50 PM UTC 24
Peak memory 213760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497100641 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.497100641
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3405739842
Short name T818
Test name
Test status
Simulation time 4166332958 ps
CPU time 300.75 seconds
Started Sep 04 04:36:30 PM UTC 24
Finished Sep 04 04:41:36 PM UTC 24
Peak memory 376688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405739842 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.3405739842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3011517629
Short name T764
Test name
Test status
Simulation time 340313058 ps
CPU time 9.07 seconds
Started Sep 04 04:36:57 PM UTC 24
Finished Sep 04 04:37:07 PM UTC 24
Peak memory 213804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011517629 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.3011517629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3366084683
Short name T842
Test name
Test status
Simulation time 18536847334 ps
CPU time 408.08 seconds
Started Sep 04 04:37:04 PM UTC 24
Finished Sep 04 04:43:58 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366084683 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc
ess_b2b.3366084683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.90756869
Short name T771
Test name
Test status
Simulation time 81117588 ps
CPU time 1.08 seconds
Started Sep 04 04:37:39 PM UTC 24
Finished Sep 04 04:37:41 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90756869 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.90756869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.2443578197
Short name T789
Test name
Test status
Simulation time 4510825953 ps
CPU time 103.28 seconds
Started Sep 04 04:37:37 PM UTC 24
Finished Sep 04 04:39:22 PM UTC 24
Peak memory 358544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443578197 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2443578197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3562914299
Short name T762
Test name
Test status
Simulation time 281527248 ps
CPU time 2.1 seconds
Started Sep 04 04:36:30 PM UTC 24
Finished Sep 04 04:36:34 PM UTC 24
Peak memory 213740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562914299 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3562914299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.628618924
Short name T878
Test name
Test status
Simulation time 57867704369 ps
CPU time 491.21 seconds
Started Sep 04 04:38:00 PM UTC 24
Finished Sep 04 04:46:17 PM UTC 24
Peak memory 377020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628618924
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.628618924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2681388377
Short name T793
Test name
Test status
Simulation time 6460916530 ps
CPU time 175 seconds
Started Sep 04 04:36:36 PM UTC 24
Finished Sep 04 04:39:34 PM UTC 24
Peak memory 213956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681388377 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.2681388377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2310360664
Short name T767
Test name
Test status
Simulation time 79873895 ps
CPU time 1.96 seconds
Started Sep 04 04:37:26 PM UTC 24
Finished Sep 04 04:37:29 PM UTC 24
Peak memory 222864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2310360664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_t
hroughput_w_partial_write.2310360664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2713618447
Short name T909
Test name
Test status
Simulation time 3286332578 ps
CPU time 851.4 seconds
Started Sep 04 04:39:05 PM UTC 24
Finished Sep 04 04:53:26 PM UTC 24
Peak memory 380708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713618447 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during
_key_req.2713618447
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2779436907
Short name T794
Test name
Test status
Simulation time 44981573 ps
CPU time 0.89 seconds
Started Sep 04 04:39:33 PM UTC 24
Finished Sep 04 04:39:35 PM UTC 24
Peak memory 212808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779436907 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2779436907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.4052137832
Short name T782
Test name
Test status
Simulation time 11436010159 ps
CPU time 30.81 seconds
Started Sep 04 04:38:28 PM UTC 24
Finished Sep 04 04:39:00 PM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052137832 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.4052137832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.2265320825
Short name T850
Test name
Test status
Simulation time 35859075791 ps
CPU time 313.52 seconds
Started Sep 04 04:39:07 PM UTC 24
Finished Sep 04 04:44:24 PM UTC 24
Peak memory 372588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265320825 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.2265320825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2648151877
Short name T787
Test name
Test status
Simulation time 517382192 ps
CPU time 7.69 seconds
Started Sep 04 04:39:04 PM UTC 24
Finished Sep 04 04:39:13 PM UTC 24
Peak memory 213880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648151877 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.2648151877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3893986937
Short name T795
Test name
Test status
Simulation time 218166369 ps
CPU time 38.53 seconds
Started Sep 04 04:38:59 PM UTC 24
Finished Sep 04 04:39:39 PM UTC 24
Peak memory 304880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
893986937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ma
x_throughput.3893986937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.375914367
Short name T792
Test name
Test status
Simulation time 528146976 ps
CPU time 7.11 seconds
Started Sep 04 04:39:23 PM UTC 24
Finished Sep 04 04:39:31 PM UTC 24
Peak memory 224172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375914367 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.375914367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.4040299387
Short name T790
Test name
Test status
Simulation time 230772268 ps
CPU time 7.55 seconds
Started Sep 04 04:39:17 PM UTC 24
Finished Sep 04 04:39:26 PM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040299387 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.4040299387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3784272935
Short name T892
Test name
Test status
Simulation time 28463231679 ps
CPU time 629.31 seconds
Started Sep 04 04:38:21 PM UTC 24
Finished Sep 04 04:48:58 PM UTC 24
Peak memory 383160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784272935 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.3784272935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2857721615
Short name T783
Test name
Test status
Simulation time 1226806695 ps
CPU time 12.69 seconds
Started Sep 04 04:38:49 PM UTC 24
Finished Sep 04 04:39:03 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857721615 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2857721615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.2762563262
Short name T864
Test name
Test status
Simulation time 22148093336 ps
CPU time 402.91 seconds
Started Sep 04 04:38:52 PM UTC 24
Finished Sep 04 04:45:40 PM UTC 24
Peak memory 214196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762563262 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc
ess_b2b.2762563262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3222693946
Short name T788
Test name
Test status
Simulation time 75657009 ps
CPU time 1.09 seconds
Started Sep 04 04:39:14 PM UTC 24
Finished Sep 04 04:39:16 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222693946 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3222693946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.2627113321
Short name T897
Test name
Test status
Simulation time 16617373675 ps
CPU time 666.8 seconds
Started Sep 04 04:39:07 PM UTC 24
Finished Sep 04 04:50:21 PM UTC 24
Peak memory 384976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627113321 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2627113321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.607215185
Short name T777
Test name
Test status
Simulation time 6761317988 ps
CPU time 10.49 seconds
Started Sep 04 04:38:07 PM UTC 24
Finished Sep 04 04:38:19 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607215185 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.607215185
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2545933002
Short name T943
Test name
Test status
Simulation time 38835143197 ps
CPU time 3446.13 seconds
Started Sep 04 04:39:27 PM UTC 24
Finished Sep 04 05:37:34 PM UTC 24
Peak memory 388716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254593300
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.2545933002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.759126977
Short name T797
Test name
Test status
Simulation time 392093455 ps
CPU time 17.76 seconds
Started Sep 04 04:39:26 PM UTC 24
Finished Sep 04 04:39:45 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759126977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.759126977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2910054062
Short name T845
Test name
Test status
Simulation time 3484786336 ps
CPU time 322.03 seconds
Started Sep 04 04:38:43 PM UTC 24
Finished Sep 04 04:44:09 PM UTC 24
Peak memory 213964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910054062 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.2910054062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.395701433
Short name T803
Test name
Test status
Simulation time 130207706 ps
CPU time 62.11 seconds
Started Sep 04 04:39:01 PM UTC 24
Finished Sep 04 04:40:05 PM UTC 24
Peak memory 339744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
395701433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_th
roughput_w_partial_write.395701433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2546250626
Short name T923
Test name
Test status
Simulation time 3656628006 ps
CPU time 1009.32 seconds
Started Sep 04 04:40:05 PM UTC 24
Finished Sep 04 04:57:06 PM UTC 24
Peak memory 385252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546250626 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during
_key_req.2546250626
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.596346261
Short name T812
Test name
Test status
Simulation time 23437981 ps
CPU time 1.02 seconds
Started Sep 04 04:40:41 PM UTC 24
Finished Sep 04 04:40:43 PM UTC 24
Peak memory 212816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596346261 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.596346261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.1643244835
Short name T807
Test name
Test status
Simulation time 6699983493 ps
CPU time 49.01 seconds
Started Sep 04 04:39:39 PM UTC 24
Finished Sep 04 04:40:30 PM UTC 24
Peak memory 213824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643244835 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.1643244835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.2795655747
Short name T904
Test name
Test status
Simulation time 3291691432 ps
CPU time 695.48 seconds
Started Sep 04 04:40:06 PM UTC 24
Finished Sep 04 04:51:50 PM UTC 24
Peak memory 384944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795655747 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.2795655747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1638264206
Short name T804
Test name
Test status
Simulation time 636034647 ps
CPU time 9.44 seconds
Started Sep 04 04:40:02 PM UTC 24
Finished Sep 04 04:40:12 PM UTC 24
Peak memory 224296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638264206 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.1638264206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.64866030
Short name T808
Test name
Test status
Simulation time 183930521 ps
CPU time 37.25 seconds
Started Sep 04 04:39:53 PM UTC 24
Finished Sep 04 04:40:32 PM UTC 24
Peak memory 302968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
4866030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_max_
throughput.64866030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.258463487
Short name T809
Test name
Test status
Simulation time 182147890 ps
CPU time 3.77 seconds
Started Sep 04 04:40:31 PM UTC 24
Finished Sep 04 04:40:36 PM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258463487 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.258463487
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1086344511
Short name T811
Test name
Test status
Simulation time 5166066300 ps
CPU time 16.74 seconds
Started Sep 04 04:40:24 PM UTC 24
Finished Sep 04 04:40:42 PM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086344511 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.1086344511
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2252953983
Short name T848
Test name
Test status
Simulation time 3574250802 ps
CPU time 276.11 seconds
Started Sep 04 04:39:36 PM UTC 24
Finished Sep 04 04:44:16 PM UTC 24
Peak memory 376752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252953983 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.2252953983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.3364505589
Short name T799
Test name
Test status
Simulation time 89789113 ps
CPU time 3.89 seconds
Started Sep 04 04:39:47 PM UTC 24
Finished Sep 04 04:39:52 PM UTC 24
Peak memory 220100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364505589 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.3364505589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.150443257
Short name T866
Test name
Test status
Simulation time 6719414142 ps
CPU time 347.39 seconds
Started Sep 04 04:39:50 PM UTC 24
Finished Sep 04 04:45:42 PM UTC 24
Peak memory 213988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150443257 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acce
ss_b2b.150443257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.207080517
Short name T806
Test name
Test status
Simulation time 33232672 ps
CPU time 1.09 seconds
Started Sep 04 04:40:21 PM UTC 24
Finished Sep 04 04:40:23 PM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207080517 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.207080517
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3290578263
Short name T875
Test name
Test status
Simulation time 1776326489 ps
CPU time 355.86 seconds
Started Sep 04 04:40:13 PM UTC 24
Finished Sep 04 04:46:14 PM UTC 24
Peak memory 384888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290578263 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3290578263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.2673732997
Short name T798
Test name
Test status
Simulation time 438590732 ps
CPU time 13.39 seconds
Started Sep 04 04:39:35 PM UTC 24
Finished Sep 04 04:39:49 PM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673732997 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2673732997
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3052841652
Short name T940
Test name
Test status
Simulation time 117128136504 ps
CPU time 2546.31 seconds
Started Sep 04 04:40:36 PM UTC 24
Finished Sep 04 05:23:31 PM UTC 24
Peak memory 396864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305284165
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.3052841652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3701665114
Short name T824
Test name
Test status
Simulation time 10888838383 ps
CPU time 112.01 seconds
Started Sep 04 04:40:33 PM UTC 24
Finished Sep 04 04:42:28 PM UTC 24
Peak memory 356256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701665114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3701665114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1348768648
Short name T836
Test name
Test status
Simulation time 5644183111 ps
CPU time 233.05 seconds
Started Sep 04 04:39:42 PM UTC 24
Finished Sep 04 04:43:38 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348768648 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1348768648
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2956607937
Short name T802
Test name
Test status
Simulation time 104229466 ps
CPU time 4.52 seconds
Started Sep 04 04:39:58 PM UTC 24
Finished Sep 04 04:40:04 PM UTC 24
Peak memory 231272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2956607937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t
hroughput_w_partial_write.2956607937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1236725043
Short name T898
Test name
Test status
Simulation time 7057282858 ps
CPU time 525.56 seconds
Started Sep 04 04:41:43 PM UTC 24
Finished Sep 04 04:50:36 PM UTC 24
Peak memory 384840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236725043 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during
_key_req.1236725043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4234607730
Short name T829
Test name
Test status
Simulation time 24508403 ps
CPU time 0.97 seconds
Started Sep 04 04:42:46 PM UTC 24
Finished Sep 04 04:42:48 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234607730 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.4234607730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.1117084872
Short name T830
Test name
Test status
Simulation time 5734200690 ps
CPU time 119.33 seconds
Started Sep 04 04:40:49 PM UTC 24
Finished Sep 04 04:42:50 PM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117084872 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.1117084872
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3194790921
Short name T895
Test name
Test status
Simulation time 4596800674 ps
CPU time 480.72 seconds
Started Sep 04 04:41:45 PM UTC 24
Finished Sep 04 04:49:51 PM UTC 24
Peak memory 382896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194790921 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.3194790921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.3651466585
Short name T819
Test name
Test status
Simulation time 790477829 ps
CPU time 4.52 seconds
Started Sep 04 04:41:37 PM UTC 24
Finished Sep 04 04:41:43 PM UTC 24
Peak memory 213796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651466585 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.3651466585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.656673770
Short name T817
Test name
Test status
Simulation time 64234614 ps
CPU time 1.66 seconds
Started Sep 04 04:41:25 PM UTC 24
Finished Sep 04 04:41:28 PM UTC 24
Peak memory 222648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
56673770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_max
_throughput.656673770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3107592540
Short name T826
Test name
Test status
Simulation time 93838642 ps
CPU time 6.6 seconds
Started Sep 04 04:42:28 PM UTC 24
Finished Sep 04 04:42:36 PM UTC 24
Peak memory 224016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107592540 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.3107592540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2364261957
Short name T827
Test name
Test status
Simulation time 683605221 ps
CPU time 16.16 seconds
Started Sep 04 04:42:27 PM UTC 24
Finished Sep 04 04:42:45 PM UTC 24
Peak memory 213864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364261957 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.2364261957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2727002186
Short name T900
Test name
Test status
Simulation time 9283494281 ps
CPU time 611.64 seconds
Started Sep 04 04:40:44 PM UTC 24
Finished Sep 04 04:51:03 PM UTC 24
Peak memory 378728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727002186 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.2727002186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3655581252
Short name T816
Test name
Test status
Simulation time 311949954 ps
CPU time 2.19 seconds
Started Sep 04 04:41:04 PM UTC 24
Finished Sep 04 04:41:08 PM UTC 24
Peak memory 213872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655581252 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.3655581252
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1633542397
Short name T903
Test name
Test status
Simulation time 49457453992 ps
CPU time 618.9 seconds
Started Sep 04 04:41:09 PM UTC 24
Finished Sep 04 04:51:35 PM UTC 24
Peak memory 213832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633542397 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc
ess_b2b.1633542397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2859676351
Short name T823
Test name
Test status
Simulation time 69815087 ps
CPU time 1.08 seconds
Started Sep 04 04:42:24 PM UTC 24
Finished Sep 04 04:42:26 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859676351 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2859676351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.3220787541
Short name T932
Test name
Test status
Simulation time 16359003819 ps
CPU time 1241.06 seconds
Started Sep 04 04:42:03 PM UTC 24
Finished Sep 04 05:02:57 PM UTC 24
Peak memory 384848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220787541 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3220787541
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2660277791
Short name T815
Test name
Test status
Simulation time 784569052 ps
CPU time 19.13 seconds
Started Sep 04 04:40:43 PM UTC 24
Finished Sep 04 04:41:03 PM UTC 24
Peak memory 213940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660277791 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2660277791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.574883523
Short name T942
Test name
Test status
Simulation time 147258138833 ps
CPU time 2658.45 seconds
Started Sep 04 04:42:37 PM UTC 24
Finished Sep 04 05:27:25 PM UTC 24
Peak memory 388924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574883523
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.574883523
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.353663356
Short name T863
Test name
Test status
Simulation time 1973893128 ps
CPU time 179.82 seconds
Started Sep 04 04:42:37 PM UTC 24
Finished Sep 04 04:45:39 PM UTC 24
Peak memory 372748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353663356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.353663356
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.422941854
Short name T886
Test name
Test status
Simulation time 2893640096 ps
CPU time 374.25 seconds
Started Sep 04 04:40:57 PM UTC 24
Finished Sep 04 04:47:16 PM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422941854 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.422941854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.802857938
Short name T822
Test name
Test status
Simulation time 481740510 ps
CPU time 52.69 seconds
Started Sep 04 04:41:29 PM UTC 24
Finished Sep 04 04:42:23 PM UTC 24
Peak memory 329580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
802857938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_th
roughput_w_partial_write.802857938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.136957977
Short name T930
Test name
Test status
Simulation time 15872275839 ps
CPU time 1132.23 seconds
Started Sep 04 04:43:43 PM UTC 24
Finished Sep 04 05:02:47 PM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136957977 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during_
key_req.136957977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3203466777
Short name T847
Test name
Test status
Simulation time 40622573 ps
CPU time 0.92 seconds
Started Sep 04 04:44:10 PM UTC 24
Finished Sep 04 04:44:12 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203466777 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3203466777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.1600393499
Short name T835
Test name
Test status
Simulation time 6698227829 ps
CPU time 37.43 seconds
Started Sep 04 04:42:52 PM UTC 24
Finished Sep 04 04:43:31 PM UTC 24
Peak memory 214204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600393499 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.1600393499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.2289012557
Short name T924
Test name
Test status
Simulation time 2624043566 ps
CPU time 825.88 seconds
Started Sep 04 04:43:43 PM UTC 24
Finished Sep 04 04:57:38 PM UTC 24
Peak memory 384960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289012557 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.2289012557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3592226945
Short name T839
Test name
Test status
Simulation time 418658919 ps
CPU time 4.25 seconds
Started Sep 04 04:43:39 PM UTC 24
Finished Sep 04 04:43:44 PM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592226945 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.3592226945
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.806504775
Short name T838
Test name
Test status
Simulation time 182548690 ps
CPU time 14.71 seconds
Started Sep 04 04:43:26 PM UTC 24
Finished Sep 04 04:43:42 PM UTC 24
Peak memory 263984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8
06504775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_max
_throughput.806504775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.4223689804
Short name T844
Test name
Test status
Simulation time 370334973 ps
CPU time 6.98 seconds
Started Sep 04 04:43:59 PM UTC 24
Finished Sep 04 04:44:07 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223689804 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.4223689804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2879139202
Short name T843
Test name
Test status
Simulation time 541214202 ps
CPU time 10.6 seconds
Started Sep 04 04:43:52 PM UTC 24
Finished Sep 04 04:44:04 PM UTC 24
Peak memory 224400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879139202 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.2879139202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3107030824
Short name T926
Test name
Test status
Simulation time 53398886697 ps
CPU time 990.03 seconds
Started Sep 04 04:42:49 PM UTC 24
Finished Sep 04 04:59:30 PM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107030824 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.3107030824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.4079957422
Short name T837
Test name
Test status
Simulation time 1170831715 ps
CPU time 19.61 seconds
Started Sep 04 04:43:21 PM UTC 24
Finished Sep 04 04:43:41 PM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079957422 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.4079957422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1404848466
Short name T896
Test name
Test status
Simulation time 15519584241 ps
CPU time 388.09 seconds
Started Sep 04 04:43:22 PM UTC 24
Finished Sep 04 04:49:55 PM UTC 24
Peak memory 214292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404848466 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc
ess_b2b.1404848466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1110563236
Short name T841
Test name
Test status
Simulation time 89103279 ps
CPU time 1.24 seconds
Started Sep 04 04:43:49 PM UTC 24
Finished Sep 04 04:43:51 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110563236 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1110563236
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.496388104
Short name T851
Test name
Test status
Simulation time 1255397715 ps
CPU time 53.2 seconds
Started Sep 04 04:43:45 PM UTC 24
Finished Sep 04 04:44:40 PM UTC 24
Peak memory 335696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496388104 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.496388104
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.40863702
Short name T831
Test name
Test status
Simulation time 198447579 ps
CPU time 16.58 seconds
Started Sep 04 04:42:47 PM UTC 24
Finished Sep 04 04:43:05 PM UTC 24
Peak memory 214084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40863702 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.40863702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1650871521
Short name T939
Test name
Test status
Simulation time 20124061204 ps
CPU time 2301.54 seconds
Started Sep 04 04:44:08 PM UTC 24
Finished Sep 04 05:22:54 PM UTC 24
Peak memory 388648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165087152
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.1650871521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2204576023
Short name T868
Test name
Test status
Simulation time 1269935076 ps
CPU time 106.37 seconds
Started Sep 04 04:44:06 PM UTC 24
Finished Sep 04 04:45:54 PM UTC 24
Peak memory 348004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204576023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2204576023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3636756171
Short name T867
Test name
Test status
Simulation time 1872196409 ps
CPU time 164.97 seconds
Started Sep 04 04:43:06 PM UTC 24
Finished Sep 04 04:45:54 PM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636756171 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.3636756171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1651119121
Short name T860
Test name
Test status
Simulation time 617986490 ps
CPU time 106.6 seconds
Started Sep 04 04:43:32 PM UTC 24
Finished Sep 04 04:45:21 PM UTC 24
Peak memory 380912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1651119121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t
hroughput_w_partial_write.1651119121
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3277688473
Short name T919
Test name
Test status
Simulation time 7486971911 ps
CPU time 682.71 seconds
Started Sep 04 04:44:56 PM UTC 24
Finished Sep 04 04:56:27 PM UTC 24
Peak memory 382884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277688473 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during
_key_req.3277688473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1850097871
Short name T865
Test name
Test status
Simulation time 20559596 ps
CPU time 0.88 seconds
Started Sep 04 04:45:40 PM UTC 24
Finished Sep 04 04:45:42 PM UTC 24
Peak memory 212816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850097871 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1850097871
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.2975859387
Short name T857
Test name
Test status
Simulation time 579846761 ps
CPU time 46.49 seconds
Started Sep 04 04:44:17 PM UTC 24
Finished Sep 04 04:45:05 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975859387 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.2975859387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.121116659
Short name T890
Test name
Test status
Simulation time 1473474348 ps
CPU time 183.31 seconds
Started Sep 04 04:45:00 PM UTC 24
Finished Sep 04 04:48:06 PM UTC 24
Peak memory 344048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121116659 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.121116659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3651402753
Short name T856
Test name
Test status
Simulation time 295310583 ps
CPU time 4.62 seconds
Started Sep 04 04:44:54 PM UTC 24
Finished Sep 04 04:44:59 PM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651402753 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.3651402753
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.980972282
Short name T858
Test name
Test status
Simulation time 391689802 ps
CPU time 21.42 seconds
Started Sep 04 04:44:50 PM UTC 24
Finished Sep 04 04:45:13 PM UTC 24
Peak memory 296752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9
80972282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max
_throughput.980972282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1298453409
Short name T861
Test name
Test status
Simulation time 418507171 ps
CPU time 7.38 seconds
Started Sep 04 04:45:21 PM UTC 24
Finished Sep 04 04:45:30 PM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298453409 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.1298453409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2702206240
Short name T862
Test name
Test status
Simulation time 675123908 ps
CPU time 15.01 seconds
Started Sep 04 04:45:17 PM UTC 24
Finished Sep 04 04:45:34 PM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702206240 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.2702206240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.615784760
Short name T918
Test name
Test status
Simulation time 17043661289 ps
CPU time 688.39 seconds
Started Sep 04 04:44:14 PM UTC 24
Finished Sep 04 04:55:51 PM UTC 24
Peak memory 382824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615784760 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.615784760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1213233766
Short name T870
Test name
Test status
Simulation time 858522842 ps
CPU time 92.29 seconds
Started Sep 04 04:44:25 PM UTC 24
Finished Sep 04 04:45:59 PM UTC 24
Peak memory 378744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213233766 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.1213233766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.4105656309
Short name T891
Test name
Test status
Simulation time 4900160457 ps
CPU time 214.08 seconds
Started Sep 04 04:44:41 PM UTC 24
Finished Sep 04 04:48:19 PM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105656309 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc
ess_b2b.4105656309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3350364235
Short name T859
Test name
Test status
Simulation time 42499406 ps
CPU time 0.9 seconds
Started Sep 04 04:45:14 PM UTC 24
Finished Sep 04 04:45:16 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350364235 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3350364235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.57649035
Short name T934
Test name
Test status
Simulation time 69392000904 ps
CPU time 1143.88 seconds
Started Sep 04 04:45:07 PM UTC 24
Finished Sep 04 05:04:23 PM UTC 24
Peak memory 382832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57649035 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.57649035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.868924279
Short name T855
Test name
Test status
Simulation time 900047056 ps
CPU time 42.15 seconds
Started Sep 04 04:44:11 PM UTC 24
Finished Sep 04 04:44:55 PM UTC 24
Peak memory 323392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868924279 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.868924279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.533515515
Short name T931
Test name
Test status
Simulation time 12579191454 ps
CPU time 1026.62 seconds
Started Sep 04 04:45:35 PM UTC 24
Finished Sep 04 05:02:54 PM UTC 24
Peak memory 387000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533515515
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.533515515
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2901110619
Short name T887
Test name
Test status
Simulation time 780705184 ps
CPU time 105.17 seconds
Started Sep 04 04:45:30 PM UTC 24
Finished Sep 04 04:47:18 PM UTC 24
Peak memory 368812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901110619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2901110619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3054608250
Short name T893
Test name
Test status
Simulation time 9161613565 ps
CPU time 282.79 seconds
Started Sep 04 04:44:23 PM UTC 24
Finished Sep 04 04:49:10 PM UTC 24
Peak memory 214220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054608250 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.3054608250
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2394092087
Short name T869
Test name
Test status
Simulation time 295508200 ps
CPU time 59.5 seconds
Started Sep 04 04:44:54 PM UTC 24
Finished Sep 04 04:45:55 PM UTC 24
Peak memory 368496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2394092087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t
hroughput_w_partial_write.2394092087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1764382531
Short name T933
Test name
Test status
Simulation time 4827434154 ps
CPU time 1011.46 seconds
Started Sep 04 04:46:06 PM UTC 24
Finished Sep 04 05:03:09 PM UTC 24
Peak memory 384932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764382531 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during
_key_req.1764382531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2244195454
Short name T882
Test name
Test status
Simulation time 14993555 ps
CPU time 0.91 seconds
Started Sep 04 04:46:28 PM UTC 24
Finished Sep 04 04:46:30 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244195454 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2244195454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.4225654113
Short name T883
Test name
Test status
Simulation time 3442083655 ps
CPU time 50.65 seconds
Started Sep 04 04:45:44 PM UTC 24
Finished Sep 04 04:46:36 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225654113 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.4225654113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.2016438894
Short name T937
Test name
Test status
Simulation time 123526076589 ps
CPU time 1691.8 seconds
Started Sep 04 04:46:13 PM UTC 24
Finished Sep 04 05:14:44 PM UTC 24
Peak memory 387100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016438894 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.2016438894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.33334037
Short name T874
Test name
Test status
Simulation time 1719341134 ps
CPU time 8.13 seconds
Started Sep 04 04:46:03 PM UTC 24
Finished Sep 04 04:46:12 PM UTC 24
Peak memory 214144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33334037 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.33334037
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.941501376
Short name T884
Test name
Test status
Simulation time 423404994 ps
CPU time 46.42 seconds
Started Sep 04 04:46:00 PM UTC 24
Finished Sep 04 04:46:47 PM UTC 24
Peak memory 338040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9
41501376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_max
_throughput.941501376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2970586867
Short name T880
Test name
Test status
Simulation time 597320712 ps
CPU time 6.88 seconds
Started Sep 04 04:46:18 PM UTC 24
Finished Sep 04 04:46:26 PM UTC 24
Peak memory 223968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970586867 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.2970586867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3618644772
Short name T881
Test name
Test status
Simulation time 487207715 ps
CPU time 7.62 seconds
Started Sep 04 04:46:18 PM UTC 24
Finished Sep 04 04:46:27 PM UTC 24
Peak memory 224420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618644772 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.3618644772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4036817459
Short name T894
Test name
Test status
Simulation time 3197407070 ps
CPU time 235.16 seconds
Started Sep 04 04:45:44 PM UTC 24
Finished Sep 04 04:49:42 PM UTC 24
Peak memory 379052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036817459 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.4036817459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.345686860
Short name T873
Test name
Test status
Simulation time 1169086010 ps
CPU time 7.72 seconds
Started Sep 04 04:45:56 PM UTC 24
Finished Sep 04 04:46:05 PM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345686860 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.345686860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1122952237
Short name T910
Test name
Test status
Simulation time 5054343598 ps
CPU time 445.37 seconds
Started Sep 04 04:45:56 PM UTC 24
Finished Sep 04 04:53:27 PM UTC 24
Peak memory 213808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122952237 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc
ess_b2b.1122952237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.822329800
Short name T877
Test name
Test status
Simulation time 51265985 ps
CPU time 1.03 seconds
Started Sep 04 04:46:15 PM UTC 24
Finished Sep 04 04:46:17 PM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822329800 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.822329800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.967924189
Short name T927
Test name
Test status
Simulation time 34829671573 ps
CPU time 801.92 seconds
Started Sep 04 04:46:15 PM UTC 24
Finished Sep 04 04:59:45 PM UTC 24
Peak memory 384900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967924189 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.967924189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.4121283478
Short name T871
Test name
Test status
Simulation time 1251743638 ps
CPU time 17.38 seconds
Started Sep 04 04:45:41 PM UTC 24
Finished Sep 04 04:46:00 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121283478 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.4121283478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.4044147979
Short name T945
Test name
Test status
Simulation time 280758013253 ps
CPU time 5517.76 seconds
Started Sep 04 04:46:28 PM UTC 24
Finished Sep 04 06:19:25 PM UTC 24
Peak memory 388668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404414797
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.4044147979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.889439619
Short name T888
Test name
Test status
Simulation time 1539237188 ps
CPU time 71.49 seconds
Started Sep 04 04:46:25 PM UTC 24
Finished Sep 04 04:47:39 PM UTC 24
Peak memory 315316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889439619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.889439619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.4266115325
Short name T901
Test name
Test status
Simulation time 3226803794 ps
CPU time 307.94 seconds
Started Sep 04 04:45:55 PM UTC 24
Finished Sep 04 04:51:07 PM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266115325 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.4266115325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.56081260
Short name T876
Test name
Test status
Simulation time 165997963 ps
CPU time 12.31 seconds
Started Sep 04 04:46:01 PM UTC 24
Finished Sep 04 04:46:14 PM UTC 24
Peak memory 280352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
56081260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_thr
oughput_w_partial_write.56081260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1178735889
Short name T241
Test name
Test status
Simulation time 13773899721 ps
CPU time 649.95 seconds
Started Sep 04 03:37:57 PM UTC 24
Finished Sep 04 03:48:54 PM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178735889 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_
key_req.1178735889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2652701962
Short name T167
Test name
Test status
Simulation time 23864948 ps
CPU time 0.94 seconds
Started Sep 04 03:38:46 PM UTC 24
Finished Sep 04 03:38:48 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652701962 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2652701962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2159573749
Short name T165
Test name
Test status
Simulation time 12017327450 ps
CPU time 69.97 seconds
Started Sep 04 03:37:21 PM UTC 24
Finished Sep 04 03:38:33 PM UTC 24
Peak memory 214232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159573749 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2159573749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.2516816711
Short name T310
Test name
Test status
Simulation time 31299656353 ps
CPU time 1057.48 seconds
Started Sep 04 03:38:02 PM UTC 24
Finished Sep 04 03:55:51 PM UTC 24
Peak memory 380840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516816711 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.2516816711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2485133333
Short name T118
Test name
Test status
Simulation time 968367546 ps
CPU time 8.87 seconds
Started Sep 04 03:37:53 PM UTC 24
Finished Sep 04 03:38:03 PM UTC 24
Peak memory 213792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485133333 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.2485133333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3968103645
Short name T162
Test name
Test status
Simulation time 522984321 ps
CPU time 14.15 seconds
Started Sep 04 03:37:37 PM UTC 24
Finished Sep 04 03:37:52 PM UTC 24
Peak memory 284520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
968103645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max
_throughput.3968103645
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1687975460
Short name T74
Test name
Test status
Simulation time 93618246 ps
CPU time 4.82 seconds
Started Sep 04 03:38:34 PM UTC 24
Finished Sep 04 03:38:40 PM UTC 24
Peak memory 224020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687975460 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1687975460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.928736833
Short name T166
Test name
Test status
Simulation time 215816561 ps
CPU time 12.56 seconds
Started Sep 04 03:38:30 PM UTC 24
Finished Sep 04 03:38:45 PM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928736833 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.928736833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1854969493
Short name T221
Test name
Test status
Simulation time 5646215595 ps
CPU time 527.16 seconds
Started Sep 04 03:37:20 PM UTC 24
Finished Sep 04 03:46:14 PM UTC 24
Peak memory 376748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854969493 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.1854969493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3263801073
Short name T163
Test name
Test status
Simulation time 745192123 ps
CPU time 21.93 seconds
Started Sep 04 03:37:32 PM UTC 24
Finished Sep 04 03:37:56 PM UTC 24
Peak memory 213804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263801073 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.3263801073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2413150412
Short name T207
Test name
Test status
Simulation time 17484885793 ps
CPU time 398.56 seconds
Started Sep 04 03:37:34 PM UTC 24
Finished Sep 04 03:44:19 PM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413150412 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce
ss_b2b.2413150412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.370947844
Short name T152
Test name
Test status
Simulation time 43629775 ps
CPU time 1.23 seconds
Started Sep 04 03:38:27 PM UTC 24
Finished Sep 04 03:38:29 PM UTC 24
Peak memory 212640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370947844 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.370947844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.2009575363
Short name T160
Test name
Test status
Simulation time 31488698 ps
CPU time 1.43 seconds
Started Sep 04 03:37:18 PM UTC 24
Finished Sep 04 03:37:21 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009575363 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2009575363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3531668307
Short name T482
Test name
Test status
Simulation time 9805277496 ps
CPU time 1962.65 seconds
Started Sep 04 03:38:46 PM UTC 24
Finished Sep 04 04:11:50 PM UTC 24
Peak memory 386668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353166830
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.3531668307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3195068623
Short name T19
Test name
Test status
Simulation time 952697534 ps
CPU time 232.7 seconds
Started Sep 04 03:38:41 PM UTC 24
Finished Sep 04 03:42:38 PM UTC 24
Peak memory 346036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195068623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3195068623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.214743990
Short name T201
Test name
Test status
Simulation time 11001974658 ps
CPU time 370 seconds
Started Sep 04 03:37:30 PM UTC 24
Finished Sep 04 03:43:46 PM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214743990 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.214743990
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3080552475
Short name T169
Test name
Test status
Simulation time 531050050 ps
CPU time 75.82 seconds
Started Sep 04 03:37:46 PM UTC 24
Finished Sep 04 03:39:03 PM UTC 24
Peak memory 358128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3080552475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th
roughput_w_partial_write.3080552475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3460748197
Short name T334
Test name
Test status
Simulation time 3401343753 ps
CPU time 1110.4 seconds
Started Sep 04 03:39:50 PM UTC 24
Finished Sep 04 03:58:32 PM UTC 24
Peak memory 385196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460748197 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_
key_req.3460748197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1281966215
Short name T177
Test name
Test status
Simulation time 44415815 ps
CPU time 1.04 seconds
Started Sep 04 03:40:24 PM UTC 24
Finished Sep 04 03:40:26 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281966215 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1281966215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.3503670572
Short name T174
Test name
Test status
Simulation time 4792577957 ps
CPU time 75.65 seconds
Started Sep 04 03:38:59 PM UTC 24
Finished Sep 04 03:40:16 PM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503670572 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.3503670572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.113552389
Short name T134
Test name
Test status
Simulation time 2219456992 ps
CPU time 25.99 seconds
Started Sep 04 03:39:57 PM UTC 24
Finished Sep 04 03:40:24 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113552389 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.113552389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3756093356
Short name T172
Test name
Test status
Simulation time 4761451960 ps
CPU time 6.69 seconds
Started Sep 04 03:39:48 PM UTC 24
Finished Sep 04 03:39:55 PM UTC 24
Peak memory 224548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756093356 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.3756093356
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.63008277
Short name T176
Test name
Test status
Simulation time 130282290 ps
CPU time 67.91 seconds
Started Sep 04 03:39:14 PM UTC 24
Finished Sep 04 03:40:24 PM UTC 24
Peak memory 370536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
3008277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_t
hroughput.63008277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3212770279
Short name T75
Test name
Test status
Simulation time 753102668 ps
CPU time 8.12 seconds
Started Sep 04 03:40:17 PM UTC 24
Finished Sep 04 03:40:26 PM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212770279 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.3212770279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1192198112
Short name T175
Test name
Test status
Simulation time 1566332644 ps
CPU time 10.57 seconds
Started Sep 04 03:40:09 PM UTC 24
Finished Sep 04 03:40:21 PM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192198112 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.1192198112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.56453132
Short name T345
Test name
Test status
Simulation time 41878917706 ps
CPU time 1205.68 seconds
Started Sep 04 03:38:55 PM UTC 24
Finished Sep 04 03:59:13 PM UTC 24
Peak memory 386988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56453132 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.56453132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2448258874
Short name T146
Test name
Test status
Simulation time 1252960170 ps
CPU time 76.56 seconds
Started Sep 04 03:39:07 PM UTC 24
Finished Sep 04 03:40:25 PM UTC 24
Peak memory 380708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448258874 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.2448258874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2481145256
Short name T145
Test name
Test status
Simulation time 58386893358 ps
CPU time 465.02 seconds
Started Sep 04 03:39:11 PM UTC 24
Finished Sep 04 03:47:02 PM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481145256 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce
ss_b2b.2481145256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1331707188
Short name T173
Test name
Test status
Simulation time 79645315 ps
CPU time 1.07 seconds
Started Sep 04 03:40:06 PM UTC 24
Finished Sep 04 03:40:08 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331707188 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1331707188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3513084474
Short name T141
Test name
Test status
Simulation time 1286556414 ps
CPU time 576.27 seconds
Started Sep 04 03:39:58 PM UTC 24
Finished Sep 04 03:49:41 PM UTC 24
Peak memory 378680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513084474 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3513084474
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3748558788
Short name T168
Test name
Test status
Simulation time 292585418 ps
CPU time 3.86 seconds
Started Sep 04 03:38:49 PM UTC 24
Finished Sep 04 03:38:54 PM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748558788 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3748558788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2424610361
Short name T558
Test name
Test status
Simulation time 155012617462 ps
CPU time 2321.62 seconds
Started Sep 04 03:40:21 PM UTC 24
Finished Sep 04 04:19:27 PM UTC 24
Peak memory 390712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242461036
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.2424610361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3307452551
Short name T55
Test name
Test status
Simulation time 3612567276 ps
CPU time 596.82 seconds
Started Sep 04 03:40:19 PM UTC 24
Finished Sep 04 03:50:23 PM UTC 24
Peak memory 389108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307452551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3307452551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1359802041
Short name T191
Test name
Test status
Simulation time 15691681465 ps
CPU time 226.71 seconds
Started Sep 04 03:39:04 PM UTC 24
Finished Sep 04 03:42:54 PM UTC 24
Peak memory 214052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359802041 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1359802041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2850558798
Short name T171
Test name
Test status
Simulation time 83069808 ps
CPU time 19.18 seconds
Started Sep 04 03:39:28 PM UTC 24
Finished Sep 04 03:39:49 PM UTC 24
Peak memory 272560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2850558798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th
roughput_w_partial_write.2850558798
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3657614385
Short name T316
Test name
Test status
Simulation time 4350905786 ps
CPU time 931.83 seconds
Started Sep 04 03:40:57 PM UTC 24
Finished Sep 04 03:56:39 PM UTC 24
Peak memory 382892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657614385 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_
key_req.3657614385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.166583984
Short name T185
Test name
Test status
Simulation time 40480227 ps
CPU time 0.99 seconds
Started Sep 04 03:41:16 PM UTC 24
Finished Sep 04 03:41:18 PM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166583984 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.166583984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.4043036174
Short name T182
Test name
Test status
Simulation time 15269484462 ps
CPU time 26.7 seconds
Started Sep 04 03:40:27 PM UTC 24
Finished Sep 04 03:40:55 PM UTC 24
Peak memory 213880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043036174 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.4043036174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.1900952443
Short name T427
Test name
Test status
Simulation time 18773040203 ps
CPU time 1494.94 seconds
Started Sep 04 03:40:57 PM UTC 24
Finished Sep 04 04:06:08 PM UTC 24
Peak memory 384904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900952443 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.1900952443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3895145418
Short name T150
Test name
Test status
Simulation time 84942945 ps
CPU time 1.44 seconds
Started Sep 04 03:40:56 PM UTC 24
Finished Sep 04 03:40:59 PM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895145418 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3895145418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3272195677
Short name T180
Test name
Test status
Simulation time 659777022 ps
CPU time 3.87 seconds
Started Sep 04 03:40:40 PM UTC 24
Finished Sep 04 03:40:45 PM UTC 24
Peak memory 231224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
272195677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max
_throughput.3272195677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.755549436
Short name T76
Test name
Test status
Simulation time 235258531 ps
CPU time 5.92 seconds
Started Sep 04 03:41:09 PM UTC 24
Finished Sep 04 03:41:16 PM UTC 24
Peak memory 224060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755549436 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.755549436
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.900033015
Short name T184
Test name
Test status
Simulation time 584310937 ps
CPU time 7.56 seconds
Started Sep 04 03:41:03 PM UTC 24
Finished Sep 04 03:41:11 PM UTC 24
Peak memory 224404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900033015 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.900033015
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.4011618200
Short name T148
Test name
Test status
Simulation time 47209758254 ps
CPU time 760.36 seconds
Started Sep 04 03:40:26 PM UTC 24
Finished Sep 04 03:53:15 PM UTC 24
Peak memory 382820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011618200 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.4011618200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3189486165
Short name T178
Test name
Test status
Simulation time 189905274 ps
CPU time 3.4 seconds
Started Sep 04 03:40:31 PM UTC 24
Finished Sep 04 03:40:35 PM UTC 24
Peak memory 220284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189486165 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.3189486165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1067643305
Short name T237
Test name
Test status
Simulation time 14034418656 ps
CPU time 439.95 seconds
Started Sep 04 03:40:36 PM UTC 24
Finished Sep 04 03:48:02 PM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067643305 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acce
ss_b2b.1067643305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2444674013
Short name T183
Test name
Test status
Simulation time 82823457 ps
CPU time 1.21 seconds
Started Sep 04 03:40:59 PM UTC 24
Finished Sep 04 03:41:02 PM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444674013 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2444674013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.240994719
Short name T366
Test name
Test status
Simulation time 65223066475 ps
CPU time 1179.88 seconds
Started Sep 04 03:40:57 PM UTC 24
Finished Sep 04 04:00:50 PM UTC 24
Peak memory 384956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240994719 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.240994719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2544356243
Short name T179
Test name
Test status
Simulation time 987780500 ps
CPU time 12.45 seconds
Started Sep 04 03:40:25 PM UTC 24
Finished Sep 04 03:40:39 PM UTC 24
Peak memory 249652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544356243 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2544356243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2558167128
Short name T921
Test name
Test status
Simulation time 258515035908 ps
CPU time 4485.85 seconds
Started Sep 04 03:41:13 PM UTC 24
Finished Sep 04 04:56:44 PM UTC 24
Peak memory 388788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255816712
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.2558167128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.741851370
Short name T212
Test name
Test status
Simulation time 50598430134 ps
CPU time 288 seconds
Started Sep 04 03:40:28 PM UTC 24
Finished Sep 04 03:45:20 PM UTC 24
Peak memory 213968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741851370 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.741851370
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2240422827
Short name T181
Test name
Test status
Simulation time 236052663 ps
CPU time 8.23 seconds
Started Sep 04 03:40:46 PM UTC 24
Finished Sep 04 03:40:55 PM UTC 24
Peak memory 249700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2240422827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th
roughput_w_partial_write.2240422827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.4161092383
Short name T281
Test name
Test status
Simulation time 3525361978 ps
CPU time 649.59 seconds
Started Sep 04 03:42:28 PM UTC 24
Finished Sep 04 03:53:26 PM UTC 24
Peak memory 382896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161092383 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_
key_req.4161092383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.573523209
Short name T195
Test name
Test status
Simulation time 60082419 ps
CPU time 0.94 seconds
Started Sep 04 03:43:15 PM UTC 24
Finished Sep 04 03:43:17 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573523209 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.573523209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.1747086761
Short name T193
Test name
Test status
Simulation time 6152231375 ps
CPU time 92.68 seconds
Started Sep 04 03:41:32 PM UTC 24
Finished Sep 04 03:43:07 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747086761 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.1747086761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1396176217
Short name T140
Test name
Test status
Simulation time 29071233866 ps
CPU time 477.4 seconds
Started Sep 04 03:42:38 PM UTC 24
Finished Sep 04 03:50:41 PM UTC 24
Peak memory 380780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396176217 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1396176217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.832407544
Short name T190
Test name
Test status
Simulation time 585049063 ps
CPU time 10.41 seconds
Started Sep 04 03:42:25 PM UTC 24
Finished Sep 04 03:42:37 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832407544 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.832407544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3330954383
Short name T189
Test name
Test status
Simulation time 44657767 ps
CPU time 3.46 seconds
Started Sep 04 03:42:03 PM UTC 24
Finished Sep 04 03:42:08 PM UTC 24
Peak memory 231216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
330954383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max
_throughput.3330954383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.952592684
Short name T45
Test name
Test status
Simulation time 95919180 ps
CPU time 8.01 seconds
Started Sep 04 03:43:08 PM UTC 24
Finished Sep 04 03:43:17 PM UTC 24
Peak memory 224008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952592684 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.952592684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3885172975
Short name T194
Test name
Test status
Simulation time 2355746661 ps
CPU time 15.07 seconds
Started Sep 04 03:42:58 PM UTC 24
Finished Sep 04 03:43:14 PM UTC 24
Peak memory 224208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885172975 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3885172975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2893998706
Short name T196
Test name
Test status
Simulation time 1036971932 ps
CPU time 109.24 seconds
Started Sep 04 03:41:27 PM UTC 24
Finished Sep 04 03:43:19 PM UTC 24
Peak memory 306980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893998706 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.2893998706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2121143465
Short name T188
Test name
Test status
Simulation time 98510676 ps
CPU time 3.5 seconds
Started Sep 04 03:41:53 PM UTC 24
Finished Sep 04 03:41:57 PM UTC 24
Peak memory 213936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121143465 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.2121143465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2486458435
Short name T272
Test name
Test status
Simulation time 24345968023 ps
CPU time 647.86 seconds
Started Sep 04 03:41:58 PM UTC 24
Finished Sep 04 03:52:54 PM UTC 24
Peak memory 213988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486458435 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce
ss_b2b.2486458435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3761780799
Short name T192
Test name
Test status
Simulation time 88385039 ps
CPU time 1.2 seconds
Started Sep 04 03:42:55 PM UTC 24
Finished Sep 04 03:42:57 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761780799 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3761780799
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3687355564
Short name T20
Test name
Test status
Simulation time 3012175772 ps
CPU time 30.05 seconds
Started Sep 04 03:42:39 PM UTC 24
Finished Sep 04 03:43:10 PM UTC 24
Peak memory 274348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687355564 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3687355564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1554417029
Short name T187
Test name
Test status
Simulation time 2893778775 ps
CPU time 19.11 seconds
Started Sep 04 03:41:19 PM UTC 24
Finished Sep 04 03:41:39 PM UTC 24
Peak memory 214208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554417029 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1554417029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1854104506
Short name T702
Test name
Test status
Simulation time 146430232641 ps
CPU time 2853.96 seconds
Started Sep 04 03:43:15 PM UTC 24
Finished Sep 04 04:31:18 PM UTC 24
Peak memory 384624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185410450
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.1854104506
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3294961932
Short name T54
Test name
Test status
Simulation time 417606768 ps
CPU time 20.77 seconds
Started Sep 04 03:43:11 PM UTC 24
Finished Sep 04 03:43:33 PM UTC 24
Peak memory 224116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294961932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3294961932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1253139933
Short name T209
Test name
Test status
Simulation time 2058068609 ps
CPU time 183.3 seconds
Started Sep 04 03:41:41 PM UTC 24
Finished Sep 04 03:44:47 PM UTC 24
Peak memory 214192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253139933 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.1253139933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1350742875
Short name T197
Test name
Test status
Simulation time 151140093 ps
CPU time 77.89 seconds
Started Sep 04 03:42:08 PM UTC 24
Finished Sep 04 03:43:28 PM UTC 24
Peak memory 374640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1350742875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th
roughput_w_partial_write.1350742875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.7446695
Short name T239
Test name
Test status
Simulation time 1972172399 ps
CPU time 293.77 seconds
Started Sep 04 03:43:46 PM UTC 24
Finished Sep 04 03:48:44 PM UTC 24
Peak memory 376612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7446695 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_key_req.7446695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2884218999
Short name T208
Test name
Test status
Simulation time 48589227 ps
CPU time 0.91 seconds
Started Sep 04 03:44:40 PM UTC 24
Finished Sep 04 03:44:42 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884218999 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2884218999
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.742963595
Short name T199
Test name
Test status
Simulation time 953590218 ps
CPU time 18.37 seconds
Started Sep 04 03:43:21 PM UTC 24
Finished Sep 04 03:43:40 PM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742963595 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.742963595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.155022162
Short name T143
Test name
Test status
Simulation time 49597831266 ps
CPU time 699.54 seconds
Started Sep 04 03:43:47 PM UTC 24
Finished Sep 04 03:55:35 PM UTC 24
Peak memory 354220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155022162 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.155022162
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1119075826
Short name T203
Test name
Test status
Simulation time 291866711 ps
CPU time 3.68 seconds
Started Sep 04 03:43:43 PM UTC 24
Finished Sep 04 03:43:48 PM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119075826 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.1119075826
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1297242912
Short name T202
Test name
Test status
Simulation time 76070296 ps
CPU time 11.88 seconds
Started Sep 04 03:43:34 PM UTC 24
Finished Sep 04 03:43:47 PM UTC 24
Peak memory 272232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
297242912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max
_throughput.1297242912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1497484502
Short name T206
Test name
Test status
Simulation time 342167905 ps
CPU time 3.88 seconds
Started Sep 04 03:44:03 PM UTC 24
Finished Sep 04 03:44:07 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497484502 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.1497484502
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.247958707
Short name T205
Test name
Test status
Simulation time 1341241540 ps
CPU time 9.17 seconds
Started Sep 04 03:43:51 PM UTC 24
Finished Sep 04 03:44:02 PM UTC 24
Peak memory 213880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247958707 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.247958707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3264254007
Short name T329
Test name
Test status
Simulation time 15958588561 ps
CPU time 884.11 seconds
Started Sep 04 03:43:18 PM UTC 24
Finished Sep 04 03:58:12 PM UTC 24
Peak memory 376620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264254007 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3264254007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.195810168
Short name T211
Test name
Test status
Simulation time 236024825 ps
CPU time 104.43 seconds
Started Sep 04 03:43:29 PM UTC 24
Finished Sep 04 03:45:16 PM UTC 24
Peak memory 378664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195810168 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.195810168
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2264272116
Short name T240
Test name
Test status
Simulation time 3897773701 ps
CPU time 316.74 seconds
Started Sep 04 03:43:32 PM UTC 24
Finished Sep 04 03:48:53 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264272116 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acce
ss_b2b.2264272116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.4010956509
Short name T204
Test name
Test status
Simulation time 116001035 ps
CPU time 1.03 seconds
Started Sep 04 03:43:48 PM UTC 24
Finished Sep 04 03:43:50 PM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010956509 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.4010956509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4084236883
Short name T284
Test name
Test status
Simulation time 1521308965 ps
CPU time 580.32 seconds
Started Sep 04 03:43:48 PM UTC 24
Finished Sep 04 03:53:36 PM UTC 24
Peak memory 381040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084236883 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.4084236883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.835317291
Short name T198
Test name
Test status
Simulation time 561367229 ps
CPU time 11.06 seconds
Started Sep 04 03:43:18 PM UTC 24
Finished Sep 04 03:43:31 PM UTC 24
Peak memory 214200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835317291 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.835317291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2221139529
Short name T612
Test name
Test status
Simulation time 10015903593 ps
CPU time 2316.14 seconds
Started Sep 04 03:44:20 PM UTC 24
Finished Sep 04 04:23:21 PM UTC 24
Peak memory 398960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222113952
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.2221139529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3883721882
Short name T42
Test name
Test status
Simulation time 5093865470 ps
CPU time 140.76 seconds
Started Sep 04 03:44:09 PM UTC 24
Finished Sep 04 03:46:32 PM UTC 24
Peak memory 334128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883721882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3883721882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3108014346
Short name T254
Test name
Test status
Simulation time 3496241621 ps
CPU time 428.19 seconds
Started Sep 04 03:43:27 PM UTC 24
Finished Sep 04 03:50:41 PM UTC 24
Peak memory 214004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108014346 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.3108014346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3112537228
Short name T200
Test name
Test status
Simulation time 185407774 ps
CPU time 1.79 seconds
Started Sep 04 03:43:43 PM UTC 24
Finished Sep 04 03:43:46 PM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3112537228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th
roughput_w_partial_write.3112537228
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%