| T799 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.3364505589 |
|
|
Sep 04 04:39:47 PM UTC 24 |
Sep 04 04:39:52 PM UTC 24 |
89789113 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.226013957 |
|
|
Sep 04 03:59:54 PM UTC 24 |
Sep 04 04:39:57 PM UTC 24 |
42767248689 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1622881362 |
|
|
Sep 04 03:47:52 PM UTC 24 |
Sep 04 04:40:00 PM UTC 24 |
42413025974 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2956607937 |
|
|
Sep 04 04:39:58 PM UTC 24 |
Sep 04 04:40:04 PM UTC 24 |
104229466 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.395701433 |
|
|
Sep 04 04:39:01 PM UTC 24 |
Sep 04 04:40:05 PM UTC 24 |
130207706 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1638264206 |
|
|
Sep 04 04:40:02 PM UTC 24 |
Sep 04 04:40:12 PM UTC 24 |
636034647 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1555310835 |
|
|
Sep 04 04:36:24 PM UTC 24 |
Sep 04 04:40:19 PM UTC 24 |
1442140044 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.207080517 |
|
|
Sep 04 04:40:21 PM UTC 24 |
Sep 04 04:40:23 PM UTC 24 |
33232672 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.1643244835 |
|
|
Sep 04 04:39:39 PM UTC 24 |
Sep 04 04:40:30 PM UTC 24 |
6699983493 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.64866030 |
|
|
Sep 04 04:39:53 PM UTC 24 |
Sep 04 04:40:32 PM UTC 24 |
183930521 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.258463487 |
|
|
Sep 04 04:40:31 PM UTC 24 |
Sep 04 04:40:36 PM UTC 24 |
182147890 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.1479275768 |
|
|
Sep 04 04:27:48 PM UTC 24 |
Sep 04 04:40:40 PM UTC 24 |
13060332588 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1086344511 |
|
|
Sep 04 04:40:24 PM UTC 24 |
Sep 04 04:40:42 PM UTC 24 |
5166066300 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.596346261 |
|
|
Sep 04 04:40:41 PM UTC 24 |
Sep 04 04:40:43 PM UTC 24 |
23437981 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3284407306 |
|
|
Sep 04 04:35:00 PM UTC 24 |
Sep 04 04:40:48 PM UTC 24 |
3766263227 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.4136376756 |
|
|
Sep 04 04:06:06 PM UTC 24 |
Sep 04 04:40:56 PM UTC 24 |
64624075857 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2660277791 |
|
|
Sep 04 04:40:43 PM UTC 24 |
Sep 04 04:41:03 PM UTC 24 |
784569052 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3655581252 |
|
|
Sep 04 04:41:04 PM UTC 24 |
Sep 04 04:41:08 PM UTC 24 |
311949954 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.656673770 |
|
|
Sep 04 04:41:25 PM UTC 24 |
Sep 04 04:41:28 PM UTC 24 |
64234614 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3405739842 |
|
|
Sep 04 04:36:30 PM UTC 24 |
Sep 04 04:41:36 PM UTC 24 |
4166332958 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.3651466585 |
|
|
Sep 04 04:41:37 PM UTC 24 |
Sep 04 04:41:43 PM UTC 24 |
790477829 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1191577970 |
|
|
Sep 04 04:29:44 PM UTC 24 |
Sep 04 04:41:44 PM UTC 24 |
8493606008 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2624778827 |
|
|
Sep 04 04:32:07 PM UTC 24 |
Sep 04 04:42:02 PM UTC 24 |
24668727718 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.802857938 |
|
|
Sep 04 04:41:29 PM UTC 24 |
Sep 04 04:42:23 PM UTC 24 |
481740510 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2859676351 |
|
|
Sep 04 04:42:24 PM UTC 24 |
Sep 04 04:42:26 PM UTC 24 |
69815087 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3701665114 |
|
|
Sep 04 04:40:33 PM UTC 24 |
Sep 04 04:42:28 PM UTC 24 |
10888838383 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2818660576 |
|
|
Sep 04 04:32:19 PM UTC 24 |
Sep 04 04:42:36 PM UTC 24 |
2200917530 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3107592540 |
|
|
Sep 04 04:42:28 PM UTC 24 |
Sep 04 04:42:36 PM UTC 24 |
93838642 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2364261957 |
|
|
Sep 04 04:42:27 PM UTC 24 |
Sep 04 04:42:45 PM UTC 24 |
683605221 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.2531134534 |
|
|
Sep 04 04:25:45 PM UTC 24 |
Sep 04 04:42:46 PM UTC 24 |
2774684950 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4234607730 |
|
|
Sep 04 04:42:46 PM UTC 24 |
Sep 04 04:42:48 PM UTC 24 |
24508403 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.1117084872 |
|
|
Sep 04 04:40:49 PM UTC 24 |
Sep 04 04:42:50 PM UTC 24 |
5734200690 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.40863702 |
|
|
Sep 04 04:42:47 PM UTC 24 |
Sep 04 04:43:05 PM UTC 24 |
198447579 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.4280540546 |
|
|
Sep 04 04:35:45 PM UTC 24 |
Sep 04 04:43:19 PM UTC 24 |
4416793661 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.424675127 |
|
|
Sep 04 04:31:09 PM UTC 24 |
Sep 04 04:43:21 PM UTC 24 |
3194701885 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.1291951102 |
|
|
Sep 04 04:27:43 PM UTC 24 |
Sep 04 04:43:24 PM UTC 24 |
16473323946 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.1600393499 |
|
|
Sep 04 04:42:52 PM UTC 24 |
Sep 04 04:43:31 PM UTC 24 |
6698227829 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1348768648 |
|
|
Sep 04 04:39:42 PM UTC 24 |
Sep 04 04:43:38 PM UTC 24 |
5644183111 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.4079957422 |
|
|
Sep 04 04:43:21 PM UTC 24 |
Sep 04 04:43:41 PM UTC 24 |
1170831715 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.806504775 |
|
|
Sep 04 04:43:26 PM UTC 24 |
Sep 04 04:43:42 PM UTC 24 |
182548690 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3592226945 |
|
|
Sep 04 04:43:39 PM UTC 24 |
Sep 04 04:43:44 PM UTC 24 |
418658919 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2513844202 |
|
|
Sep 04 04:31:54 PM UTC 24 |
Sep 04 04:43:48 PM UTC 24 |
18889585645 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1110563236 |
|
|
Sep 04 04:43:49 PM UTC 24 |
Sep 04 04:43:51 PM UTC 24 |
89103279 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3366084683 |
|
|
Sep 04 04:37:04 PM UTC 24 |
Sep 04 04:43:58 PM UTC 24 |
18536847334 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2879139202 |
|
|
Sep 04 04:43:52 PM UTC 24 |
Sep 04 04:44:04 PM UTC 24 |
541214202 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.4223689804 |
|
|
Sep 04 04:43:59 PM UTC 24 |
Sep 04 04:44:07 PM UTC 24 |
370334973 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2910054062 |
|
|
Sep 04 04:38:43 PM UTC 24 |
Sep 04 04:44:09 PM UTC 24 |
3484786336 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3642072393 |
|
|
Sep 04 04:35:56 PM UTC 24 |
Sep 04 04:44:11 PM UTC 24 |
40548410112 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3203466777 |
|
|
Sep 04 04:44:10 PM UTC 24 |
Sep 04 04:44:12 PM UTC 24 |
40622573 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2252953983 |
|
|
Sep 04 04:39:36 PM UTC 24 |
Sep 04 04:44:16 PM UTC 24 |
3574250802 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.414935054 |
|
|
Sep 04 03:57:23 PM UTC 24 |
Sep 04 04:44:22 PM UTC 24 |
161762435998 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.2265320825 |
|
|
Sep 04 04:39:07 PM UTC 24 |
Sep 04 04:44:24 PM UTC 24 |
35859075791 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.496388104 |
|
|
Sep 04 04:43:45 PM UTC 24 |
Sep 04 04:44:40 PM UTC 24 |
1255397715 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.897193501 |
|
|
Sep 04 04:30:32 PM UTC 24 |
Sep 04 04:44:49 PM UTC 24 |
70585338170 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1136379889 |
|
|
Sep 04 04:29:41 PM UTC 24 |
Sep 04 04:44:53 PM UTC 24 |
15659316915 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3223679975 |
|
|
Sep 04 04:31:05 PM UTC 24 |
Sep 04 04:44:53 PM UTC 24 |
43286671212 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.868924279 |
|
|
Sep 04 04:44:11 PM UTC 24 |
Sep 04 04:44:55 PM UTC 24 |
900047056 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3651402753 |
|
|
Sep 04 04:44:54 PM UTC 24 |
Sep 04 04:44:59 PM UTC 24 |
295310583 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.2975859387 |
|
|
Sep 04 04:44:17 PM UTC 24 |
Sep 04 04:45:05 PM UTC 24 |
579846761 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.980972282 |
|
|
Sep 04 04:44:50 PM UTC 24 |
Sep 04 04:45:13 PM UTC 24 |
391689802 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3350364235 |
|
|
Sep 04 04:45:14 PM UTC 24 |
Sep 04 04:45:16 PM UTC 24 |
42499406 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1651119121 |
|
|
Sep 04 04:43:32 PM UTC 24 |
Sep 04 04:45:21 PM UTC 24 |
617986490 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1298453409 |
|
|
Sep 04 04:45:21 PM UTC 24 |
Sep 04 04:45:30 PM UTC 24 |
418507171 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2702206240 |
|
|
Sep 04 04:45:17 PM UTC 24 |
Sep 04 04:45:34 PM UTC 24 |
675123908 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.353663356 |
|
|
Sep 04 04:42:37 PM UTC 24 |
Sep 04 04:45:39 PM UTC 24 |
1973893128 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.2762563262 |
|
|
Sep 04 04:38:52 PM UTC 24 |
Sep 04 04:45:40 PM UTC 24 |
22148093336 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1850097871 |
|
|
Sep 04 04:45:40 PM UTC 24 |
Sep 04 04:45:42 PM UTC 24 |
20559596 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.150443257 |
|
|
Sep 04 04:39:50 PM UTC 24 |
Sep 04 04:45:42 PM UTC 24 |
6719414142 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3636756171 |
|
|
Sep 04 04:43:06 PM UTC 24 |
Sep 04 04:45:54 PM UTC 24 |
1872196409 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2204576023 |
|
|
Sep 04 04:44:06 PM UTC 24 |
Sep 04 04:45:54 PM UTC 24 |
1269935076 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2394092087 |
|
|
Sep 04 04:44:54 PM UTC 24 |
Sep 04 04:45:55 PM UTC 24 |
295508200 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1213233766 |
|
|
Sep 04 04:44:25 PM UTC 24 |
Sep 04 04:45:59 PM UTC 24 |
858522842 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.4121283478 |
|
|
Sep 04 04:45:41 PM UTC 24 |
Sep 04 04:46:00 PM UTC 24 |
1251743638 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3984909287 |
|
|
Sep 04 04:25:40 PM UTC 24 |
Sep 04 04:46:02 PM UTC 24 |
56900678061 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.345686860 |
|
|
Sep 04 04:45:56 PM UTC 24 |
Sep 04 04:46:05 PM UTC 24 |
1169086010 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.33334037 |
|
|
Sep 04 04:46:03 PM UTC 24 |
Sep 04 04:46:12 PM UTC 24 |
1719341134 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3290578263 |
|
|
Sep 04 04:40:13 PM UTC 24 |
Sep 04 04:46:14 PM UTC 24 |
1776326489 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.56081260 |
|
|
Sep 04 04:46:01 PM UTC 24 |
Sep 04 04:46:14 PM UTC 24 |
165997963 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.822329800 |
|
|
Sep 04 04:46:15 PM UTC 24 |
Sep 04 04:46:17 PM UTC 24 |
51265985 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.628618924 |
|
|
Sep 04 04:38:00 PM UTC 24 |
Sep 04 04:46:17 PM UTC 24 |
57867704369 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2963675912 |
|
|
Sep 04 04:20:54 PM UTC 24 |
Sep 04 04:46:25 PM UTC 24 |
5764155415 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2970586867 |
|
|
Sep 04 04:46:18 PM UTC 24 |
Sep 04 04:46:26 PM UTC 24 |
597320712 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3618644772 |
|
|
Sep 04 04:46:18 PM UTC 24 |
Sep 04 04:46:27 PM UTC 24 |
487207715 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2244195454 |
|
|
Sep 04 04:46:28 PM UTC 24 |
Sep 04 04:46:30 PM UTC 24 |
14993555 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.4225654113 |
|
|
Sep 04 04:45:44 PM UTC 24 |
Sep 04 04:46:36 PM UTC 24 |
3442083655 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.941501376 |
|
|
Sep 04 04:46:00 PM UTC 24 |
Sep 04 04:46:47 PM UTC 24 |
423404994 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2336906589 |
|
|
Sep 04 04:33:18 PM UTC 24 |
Sep 04 04:46:54 PM UTC 24 |
74130476675 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.422941854 |
|
|
Sep 04 04:40:57 PM UTC 24 |
Sep 04 04:47:16 PM UTC 24 |
2893640096 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2901110619 |
|
|
Sep 04 04:45:30 PM UTC 24 |
Sep 04 04:47:18 PM UTC 24 |
780705184 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.889439619 |
|
|
Sep 04 04:46:25 PM UTC 24 |
Sep 04 04:47:39 PM UTC 24 |
1539237188 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.502557115 |
|
|
Sep 04 04:26:02 PM UTC 24 |
Sep 04 04:47:59 PM UTC 24 |
19448000433 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.121116659 |
|
|
Sep 04 04:45:00 PM UTC 24 |
Sep 04 04:48:06 PM UTC 24 |
1473474348 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.4105656309 |
|
|
Sep 04 04:44:41 PM UTC 24 |
Sep 04 04:48:19 PM UTC 24 |
4900160457 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3784272935 |
|
|
Sep 04 04:38:21 PM UTC 24 |
Sep 04 04:48:58 PM UTC 24 |
28463231679 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3054608250 |
|
|
Sep 04 04:44:23 PM UTC 24 |
Sep 04 04:49:10 PM UTC 24 |
9161613565 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4036817459 |
|
|
Sep 04 04:45:44 PM UTC 24 |
Sep 04 04:49:42 PM UTC 24 |
3197407070 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3194790921 |
|
|
Sep 04 04:41:45 PM UTC 24 |
Sep 04 04:49:51 PM UTC 24 |
4596800674 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1404848466 |
|
|
Sep 04 04:43:22 PM UTC 24 |
Sep 04 04:49:55 PM UTC 24 |
15519584241 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.2627113321 |
|
|
Sep 04 04:39:07 PM UTC 24 |
Sep 04 04:50:21 PM UTC 24 |
16617373675 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1236725043 |
|
|
Sep 04 04:41:43 PM UTC 24 |
Sep 04 04:50:36 PM UTC 24 |
7057282858 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.980454072 |
|
|
Sep 04 04:34:36 PM UTC 24 |
Sep 04 04:50:46 PM UTC 24 |
13081126242 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2727002186 |
|
|
Sep 04 04:40:44 PM UTC 24 |
Sep 04 04:51:03 PM UTC 24 |
9283494281 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.4266115325 |
|
|
Sep 04 04:45:55 PM UTC 24 |
Sep 04 04:51:07 PM UTC 24 |
3226803794 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3205568735 |
|
|
Sep 04 04:19:49 PM UTC 24 |
Sep 04 04:51:13 PM UTC 24 |
3782973027 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1633542397 |
|
|
Sep 04 04:41:09 PM UTC 24 |
Sep 04 04:51:35 PM UTC 24 |
49457453992 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.2795655747 |
|
|
Sep 04 04:40:06 PM UTC 24 |
Sep 04 04:51:50 PM UTC 24 |
3291691432 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1346993545 |
|
|
Sep 04 04:28:11 PM UTC 24 |
Sep 04 04:52:04 PM UTC 24 |
20180878970 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.577186279 |
|
|
Sep 04 04:32:24 PM UTC 24 |
Sep 04 04:52:20 PM UTC 24 |
62961862115 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.62389494 |
|
|
Sep 04 03:55:36 PM UTC 24 |
Sep 04 04:52:36 PM UTC 24 |
35717996517 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.144206753 |
|
|
Sep 04 04:01:48 PM UTC 24 |
Sep 04 04:52:49 PM UTC 24 |
184261117152 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2713618447 |
|
|
Sep 04 04:39:05 PM UTC 24 |
Sep 04 04:53:26 PM UTC 24 |
3286332578 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1122952237 |
|
|
Sep 04 04:45:56 PM UTC 24 |
Sep 04 04:53:27 PM UTC 24 |
5054343598 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.753144257 |
|
|
Sep 04 04:16:52 PM UTC 24 |
Sep 04 04:54:28 PM UTC 24 |
126128287890 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1202529579 |
|
|
Sep 04 04:34:28 PM UTC 24 |
Sep 04 04:54:29 PM UTC 24 |
18756263979 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2561671 |
|
|
Sep 04 04:32:49 PM UTC 24 |
Sep 04 04:54:43 PM UTC 24 |
51118171577 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2161051672 |
|
|
Sep 04 04:37:33 PM UTC 24 |
Sep 04 04:54:55 PM UTC 24 |
38622353042 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1677904138 |
|
|
Sep 04 04:37:30 PM UTC 24 |
Sep 04 04:55:29 PM UTC 24 |
14992717768 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.1720917058 |
|
|
Sep 04 04:36:11 PM UTC 24 |
Sep 04 04:55:35 PM UTC 24 |
3543997835 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2283470978 |
|
|
Sep 04 04:34:35 PM UTC 24 |
Sep 04 04:55:48 PM UTC 24 |
35528372592 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.615784760 |
|
|
Sep 04 04:44:14 PM UTC 24 |
Sep 04 04:55:51 PM UTC 24 |
17043661289 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3277688473 |
|
|
Sep 04 04:44:56 PM UTC 24 |
Sep 04 04:56:27 PM UTC 24 |
7486971911 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1541989486 |
|
|
Sep 04 04:36:26 PM UTC 24 |
Sep 04 04:56:38 PM UTC 24 |
17547290003 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2558167128 |
|
|
Sep 04 03:41:13 PM UTC 24 |
Sep 04 04:56:44 PM UTC 24 |
258515035908 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.4071628027 |
|
|
Sep 04 04:19:44 PM UTC 24 |
Sep 04 04:57:04 PM UTC 24 |
8666245451 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2546250626 |
|
|
Sep 04 04:40:05 PM UTC 24 |
Sep 04 04:57:06 PM UTC 24 |
3656628006 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.2289012557 |
|
|
Sep 04 04:43:43 PM UTC 24 |
Sep 04 04:57:38 PM UTC 24 |
2624043566 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1571502740 |
|
|
Sep 04 04:28:32 PM UTC 24 |
Sep 04 04:58:00 PM UTC 24 |
269980051153 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3107030824 |
|
|
Sep 04 04:42:49 PM UTC 24 |
Sep 04 04:59:30 PM UTC 24 |
53398886697 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.967924189 |
|
|
Sep 04 04:46:15 PM UTC 24 |
Sep 04 04:59:45 PM UTC 24 |
34829671573 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.4168095606 |
|
|
Sep 04 04:31:29 PM UTC 24 |
Sep 04 05:00:26 PM UTC 24 |
13382725481 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.200290628 |
|
|
Sep 04 04:25:06 PM UTC 24 |
Sep 04 05:01:10 PM UTC 24 |
34975784870 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.136957977 |
|
|
Sep 04 04:43:43 PM UTC 24 |
Sep 04 05:02:47 PM UTC 24 |
15872275839 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.533515515 |
|
|
Sep 04 04:45:35 PM UTC 24 |
Sep 04 05:02:54 PM UTC 24 |
12579191454 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.3220787541 |
|
|
Sep 04 04:42:03 PM UTC 24 |
Sep 04 05:02:57 PM UTC 24 |
16359003819 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1764382531 |
|
|
Sep 04 04:46:06 PM UTC 24 |
Sep 04 05:03:09 PM UTC 24 |
4827434154 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.57649035 |
|
|
Sep 04 04:45:07 PM UTC 24 |
Sep 04 05:04:23 PM UTC 24 |
69392000904 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.652626482 |
|
|
Sep 04 04:04:36 PM UTC 24 |
Sep 04 05:06:30 PM UTC 24 |
330292499826 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3071607968 |
|
|
Sep 04 03:54:15 PM UTC 24 |
Sep 04 05:10:25 PM UTC 24 |
507006435927 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.2016438894 |
|
|
Sep 04 04:46:13 PM UTC 24 |
Sep 04 05:14:44 PM UTC 24 |
123526076589 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2158024742 |
|
|
Sep 04 04:34:51 PM UTC 24 |
Sep 04 05:16:43 PM UTC 24 |
33139176319 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1650871521 |
|
|
Sep 04 04:44:08 PM UTC 24 |
Sep 04 05:22:54 PM UTC 24 |
20124061204 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3052841652 |
|
|
Sep 04 04:40:36 PM UTC 24 |
Sep 04 05:23:31 PM UTC 24 |
117128136504 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1762513465 |
|
|
Sep 04 04:30:09 PM UTC 24 |
Sep 04 05:25:17 PM UTC 24 |
89413349648 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.574883523 |
|
|
Sep 04 04:42:37 PM UTC 24 |
Sep 04 05:27:25 PM UTC 24 |
147258138833 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2545933002 |
|
|
Sep 04 04:39:27 PM UTC 24 |
Sep 04 05:37:34 PM UTC 24 |
38835143197 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.226943558 |
|
|
Sep 04 04:22:32 PM UTC 24 |
Sep 04 06:01:47 PM UTC 24 |
347385719955 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.4044147979 |
|
|
Sep 04 04:46:28 PM UTC 24 |
Sep 04 06:19:25 PM UTC 24 |
280758013253 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3522951481 |
|
|
Sep 04 03:30:05 PM UTC 24 |
Sep 04 03:30:10 PM UTC 24 |
208045168 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3479560424 |
|
|
Sep 04 03:30:09 PM UTC 24 |
Sep 04 03:30:11 PM UTC 24 |
44956711 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2330384112 |
|
|
Sep 04 03:30:05 PM UTC 24 |
Sep 04 03:30:11 PM UTC 24 |
1669278580 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.141032776 |
|
|
Sep 04 03:30:07 PM UTC 24 |
Sep 04 03:30:11 PM UTC 24 |
350156643 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3386664042 |
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|
Sep 04 03:30:10 PM UTC 24 |
Sep 04 03:30:12 PM UTC 24 |
14814965 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3679596461 |
|
|
Sep 04 03:30:11 PM UTC 24 |
Sep 04 03:30:13 PM UTC 24 |
34608283 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3499025986 |
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|
Sep 04 03:30:12 PM UTC 24 |
Sep 04 03:30:14 PM UTC 24 |
15667999 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1983507455 |
|
|
Sep 04 03:30:10 PM UTC 24 |
Sep 04 03:30:15 PM UTC 24 |
125849041 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1731955228 |
|
|
Sep 04 03:30:12 PM UTC 24 |
Sep 04 03:30:16 PM UTC 24 |
64926885 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2070894652 |
|
|
Sep 04 03:30:12 PM UTC 24 |
Sep 04 03:30:17 PM UTC 24 |
263969542 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1632923161 |
|
|
Sep 04 03:30:14 PM UTC 24 |
Sep 04 03:30:18 PM UTC 24 |
120390486 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4267629516 |
|
|
Sep 04 03:30:16 PM UTC 24 |
Sep 04 03:30:18 PM UTC 24 |
14837053 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3539892068 |
|
|
Sep 04 03:30:16 PM UTC 24 |
Sep 04 03:30:18 PM UTC 24 |
25455396 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.994076523 |
|
|
Sep 04 03:30:15 PM UTC 24 |
Sep 04 03:30:18 PM UTC 24 |
88438375 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3315516802 |
|
|
Sep 04 03:30:17 PM UTC 24 |
Sep 04 03:30:20 PM UTC 24 |
50885332 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3363894670 |
|
|
Sep 04 03:30:18 PM UTC 24 |
Sep 04 03:30:20 PM UTC 24 |
49529559 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2171742968 |
|
|
Sep 04 03:30:18 PM UTC 24 |
Sep 04 03:30:20 PM UTC 24 |
26163920 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3535495320 |
|
|
Sep 04 03:30:21 PM UTC 24 |
Sep 04 03:30:23 PM UTC 24 |
59416462 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2037362356 |
|
|
Sep 04 03:30:21 PM UTC 24 |
Sep 04 03:30:23 PM UTC 24 |
36246502 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1069674023 |
|
|
Sep 04 03:30:19 PM UTC 24 |
Sep 04 03:30:23 PM UTC 24 |
498049400 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2997815986 |
|
|
Sep 04 03:30:22 PM UTC 24 |
Sep 04 03:30:24 PM UTC 24 |
18451842 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.265765959 |
|
|
Sep 04 03:30:20 PM UTC 24 |
Sep 04 03:30:24 PM UTC 24 |
106562033 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2711611066 |
|
|
Sep 04 03:30:19 PM UTC 24 |
Sep 04 03:30:25 PM UTC 24 |
380650459 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1233179156 |
|
|
Sep 04 03:30:23 PM UTC 24 |
Sep 04 03:30:25 PM UTC 24 |
54488330 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1512643113 |
|
|
Sep 04 03:30:22 PM UTC 24 |
Sep 04 03:30:26 PM UTC 24 |
218389277 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1804700310 |
|
|
Sep 04 03:30:23 PM UTC 24 |
Sep 04 03:30:26 PM UTC 24 |
149506285 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3058192232 |
|
|
Sep 04 03:30:19 PM UTC 24 |
Sep 04 03:30:27 PM UTC 24 |
95288990 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1516764255 |
|
|
Sep 04 03:30:26 PM UTC 24 |
Sep 04 03:30:28 PM UTC 24 |
41393560 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.722433718 |
|
|
Sep 04 03:30:24 PM UTC 24 |
Sep 04 03:30:28 PM UTC 24 |
584210060 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.755143912 |
|
|
Sep 04 03:30:26 PM UTC 24 |
Sep 04 03:30:28 PM UTC 24 |
42903478 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3268602935 |
|
|
Sep 04 03:30:26 PM UTC 24 |
Sep 04 03:30:28 PM UTC 24 |
13085312 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.605790248 |
|
|
Sep 04 03:30:25 PM UTC 24 |
Sep 04 03:30:29 PM UTC 24 |
188098633 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3176589419 |
|
|
Sep 04 03:30:25 PM UTC 24 |
Sep 04 03:30:29 PM UTC 24 |
171403174 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4096568950 |
|
|
Sep 04 03:30:29 PM UTC 24 |
Sep 04 03:30:31 PM UTC 24 |
83369087 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1843389228 |
|
|
Sep 04 03:30:26 PM UTC 24 |
Sep 04 03:30:31 PM UTC 24 |
170264157 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.170474881 |
|
|
Sep 04 03:30:43 PM UTC 24 |
Sep 04 03:30:47 PM UTC 24 |
96611572 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.482157082 |
|
|
Sep 04 03:30:30 PM UTC 24 |
Sep 04 03:30:32 PM UTC 24 |
14676436 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1262876433 |
|
|
Sep 04 03:30:30 PM UTC 24 |
Sep 04 03:30:32 PM UTC 24 |
12111360 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2956802403 |
|
|
Sep 04 03:30:31 PM UTC 24 |
Sep 04 03:30:33 PM UTC 24 |
18819898 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3149980202 |
|
|
Sep 04 03:30:30 PM UTC 24 |
Sep 04 03:30:34 PM UTC 24 |
83025246 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1929433528 |
|
|
Sep 04 03:30:30 PM UTC 24 |
Sep 04 03:30:34 PM UTC 24 |
521893595 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4210344894 |
|
|
Sep 04 03:30:30 PM UTC 24 |
Sep 04 03:30:34 PM UTC 24 |
26681727 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3077480346 |
|
|
Sep 04 03:30:32 PM UTC 24 |
Sep 04 03:30:34 PM UTC 24 |
43283385 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2665184460 |
|
|
Sep 04 03:30:32 PM UTC 24 |
Sep 04 03:30:36 PM UTC 24 |
76831204 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3578048272 |
|
|
Sep 04 03:30:30 PM UTC 24 |
Sep 04 03:30:36 PM UTC 24 |
1579232079 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2690922685 |
|
|
Sep 04 03:30:35 PM UTC 24 |
Sep 04 03:30:37 PM UTC 24 |
16051141 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1207961939 |
|
|
Sep 04 03:30:33 PM UTC 24 |
Sep 04 03:30:38 PM UTC 24 |
860646051 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.40965862 |
|
|
Sep 04 03:30:36 PM UTC 24 |
Sep 04 03:30:38 PM UTC 24 |
45158112 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4277169407 |
|
|
Sep 04 03:30:33 PM UTC 24 |
Sep 04 03:30:39 PM UTC 24 |
81091648 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3793406220 |
|
|
Sep 04 03:30:36 PM UTC 24 |
Sep 04 03:30:39 PM UTC 24 |
106162628 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.383505163 |
|
|
Sep 04 03:30:35 PM UTC 24 |
Sep 04 03:30:39 PM UTC 24 |
617202127 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2636849503 |
|
|
Sep 04 03:30:38 PM UTC 24 |
Sep 04 03:30:40 PM UTC 24 |
12579127 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2790156741 |
|
|
Sep 04 03:30:36 PM UTC 24 |
Sep 04 03:30:40 PM UTC 24 |
209489149 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3456176575 |
|
|
Sep 04 03:30:37 PM UTC 24 |
Sep 04 03:30:41 PM UTC 24 |
883735070 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.63863827 |
|
|
Sep 04 03:30:39 PM UTC 24 |
Sep 04 03:30:41 PM UTC 24 |
49606327 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3451904312 |
|
|
Sep 04 03:30:37 PM UTC 24 |
Sep 04 03:30:42 PM UTC 24 |
103917105 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.948835852 |
|
|
Sep 04 03:30:39 PM UTC 24 |
Sep 04 03:30:42 PM UTC 24 |
82384073 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.902362997 |
|
|
Sep 04 03:30:40 PM UTC 24 |
Sep 04 03:30:42 PM UTC 24 |
27882272 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1834204534 |
|
|
Sep 04 03:30:39 PM UTC 24 |
Sep 04 03:30:43 PM UTC 24 |
202282570 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1900242812 |
|
|
Sep 04 03:30:42 PM UTC 24 |
Sep 04 03:30:43 PM UTC 24 |
22304993 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1370017908 |
|
|
Sep 04 03:30:40 PM UTC 24 |
Sep 04 03:30:44 PM UTC 24 |
175951913 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2652792081 |
|
|
Sep 04 03:30:42 PM UTC 24 |
Sep 04 03:30:44 PM UTC 24 |
32267274 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.844189838 |
|
|
Sep 04 03:30:43 PM UTC 24 |
Sep 04 03:30:45 PM UTC 24 |
23414133 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3200992141 |
|
|
Sep 04 03:30:43 PM UTC 24 |
Sep 04 03:30:45 PM UTC 24 |
12394173 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2875409363 |
|
|
Sep 04 03:30:42 PM UTC 24 |
Sep 04 03:30:46 PM UTC 24 |
493478932 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1051646212 |
|
|
Sep 04 03:30:45 PM UTC 24 |
Sep 04 03:30:47 PM UTC 24 |
37211143 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1645215467 |
|
|
Sep 04 03:30:40 PM UTC 24 |
Sep 04 03:30:48 PM UTC 24 |
152204660 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1358691325 |
|
|
Sep 04 03:30:44 PM UTC 24 |
Sep 04 03:30:48 PM UTC 24 |
60790218 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3030509337 |
|
|
Sep 04 03:30:46 PM UTC 24 |
Sep 04 03:30:49 PM UTC 24 |
149772624 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1646695230 |
|
|
Sep 04 03:30:44 PM UTC 24 |
Sep 04 03:30:49 PM UTC 24 |
1269236976 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4188987220 |
|
|
Sep 04 03:30:45 PM UTC 24 |
Sep 04 03:30:50 PM UTC 24 |
673735639 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2053224628 |
|
|
Sep 04 03:30:49 PM UTC 24 |
Sep 04 03:30:51 PM UTC 24 |
96180884 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.511847711 |
|
|
Sep 04 03:30:43 PM UTC 24 |
Sep 04 03:30:51 PM UTC 24 |
145426135 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.703633953 |
|
|
Sep 04 03:30:44 PM UTC 24 |
Sep 04 03:30:52 PM UTC 24 |
530948760 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3227048089 |
|
|
Sep 04 03:30:50 PM UTC 24 |
Sep 04 03:30:52 PM UTC 24 |
51992688 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2704074111 |
|
|
Sep 04 03:30:47 PM UTC 24 |
Sep 04 03:30:52 PM UTC 24 |
76777950 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.424268459 |
|
|
Sep 04 03:30:48 PM UTC 24 |
Sep 04 03:30:52 PM UTC 24 |
2892541058 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1750176073 |
|
|
Sep 04 03:30:50 PM UTC 24 |
Sep 04 03:30:52 PM UTC 24 |
452146075 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.234610180 |
|
|
Sep 04 03:30:49 PM UTC 24 |
Sep 04 03:30:53 PM UTC 24 |
208520651 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.501457012 |
|
|
Sep 04 03:30:49 PM UTC 24 |
Sep 04 03:30:53 PM UTC 24 |
23915420 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1069540756 |
|
|
Sep 04 03:30:54 PM UTC 24 |
Sep 04 03:30:56 PM UTC 24 |
16207478 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3569822611 |
|
|
Sep 04 03:30:54 PM UTC 24 |
Sep 04 03:30:56 PM UTC 24 |
22265800 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2728094347 |
|
|
Sep 04 03:30:54 PM UTC 24 |
Sep 04 03:30:56 PM UTC 24 |
47876262 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4117398374 |
|
|
Sep 04 03:30:53 PM UTC 24 |
Sep 04 03:30:57 PM UTC 24 |
627344406 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1228057711 |
|
|
Sep 04 03:30:54 PM UTC 24 |
Sep 04 03:30:57 PM UTC 24 |
26089789 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1794947527 |
|
|
Sep 04 03:30:53 PM UTC 24 |
Sep 04 03:30:57 PM UTC 24 |
286175765 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1069825223 |
|
|
Sep 04 03:30:57 PM UTC 24 |
Sep 04 03:30:59 PM UTC 24 |
27699808 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1590096388 |
|
|
Sep 04 03:30:54 PM UTC 24 |
Sep 04 03:30:59 PM UTC 24 |
208116010 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.761638672 |
|
|
Sep 04 03:30:58 PM UTC 24 |
Sep 04 03:31:00 PM UTC 24 |
13130598 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.708950809 |
|
|
Sep 04 03:30:58 PM UTC 24 |
Sep 04 03:31:00 PM UTC 24 |
21901304 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.92605022 |
|
|
Sep 04 03:30:54 PM UTC 24 |
Sep 04 03:31:00 PM UTC 24 |
1050101363 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3100294663 |
|
|
Sep 04 03:30:53 PM UTC 24 |
Sep 04 03:31:00 PM UTC 24 |
158770376 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.804700341 |
|
|
Sep 04 03:30:57 PM UTC 24 |
Sep 04 03:31:01 PM UTC 24 |
186030747 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1400966874 |
|
|
Sep 04 03:30:54 PM UTC 24 |
Sep 04 03:31:02 PM UTC 24 |
45566654 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.929780693 |
|
|
Sep 04 03:30:58 PM UTC 24 |
Sep 04 03:31:03 PM UTC 24 |
229374472 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2536675949 |
|
|
Sep 04 03:30:57 PM UTC 24 |
Sep 04 03:31:03 PM UTC 24 |
409862675 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1711879607 |
|
|
Sep 04 03:31:01 PM UTC 24 |
Sep 04 03:31:03 PM UTC 24 |
30132291 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.227148955 |
|
|
Sep 04 03:31:00 PM UTC 24 |
Sep 04 03:31:03 PM UTC 24 |
78253788 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3056080663 |
|
|
Sep 04 03:31:01 PM UTC 24 |
Sep 04 03:31:04 PM UTC 24 |
288387649 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1647853894 |
|
|
Sep 04 03:31:03 PM UTC 24 |
Sep 04 03:31:05 PM UTC 24 |
20887844 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2632899768 |
|
|
Sep 04 03:30:57 PM UTC 24 |
Sep 04 03:31:05 PM UTC 24 |
238335934 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.354992948 |
|
|
Sep 04 03:31:00 PM UTC 24 |
Sep 04 03:31:05 PM UTC 24 |
57777331 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3500468288 |
|
|
Sep 04 03:31:04 PM UTC 24 |
Sep 04 03:31:06 PM UTC 24 |
76444782 ps |