| T552 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2622163824 |
|
|
Sep 04 04:02:46 PM UTC 24 |
Sep 04 04:18:49 PM UTC 24 |
8389791963 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.1612250049 |
|
|
Sep 04 04:08:22 PM UTC 24 |
Sep 04 04:18:51 PM UTC 24 |
10024177447 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.342934128 |
|
|
Sep 04 04:12:47 PM UTC 24 |
Sep 04 04:19:03 PM UTC 24 |
2754930611 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2784615729 |
|
|
Sep 04 04:04:39 PM UTC 24 |
Sep 04 04:19:03 PM UTC 24 |
2768372231 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1894412925 |
|
|
Sep 04 04:18:50 PM UTC 24 |
Sep 04 04:19:13 PM UTC 24 |
6846898672 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1546894962 |
|
|
Sep 04 04:02:45 PM UTC 24 |
Sep 04 04:19:18 PM UTC 24 |
5809891426 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2424610361 |
|
|
Sep 04 03:40:21 PM UTC 24 |
Sep 04 04:19:27 PM UTC 24 |
155012617462 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.255805450 |
|
|
Sep 04 03:58:29 PM UTC 24 |
Sep 04 04:19:27 PM UTC 24 |
72286015676 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3588113943 |
|
|
Sep 04 04:19:03 PM UTC 24 |
Sep 04 04:19:29 PM UTC 24 |
312654751 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.764878172 |
|
|
Sep 04 04:19:20 PM UTC 24 |
Sep 04 04:19:30 PM UTC 24 |
429363207 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2846790124 |
|
|
Sep 04 04:16:47 PM UTC 24 |
Sep 04 04:19:31 PM UTC 24 |
2849777099 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3674883301 |
|
|
Sep 04 04:19:31 PM UTC 24 |
Sep 04 04:19:33 PM UTC 24 |
35481882 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.67626967 |
|
|
Sep 04 04:12:35 PM UTC 24 |
Sep 04 04:19:36 PM UTC 24 |
29521362617 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2273545070 |
|
|
Sep 04 04:13:18 PM UTC 24 |
Sep 04 04:19:37 PM UTC 24 |
2467682971 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3647435130 |
|
|
Sep 04 04:19:29 PM UTC 24 |
Sep 04 04:19:42 PM UTC 24 |
7863668828 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3378877388 |
|
|
Sep 04 04:19:36 PM UTC 24 |
Sep 04 04:19:42 PM UTC 24 |
816953662 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.907949192 |
|
|
Sep 04 04:19:44 PM UTC 24 |
Sep 04 04:19:45 PM UTC 24 |
15230159 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3755895922 |
|
|
Sep 04 04:09:03 PM UTC 24 |
Sep 04 04:19:48 PM UTC 24 |
17123007083 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2244981596 |
|
|
Sep 04 04:19:34 PM UTC 24 |
Sep 04 04:19:50 PM UTC 24 |
571894961 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.680096319 |
|
|
Sep 04 03:58:26 PM UTC 24 |
Sep 04 04:20:07 PM UTC 24 |
17685395292 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.3755321845 |
|
|
Sep 04 04:19:47 PM UTC 24 |
Sep 04 04:20:07 PM UTC 24 |
158850679 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.3239122280 |
|
|
Sep 04 04:18:42 PM UTC 24 |
Sep 04 04:20:15 PM UTC 24 |
1194494818 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.4241272414 |
|
|
Sep 04 04:07:31 PM UTC 24 |
Sep 04 04:20:28 PM UTC 24 |
6950361407 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2193764294 |
|
|
Sep 04 04:16:05 PM UTC 24 |
Sep 04 04:20:29 PM UTC 24 |
10152158226 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1615849731 |
|
|
Sep 04 04:20:07 PM UTC 24 |
Sep 04 04:20:30 PM UTC 24 |
915220730 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.121171170 |
|
|
Sep 04 04:19:14 PM UTC 24 |
Sep 04 04:20:34 PM UTC 24 |
385883697 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1554851538 |
|
|
Sep 04 04:14:02 PM UTC 24 |
Sep 04 04:20:36 PM UTC 24 |
49595023365 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.367060212 |
|
|
Sep 04 04:20:30 PM UTC 24 |
Sep 04 04:20:37 PM UTC 24 |
586363044 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3796853058 |
|
|
Sep 04 04:20:38 PM UTC 24 |
Sep 04 04:20:40 PM UTC 24 |
35689398 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3633602568 |
|
|
Sep 04 04:03:21 PM UTC 24 |
Sep 04 04:20:44 PM UTC 24 |
3865837902 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.4045820693 |
|
|
Sep 04 04:04:01 PM UTC 24 |
Sep 04 04:20:46 PM UTC 24 |
4247108844 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4009280033 |
|
|
Sep 04 04:20:44 PM UTC 24 |
Sep 04 04:20:52 PM UTC 24 |
194646971 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.918237491 |
|
|
Sep 04 04:19:51 PM UTC 24 |
Sep 04 04:20:57 PM UTC 24 |
1673160551 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.817863686 |
|
|
Sep 04 04:20:56 PM UTC 24 |
Sep 04 04:20:58 PM UTC 24 |
40631375 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.2520069301 |
|
|
Sep 04 04:20:58 PM UTC 24 |
Sep 04 04:21:03 PM UTC 24 |
191282030 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.5516260 |
|
|
Sep 04 04:10:53 PM UTC 24 |
Sep 04 04:21:20 PM UTC 24 |
43643571445 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2878654026 |
|
|
Sep 04 04:20:46 PM UTC 24 |
Sep 04 04:21:22 PM UTC 24 |
803984972 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.1146619169 |
|
|
Sep 04 04:05:46 PM UTC 24 |
Sep 04 04:21:34 PM UTC 24 |
3261121953 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.3661145457 |
|
|
Sep 04 04:21:04 PM UTC 24 |
Sep 04 04:21:43 PM UTC 24 |
2046312903 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.4059432674 |
|
|
Sep 04 04:21:45 PM UTC 24 |
Sep 04 04:21:48 PM UTC 24 |
56752202 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1494725446 |
|
|
Sep 04 04:21:29 PM UTC 24 |
Sep 04 04:22:01 PM UTC 24 |
121467724 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1055656768 |
|
|
Sep 04 04:17:11 PM UTC 24 |
Sep 04 04:22:02 PM UTC 24 |
9851039765 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2338262535 |
|
|
Sep 04 04:17:56 PM UTC 24 |
Sep 04 04:22:13 PM UTC 24 |
7467456135 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3783414461 |
|
|
Sep 04 04:22:01 PM UTC 24 |
Sep 04 04:22:13 PM UTC 24 |
775688940 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3415168324 |
|
|
Sep 04 04:20:29 PM UTC 24 |
Sep 04 04:22:14 PM UTC 24 |
598114183 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2011831132 |
|
|
Sep 04 04:22:16 PM UTC 24 |
Sep 04 04:22:18 PM UTC 24 |
150326370 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3989444356 |
|
|
Sep 04 04:20:21 PM UTC 24 |
Sep 04 04:22:23 PM UTC 24 |
144938901 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2861125006 |
|
|
Sep 04 04:22:24 PM UTC 24 |
Sep 04 04:22:31 PM UTC 24 |
847763715 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1788246580 |
|
|
Sep 04 04:22:20 PM UTC 24 |
Sep 04 04:22:31 PM UTC 24 |
147258709 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1137916475 |
|
|
Sep 04 04:17:18 PM UTC 24 |
Sep 04 04:22:34 PM UTC 24 |
6637834856 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3446876333 |
|
|
Sep 04 04:20:31 PM UTC 24 |
Sep 04 04:22:36 PM UTC 24 |
773907148 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.2131644951 |
|
|
Sep 04 04:12:51 PM UTC 24 |
Sep 04 04:22:37 PM UTC 24 |
16198496333 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2215151077 |
|
|
Sep 04 04:22:36 PM UTC 24 |
Sep 04 04:22:38 PM UTC 24 |
36500960 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.896209537 |
|
|
Sep 04 04:16:01 PM UTC 24 |
Sep 04 04:22:41 PM UTC 24 |
9523684826 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.1758836287 |
|
|
Sep 04 04:22:38 PM UTC 24 |
Sep 04 04:22:46 PM UTC 24 |
270162941 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1982938102 |
|
|
Sep 04 04:21:49 PM UTC 24 |
Sep 04 04:22:54 PM UTC 24 |
132392449 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2098923387 |
|
|
Sep 04 04:22:48 PM UTC 24 |
Sep 04 04:23:00 PM UTC 24 |
432701641 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2189049596 |
|
|
Sep 04 04:16:34 PM UTC 24 |
Sep 04 04:23:07 PM UTC 24 |
3792169252 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2567003515 |
|
|
Sep 04 04:22:32 PM UTC 24 |
Sep 04 04:23:08 PM UTC 24 |
3586165631 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.4094793556 |
|
|
Sep 04 04:23:08 PM UTC 24 |
Sep 04 04:23:12 PM UTC 24 |
147006528 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.521080422 |
|
|
Sep 04 04:22:55 PM UTC 24 |
Sep 04 04:23:20 PM UTC 24 |
207947280 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2221139529 |
|
|
Sep 04 03:44:20 PM UTC 24 |
Sep 04 04:23:21 PM UTC 24 |
10015903593 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.4078691040 |
|
|
Sep 04 04:23:22 PM UTC 24 |
Sep 04 04:23:24 PM UTC 24 |
27949306 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1420320419 |
|
|
Sep 04 03:31:27 PM UTC 24 |
Sep 04 04:23:33 PM UTC 24 |
166702183521 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.185882981 |
|
|
Sep 04 04:18:52 PM UTC 24 |
Sep 04 04:23:35 PM UTC 24 |
3084428733 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2156792698 |
|
|
Sep 04 04:23:25 PM UTC 24 |
Sep 04 04:23:39 PM UTC 24 |
1563663502 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3861118669 |
|
|
Sep 04 04:20:59 PM UTC 24 |
Sep 04 04:23:41 PM UTC 24 |
3885808517 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3604835000 |
|
|
Sep 04 04:03:14 PM UTC 24 |
Sep 04 04:23:43 PM UTC 24 |
36850121477 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1409832968 |
|
|
Sep 04 04:23:34 PM UTC 24 |
Sep 04 04:23:43 PM UTC 24 |
193652835 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.961722651 |
|
|
Sep 04 04:23:42 PM UTC 24 |
Sep 04 04:23:44 PM UTC 24 |
15330885 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.318290395 |
|
|
Sep 04 04:23:43 PM UTC 24 |
Sep 04 04:23:47 PM UTC 24 |
489579011 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.3972053931 |
|
|
Sep 04 04:22:40 PM UTC 24 |
Sep 04 04:23:59 PM UTC 24 |
3688562783 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3518151045 |
|
|
Sep 04 04:24:00 PM UTC 24 |
Sep 04 04:24:13 PM UTC 24 |
523710454 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2391594719 |
|
|
Sep 04 04:11:51 PM UTC 24 |
Sep 04 04:24:21 PM UTC 24 |
3650435337 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.826279934 |
|
|
Sep 04 04:23:01 PM UTC 24 |
Sep 04 04:24:24 PM UTC 24 |
151484445 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.3620446683 |
|
|
Sep 04 04:02:51 PM UTC 24 |
Sep 04 04:24:39 PM UTC 24 |
16002754012 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1397426241 |
|
|
Sep 04 04:24:22 PM UTC 24 |
Sep 04 04:24:42 PM UTC 24 |
198670384 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1933582857 |
|
|
Sep 04 03:49:42 PM UTC 24 |
Sep 04 04:24:43 PM UTC 24 |
27043093379 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.4092818951 |
|
|
Sep 04 04:18:48 PM UTC 24 |
Sep 04 04:24:48 PM UTC 24 |
5482927533 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2295150617 |
|
|
Sep 04 04:24:40 PM UTC 24 |
Sep 04 04:24:49 PM UTC 24 |
625984906 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2993757675 |
|
|
Sep 04 04:24:50 PM UTC 24 |
Sep 04 04:24:52 PM UTC 24 |
30783802 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.3943633307 |
|
|
Sep 04 04:14:54 PM UTC 24 |
Sep 04 04:24:57 PM UTC 24 |
10154498806 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.2551635264 |
|
|
Sep 04 04:24:58 PM UTC 24 |
Sep 04 04:25:04 PM UTC 24 |
207844785 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3305828951 |
|
|
Sep 04 04:24:53 PM UTC 24 |
Sep 04 04:25:05 PM UTC 24 |
544887822 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3043195845 |
|
|
Sep 04 04:19:03 PM UTC 24 |
Sep 04 04:25:06 PM UTC 24 |
45420302623 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1365626984 |
|
|
Sep 04 04:25:06 PM UTC 24 |
Sep 04 04:25:08 PM UTC 24 |
38420714 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.4117447827 |
|
|
Sep 04 04:16:40 PM UTC 24 |
Sep 04 04:25:10 PM UTC 24 |
19148300164 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2514961457 |
|
|
Sep 04 04:07:25 PM UTC 24 |
Sep 04 04:25:10 PM UTC 24 |
5083469515 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1209054570 |
|
|
Sep 04 04:21:35 PM UTC 24 |
Sep 04 04:25:12 PM UTC 24 |
7701867328 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.1021845090 |
|
|
Sep 04 04:23:45 PM UTC 24 |
Sep 04 04:25:17 PM UTC 24 |
6806720569 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.993770479 |
|
|
Sep 04 04:19:38 PM UTC 24 |
Sep 04 04:25:17 PM UTC 24 |
4214909539 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3250721265 |
|
|
Sep 04 04:24:25 PM UTC 24 |
Sep 04 04:25:21 PM UTC 24 |
478499562 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.3764069248 |
|
|
Sep 04 04:25:09 PM UTC 24 |
Sep 04 04:25:27 PM UTC 24 |
920774052 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.2293943682 |
|
|
Sep 04 04:25:18 PM UTC 24 |
Sep 04 04:25:30 PM UTC 24 |
1759474679 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.389546528 |
|
|
Sep 04 04:20:16 PM UTC 24 |
Sep 04 04:25:36 PM UTC 24 |
34041466177 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3681319017 |
|
|
Sep 04 04:25:22 PM UTC 24 |
Sep 04 04:25:39 PM UTC 24 |
75261907 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.347927838 |
|
|
Sep 04 04:25:31 PM UTC 24 |
Sep 04 04:25:44 PM UTC 24 |
2491083603 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.420335518 |
|
|
Sep 04 03:58:38 PM UTC 24 |
Sep 04 04:26:38 PM UTC 24 |
27742404547 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1482931533 |
|
|
Sep 04 04:25:05 PM UTC 24 |
Sep 04 04:25:47 PM UTC 24 |
20676943070 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.71033227 |
|
|
Sep 04 04:25:12 PM UTC 24 |
Sep 04 04:25:51 PM UTC 24 |
483712416 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.664721971 |
|
|
Sep 04 04:25:49 PM UTC 24 |
Sep 04 04:25:51 PM UTC 24 |
151778349 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3994698162 |
|
|
Sep 04 04:25:28 PM UTC 24 |
Sep 04 04:25:51 PM UTC 24 |
340557719 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.968368427 |
|
|
Sep 04 04:25:53 PM UTC 24 |
Sep 04 04:26:02 PM UTC 24 |
170066781 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3920023536 |
|
|
Sep 04 04:25:53 PM UTC 24 |
Sep 04 04:26:10 PM UTC 24 |
2094102828 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.641085351 |
|
|
Sep 04 04:26:11 PM UTC 24 |
Sep 04 04:26:14 PM UTC 24 |
12638452 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.835249509 |
|
|
Sep 04 04:26:15 PM UTC 24 |
Sep 04 04:26:25 PM UTC 24 |
318156086 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.972605186 |
|
|
Sep 04 04:23:36 PM UTC 24 |
Sep 04 04:26:37 PM UTC 24 |
3284280383 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3076836778 |
|
|
Sep 04 04:20:07 PM UTC 24 |
Sep 04 04:26:55 PM UTC 24 |
7069126806 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3426399881 |
|
|
Sep 04 04:10:56 PM UTC 24 |
Sep 04 04:27:17 PM UTC 24 |
114867734138 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.277856843 |
|
|
Sep 04 04:26:56 PM UTC 24 |
Sep 04 04:27:21 PM UTC 24 |
5989671981 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2127886979 |
|
|
Sep 04 04:26:38 PM UTC 24 |
Sep 04 04:27:21 PM UTC 24 |
2014598483 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1031887117 |
|
|
Sep 04 04:17:07 PM UTC 24 |
Sep 04 04:27:32 PM UTC 24 |
27720949503 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2577870640 |
|
|
Sep 04 04:22:43 PM UTC 24 |
Sep 04 04:27:34 PM UTC 24 |
10652170006 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3198220055 |
|
|
Sep 04 04:27:34 PM UTC 24 |
Sep 04 04:27:43 PM UTC 24 |
3174611453 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.597271466 |
|
|
Sep 04 04:23:47 PM UTC 24 |
Sep 04 04:27:48 PM UTC 24 |
2671825567 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.2197756752 |
|
|
Sep 04 04:23:13 PM UTC 24 |
Sep 04 04:27:58 PM UTC 24 |
17332981317 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1627479134 |
|
|
Sep 04 04:07:12 PM UTC 24 |
Sep 04 04:27:59 PM UTC 24 |
24771228205 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3795368124 |
|
|
Sep 04 04:21:20 PM UTC 24 |
Sep 04 04:28:01 PM UTC 24 |
18777082381 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.665041034 |
|
|
Sep 04 04:28:00 PM UTC 24 |
Sep 04 04:28:02 PM UTC 24 |
89804906 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1016657384 |
|
|
Sep 04 04:28:02 PM UTC 24 |
Sep 04 04:28:10 PM UTC 24 |
91704987 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2925026247 |
|
|
Sep 04 04:28:00 PM UTC 24 |
Sep 04 04:28:13 PM UTC 24 |
229164179 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1410671512 |
|
|
Sep 04 04:28:14 PM UTC 24 |
Sep 04 04:28:16 PM UTC 24 |
61365872 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2276200367 |
|
|
Sep 04 04:28:17 PM UTC 24 |
Sep 04 04:28:31 PM UTC 24 |
175615531 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3830479050 |
|
|
Sep 04 04:27:23 PM UTC 24 |
Sep 04 04:28:56 PM UTC 24 |
669132958 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.939853276 |
|
|
Sep 04 04:14:54 PM UTC 24 |
Sep 04 04:29:00 PM UTC 24 |
36207554594 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1175282621 |
|
|
Sep 04 04:33:32 PM UTC 24 |
Sep 04 04:33:48 PM UTC 24 |
1898954274 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3834690391 |
|
|
Sep 04 04:25:12 PM UTC 24 |
Sep 04 04:29:02 PM UTC 24 |
10073545707 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.592347654 |
|
|
Sep 04 04:27:22 PM UTC 24 |
Sep 04 04:29:14 PM UTC 24 |
281935963 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.45536124 |
|
|
Sep 04 04:22:15 PM UTC 24 |
Sep 04 04:29:18 PM UTC 24 |
1630146477 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.65531888 |
|
|
Sep 04 04:22:03 PM UTC 24 |
Sep 04 04:29:34 PM UTC 24 |
1901528388 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1375510288 |
|
|
Sep 04 04:29:03 PM UTC 24 |
Sep 04 04:29:35 PM UTC 24 |
336544754 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3595153051 |
|
|
Sep 04 04:29:36 PM UTC 24 |
Sep 04 04:29:39 PM UTC 24 |
653257446 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2980367046 |
|
|
Sep 04 04:29:34 PM UTC 24 |
Sep 04 04:29:43 PM UTC 24 |
95998644 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3564681287 |
|
|
Sep 04 04:28:02 PM UTC 24 |
Sep 04 04:29:44 PM UTC 24 |
951006268 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3779387742 |
|
|
Sep 04 04:17:55 PM UTC 24 |
Sep 04 04:29:46 PM UTC 24 |
16136270124 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.347500468 |
|
|
Sep 04 04:29:46 PM UTC 24 |
Sep 04 04:29:48 PM UTC 24 |
63781160 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.246558911 |
|
|
Sep 04 04:29:49 PM UTC 24 |
Sep 04 04:29:58 PM UTC 24 |
195292343 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.79793031 |
|
|
Sep 04 04:29:59 PM UTC 24 |
Sep 04 04:30:04 PM UTC 24 |
125948985 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.493606900 |
|
|
Sep 04 04:28:57 PM UTC 24 |
Sep 04 04:30:09 PM UTC 24 |
14513428460 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.185009858 |
|
|
Sep 04 04:29:18 PM UTC 24 |
Sep 04 04:30:15 PM UTC 24 |
115029026 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1567364492 |
|
|
Sep 04 04:30:17 PM UTC 24 |
Sep 04 04:30:19 PM UTC 24 |
128244998 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2852368043 |
|
|
Sep 04 04:26:38 PM UTC 24 |
Sep 04 04:30:31 PM UTC 24 |
3710258408 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2645394750 |
|
|
Sep 04 04:25:53 PM UTC 24 |
Sep 04 04:30:33 PM UTC 24 |
4444399449 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.2961559081 |
|
|
Sep 04 04:19:30 PM UTC 24 |
Sep 04 04:30:36 PM UTC 24 |
1777457411 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.3270429629 |
|
|
Sep 04 04:24:44 PM UTC 24 |
Sep 04 04:30:43 PM UTC 24 |
1290033382 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1039804258 |
|
|
Sep 04 04:30:20 PM UTC 24 |
Sep 04 04:30:52 PM UTC 24 |
589768483 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2221911189 |
|
|
Sep 04 04:22:55 PM UTC 24 |
Sep 04 04:30:53 PM UTC 24 |
14875623804 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1122165358 |
|
|
Sep 04 04:30:05 PM UTC 24 |
Sep 04 04:30:57 PM UTC 24 |
1327085902 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1051384541 |
|
|
Sep 04 04:24:15 PM UTC 24 |
Sep 04 04:31:00 PM UTC 24 |
103546681284 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1570648160 |
|
|
Sep 04 04:27:35 PM UTC 24 |
Sep 04 04:31:01 PM UTC 24 |
2743734006 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.4252173144 |
|
|
Sep 04 04:30:34 PM UTC 24 |
Sep 04 04:31:03 PM UTC 24 |
1067528705 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.540717884 |
|
|
Sep 04 04:31:00 PM UTC 24 |
Sep 04 04:31:13 PM UTC 24 |
862612018 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3079573783 |
|
|
Sep 04 04:31:13 PM UTC 24 |
Sep 04 04:31:15 PM UTC 24 |
29714533 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1854104506 |
|
|
Sep 04 03:43:15 PM UTC 24 |
Sep 04 04:31:18 PM UTC 24 |
146430232641 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1378395908 |
|
|
Sep 04 04:31:17 PM UTC 24 |
Sep 04 04:31:25 PM UTC 24 |
465066888 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1613445019 |
|
|
Sep 04 04:31:19 PM UTC 24 |
Sep 04 04:31:28 PM UTC 24 |
974338258 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3142087564 |
|
|
Sep 04 04:15:35 PM UTC 24 |
Sep 04 04:31:38 PM UTC 24 |
12219162409 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1365251333 |
|
|
Sep 04 04:31:39 PM UTC 24 |
Sep 04 04:31:41 PM UTC 24 |
24772883 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1249224797 |
|
|
Sep 04 04:30:45 PM UTC 24 |
Sep 04 04:31:54 PM UTC 24 |
545019823 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2088247507 |
|
|
Sep 04 04:23:20 PM UTC 24 |
Sep 04 04:32:00 PM UTC 24 |
6509489503 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.497580214 |
|
|
Sep 04 04:30:54 PM UTC 24 |
Sep 04 04:32:00 PM UTC 24 |
108102708 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3070791030 |
|
|
Sep 04 04:31:42 PM UTC 24 |
Sep 04 04:32:02 PM UTC 24 |
235721350 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1272427618 |
|
|
Sep 04 04:19:29 PM UTC 24 |
Sep 04 04:32:05 PM UTC 24 |
39784898477 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.3867503749 |
|
|
Sep 04 04:30:58 PM UTC 24 |
Sep 04 04:32:15 PM UTC 24 |
257807752 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2795351676 |
|
|
Sep 04 04:31:26 PM UTC 24 |
Sep 04 04:32:16 PM UTC 24 |
2102057922 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.573690602 |
|
|
Sep 04 04:24:49 PM UTC 24 |
Sep 04 04:32:18 PM UTC 24 |
1626035956 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1912067564 |
|
|
Sep 04 04:18:25 PM UTC 24 |
Sep 04 04:32:18 PM UTC 24 |
34773913258 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3925835311 |
|
|
Sep 04 04:32:16 PM UTC 24 |
Sep 04 04:32:23 PM UTC 24 |
63101202 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2394288742 |
|
|
Sep 04 04:32:04 PM UTC 24 |
Sep 04 04:32:23 PM UTC 24 |
614275635 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1235345948 |
|
|
Sep 04 04:32:19 PM UTC 24 |
Sep 04 04:32:28 PM UTC 24 |
788147873 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.4161648371 |
|
|
Sep 04 04:32:28 PM UTC 24 |
Sep 04 04:32:30 PM UTC 24 |
75389879 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2945275789 |
|
|
Sep 04 04:32:31 PM UTC 24 |
Sep 04 04:32:42 PM UTC 24 |
603192246 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.435053483 |
|
|
Sep 04 04:32:43 PM UTC 24 |
Sep 04 04:32:48 PM UTC 24 |
335719365 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.184797118 |
|
|
Sep 04 04:32:00 PM UTC 24 |
Sep 04 04:32:48 PM UTC 24 |
2395137333 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1393266853 |
|
|
Sep 04 04:32:17 PM UTC 24 |
Sep 04 04:33:06 PM UTC 24 |
118392952 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1733666347 |
|
|
Sep 04 04:33:07 PM UTC 24 |
Sep 04 04:33:09 PM UTC 24 |
22904990 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.921251505 |
|
|
Sep 04 04:32:24 PM UTC 24 |
Sep 04 04:33:17 PM UTC 24 |
2095888115 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3823395008 |
|
|
Sep 04 04:22:13 PM UTC 24 |
Sep 04 04:33:25 PM UTC 24 |
2009795632 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2436699087 |
|
|
Sep 04 04:33:11 PM UTC 24 |
Sep 04 04:33:26 PM UTC 24 |
362578325 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.215495170 |
|
|
Sep 04 04:20:38 PM UTC 24 |
Sep 04 04:33:30 PM UTC 24 |
39700198308 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.1629816819 |
|
|
Sep 04 04:29:00 PM UTC 24 |
Sep 04 04:33:33 PM UTC 24 |
2333562161 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3001226106 |
|
|
Sep 04 04:23:09 PM UTC 24 |
Sep 04 04:33:46 PM UTC 24 |
2892006090 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.1901989653 |
|
|
Sep 04 04:26:26 PM UTC 24 |
Sep 04 04:34:26 PM UTC 24 |
18587157293 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2486359205 |
|
|
Sep 04 04:30:53 PM UTC 24 |
Sep 04 04:34:28 PM UTC 24 |
9071184558 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2329600214 |
|
|
Sep 04 04:14:52 PM UTC 24 |
Sep 04 04:34:33 PM UTC 24 |
4187652954 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1793326172 |
|
|
Sep 04 04:34:27 PM UTC 24 |
Sep 04 04:34:35 PM UTC 24 |
1743873438 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1057710816 |
|
|
Sep 04 04:27:18 PM UTC 24 |
Sep 04 04:34:42 PM UTC 24 |
4421407049 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3611791953 |
|
|
Sep 04 04:33:26 PM UTC 24 |
Sep 04 04:34:42 PM UTC 24 |
23075618567 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4027881169 |
|
|
Sep 04 04:34:43 PM UTC 24 |
Sep 04 04:34:45 PM UTC 24 |
28509604 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.2078883557 |
|
|
Sep 04 04:23:45 PM UTC 24 |
Sep 04 04:34:49 PM UTC 24 |
42522030320 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1857251757 |
|
|
Sep 04 04:34:43 PM UTC 24 |
Sep 04 04:34:50 PM UTC 24 |
281173998 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3390043481 |
|
|
Sep 04 04:16:38 PM UTC 24 |
Sep 04 04:34:55 PM UTC 24 |
2376304460 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.1122184956 |
|
|
Sep 04 04:34:46 PM UTC 24 |
Sep 04 04:34:56 PM UTC 24 |
164513333 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.2908833076 |
|
|
Sep 04 04:34:57 PM UTC 24 |
Sep 04 04:34:59 PM UTC 24 |
15611332 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1384540686 |
|
|
Sep 04 04:22:38 PM UTC 24 |
Sep 04 04:35:02 PM UTC 24 |
14171788550 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.4132317134 |
|
|
Sep 04 04:33:48 PM UTC 24 |
Sep 04 04:35:02 PM UTC 24 |
508427753 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.285156377 |
|
|
Sep 04 04:18:05 PM UTC 24 |
Sep 04 04:35:05 PM UTC 24 |
31154768130 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.4064010380 |
|
|
Sep 04 04:34:57 PM UTC 24 |
Sep 04 04:35:09 PM UTC 24 |
965118398 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4192708206 |
|
|
Sep 04 04:33:49 PM UTC 24 |
Sep 04 04:35:34 PM UTC 24 |
1210891040 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1809600076 |
|
|
Sep 04 04:11:32 PM UTC 24 |
Sep 04 04:35:38 PM UTC 24 |
56780433887 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2264817358 |
|
|
Sep 04 04:35:35 PM UTC 24 |
Sep 04 04:35:43 PM UTC 24 |
73403381 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.556408994 |
|
|
Sep 04 04:29:15 PM UTC 24 |
Sep 04 04:35:44 PM UTC 24 |
15375744933 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2503289955 |
|
|
Sep 04 04:35:45 PM UTC 24 |
Sep 04 04:35:56 PM UTC 24 |
412853623 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3193134642 |
|
|
Sep 04 04:35:39 PM UTC 24 |
Sep 04 04:36:09 PM UTC 24 |
410231545 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.258128764 |
|
|
Sep 04 04:31:03 PM UTC 24 |
Sep 04 04:36:12 PM UTC 24 |
1448056299 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2784727004 |
|
|
Sep 04 04:36:13 PM UTC 24 |
Sep 04 04:36:15 PM UTC 24 |
84662704 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1396820747 |
|
|
Sep 04 04:30:37 PM UTC 24 |
Sep 04 04:36:16 PM UTC 24 |
3120779063 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.908033727 |
|
|
Sep 04 04:36:17 PM UTC 24 |
Sep 04 04:36:23 PM UTC 24 |
459083313 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3596470114 |
|
|
Sep 04 04:35:07 PM UTC 24 |
Sep 04 04:36:25 PM UTC 24 |
4299182035 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.455689785 |
|
|
Sep 04 04:36:16 PM UTC 24 |
Sep 04 04:36:27 PM UTC 24 |
499627729 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2219482274 |
|
|
Sep 04 04:25:37 PM UTC 24 |
Sep 04 04:36:29 PM UTC 24 |
12115017581 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.358288823 |
|
|
Sep 04 04:36:28 PM UTC 24 |
Sep 04 04:36:30 PM UTC 24 |
41359219 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1914594393 |
|
|
Sep 04 04:32:49 PM UTC 24 |
Sep 04 04:36:31 PM UTC 24 |
4218009899 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3562914299 |
|
|
Sep 04 04:36:30 PM UTC 24 |
Sep 04 04:36:34 PM UTC 24 |
281527248 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3721048372 |
|
|
Sep 04 04:35:03 PM UTC 24 |
Sep 04 04:37:03 PM UTC 24 |
49576117548 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3011517629 |
|
|
Sep 04 04:36:57 PM UTC 24 |
Sep 04 04:37:07 PM UTC 24 |
340313058 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1646947755 |
|
|
Sep 04 04:32:02 PM UTC 24 |
Sep 04 04:37:24 PM UTC 24 |
12473177203 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.1298101744 |
|
|
Sep 04 04:19:31 PM UTC 24 |
Sep 04 04:37:26 PM UTC 24 |
14108981507 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2310360664 |
|
|
Sep 04 04:37:26 PM UTC 24 |
Sep 04 04:37:29 PM UTC 24 |
79873895 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3650295240 |
|
|
Sep 04 04:33:27 PM UTC 24 |
Sep 04 04:37:32 PM UTC 24 |
2166089436 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4239733185 |
|
|
Sep 04 04:37:28 PM UTC 24 |
Sep 04 04:37:36 PM UTC 24 |
528246415 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.2656712379 |
|
|
Sep 04 04:36:31 PM UTC 24 |
Sep 04 04:37:38 PM UTC 24 |
2915910154 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.90756869 |
|
|
Sep 04 04:37:39 PM UTC 24 |
Sep 04 04:37:41 PM UTC 24 |
81117588 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.497100641 |
|
|
Sep 04 04:37:42 PM UTC 24 |
Sep 04 04:37:50 PM UTC 24 |
530577593 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.653413866 |
|
|
Sep 04 03:51:41 PM UTC 24 |
Sep 04 04:37:53 PM UTC 24 |
40249732192 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2235067923 |
|
|
Sep 04 04:37:51 PM UTC 24 |
Sep 04 04:37:59 PM UTC 24 |
663165019 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.56957590 |
|
|
Sep 04 04:25:19 PM UTC 24 |
Sep 04 04:38:04 PM UTC 24 |
49622973378 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.464286507 |
|
|
Sep 04 04:38:04 PM UTC 24 |
Sep 04 04:38:06 PM UTC 24 |
44828313 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.607215185 |
|
|
Sep 04 04:38:07 PM UTC 24 |
Sep 04 04:38:19 PM UTC 24 |
6761317988 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3808376482 |
|
|
Sep 04 04:37:08 PM UTC 24 |
Sep 04 04:38:27 PM UTC 24 |
134827457 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2971728568 |
|
|
Sep 04 04:15:20 PM UTC 24 |
Sep 04 04:38:42 PM UTC 24 |
24320194408 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.925731498 |
|
|
Sep 04 04:24:43 PM UTC 24 |
Sep 04 04:38:50 PM UTC 24 |
16065160835 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.3409478390 |
|
|
Sep 04 04:35:03 PM UTC 24 |
Sep 04 04:38:58 PM UTC 24 |
2306508951 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.4052137832 |
|
|
Sep 04 04:38:28 PM UTC 24 |
Sep 04 04:39:00 PM UTC 24 |
11436010159 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2857721615 |
|
|
Sep 04 04:38:49 PM UTC 24 |
Sep 04 04:39:03 PM UTC 24 |
1226806695 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2847572206 |
|
|
Sep 04 04:20:35 PM UTC 24 |
Sep 04 04:39:04 PM UTC 24 |
11330778979 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.2853764436 |
|
|
Sep 04 04:25:11 PM UTC 24 |
Sep 04 04:39:05 PM UTC 24 |
12841581752 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1537797583 |
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|
Sep 04 04:08:52 PM UTC 24 |
Sep 04 04:39:06 PM UTC 24 |
12575143872 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2648151877 |
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|
Sep 04 04:39:04 PM UTC 24 |
Sep 04 04:39:13 PM UTC 24 |
517382192 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3222693946 |
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|
Sep 04 04:39:14 PM UTC 24 |
Sep 04 04:39:16 PM UTC 24 |
75657009 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.2443578197 |
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|
Sep 04 04:37:37 PM UTC 24 |
Sep 04 04:39:22 PM UTC 24 |
4510825953 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.4040299387 |
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|
Sep 04 04:39:17 PM UTC 24 |
Sep 04 04:39:26 PM UTC 24 |
230772268 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.706587389 |
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Sep 04 04:33:34 PM UTC 24 |
Sep 04 04:39:26 PM UTC 24 |
13091910197 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.375914367 |
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Sep 04 04:39:23 PM UTC 24 |
Sep 04 04:39:31 PM UTC 24 |
528146976 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2681388377 |
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|
Sep 04 04:36:36 PM UTC 24 |
Sep 04 04:39:34 PM UTC 24 |
6460916530 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2779436907 |
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Sep 04 04:39:33 PM UTC 24 |
Sep 04 04:39:35 PM UTC 24 |
44981573 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3893986937 |
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Sep 04 04:38:59 PM UTC 24 |
Sep 04 04:39:39 PM UTC 24 |
218166369 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.927576889 |
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|
Sep 04 04:35:10 PM UTC 24 |
Sep 04 04:39:41 PM UTC 24 |
7349805382 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.759126977 |
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Sep 04 04:39:26 PM UTC 24 |
Sep 04 04:39:45 PM UTC 24 |
392093455 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.2673732997 |
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Sep 04 04:39:35 PM UTC 24 |
Sep 04 04:39:49 PM UTC 24 |
438590732 ps |