| T311 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.321091544 |
|
|
Sep 09 09:10:31 PM UTC 24 |
Sep 09 09:29:39 PM UTC 24 |
7960142936 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4108952521 |
|
|
Sep 09 09:18:26 PM UTC 24 |
Sep 09 09:29:59 PM UTC 24 |
52376710232 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.1412097372 |
|
|
Sep 09 09:26:07 PM UTC 24 |
Sep 09 09:30:03 PM UTC 24 |
999014069 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3680738103 |
|
|
Sep 09 09:28:49 PM UTC 24 |
Sep 09 09:30:06 PM UTC 24 |
158381512 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.403127870 |
|
|
Sep 09 09:29:40 PM UTC 24 |
Sep 09 09:30:06 PM UTC 24 |
4137801829 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3622218497 |
|
|
Sep 09 09:10:26 PM UTC 24 |
Sep 09 09:30:09 PM UTC 24 |
50894512471 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.3789397005 |
|
|
Sep 09 09:30:07 PM UTC 24 |
Sep 09 09:30:10 PM UTC 24 |
132871190 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.1016538276 |
|
|
Sep 09 09:29:38 PM UTC 24 |
Sep 09 09:30:11 PM UTC 24 |
10189673301 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3689675112 |
|
|
Sep 09 09:30:07 PM UTC 24 |
Sep 09 09:30:16 PM UTC 24 |
2521600370 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2987403960 |
|
|
Sep 09 09:30:04 PM UTC 24 |
Sep 09 09:30:16 PM UTC 24 |
449692937 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3002706252 |
|
|
Sep 09 09:30:17 PM UTC 24 |
Sep 09 09:30:19 PM UTC 24 |
51534757 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1534906358 |
|
|
Sep 09 09:30:20 PM UTC 24 |
Sep 09 09:30:26 PM UTC 24 |
195586583 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3330453018 |
|
|
Sep 09 09:29:31 PM UTC 24 |
Sep 09 09:30:31 PM UTC 24 |
1247517273 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.674853391 |
|
|
Sep 09 09:22:19 PM UTC 24 |
Sep 09 09:30:34 PM UTC 24 |
1710675927 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2610499095 |
|
|
Sep 09 09:30:17 PM UTC 24 |
Sep 09 09:30:36 PM UTC 24 |
2615077176 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2394647991 |
|
|
Sep 09 09:30:35 PM UTC 24 |
Sep 09 09:30:37 PM UTC 24 |
46740261 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4159157004 |
|
|
Sep 09 09:29:22 PM UTC 24 |
Sep 09 09:30:46 PM UTC 24 |
1490945939 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.278743172 |
|
|
Sep 09 09:30:37 PM UTC 24 |
Sep 09 09:30:53 PM UTC 24 |
3607803488 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3566666946 |
|
|
Sep 09 09:23:24 PM UTC 24 |
Sep 09 09:30:58 PM UTC 24 |
6501192401 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1818885802 |
|
|
Sep 09 09:10:21 PM UTC 24 |
Sep 09 09:30:58 PM UTC 24 |
27493525039 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2074697183 |
|
|
Sep 09 09:24:14 PM UTC 24 |
Sep 09 09:31:02 PM UTC 24 |
6441526695 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2798146542 |
|
|
Sep 09 09:30:58 PM UTC 24 |
Sep 09 09:31:08 PM UTC 24 |
64063237 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.180280203 |
|
|
Sep 09 09:31:02 PM UTC 24 |
Sep 09 09:31:09 PM UTC 24 |
236455097 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2104717394 |
|
|
Sep 09 09:19:35 PM UTC 24 |
Sep 09 09:31:32 PM UTC 24 |
13098872431 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.448440564 |
|
|
Sep 09 09:30:47 PM UTC 24 |
Sep 09 09:31:35 PM UTC 24 |
431886495 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.905699319 |
|
|
Sep 09 09:31:36 PM UTC 24 |
Sep 09 09:31:38 PM UTC 24 |
88000513 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.4089755360 |
|
|
Sep 09 09:30:59 PM UTC 24 |
Sep 09 09:31:48 PM UTC 24 |
213875488 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2459391344 |
|
|
Sep 09 09:31:39 PM UTC 24 |
Sep 09 09:31:53 PM UTC 24 |
181394022 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.91537955 |
|
|
Sep 09 09:26:43 PM UTC 24 |
Sep 09 09:31:56 PM UTC 24 |
1238082181 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3870240194 |
|
|
Sep 09 09:31:49 PM UTC 24 |
Sep 09 09:31:56 PM UTC 24 |
176254157 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3848487336 |
|
|
Sep 09 09:31:57 PM UTC 24 |
Sep 09 09:31:59 PM UTC 24 |
50567472 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3430337268 |
|
|
Sep 09 09:27:54 PM UTC 24 |
Sep 09 09:32:05 PM UTC 24 |
2515709053 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2888435516 |
|
|
Sep 09 09:15:03 PM UTC 24 |
Sep 09 09:32:08 PM UTC 24 |
10272876576 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.4172357089 |
|
|
Sep 09 09:30:45 PM UTC 24 |
Sep 09 09:32:23 PM UTC 24 |
3588472112 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.458022187 |
|
|
Sep 09 09:30:10 PM UTC 24 |
Sep 09 09:32:25 PM UTC 24 |
1880119481 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1435516054 |
|
|
Sep 09 09:32:08 PM UTC 24 |
Sep 09 09:32:32 PM UTC 24 |
3078167945 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.953898863 |
|
|
Sep 09 09:32:26 PM UTC 24 |
Sep 09 09:32:38 PM UTC 24 |
177795407 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1739926304 |
|
|
Sep 09 09:28:26 PM UTC 24 |
Sep 09 09:32:48 PM UTC 24 |
8283165345 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.2578999568 |
|
|
Sep 09 09:24:04 PM UTC 24 |
Sep 09 09:33:04 PM UTC 24 |
16977562184 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1337181601 |
|
|
Sep 09 09:32:48 PM UTC 24 |
Sep 09 09:33:05 PM UTC 24 |
109373970 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.2275356124 |
|
|
Sep 09 09:33:05 PM UTC 24 |
Sep 09 09:33:14 PM UTC 24 |
1593933794 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.694163084 |
|
|
Sep 09 09:22:23 PM UTC 24 |
Sep 09 09:33:19 PM UTC 24 |
8906782817 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3053253435 |
|
|
Sep 09 09:22:35 PM UTC 24 |
Sep 09 09:33:20 PM UTC 24 |
2677060132 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1593968033 |
|
|
Sep 09 09:33:21 PM UTC 24 |
Sep 09 09:33:24 PM UTC 24 |
103363711 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2352681630 |
|
|
Sep 09 09:32:00 PM UTC 24 |
Sep 09 09:33:27 PM UTC 24 |
123932348 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2023547865 |
|
|
Sep 09 09:32:39 PM UTC 24 |
Sep 09 09:33:32 PM UTC 24 |
111938204 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3313705778 |
|
|
Sep 09 09:33:28 PM UTC 24 |
Sep 09 09:33:33 PM UTC 24 |
54677209 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.407673571 |
|
|
Sep 09 09:33:25 PM UTC 24 |
Sep 09 09:33:40 PM UTC 24 |
2828727093 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.45156020 |
|
|
Sep 09 09:31:08 PM UTC 24 |
Sep 09 09:33:43 PM UTC 24 |
3964197703 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.4000522855 |
|
|
Sep 09 09:33:41 PM UTC 24 |
Sep 09 09:33:43 PM UTC 24 |
15621821 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.177361107 |
|
|
Sep 09 09:33:43 PM UTC 24 |
Sep 09 09:33:56 PM UTC 24 |
1033879524 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1924762074 |
|
|
Sep 09 09:29:02 PM UTC 24 |
Sep 09 09:33:59 PM UTC 24 |
1358745078 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3327887103 |
|
|
Sep 09 09:26:58 PM UTC 24 |
Sep 09 09:34:05 PM UTC 24 |
3295832456 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2580670353 |
|
|
Sep 09 09:33:05 PM UTC 24 |
Sep 09 09:34:24 PM UTC 24 |
6677226600 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.965504768 |
|
|
Sep 09 09:34:06 PM UTC 24 |
Sep 09 09:34:24 PM UTC 24 |
866049490 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3137739766 |
|
|
Sep 09 09:29:34 PM UTC 24 |
Sep 09 09:34:32 PM UTC 24 |
5444965244 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1051983095 |
|
|
Sep 09 09:34:33 PM UTC 24 |
Sep 09 09:34:36 PM UTC 24 |
66025794 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1316062386 |
|
|
Sep 09 09:34:37 PM UTC 24 |
Sep 09 09:34:51 PM UTC 24 |
753460781 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3832649895 |
|
|
Sep 09 09:34:25 PM UTC 24 |
Sep 09 09:35:03 PM UTC 24 |
95532800 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3859227990 |
|
|
Sep 09 09:33:57 PM UTC 24 |
Sep 09 09:35:11 PM UTC 24 |
18924906140 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.161478041 |
|
|
Sep 09 09:19:02 PM UTC 24 |
Sep 09 09:35:18 PM UTC 24 |
13408735946 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2211691433 |
|
|
Sep 09 09:35:18 PM UTC 24 |
Sep 09 09:35:20 PM UTC 24 |
36982384 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2864434269 |
|
|
Sep 09 09:27:40 PM UTC 24 |
Sep 09 09:35:22 PM UTC 24 |
3012899787 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1025030429 |
|
|
Sep 09 09:35:23 PM UTC 24 |
Sep 09 09:35:31 PM UTC 24 |
137984508 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3696136510 |
|
|
Sep 09 09:35:21 PM UTC 24 |
Sep 09 09:35:34 PM UTC 24 |
266789757 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.1151608707 |
|
|
Sep 09 09:30:11 PM UTC 24 |
Sep 09 09:35:40 PM UTC 24 |
6426910304 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2159190354 |
|
|
Sep 09 09:35:42 PM UTC 24 |
Sep 09 09:35:44 PM UTC 24 |
50541694 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.2532691193 |
|
|
Sep 09 09:35:45 PM UTC 24 |
Sep 09 09:35:56 PM UTC 24 |
187429669 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2314208480 |
|
|
Sep 09 09:31:54 PM UTC 24 |
Sep 09 09:36:01 PM UTC 24 |
4774743273 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1017286281 |
|
|
Sep 09 09:27:47 PM UTC 24 |
Sep 09 09:36:05 PM UTC 24 |
1831653465 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.237966964 |
|
|
Sep 09 09:27:19 PM UTC 24 |
Sep 09 09:36:11 PM UTC 24 |
76535269802 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1281076079 |
|
|
Sep 09 09:25:36 PM UTC 24 |
Sep 09 09:36:19 PM UTC 24 |
130480646818 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.229347887 |
|
|
Sep 09 09:36:02 PM UTC 24 |
Sep 09 09:36:23 PM UTC 24 |
237638000 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1635541306 |
|
|
Sep 09 09:36:23 PM UTC 24 |
Sep 09 09:36:37 PM UTC 24 |
475526489 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2900291404 |
|
|
Sep 09 09:36:12 PM UTC 24 |
Sep 09 09:36:42 PM UTC 24 |
3459143163 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2072394221 |
|
|
Sep 09 09:28:38 PM UTC 24 |
Sep 09 09:36:48 PM UTC 24 |
14544879320 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1049688101 |
|
|
Sep 09 09:36:43 PM UTC 24 |
Sep 09 09:36:49 PM UTC 24 |
1121882860 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4213548291 |
|
|
Sep 09 09:33:33 PM UTC 24 |
Sep 09 09:36:54 PM UTC 24 |
3777298208 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2397604078 |
|
|
Sep 09 09:10:39 PM UTC 24 |
Sep 09 09:36:57 PM UTC 24 |
25743676138 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1863845429 |
|
|
Sep 09 09:36:58 PM UTC 24 |
Sep 09 09:37:00 PM UTC 24 |
71296457 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.2966009345 |
|
|
Sep 09 09:23:31 PM UTC 24 |
Sep 09 09:37:05 PM UTC 24 |
9613292942 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1723115096 |
|
|
Sep 09 09:36:37 PM UTC 24 |
Sep 09 09:37:07 PM UTC 24 |
95151246 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.332816276 |
|
|
Sep 09 09:37:06 PM UTC 24 |
Sep 09 09:37:12 PM UTC 24 |
369375395 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.962959164 |
|
|
Sep 09 09:37:01 PM UTC 24 |
Sep 09 09:37:12 PM UTC 24 |
2731584957 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3837271988 |
|
|
Sep 09 09:37:13 PM UTC 24 |
Sep 09 09:37:15 PM UTC 24 |
38068748 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1478221616 |
|
|
Sep 09 09:31:33 PM UTC 24 |
Sep 09 09:37:19 PM UTC 24 |
26731169623 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.530751028 |
|
|
Sep 09 09:30:00 PM UTC 24 |
Sep 09 09:37:30 PM UTC 24 |
60291206918 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2952644899 |
|
|
Sep 09 09:30:45 PM UTC 24 |
Sep 09 09:37:36 PM UTC 24 |
2980656850 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3516718923 |
|
|
Sep 09 09:35:32 PM UTC 24 |
Sep 09 09:37:46 PM UTC 24 |
4758873222 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1663482957 |
|
|
Sep 09 09:37:47 PM UTC 24 |
Sep 09 09:38:13 PM UTC 24 |
1202817201 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1289327973 |
|
|
Sep 09 09:29:39 PM UTC 24 |
Sep 09 09:38:31 PM UTC 24 |
19159420408 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.313159108 |
|
|
Sep 09 09:10:20 PM UTC 24 |
Sep 09 09:38:34 PM UTC 24 |
53405151945 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3355416804 |
|
|
Sep 09 09:32:24 PM UTC 24 |
Sep 09 09:38:35 PM UTC 24 |
18397613824 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.220346404 |
|
|
Sep 09 09:38:35 PM UTC 24 |
Sep 09 09:38:39 PM UTC 24 |
163910947 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.455044078 |
|
|
Sep 09 09:32:33 PM UTC 24 |
Sep 09 09:38:42 PM UTC 24 |
15856418100 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1129640332 |
|
|
Sep 09 09:38:36 PM UTC 24 |
Sep 09 09:38:45 PM UTC 24 |
663173893 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.109253055 |
|
|
Sep 09 09:36:06 PM UTC 24 |
Sep 09 09:38:49 PM UTC 24 |
1689301902 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3433205277 |
|
|
Sep 09 09:38:50 PM UTC 24 |
Sep 09 09:38:52 PM UTC 24 |
47301694 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.4213032519 |
|
|
Sep 09 09:37:31 PM UTC 24 |
Sep 09 09:38:52 PM UTC 24 |
14995390133 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.751641701 |
|
|
Sep 09 09:38:53 PM UTC 24 |
Sep 09 09:39:00 PM UTC 24 |
74944062 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3380237107 |
|
|
Sep 09 09:29:01 PM UTC 24 |
Sep 09 09:39:00 PM UTC 24 |
9342428741 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.193951106 |
|
|
Sep 09 09:37:16 PM UTC 24 |
Sep 09 09:39:00 PM UTC 24 |
654057634 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.197105194 |
|
|
Sep 09 09:38:53 PM UTC 24 |
Sep 09 09:39:01 PM UTC 24 |
162672750 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.734490805 |
|
|
Sep 09 09:39:00 PM UTC 24 |
Sep 09 09:39:02 PM UTC 24 |
27898831 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2107206017 |
|
|
Sep 09 09:38:32 PM UTC 24 |
Sep 09 09:39:03 PM UTC 24 |
89100203 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.302026163 |
|
|
Sep 09 09:23:23 PM UTC 24 |
Sep 09 09:39:27 PM UTC 24 |
5475126623 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3014138773 |
|
|
Sep 09 09:30:54 PM UTC 24 |
Sep 09 09:39:34 PM UTC 24 |
58647069176 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1556956999 |
|
|
Sep 09 09:12:04 PM UTC 24 |
Sep 09 09:39:52 PM UTC 24 |
104089218270 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.4010657560 |
|
|
Sep 09 09:33:59 PM UTC 24 |
Sep 09 09:39:54 PM UTC 24 |
28880009680 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1551841530 |
|
|
Sep 09 09:39:44 PM UTC 24 |
Sep 09 09:40:01 PM UTC 24 |
86868576 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3565295286 |
|
|
Sep 09 09:22:41 PM UTC 24 |
Sep 09 09:40:03 PM UTC 24 |
65293750236 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1531109314 |
|
|
Sep 09 09:24:48 PM UTC 24 |
Sep 09 09:40:03 PM UTC 24 |
27630174743 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.325477788 |
|
|
Sep 09 09:39:55 PM UTC 24 |
Sep 09 09:40:07 PM UTC 24 |
1343021907 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2801702846 |
|
|
Sep 09 09:36:19 PM UTC 24 |
Sep 09 09:40:08 PM UTC 24 |
4318819462 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2001855985 |
|
|
Sep 09 09:40:08 PM UTC 24 |
Sep 09 09:40:11 PM UTC 24 |
25948621 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2348372207 |
|
|
Sep 09 09:39:29 PM UTC 24 |
Sep 09 09:40:16 PM UTC 24 |
545772748 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3552763389 |
|
|
Sep 09 09:40:11 PM UTC 24 |
Sep 09 09:40:20 PM UTC 24 |
176986679 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2630642231 |
|
|
Sep 09 09:40:09 PM UTC 24 |
Sep 09 09:40:20 PM UTC 24 |
456901992 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1046131320 |
|
|
Sep 09 09:40:21 PM UTC 24 |
Sep 09 09:40:23 PM UTC 24 |
16932737 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.468071665 |
|
|
Sep 09 09:39:04 PM UTC 24 |
Sep 09 09:40:24 PM UTC 24 |
2383808140 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.795491459 |
|
|
Sep 09 09:39:52 PM UTC 24 |
Sep 09 09:40:36 PM UTC 24 |
519888968 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.894395012 |
|
|
Sep 09 09:39:02 PM UTC 24 |
Sep 09 09:40:37 PM UTC 24 |
648045921 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2182951011 |
|
|
Sep 09 09:34:25 PM UTC 24 |
Sep 09 09:40:37 PM UTC 24 |
136739830724 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.573784911 |
|
|
Sep 09 09:18:21 PM UTC 24 |
Sep 09 09:40:54 PM UTC 24 |
26276156018 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2661497016 |
|
|
Sep 09 09:40:38 PM UTC 24 |
Sep 09 09:41:09 PM UTC 24 |
313559736 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3371272487 |
|
|
Sep 09 09:40:24 PM UTC 24 |
Sep 09 09:41:10 PM UTC 24 |
3901027005 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.954255799 |
|
|
Sep 09 09:40:37 PM UTC 24 |
Sep 09 09:41:11 PM UTC 24 |
2356108247 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2987336713 |
|
|
Sep 09 09:39:04 PM UTC 24 |
Sep 09 09:41:12 PM UTC 24 |
9077571842 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1275071796 |
|
|
Sep 09 09:38:13 PM UTC 24 |
Sep 09 09:41:20 PM UTC 24 |
8616223070 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.891035501 |
|
|
Sep 09 09:24:52 PM UTC 24 |
Sep 09 09:41:21 PM UTC 24 |
111002955100 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.3202409033 |
|
|
Sep 09 09:41:11 PM UTC 24 |
Sep 09 09:41:21 PM UTC 24 |
1138836430 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1546555393 |
|
|
Sep 09 09:41:22 PM UTC 24 |
Sep 09 09:41:24 PM UTC 24 |
97825212 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.3514832241 |
|
|
Sep 09 09:33:20 PM UTC 24 |
Sep 09 09:41:28 PM UTC 24 |
24107634829 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2990879557 |
|
|
Sep 09 09:41:25 PM UTC 24 |
Sep 09 09:41:33 PM UTC 24 |
347605860 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2001229438 |
|
|
Sep 09 09:41:10 PM UTC 24 |
Sep 09 09:41:34 PM UTC 24 |
426722487 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2921792528 |
|
|
Sep 09 09:41:22 PM UTC 24 |
Sep 09 09:41:37 PM UTC 24 |
921542623 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.420933570 |
|
|
Sep 09 09:41:35 PM UTC 24 |
Sep 09 09:41:37 PM UTC 24 |
44314987 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1217143595 |
|
|
Sep 09 09:21:13 PM UTC 24 |
Sep 09 09:42:20 PM UTC 24 |
15874648244 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3913132301 |
|
|
Sep 09 09:26:07 PM UTC 24 |
Sep 09 09:42:24 PM UTC 24 |
2229073986 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3291765266 |
|
|
Sep 09 09:41:07 PM UTC 24 |
Sep 09 09:42:31 PM UTC 24 |
286562554 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3884791200 |
|
|
Sep 09 09:41:30 PM UTC 24 |
Sep 09 09:42:35 PM UTC 24 |
2212436144 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1501507016 |
|
|
Sep 09 09:31:10 PM UTC 24 |
Sep 09 09:42:42 PM UTC 24 |
6609675118 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.994011801 |
|
|
Sep 09 09:41:37 PM UTC 24 |
Sep 09 09:42:43 PM UTC 24 |
150276733 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.4105975159 |
|
|
Sep 09 09:42:21 PM UTC 24 |
Sep 09 09:42:59 PM UTC 24 |
7116368451 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3579564349 |
|
|
Sep 09 09:42:32 PM UTC 24 |
Sep 09 09:43:00 PM UTC 24 |
570436926 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3241591976 |
|
|
Sep 09 09:43:00 PM UTC 24 |
Sep 09 09:43:04 PM UTC 24 |
309277838 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.4259677203 |
|
|
Sep 09 09:42:44 PM UTC 24 |
Sep 09 09:43:20 PM UTC 24 |
106458396 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3063453695 |
|
|
Sep 09 09:28:11 PM UTC 24 |
Sep 09 09:43:25 PM UTC 24 |
46706765731 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.384217945 |
|
|
Sep 09 09:39:35 PM UTC 24 |
Sep 09 09:43:27 PM UTC 24 |
7151832793 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.4022841632 |
|
|
Sep 09 09:43:26 PM UTC 24 |
Sep 09 09:43:28 PM UTC 24 |
44204029 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2439492664 |
|
|
Sep 09 09:42:43 PM UTC 24 |
Sep 09 09:43:32 PM UTC 24 |
215194405 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3326789898 |
|
|
Sep 09 09:43:29 PM UTC 24 |
Sep 09 09:43:34 PM UTC 24 |
101613385 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1953032347 |
|
|
Sep 09 09:43:28 PM UTC 24 |
Sep 09 09:43:45 PM UTC 24 |
686899602 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.708746486 |
|
|
Sep 09 09:43:45 PM UTC 24 |
Sep 09 09:43:47 PM UTC 24 |
44366178 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3036916762 |
|
|
Sep 09 09:29:08 PM UTC 24 |
Sep 09 09:43:49 PM UTC 24 |
12265990166 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2144515062 |
|
|
Sep 09 09:30:27 PM UTC 24 |
Sep 09 09:43:56 PM UTC 24 |
10510896657 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3752632197 |
|
|
Sep 09 09:41:13 PM UTC 24 |
Sep 09 09:43:56 PM UTC 24 |
4059800169 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3313788166 |
|
|
Sep 09 09:43:33 PM UTC 24 |
Sep 09 09:44:00 PM UTC 24 |
7942103572 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.2994389713 |
|
|
Sep 09 09:43:48 PM UTC 24 |
Sep 09 09:44:06 PM UTC 24 |
839320413 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3638840873 |
|
|
Sep 09 09:15:52 PM UTC 24 |
Sep 09 09:44:09 PM UTC 24 |
38734493551 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3614462202 |
|
|
Sep 09 09:22:38 PM UTC 24 |
Sep 09 09:44:10 PM UTC 24 |
17540716814 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.12418174 |
|
|
Sep 09 09:41:37 PM UTC 24 |
Sep 09 09:44:27 PM UTC 24 |
647613410 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.8431242 |
|
|
Sep 09 09:39:28 PM UTC 24 |
Sep 09 09:44:32 PM UTC 24 |
2529966392 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.4275044690 |
|
|
Sep 09 09:44:27 PM UTC 24 |
Sep 09 09:44:36 PM UTC 24 |
805707378 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.384922497 |
|
|
Sep 09 09:43:57 PM UTC 24 |
Sep 09 09:44:40 PM UTC 24 |
10510492424 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2323810075 |
|
|
Sep 09 09:33:44 PM UTC 24 |
Sep 09 09:44:45 PM UTC 24 |
2706226056 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3275750895 |
|
|
Sep 09 09:44:46 PM UTC 24 |
Sep 09 09:44:48 PM UTC 24 |
28407679 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3568320179 |
|
|
Sep 09 09:10:36 PM UTC 24 |
Sep 09 09:44:49 PM UTC 24 |
9805120950 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1538839850 |
|
|
Sep 09 09:44:50 PM UTC 24 |
Sep 09 09:44:56 PM UTC 24 |
364120756 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1955125212 |
|
|
Sep 09 09:44:49 PM UTC 24 |
Sep 09 09:44:57 PM UTC 24 |
244047518 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3810015719 |
|
|
Sep 09 09:40:38 PM UTC 24 |
Sep 09 09:45:00 PM UTC 24 |
8764657078 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.4189095273 |
|
|
Sep 09 09:37:37 PM UTC 24 |
Sep 09 09:45:00 PM UTC 24 |
15484137362 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2978783037 |
|
|
Sep 09 09:45:00 PM UTC 24 |
Sep 09 09:45:02 PM UTC 24 |
14813336 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.610281883 |
|
|
Sep 09 09:38:46 PM UTC 24 |
Sep 09 09:45:14 PM UTC 24 |
68560924739 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2343519180 |
|
|
Sep 09 09:40:17 PM UTC 24 |
Sep 09 09:45:26 PM UTC 24 |
12892666453 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2115433352 |
|
|
Sep 09 09:44:01 PM UTC 24 |
Sep 09 09:45:30 PM UTC 24 |
385114527 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.2682582157 |
|
|
Sep 09 09:36:55 PM UTC 24 |
Sep 09 09:45:31 PM UTC 24 |
30840619253 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.2197726735 |
|
|
Sep 09 09:45:01 PM UTC 24 |
Sep 09 09:45:32 PM UTC 24 |
297470078 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3963781182 |
|
|
Sep 09 09:45:31 PM UTC 24 |
Sep 09 09:45:35 PM UTC 24 |
46612004 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.864961557 |
|
|
Sep 09 09:45:32 PM UTC 24 |
Sep 09 09:45:37 PM UTC 24 |
89328919 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3404011949 |
|
|
Sep 09 09:44:11 PM UTC 24 |
Sep 09 09:45:40 PM UTC 24 |
141795446 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.962177819 |
|
|
Sep 09 09:44:10 PM UTC 24 |
Sep 09 09:45:43 PM UTC 24 |
163660494 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3222114947 |
|
|
Sep 09 09:45:35 PM UTC 24 |
Sep 09 09:45:45 PM UTC 24 |
75959956 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3117701141 |
|
|
Sep 09 09:45:38 PM UTC 24 |
Sep 09 09:45:47 PM UTC 24 |
2557862071 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2254657144 |
|
|
Sep 09 09:45:48 PM UTC 24 |
Sep 09 09:45:50 PM UTC 24 |
95664596 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.3480750001 |
|
|
Sep 09 09:27:43 PM UTC 24 |
Sep 09 09:45:58 PM UTC 24 |
15121789430 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1983428827 |
|
|
Sep 09 09:42:37 PM UTC 24 |
Sep 09 09:46:05 PM UTC 24 |
2592443427 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1495145813 |
|
|
Sep 09 09:37:08 PM UTC 24 |
Sep 09 09:46:06 PM UTC 24 |
1888444790 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1173305832 |
|
|
Sep 09 09:45:51 PM UTC 24 |
Sep 09 09:46:06 PM UTC 24 |
459560981 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3051926013 |
|
|
Sep 09 09:45:59 PM UTC 24 |
Sep 09 09:46:07 PM UTC 24 |
217547452 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3069545018 |
|
|
Sep 09 09:46:07 PM UTC 24 |
Sep 09 09:46:09 PM UTC 24 |
44234376 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.461395862 |
|
|
Sep 09 09:42:25 PM UTC 24 |
Sep 09 09:46:20 PM UTC 24 |
1923692807 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.49311216 |
|
|
Sep 09 09:45:15 PM UTC 24 |
Sep 09 09:46:21 PM UTC 24 |
7006495770 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.295412052 |
|
|
Sep 09 09:40:55 PM UTC 24 |
Sep 09 09:46:25 PM UTC 24 |
50577264066 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2012348338 |
|
|
Sep 09 09:46:07 PM UTC 24 |
Sep 09 09:46:25 PM UTC 24 |
1165587680 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3436974950 |
|
|
Sep 09 09:46:29 PM UTC 24 |
Sep 09 09:46:41 PM UTC 24 |
414984762 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.1945605220 |
|
|
Sep 09 09:40:03 PM UTC 24 |
Sep 09 09:46:43 PM UTC 24 |
3313306597 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3389576996 |
|
|
Sep 09 09:44:41 PM UTC 24 |
Sep 09 09:46:49 PM UTC 24 |
1598933202 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2556557277 |
|
|
Sep 09 09:46:44 PM UTC 24 |
Sep 09 09:46:53 PM UTC 24 |
1845361527 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1576108798 |
|
|
Sep 09 09:46:42 PM UTC 24 |
Sep 09 09:47:27 PM UTC 24 |
408027228 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1425170361 |
|
|
Sep 09 09:46:20 PM UTC 24 |
Sep 09 09:47:33 PM UTC 24 |
16387736908 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.448760570 |
|
|
Sep 09 09:47:34 PM UTC 24 |
Sep 09 09:47:36 PM UTC 24 |
28269224 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2010331819 |
|
|
Sep 09 09:47:37 PM UTC 24 |
Sep 09 09:47:53 PM UTC 24 |
366103399 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3446782160 |
|
|
Sep 09 09:43:57 PM UTC 24 |
Sep 09 09:48:01 PM UTC 24 |
9769092769 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.448946516 |
|
|
Sep 09 09:47:54 PM UTC 24 |
Sep 09 09:48:03 PM UTC 24 |
192054135 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1771616163 |
|
|
Sep 09 09:46:26 PM UTC 24 |
Sep 09 09:48:03 PM UTC 24 |
378300324 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1765722778 |
|
|
Sep 09 09:48:04 PM UTC 24 |
Sep 09 09:48:07 PM UTC 24 |
37775626 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.883776338 |
|
|
Sep 09 09:48:07 PM UTC 24 |
Sep 09 09:50:14 PM UTC 24 |
4862583419 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3616228984 |
|
|
Sep 09 09:44:57 PM UTC 24 |
Sep 09 09:48:10 PM UTC 24 |
1493436795 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3274609636 |
|
|
Sep 09 09:40:04 PM UTC 24 |
Sep 09 09:48:12 PM UTC 24 |
56448779511 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3312759603 |
|
|
Sep 09 09:45:27 PM UTC 24 |
Sep 09 09:48:27 PM UTC 24 |
5906763303 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.1923300790 |
|
|
Sep 09 09:41:21 PM UTC 24 |
Sep 09 09:48:27 PM UTC 24 |
13528455882 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.841337619 |
|
|
Sep 09 09:54:56 PM UTC 24 |
Sep 09 09:55:14 PM UTC 24 |
1533101781 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.4132283460 |
|
|
Sep 09 09:15:56 PM UTC 24 |
Sep 09 09:48:29 PM UTC 24 |
34358197607 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3382432619 |
|
|
Sep 09 09:41:34 PM UTC 24 |
Sep 09 09:48:29 PM UTC 24 |
3734249188 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1524570752 |
|
|
Sep 09 09:48:29 PM UTC 24 |
Sep 09 09:48:35 PM UTC 24 |
168583562 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2985955906 |
|
|
Sep 09 09:48:36 PM UTC 24 |
Sep 09 09:48:40 PM UTC 24 |
65878905 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1480794842 |
|
|
Sep 09 09:48:28 PM UTC 24 |
Sep 09 09:48:46 PM UTC 24 |
4362336893 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.348769257 |
|
|
Sep 09 09:48:14 PM UTC 24 |
Sep 09 09:49:09 PM UTC 24 |
4179974584 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3152435591 |
|
|
Sep 09 09:45:31 PM UTC 24 |
Sep 09 09:49:13 PM UTC 24 |
6802917172 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1710653780 |
|
|
Sep 09 09:48:30 PM UTC 24 |
Sep 09 09:49:13 PM UTC 24 |
484090911 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1769114865 |
|
|
Sep 09 09:49:14 PM UTC 24 |
Sep 09 09:49:16 PM UTC 24 |
180560243 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3474472039 |
|
|
Sep 09 09:49:14 PM UTC 24 |
Sep 09 09:49:23 PM UTC 24 |
1876398093 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.255242117 |
|
|
Sep 09 09:49:17 PM UTC 24 |
Sep 09 09:49:27 PM UTC 24 |
231116638 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1963068464 |
|
|
Sep 09 09:49:30 PM UTC 24 |
Sep 09 09:49:33 PM UTC 24 |
27548066 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.2854257476 |
|
|
Sep 09 09:49:34 PM UTC 24 |
Sep 09 09:49:36 PM UTC 24 |
177960398 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.263518829 |
|
|
Sep 09 09:11:18 PM UTC 24 |
Sep 09 09:50:09 PM UTC 24 |
6769771245 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3655418459 |
|
|
Sep 09 09:46:22 PM UTC 24 |
Sep 09 09:50:24 PM UTC 24 |
10150300643 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2759816192 |
|
|
Sep 09 09:40:25 PM UTC 24 |
Sep 09 09:50:31 PM UTC 24 |
18746592290 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.2875148017 |
|
|
Sep 09 09:43:05 PM UTC 24 |
Sep 09 09:50:41 PM UTC 24 |
38690220976 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.342666958 |
|
|
Sep 09 09:35:12 PM UTC 24 |
Sep 09 09:50:47 PM UTC 24 |
62311327918 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3080352338 |
|
|
Sep 09 09:38:43 PM UTC 24 |
Sep 09 09:50:56 PM UTC 24 |
8581951261 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2471162461 |
|
|
Sep 09 09:46:10 PM UTC 24 |
Sep 09 09:50:58 PM UTC 24 |
1971016252 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.418096561 |
|
|
Sep 09 09:40:04 PM UTC 24 |
Sep 09 09:51:03 PM UTC 24 |
2455343754 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2039332478 |
|
|
Sep 09 09:50:57 PM UTC 24 |
Sep 09 09:51:07 PM UTC 24 |
877944815 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1856822327 |
|
|
Sep 09 09:44:06 PM UTC 24 |
Sep 09 09:51:07 PM UTC 24 |
13833010563 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1104647050 |
|
|
Sep 09 09:51:08 PM UTC 24 |
Sep 09 09:51:10 PM UTC 24 |
47532258 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.2897518953 |
|
|
Sep 09 09:51:11 PM UTC 24 |
Sep 09 09:51:19 PM UTC 24 |
95241471 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2177538265 |
|
|
Sep 09 09:50:10 PM UTC 24 |
Sep 09 09:51:22 PM UTC 24 |
2526872251 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1916872282 |
|
|
Sep 09 09:45:04 PM UTC 24 |
Sep 09 09:51:26 PM UTC 24 |
2861709135 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3840501210 |
|
|
Sep 09 09:51:20 PM UTC 24 |
Sep 09 09:51:26 PM UTC 24 |
99465679 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.380598590 |
|
|
Sep 09 09:50:48 PM UTC 24 |
Sep 09 09:51:27 PM UTC 24 |
1238231646 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.852773564 |
|
|
Sep 09 09:51:28 PM UTC 24 |
Sep 09 09:51:29 PM UTC 24 |
21318733 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.802655723 |
|
|
Sep 09 09:51:28 PM UTC 24 |
Sep 09 09:51:30 PM UTC 24 |
51550955 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.2367865921 |
|
|
Sep 09 09:47:28 PM UTC 24 |
Sep 09 09:51:34 PM UTC 24 |
7829027547 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.171084812 |
|
|
Sep 09 09:30:10 PM UTC 24 |
Sep 09 09:51:42 PM UTC 24 |
18864708145 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2152849361 |
|
|
Sep 09 09:50:25 PM UTC 24 |
Sep 09 09:51:46 PM UTC 24 |
2371832706 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3889428898 |
|
|
Sep 09 09:50:41 PM UTC 24 |
Sep 09 09:51:47 PM UTC 24 |
453581646 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.3266449849 |
|
|
Sep 09 09:51:47 PM UTC 24 |
Sep 09 09:51:54 PM UTC 24 |
48986901 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3347046328 |
|
|
Sep 09 09:51:55 PM UTC 24 |
Sep 09 09:51:59 PM UTC 24 |
73188799 ps |