| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3701342779 |
|
|
Sep 09 10:12:35 PM UTC 24 |
Sep 09 10:14:08 PM UTC 24 |
277793657 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3986218046 |
|
|
Sep 09 10:13:53 PM UTC 24 |
Sep 09 10:14:09 PM UTC 24 |
761094957 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1232433372 |
|
|
Sep 09 10:14:10 PM UTC 24 |
Sep 09 10:14:12 PM UTC 24 |
73088884 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1097775855 |
|
|
Sep 09 10:07:23 PM UTC 24 |
Sep 09 10:14:19 PM UTC 24 |
57262634629 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2971705894 |
|
|
Sep 09 10:14:20 PM UTC 24 |
Sep 09 10:14:25 PM UTC 24 |
104290553 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2126928267 |
|
|
Sep 09 10:14:13 PM UTC 24 |
Sep 09 10:14:27 PM UTC 24 |
448267798 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.2989547444 |
|
|
Sep 09 10:05:24 PM UTC 24 |
Sep 09 10:14:32 PM UTC 24 |
20419456504 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3941304770 |
|
|
Sep 09 10:14:33 PM UTC 24 |
Sep 09 10:14:35 PM UTC 24 |
32113305 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.2749734976 |
|
|
Sep 09 10:13:05 PM UTC 24 |
Sep 09 10:14:46 PM UTC 24 |
643167564 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.388683727 |
|
|
Sep 09 10:13:37 PM UTC 24 |
Sep 09 10:14:47 PM UTC 24 |
243759500 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2132387275 |
|
|
Sep 09 10:13:11 PM UTC 24 |
Sep 09 10:14:51 PM UTC 24 |
21690444647 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.4098967354 |
|
|
Sep 09 10:14:36 PM UTC 24 |
Sep 09 10:14:54 PM UTC 24 |
229082787 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.2110947288 |
|
|
Sep 09 10:14:55 PM UTC 24 |
Sep 09 10:15:12 PM UTC 24 |
962075155 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.85595924 |
|
|
Sep 09 10:03:09 PM UTC 24 |
Sep 09 10:15:12 PM UTC 24 |
11178884559 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3439578778 |
|
|
Sep 09 10:14:47 PM UTC 24 |
Sep 09 10:15:29 PM UTC 24 |
5939618247 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3877537361 |
|
|
Sep 09 10:11:25 PM UTC 24 |
Sep 09 10:15:30 PM UTC 24 |
33305712027 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.964221763 |
|
|
Sep 09 10:15:13 PM UTC 24 |
Sep 09 10:15:31 PM UTC 24 |
77738063 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.839150513 |
|
|
Sep 09 10:12:41 PM UTC 24 |
Sep 09 10:15:31 PM UTC 24 |
15616321629 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1852697704 |
|
|
Sep 09 10:10:01 PM UTC 24 |
Sep 09 10:15:31 PM UTC 24 |
17886321709 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1986744544 |
|
|
Sep 09 10:15:29 PM UTC 24 |
Sep 09 10:15:36 PM UTC 24 |
56014284 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.1761888428 |
|
|
Sep 09 10:15:37 PM UTC 24 |
Sep 09 10:15:39 PM UTC 24 |
125368419 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2273209983 |
|
|
Sep 09 10:02:19 PM UTC 24 |
Sep 09 10:15:40 PM UTC 24 |
75392660941 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.4276168050 |
|
|
Sep 09 10:15:30 PM UTC 24 |
Sep 09 10:15:42 PM UTC 24 |
2086966849 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3585080222 |
|
|
Sep 09 10:14:47 PM UTC 24 |
Sep 09 10:15:48 PM UTC 24 |
12103427112 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1871668001 |
|
|
Sep 09 10:10:02 PM UTC 24 |
Sep 09 10:15:49 PM UTC 24 |
48809619580 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3061174391 |
|
|
Sep 09 10:15:41 PM UTC 24 |
Sep 09 10:15:50 PM UTC 24 |
399106236 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1107416695 |
|
|
Sep 09 10:15:50 PM UTC 24 |
Sep 09 10:15:52 PM UTC 24 |
13581061 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2456782711 |
|
|
Sep 09 10:15:40 PM UTC 24 |
Sep 09 10:15:58 PM UTC 24 |
6540947218 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3681949898 |
|
|
Sep 09 10:00:19 PM UTC 24 |
Sep 09 10:16:01 PM UTC 24 |
12470133410 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3320963967 |
|
|
Sep 09 10:15:50 PM UTC 24 |
Sep 09 10:16:13 PM UTC 24 |
944133754 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3038830289 |
|
|
Sep 09 10:15:31 PM UTC 24 |
Sep 09 10:16:25 PM UTC 24 |
558225044 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3896832821 |
|
|
Sep 09 10:15:59 PM UTC 24 |
Sep 09 10:16:26 PM UTC 24 |
4725359719 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3710209918 |
|
|
Sep 09 10:14:04 PM UTC 24 |
Sep 09 10:16:29 PM UTC 24 |
10574441802 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2860756827 |
|
|
Sep 09 09:51:31 PM UTC 24 |
Sep 09 10:16:31 PM UTC 24 |
157162539073 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.528406555 |
|
|
Sep 09 09:57:53 PM UTC 24 |
Sep 09 10:16:35 PM UTC 24 |
12371316404 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3430740508 |
|
|
Sep 09 10:16:31 PM UTC 24 |
Sep 09 10:16:35 PM UTC 24 |
283296960 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.241921726 |
|
|
Sep 09 10:12:31 PM UTC 24 |
Sep 09 10:16:41 PM UTC 24 |
3601721033 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1922981670 |
|
|
Sep 09 10:11:33 PM UTC 24 |
Sep 09 10:16:52 PM UTC 24 |
39405599750 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3464367745 |
|
|
Sep 09 10:16:14 PM UTC 24 |
Sep 09 10:16:53 PM UTC 24 |
140464749 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.3713514445 |
|
|
Sep 09 10:16:53 PM UTC 24 |
Sep 09 10:16:55 PM UTC 24 |
107383105 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1830001823 |
|
|
Sep 09 10:16:54 PM UTC 24 |
Sep 09 10:17:03 PM UTC 24 |
379320954 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1763208424 |
|
|
Sep 09 10:16:56 PM UTC 24 |
Sep 09 10:17:03 PM UTC 24 |
683079278 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2263242000 |
|
|
Sep 09 10:16:42 PM UTC 24 |
Sep 09 10:17:11 PM UTC 24 |
1570771412 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3624111378 |
|
|
Sep 09 10:17:12 PM UTC 24 |
Sep 09 10:17:14 PM UTC 24 |
16074669 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2495862566 |
|
|
Sep 09 10:12:18 PM UTC 24 |
Sep 09 10:17:21 PM UTC 24 |
12757464368 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1251141288 |
|
|
Sep 09 10:06:42 PM UTC 24 |
Sep 09 10:17:27 PM UTC 24 |
2612857435 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.569779026 |
|
|
Sep 09 10:17:15 PM UTC 24 |
Sep 09 10:17:35 PM UTC 24 |
3633042164 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3553001250 |
|
|
Sep 09 10:16:30 PM UTC 24 |
Sep 09 10:17:46 PM UTC 24 |
544915875 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.58996153 |
|
|
Sep 09 10:17:47 PM UTC 24 |
Sep 09 10:17:49 PM UTC 24 |
107272729 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.709532240 |
|
|
Sep 09 10:14:53 PM UTC 24 |
Sep 09 10:18:00 PM UTC 24 |
4057485080 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1428448754 |
|
|
Sep 09 10:17:04 PM UTC 24 |
Sep 09 10:18:05 PM UTC 24 |
523844873 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1261486416 |
|
|
Sep 09 10:13:26 PM UTC 24 |
Sep 09 10:18:08 PM UTC 24 |
10461530361 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.966654362 |
|
|
Sep 09 10:15:43 PM UTC 24 |
Sep 09 10:18:09 PM UTC 24 |
2305740586 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2625643400 |
|
|
Sep 09 10:18:09 PM UTC 24 |
Sep 09 10:18:24 PM UTC 24 |
5438053740 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4205045334 |
|
|
Sep 09 10:16:27 PM UTC 24 |
Sep 09 10:18:26 PM UTC 24 |
517191884 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.4022830780 |
|
|
Sep 09 10:10:34 PM UTC 24 |
Sep 09 10:18:32 PM UTC 24 |
23650775364 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.826900573 |
|
|
Sep 09 10:18:33 PM UTC 24 |
Sep 09 10:18:35 PM UTC 24 |
28146377 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1639107375 |
|
|
Sep 09 10:17:28 PM UTC 24 |
Sep 09 10:18:40 PM UTC 24 |
2703547180 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3448875890 |
|
|
Sep 09 10:18:36 PM UTC 24 |
Sep 09 10:18:44 PM UTC 24 |
466855561 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.946112314 |
|
|
Sep 09 09:37:12 PM UTC 24 |
Sep 09 10:18:45 PM UTC 24 |
365712679319 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2522105454 |
|
|
Sep 09 10:18:41 PM UTC 24 |
Sep 09 10:18:48 PM UTC 24 |
91348143 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2612052289 |
|
|
Sep 09 10:18:49 PM UTC 24 |
Sep 09 10:18:51 PM UTC 24 |
26012617 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.2341390979 |
|
|
Sep 09 10:18:52 PM UTC 24 |
Sep 09 10:19:07 PM UTC 24 |
191971718 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1167531042 |
|
|
Sep 09 10:13:23 PM UTC 24 |
Sep 09 10:19:10 PM UTC 24 |
36816032459 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.734813585 |
|
|
Sep 09 10:18:01 PM UTC 24 |
Sep 09 10:19:35 PM UTC 24 |
543703583 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2873990135 |
|
|
Sep 09 10:19:11 PM UTC 24 |
Sep 09 10:19:47 PM UTC 24 |
3459470489 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3499532581 |
|
|
Sep 09 10:18:06 PM UTC 24 |
Sep 09 10:19:59 PM UTC 24 |
179655083 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1825429657 |
|
|
Sep 09 10:17:22 PM UTC 24 |
Sep 09 10:20:04 PM UTC 24 |
8962542690 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3501297551 |
|
|
Sep 09 10:18:46 PM UTC 24 |
Sep 09 10:20:07 PM UTC 24 |
1709444534 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1868918915 |
|
|
Sep 09 10:20:08 PM UTC 24 |
Sep 09 10:20:19 PM UTC 24 |
256318910 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2345041098 |
|
|
Sep 09 10:15:13 PM UTC 24 |
Sep 09 10:20:27 PM UTC 24 |
18507423058 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2005777907 |
|
|
Sep 09 10:19:48 PM UTC 24 |
Sep 09 10:20:36 PM UTC 24 |
1737074210 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1686802988 |
|
|
Sep 09 10:20:21 PM UTC 24 |
Sep 09 10:20:36 PM UTC 24 |
722333824 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.4078706829 |
|
|
Sep 09 10:15:33 PM UTC 24 |
Sep 09 10:20:55 PM UTC 24 |
7372930474 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4284312104 |
|
|
Sep 09 10:20:56 PM UTC 24 |
Sep 09 10:20:58 PM UTC 24 |
47481512 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2755718323 |
|
|
Sep 09 10:08:49 PM UTC 24 |
Sep 09 10:20:59 PM UTC 24 |
19443694079 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.813530312 |
|
|
Sep 09 10:20:59 PM UTC 24 |
Sep 09 10:21:06 PM UTC 24 |
141381832 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1838633904 |
|
|
Sep 09 10:21:00 PM UTC 24 |
Sep 09 10:21:10 PM UTC 24 |
1130697389 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1454096682 |
|
|
Sep 09 10:16:03 PM UTC 24 |
Sep 09 10:21:16 PM UTC 24 |
38650550461 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2932519812 |
|
|
Sep 09 10:21:17 PM UTC 24 |
Sep 09 10:21:19 PM UTC 24 |
14222300 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2634343921 |
|
|
Sep 09 10:07:59 PM UTC 24 |
Sep 09 10:21:27 PM UTC 24 |
12154365546 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.786276155 |
|
|
Sep 09 10:10:42 PM UTC 24 |
Sep 09 10:21:29 PM UTC 24 |
4956553186 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.329932868 |
|
|
Sep 09 10:06:34 PM UTC 24 |
Sep 09 10:21:31 PM UTC 24 |
3629766865 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.3616736909 |
|
|
Sep 09 10:09:41 PM UTC 24 |
Sep 09 10:21:34 PM UTC 24 |
11747368042 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3734171877 |
|
|
Sep 09 10:12:15 PM UTC 24 |
Sep 09 10:21:34 PM UTC 24 |
14244252841 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.2018120165 |
|
|
Sep 09 10:12:41 PM UTC 24 |
Sep 09 10:21:54 PM UTC 24 |
10648096204 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1402509826 |
|
|
Sep 09 10:20:04 PM UTC 24 |
Sep 09 10:21:55 PM UTC 24 |
1278865681 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1264957365 |
|
|
Sep 09 10:14:26 PM UTC 24 |
Sep 09 10:22:02 PM UTC 24 |
6610651088 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.403640743 |
|
|
Sep 09 10:10:30 PM UTC 24 |
Sep 09 10:22:03 PM UTC 24 |
22415409280 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.583152750 |
|
|
Sep 09 10:07:53 PM UTC 24 |
Sep 09 10:22:16 PM UTC 24 |
13798890914 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3391494028 |
|
|
Sep 09 10:16:26 PM UTC 24 |
Sep 09 10:22:17 PM UTC 24 |
4663423626 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3859849920 |
|
|
Sep 09 10:01:56 PM UTC 24 |
Sep 09 10:22:26 PM UTC 24 |
11694388991 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.944264035 |
|
|
Sep 09 10:00:06 PM UTC 24 |
Sep 09 10:23:06 PM UTC 24 |
32970484599 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.1877162159 |
|
|
Sep 09 10:14:10 PM UTC 24 |
Sep 09 10:23:09 PM UTC 24 |
13593136611 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1739102532 |
|
|
Sep 09 10:17:36 PM UTC 24 |
Sep 09 10:23:15 PM UTC 24 |
6103812173 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.2821555068 |
|
|
Sep 09 10:16:36 PM UTC 24 |
Sep 09 10:23:17 PM UTC 24 |
12872893554 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2061779396 |
|
|
Sep 09 10:09:59 PM UTC 24 |
Sep 09 10:23:22 PM UTC 24 |
7216489639 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3994574194 |
|
|
Sep 09 10:11:48 PM UTC 24 |
Sep 09 10:23:40 PM UTC 24 |
2854397021 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1878813311 |
|
|
Sep 09 10:15:53 PM UTC 24 |
Sep 09 10:23:40 PM UTC 24 |
4140439393 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.433048016 |
|
|
Sep 09 10:19:36 PM UTC 24 |
Sep 09 10:24:10 PM UTC 24 |
12738828165 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2794051669 |
|
|
Sep 09 10:21:06 PM UTC 24 |
Sep 09 10:24:27 PM UTC 24 |
2719501974 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2608954777 |
|
|
Sep 09 10:16:35 PM UTC 24 |
Sep 09 10:24:43 PM UTC 24 |
15112651365 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3590437443 |
|
|
Sep 09 10:20:00 PM UTC 24 |
Sep 09 10:24:56 PM UTC 24 |
3751769510 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3406168259 |
|
|
Sep 09 10:15:49 PM UTC 24 |
Sep 09 10:24:56 PM UTC 24 |
48622073289 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3246213488 |
|
|
Sep 09 09:48:03 PM UTC 24 |
Sep 09 10:25:17 PM UTC 24 |
33412340614 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2637683954 |
|
|
Sep 09 10:11:41 PM UTC 24 |
Sep 09 10:26:36 PM UTC 24 |
3479462438 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3674048597 |
|
|
Sep 09 10:17:50 PM UTC 24 |
Sep 09 10:26:50 PM UTC 24 |
82539233258 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3108846126 |
|
|
Sep 09 10:14:03 PM UTC 24 |
Sep 09 10:26:51 PM UTC 24 |
3025311312 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2456461404 |
|
|
Sep 09 10:19:09 PM UTC 24 |
Sep 09 10:27:34 PM UTC 24 |
8521579679 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2829481399 |
|
|
Sep 09 10:12:41 PM UTC 24 |
Sep 09 10:30:31 PM UTC 24 |
3848918680 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1559401058 |
|
|
Sep 09 10:13:06 PM UTC 24 |
Sep 09 10:30:56 PM UTC 24 |
68515372622 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.415729008 |
|
|
Sep 09 10:08:35 PM UTC 24 |
Sep 09 10:31:45 PM UTC 24 |
25431411481 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.255987593 |
|
|
Sep 09 10:15:33 PM UTC 24 |
Sep 09 10:31:49 PM UTC 24 |
14689568245 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1221839982 |
|
|
Sep 09 10:14:28 PM UTC 24 |
Sep 09 10:31:54 PM UTC 24 |
5771882284 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1873558233 |
|
|
Sep 09 10:20:28 PM UTC 24 |
Sep 09 10:32:03 PM UTC 24 |
16248364899 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1089157095 |
|
|
Sep 09 09:40:21 PM UTC 24 |
Sep 09 10:32:12 PM UTC 24 |
373921730125 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1410474523 |
|
|
Sep 09 10:11:13 PM UTC 24 |
Sep 09 10:32:38 PM UTC 24 |
21587179068 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1332778061 |
|
|
Sep 09 10:09:54 PM UTC 24 |
Sep 09 10:33:25 PM UTC 24 |
121011586997 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3272937204 |
|
|
Sep 09 10:18:45 PM UTC 24 |
Sep 09 10:33:25 PM UTC 24 |
13917808890 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.4100026363 |
|
|
Sep 09 10:20:38 PM UTC 24 |
Sep 09 10:34:44 PM UTC 24 |
58419515395 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1203793411 |
|
|
Sep 09 10:18:25 PM UTC 24 |
Sep 09 10:35:20 PM UTC 24 |
12818707454 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.609653942 |
|
|
Sep 09 10:20:37 PM UTC 24 |
Sep 09 10:36:56 PM UTC 24 |
12969710796 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1400945161 |
|
|
Sep 09 10:18:09 PM UTC 24 |
Sep 09 10:37:00 PM UTC 24 |
4136899571 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1857400860 |
|
|
Sep 09 09:16:52 PM UTC 24 |
Sep 09 10:37:53 PM UTC 24 |
78545525403 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.3054304969 |
|
|
Sep 09 09:43:35 PM UTC 24 |
Sep 09 10:38:06 PM UTC 24 |
39575276438 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3041966019 |
|
|
Sep 09 10:03:30 PM UTC 24 |
Sep 09 10:38:07 PM UTC 24 |
42343203622 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3317356975 |
|
|
Sep 09 09:58:24 PM UTC 24 |
Sep 09 10:38:43 PM UTC 24 |
156516140551 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3450822083 |
|
|
Sep 09 09:33:34 PM UTC 24 |
Sep 09 10:39:22 PM UTC 24 |
11357350089 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.353715702 |
|
|
Sep 09 10:18:27 PM UTC 24 |
Sep 09 10:41:31 PM UTC 24 |
8736979821 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2287156237 |
|
|
Sep 09 10:11:42 PM UTC 24 |
Sep 09 10:42:02 PM UTC 24 |
77694942425 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.947897980 |
|
|
Sep 09 10:12:05 PM UTC 24 |
Sep 09 10:42:13 PM UTC 24 |
37622372037 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1526237369 |
|
|
Sep 09 10:02:11 PM UTC 24 |
Sep 09 10:42:19 PM UTC 24 |
190737796878 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.749415198 |
|
|
Sep 09 09:52:56 PM UTC 24 |
Sep 09 10:42:50 PM UTC 24 |
47243314458 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1738208334 |
|
|
Sep 09 09:54:52 PM UTC 24 |
Sep 09 10:43:42 PM UTC 24 |
75965310872 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3299034055 |
|
|
Sep 09 09:31:57 PM UTC 24 |
Sep 09 10:43:46 PM UTC 24 |
27833890515 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1553347281 |
|
|
Sep 09 09:56:25 PM UTC 24 |
Sep 09 10:47:14 PM UTC 24 |
98119229142 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.2390460804 |
|
|
Sep 09 10:10:57 PM UTC 24 |
Sep 09 10:49:50 PM UTC 24 |
44379134172 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.4015427557 |
|
|
Sep 09 10:17:04 PM UTC 24 |
Sep 09 10:51:04 PM UTC 24 |
67858964748 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3805173229 |
|
|
Sep 09 10:05:19 PM UTC 24 |
Sep 09 10:52:43 PM UTC 24 |
176693380925 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1910551708 |
|
|
Sep 09 10:12:57 PM UTC 24 |
Sep 09 10:53:16 PM UTC 24 |
184530654979 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3272548965 |
|
|
Sep 09 09:49:27 PM UTC 24 |
Sep 09 10:53:43 PM UTC 24 |
49939577322 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3545533067 |
|
|
Sep 09 09:51:27 PM UTC 24 |
Sep 09 10:54:12 PM UTC 24 |
13304340009 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.391351432 |
|
|
Sep 09 10:21:11 PM UTC 24 |
Sep 09 11:37:34 PM UTC 24 |
86969597035 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3282673067 |
|
|
Sep 09 10:21:20 PM UTC 24 |
Sep 09 10:21:27 PM UTC 24 |
1411726524 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3025171134 |
|
|
Sep 09 10:21:29 PM UTC 24 |
Sep 09 10:21:31 PM UTC 24 |
29806900 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1716306756 |
|
|
Sep 09 10:21:28 PM UTC 24 |
Sep 09 10:21:33 PM UTC 24 |
1435753633 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.405743780 |
|
|
Sep 09 10:21:31 PM UTC 24 |
Sep 09 10:21:33 PM UTC 24 |
14356842 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3385798521 |
|
|
Sep 09 10:21:28 PM UTC 24 |
Sep 09 10:21:35 PM UTC 24 |
482217178 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1775763447 |
|
|
Sep 09 10:21:33 PM UTC 24 |
Sep 09 10:21:36 PM UTC 24 |
30588479 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4011131533 |
|
|
Sep 09 10:21:32 PM UTC 24 |
Sep 09 10:21:36 PM UTC 24 |
43978832 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3771080170 |
|
|
Sep 09 10:21:35 PM UTC 24 |
Sep 09 10:21:37 PM UTC 24 |
30311075 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1066947305 |
|
|
Sep 09 10:21:37 PM UTC 24 |
Sep 09 10:21:39 PM UTC 24 |
20465499 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2147711242 |
|
|
Sep 09 10:21:37 PM UTC 24 |
Sep 09 10:21:39 PM UTC 24 |
14196479 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3231666879 |
|
|
Sep 09 10:21:36 PM UTC 24 |
Sep 09 10:21:40 PM UTC 24 |
81647540 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2627590346 |
|
|
Sep 09 10:21:35 PM UTC 24 |
Sep 09 10:21:40 PM UTC 24 |
214519199 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2868146737 |
|
|
Sep 09 10:21:37 PM UTC 24 |
Sep 09 10:21:41 PM UTC 24 |
101608078 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1601908654 |
|
|
Sep 09 10:21:39 PM UTC 24 |
Sep 09 10:21:42 PM UTC 24 |
45900237 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.496910488 |
|
|
Sep 09 10:21:38 PM UTC 24 |
Sep 09 10:21:42 PM UTC 24 |
463646672 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3505249936 |
|
|
Sep 09 10:21:41 PM UTC 24 |
Sep 09 10:21:43 PM UTC 24 |
71274485 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4201775834 |
|
|
Sep 09 10:21:41 PM UTC 24 |
Sep 09 10:21:44 PM UTC 24 |
99600899 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2414886923 |
|
|
Sep 09 10:21:43 PM UTC 24 |
Sep 09 10:21:45 PM UTC 24 |
14015044 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2488080049 |
|
|
Sep 09 10:21:42 PM UTC 24 |
Sep 09 10:21:46 PM UTC 24 |
118877381 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1832234074 |
|
|
Sep 09 10:21:45 PM UTC 24 |
Sep 09 10:21:47 PM UTC 24 |
64775820 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2506689302 |
|
|
Sep 09 10:21:45 PM UTC 24 |
Sep 09 10:21:48 PM UTC 24 |
190940802 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1299564260 |
|
|
Sep 09 10:21:43 PM UTC 24 |
Sep 09 10:21:49 PM UTC 24 |
254636363 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2048310026 |
|
|
Sep 09 10:21:41 PM UTC 24 |
Sep 09 10:21:49 PM UTC 24 |
1870784094 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.883652804 |
|
|
Sep 09 10:21:47 PM UTC 24 |
Sep 09 10:21:49 PM UTC 24 |
15279839 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2466554963 |
|
|
Sep 09 10:21:48 PM UTC 24 |
Sep 09 10:21:50 PM UTC 24 |
19796906 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.736508002 |
|
|
Sep 09 10:21:48 PM UTC 24 |
Sep 09 10:21:52 PM UTC 24 |
222366258 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.640420078 |
|
|
Sep 09 10:21:50 PM UTC 24 |
Sep 09 10:21:52 PM UTC 24 |
17389395 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.297524828 |
|
|
Sep 09 10:21:51 PM UTC 24 |
Sep 09 10:21:53 PM UTC 24 |
32803516 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.818811581 |
|
|
Sep 09 10:21:50 PM UTC 24 |
Sep 09 10:21:54 PM UTC 24 |
278593594 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.407648355 |
|
|
Sep 09 10:21:50 PM UTC 24 |
Sep 09 10:21:54 PM UTC 24 |
220497658 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1016505673 |
|
|
Sep 09 10:21:52 PM UTC 24 |
Sep 09 10:21:54 PM UTC 24 |
61536906 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.740044777 |
|
|
Sep 09 10:21:54 PM UTC 24 |
Sep 09 10:21:56 PM UTC 24 |
16829516 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4154817081 |
|
|
Sep 09 10:21:52 PM UTC 24 |
Sep 09 10:21:56 PM UTC 24 |
47671035 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1624871536 |
|
|
Sep 09 10:21:50 PM UTC 24 |
Sep 09 10:21:56 PM UTC 24 |
124780915 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.393029372 |
|
|
Sep 09 10:21:55 PM UTC 24 |
Sep 09 10:21:57 PM UTC 24 |
58309958 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.606973348 |
|
|
Sep 09 10:21:56 PM UTC 24 |
Sep 09 10:21:58 PM UTC 24 |
12161336 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2063378075 |
|
|
Sep 09 10:21:56 PM UTC 24 |
Sep 09 10:21:58 PM UTC 24 |
40134116 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1510513426 |
|
|
Sep 09 10:21:58 PM UTC 24 |
Sep 09 10:22:00 PM UTC 24 |
54848268 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3986528351 |
|
|
Sep 09 10:21:55 PM UTC 24 |
Sep 09 10:22:00 PM UTC 24 |
458649948 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1838208697 |
|
|
Sep 09 10:21:58 PM UTC 24 |
Sep 09 10:22:01 PM UTC 24 |
569739477 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1483442190 |
|
|
Sep 09 10:21:59 PM UTC 24 |
Sep 09 10:22:01 PM UTC 24 |
53813029 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1284968474 |
|
|
Sep 09 10:21:56 PM UTC 24 |
Sep 09 10:22:02 PM UTC 24 |
584840258 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1868186277 |
|
|
Sep 09 10:21:59 PM UTC 24 |
Sep 09 10:22:02 PM UTC 24 |
47363788 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3708926011 |
|
|
Sep 09 10:22:02 PM UTC 24 |
Sep 09 10:22:04 PM UTC 24 |
14296618 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3958353877 |
|
|
Sep 09 10:22:02 PM UTC 24 |
Sep 09 10:22:04 PM UTC 24 |
105220625 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2677053102 |
|
|
Sep 09 10:21:56 PM UTC 24 |
Sep 09 10:22:05 PM UTC 24 |
138281701 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4086329308 |
|
|
Sep 09 10:22:02 PM UTC 24 |
Sep 09 10:22:06 PM UTC 24 |
466968261 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2625967648 |
|
|
Sep 09 10:22:00 PM UTC 24 |
Sep 09 10:22:06 PM UTC 24 |
130359127 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1676865583 |
|
|
Sep 09 10:22:05 PM UTC 24 |
Sep 09 10:22:06 PM UTC 24 |
61003291 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3139155205 |
|
|
Sep 09 10:22:05 PM UTC 24 |
Sep 09 10:22:06 PM UTC 24 |
27968742 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3318572390 |
|
|
Sep 09 10:21:59 PM UTC 24 |
Sep 09 10:22:07 PM UTC 24 |
785170297 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2258962248 |
|
|
Sep 09 10:22:03 PM UTC 24 |
Sep 09 10:22:07 PM UTC 24 |
801320287 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2178894938 |
|
|
Sep 09 10:22:03 PM UTC 24 |
Sep 09 10:22:07 PM UTC 24 |
50424663 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.578382188 |
|
|
Sep 09 10:22:04 PM UTC 24 |
Sep 09 10:22:08 PM UTC 24 |
222635556 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1792919220 |
|
|
Sep 09 10:22:07 PM UTC 24 |
Sep 09 10:22:09 PM UTC 24 |
37592746 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3117577212 |
|
|
Sep 09 10:22:03 PM UTC 24 |
Sep 09 10:22:10 PM UTC 24 |
428541073 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2746939514 |
|
|
Sep 09 10:22:09 PM UTC 24 |
Sep 09 10:22:14 PM UTC 24 |
105065049 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.297930033 |
|
|
Sep 09 10:22:07 PM UTC 24 |
Sep 09 10:22:11 PM UTC 24 |
370239895 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.983817203 |
|
|
Sep 09 10:22:09 PM UTC 24 |
Sep 09 10:22:11 PM UTC 24 |
33409608 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.367612 |
|
|
Sep 09 10:22:07 PM UTC 24 |
Sep 09 10:22:11 PM UTC 24 |
165505111 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1635232833 |
|
|
Sep 09 10:22:09 PM UTC 24 |
Sep 09 10:22:11 PM UTC 24 |
116492351 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3497656936 |
|
|
Sep 09 10:22:07 PM UTC 24 |
Sep 09 10:22:12 PM UTC 24 |
486694758 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3887367800 |
|
|
Sep 09 10:22:10 PM UTC 24 |
Sep 09 10:22:12 PM UTC 24 |
58441308 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3296115355 |
|
|
Sep 09 10:22:09 PM UTC 24 |
Sep 09 10:22:13 PM UTC 24 |
840350193 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3121083509 |
|
|
Sep 09 10:22:10 PM UTC 24 |
Sep 09 10:22:13 PM UTC 24 |
386946519 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.376052990 |
|
|
Sep 09 10:22:12 PM UTC 24 |
Sep 09 10:22:14 PM UTC 24 |
22998693 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.433494158 |
|
|
Sep 09 10:22:12 PM UTC 24 |
Sep 09 10:22:15 PM UTC 24 |
37706470 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2457440130 |
|
|
Sep 09 10:22:14 PM UTC 24 |
Sep 09 10:22:16 PM UTC 24 |
17443740 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3792933379 |
|
|
Sep 09 10:22:14 PM UTC 24 |
Sep 09 10:22:16 PM UTC 24 |
24303549 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.618356102 |
|
|
Sep 09 10:22:12 PM UTC 24 |
Sep 09 10:22:16 PM UTC 24 |
704862483 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1948737806 |
|
|
Sep 09 10:22:14 PM UTC 24 |
Sep 09 10:22:17 PM UTC 24 |
35177815 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2758755680 |
|
|
Sep 09 10:22:12 PM UTC 24 |
Sep 09 10:22:17 PM UTC 24 |
240388761 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2666260611 |
|
|
Sep 09 10:22:12 PM UTC 24 |
Sep 09 10:22:17 PM UTC 24 |
264540071 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.676696747 |
|
|
Sep 09 10:22:16 PM UTC 24 |
Sep 09 10:22:18 PM UTC 24 |
18072641 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2983751432 |
|
|
Sep 09 10:22:16 PM UTC 24 |
Sep 09 10:22:18 PM UTC 24 |
105887419 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.480784910 |
|
|
Sep 09 10:22:17 PM UTC 24 |
Sep 09 10:22:20 PM UTC 24 |
20119670 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.513348669 |
|
|
Sep 09 10:22:18 PM UTC 24 |
Sep 09 10:22:20 PM UTC 24 |
41511775 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2856853576 |
|
|
Sep 09 10:22:16 PM UTC 24 |
Sep 09 10:22:20 PM UTC 24 |
1304731390 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.887441607 |
|
|
Sep 09 10:22:18 PM UTC 24 |
Sep 09 10:22:20 PM UTC 24 |
25469786 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4246834885 |
|
|
Sep 09 10:22:18 PM UTC 24 |
Sep 09 10:22:20 PM UTC 24 |
158487628 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3937641327 |
|
|
Sep 09 10:22:16 PM UTC 24 |
Sep 09 10:22:21 PM UTC 24 |
102391105 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1709214355 |
|
|
Sep 09 10:22:19 PM UTC 24 |
Sep 09 10:22:21 PM UTC 24 |
97357521 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2114987436 |
|
|
Sep 09 10:22:18 PM UTC 24 |
Sep 09 10:22:22 PM UTC 24 |
313541760 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1594224705 |
|
|
Sep 09 10:22:18 PM UTC 24 |
Sep 09 10:22:22 PM UTC 24 |
980011142 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4047369903 |
|
|
Sep 09 10:22:18 PM UTC 24 |
Sep 09 10:22:23 PM UTC 24 |
2099352603 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3667014220 |
|
|
Sep 09 10:22:21 PM UTC 24 |
Sep 09 10:22:23 PM UTC 24 |
39534071 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2068634734 |
|
|
Sep 09 10:22:21 PM UTC 24 |
Sep 09 10:22:23 PM UTC 24 |
41969142 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2277383935 |
|
|
Sep 09 10:22:19 PM UTC 24 |
Sep 09 10:22:24 PM UTC 24 |
455761916 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4275788854 |
|
|
Sep 09 10:22:21 PM UTC 24 |
Sep 09 10:22:24 PM UTC 24 |
152690976 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3480173293 |
|
|
Sep 09 10:22:23 PM UTC 24 |
Sep 09 10:22:25 PM UTC 24 |
86731101 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3433331227 |
|
|
Sep 09 10:22:21 PM UTC 24 |
Sep 09 10:22:25 PM UTC 24 |
538417666 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.628569893 |
|
|
Sep 09 10:22:21 PM UTC 24 |
Sep 09 10:22:25 PM UTC 24 |
312402022 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2788654305 |
|
|
Sep 09 10:22:19 PM UTC 24 |
Sep 09 10:22:26 PM UTC 24 |
468511569 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3341608703 |
|
|
Sep 09 10:22:23 PM UTC 24 |
Sep 09 10:22:26 PM UTC 24 |
161358090 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.827736580 |
|
|
Sep 09 10:22:25 PM UTC 24 |
Sep 09 10:22:27 PM UTC 24 |
15782600 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2543995015 |
|
|
Sep 09 10:22:25 PM UTC 24 |
Sep 09 10:22:27 PM UTC 24 |
45738937 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1909243250 |
|
|
Sep 09 10:22:25 PM UTC 24 |
Sep 09 10:22:27 PM UTC 24 |
141578958 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1674600737 |
|
|
Sep 09 10:22:25 PM UTC 24 |
Sep 09 10:22:28 PM UTC 24 |
432064821 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.941411514 |
|
|
Sep 09 10:22:23 PM UTC 24 |
Sep 09 10:22:28 PM UTC 24 |
80862412 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.213704949 |
|
|
Sep 09 10:22:26 PM UTC 24 |
Sep 09 10:22:29 PM UTC 24 |
17242217 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.995981997 |
|
|
Sep 09 10:22:25 PM UTC 24 |
Sep 09 10:22:29 PM UTC 24 |
27686146 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337086266 |
|
|
Sep 09 10:22:26 PM UTC 24 |
Sep 09 10:22:29 PM UTC 24 |
116268100 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1515794291 |
|
|
Sep 09 10:22:25 PM UTC 24 |
Sep 09 10:22:31 PM UTC 24 |
1290693842 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2834917884 |
|
|
Sep 09 10:22:28 PM UTC 24 |
Sep 09 10:22:31 PM UTC 24 |
18143668 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.565552817 |
|
|
Sep 09 10:22:29 PM UTC 24 |
Sep 09 10:22:31 PM UTC 24 |
49516810 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.70324659 |
|
|
Sep 09 10:22:29 PM UTC 24 |
Sep 09 10:22:31 PM UTC 24 |
113216223 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3360729590 |
|
|
Sep 09 10:22:30 PM UTC 24 |
Sep 09 10:22:32 PM UTC 24 |
27161173 ps |