| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.95 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
| T1005 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3998881038 | Sep 09 10:22:30 PM UTC 24 | Sep 09 10:22:33 PM UTC 24 | 22899515 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4096285204 | Sep 09 10:22:28 PM UTC 24 | Sep 09 10:22:33 PM UTC 24 | 24333463 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.823581477 | Sep 09 10:22:31 PM UTC 24 | Sep 09 10:22:33 PM UTC 24 | 30290266 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3744330987 | Sep 09 10:22:28 PM UTC 24 | Sep 09 10:22:34 PM UTC 24 | 345518347 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3650012847 | Sep 09 10:22:30 PM UTC 24 | Sep 09 10:22:34 PM UTC 24 | 567589861 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3969793356 | Sep 09 10:22:29 PM UTC 24 | Sep 09 10:22:34 PM UTC 24 | 751277807 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3441003432 | Sep 09 10:22:32 PM UTC 24 | Sep 09 10:22:34 PM UTC 24 | 35709218 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.412487010 | Sep 09 10:22:26 PM UTC 24 | Sep 09 10:22:36 PM UTC 24 | 753017273 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.851364230 | Sep 09 10:22:34 PM UTC 24 | Sep 09 10:22:36 PM UTC 24 | 23236498 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.357883179 | Sep 09 10:22:30 PM UTC 24 | Sep 09 10:22:36 PM UTC 24 | 126565677 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3616723720 | Sep 09 10:22:32 PM UTC 24 | Sep 09 10:22:37 PM UTC 24 | 2676941677 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1527883357 | Sep 09 10:22:36 PM UTC 24 | Sep 09 10:22:37 PM UTC 24 | 20522715 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1857352280 | Sep 09 10:22:36 PM UTC 24 | Sep 09 10:22:38 PM UTC 24 | 17071450 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2254366961 | Sep 09 10:22:34 PM UTC 24 | Sep 09 10:22:38 PM UTC 24 | 434626436 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2393899285 | Sep 09 10:22:34 PM UTC 24 | Sep 09 10:22:38 PM UTC 24 | 71264920 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2000591216 | Sep 09 10:22:32 PM UTC 24 | Sep 09 10:22:38 PM UTC 24 | 1917084053 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1377259260 | Sep 09 10:22:36 PM UTC 24 | Sep 09 10:22:38 PM UTC 24 | 255497916 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1726555958 | Sep 09 10:22:34 PM UTC 24 | Sep 09 10:22:39 PM UTC 24 | 139579415 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1943022557 | Sep 09 10:22:32 PM UTC 24 | Sep 09 10:22:39 PM UTC 24 | 129203926 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4268025885 | Sep 09 10:22:35 PM UTC 24 | Sep 09 10:22:40 PM UTC 24 | 959293927 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2633991059 | Sep 09 10:22:37 PM UTC 24 | Sep 09 10:22:41 PM UTC 24 | 845152095 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4067496075 | Sep 09 10:22:39 PM UTC 24 | Sep 09 10:22:41 PM UTC 24 | 43293699 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4124850759 | Sep 09 10:22:39 PM UTC 24 | Sep 09 10:22:41 PM UTC 24 | 23512177 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3811149029 | Sep 09 10:22:39 PM UTC 24 | Sep 09 10:22:42 PM UTC 24 | 81901540 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3426705361 | Sep 09 10:22:37 PM UTC 24 | Sep 09 10:22:42 PM UTC 24 | 32392233 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2533500673 | Sep 09 10:22:37 PM UTC 24 | Sep 09 10:22:43 PM UTC 24 | 866782597 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2148241517 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 752857225 ps |
| CPU time | 5 seconds |
| Started | Sep 09 09:10:23 PM UTC 24 |
| Finished | Sep 09 09:10:29 PM UTC 24 |
| Peak memory | 223928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148241517 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.2148241517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1558489221 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1335949875 ps |
| CPU time | 4.31 seconds |
| Started | Sep 09 09:10:21 PM UTC 24 |
| Finished | Sep 09 09:10:28 PM UTC 24 |
| Peak memory | 213744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558489221 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.1558489221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.41212927 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5400873933 ps |
| CPU time | 158.23 seconds |
| Started | Sep 09 09:10:38 PM UTC 24 |
| Finished | Sep 09 09:13:20 PM UTC 24 |
| Peak memory | 395252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41212927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.41212927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3002572004 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 288113328 ps |
| CPU time | 5.21 seconds |
| Started | Sep 09 09:10:40 PM UTC 24 |
| Finished | Sep 09 09:10:46 PM UTC 24 |
| Peak memory | 250160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002572004 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3002572004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.578382188 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 222635556 ps |
| CPU time | 3.01 seconds |
| Started | Sep 09 10:22:04 PM UTC 24 |
| Finished | Sep 09 10:22:08 PM UTC 24 |
| Peak memory | 221568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57838 2188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_int g_err.578382188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.1071175398 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4817869558 ps |
| CPU time | 170.73 seconds |
| Started | Sep 09 09:13:35 PM UTC 24 |
| Finished | Sep 09 09:16:29 PM UTC 24 |
| Peak memory | 352112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071175398 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1071175398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1687215393 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1048113351 ps |
| CPU time | 37.56 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:11:16 PM UTC 24 |
| Peak memory | 343932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687215393 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1687215393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2778608330 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 12174351759 ps |
| CPU time | 853.91 seconds |
| Started | Sep 09 09:10:22 PM UTC 24 |
| Finished | Sep 09 09:24:46 PM UTC 24 |
| Peak memory | 374972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778608330 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2778608330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1478116643 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 25843850787 ps |
| CPU time | 356.71 seconds |
| Started | Sep 09 09:10:43 PM UTC 24 |
| Finished | Sep 09 09:16:45 PM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478116643 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce ss_b2b.1478116643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1775763447 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 30588479 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 10:21:33 PM UTC 24 |
| Finished | Sep 09 10:21:36 PM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17757634 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alia sing.1775763447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.841577836 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2781750487 ps |
| CPU time | 35.39 seconds |
| Started | Sep 09 09:10:24 PM UTC 24 |
| Finished | Sep 09 09:11:18 PM UTC 24 |
| Peak memory | 224224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841577836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.841577836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1687253834 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 180303963 ps |
| CPU time | 0.79 seconds |
| Started | Sep 09 09:10:23 PM UTC 24 |
| Finished | Sep 09 09:10:25 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687253834 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1687253834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2641937328 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1422988467 ps |
| CPU time | 131.64 seconds |
| Started | Sep 09 09:10:20 PM UTC 24 |
| Finished | Sep 09 09:12:41 PM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641937328 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.2641937328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.202654064 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14267107 ps |
| CPU time | 0.63 seconds |
| Started | Sep 09 09:10:26 PM UTC 24 |
| Finished | Sep 09 09:10:34 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202654064 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.202654064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1594224705 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 980011142 ps |
| CPU time | 3.62 seconds |
| Started | Sep 09 10:22:18 PM UTC 24 |
| Finished | Sep 09 10:22:22 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15942 24705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_i ntg_err.1594224705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3282673067 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1411726524 ps |
| CPU time | 5.28 seconds |
| Started | Sep 09 10:21:20 PM UTC 24 |
| Finished | Sep 09 10:21:27 PM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 82673067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa ssthru_mem_tl_intg_err.3282673067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.628569893 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 312402022 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 10:22:21 PM UTC 24 |
| Finished | Sep 09 10:22:25 PM UTC 24 |
| Peak memory | 221644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62856 9893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_in tg_err.628569893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3318572390 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 785170297 ps |
| CPU time | 6.59 seconds |
| Started | Sep 09 10:21:59 PM UTC 24 |
| Finished | Sep 09 10:22:07 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 18572390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa ssthru_mem_tl_intg_err.3318572390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3385798521 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 482217178 ps |
| CPU time | 6.23 seconds |
| Started | Sep 09 10:21:28 PM UTC 24 |
| Finished | Sep 09 10:21:35 PM UTC 24 |
| Peak memory | 221664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385798521 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.3385798521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3605890186 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1283272257 ps |
| CPU time | 5.37 seconds |
| Started | Sep 09 09:10:29 PM UTC 24 |
| Finished | Sep 09 09:10:39 PM UTC 24 |
| Peak memory | 213832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605890186 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3605890186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3121083509 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 386946519 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 10:22:10 PM UTC 24 |
| Finished | Sep 09 10:22:13 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31210 83509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in tg_err.3121083509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2603063453 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 245904388 ps |
| CPU time | 63.03 seconds |
| Started | Sep 09 09:10:21 PM UTC 24 |
| Finished | Sep 09 09:11:28 PM UTC 24 |
| Peak memory | 370592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 603063453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max _throughput.2603063453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2400039510 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 7044255068 ps |
| CPU time | 533.51 seconds |
| Started | Sep 09 09:19:37 PM UTC 24 |
| Finished | Sep 09 09:28:37 PM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400039510 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2400039510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4047369903 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2099352603 ps |
| CPU time | 4.43 seconds |
| Started | Sep 09 10:22:18 PM UTC 24 |
| Finished | Sep 09 10:22:23 PM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 47369903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p assthru_mem_tl_intg_err.4047369903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4011131533 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 43978832 ps |
| CPU time | 2.36 seconds |
| Started | Sep 09 10:21:32 PM UTC 24 |
| Finished | Sep 09 10:21:36 PM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40111315 33 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_ bash.4011131533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3025171134 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 29806900 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 10:21:29 PM UTC 24 |
| Finished | Sep 09 10:21:31 PM UTC 24 |
| Peak memory | 209896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30251711 34 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_r eset.3025171134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.405743780 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 14356842 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 10:21:31 PM UTC 24 |
| Finished | Sep 09 10:21:33 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405743780 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.405743780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3771080170 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 30311075 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 10:21:35 PM UTC 24 |
| Finished | Sep 09 10:21:37 PM UTC 24 |
| Peak memory | 210360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3771080170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c trl_same_csr_outstanding.3771080170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1716306756 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1435753633 ps |
| CPU time | 3.48 seconds |
| Started | Sep 09 10:21:28 PM UTC 24 |
| Finished | Sep 09 10:21:33 PM UTC 24 |
| Peak memory | 221664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17163 06756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_in tg_err.1716306756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1601908654 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 45900237 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 10:21:39 PM UTC 24 |
| Finished | Sep 09 10:21:42 PM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16019086 54 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alia sing.1601908654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.496910488 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 463646672 ps |
| CPU time | 2.49 seconds |
| Started | Sep 09 10:21:38 PM UTC 24 |
| Finished | Sep 09 10:21:42 PM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49691048 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_b ash.496910488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1066947305 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 20465499 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 10:21:37 PM UTC 24 |
| Finished | Sep 09 10:21:39 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10669473 05 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r eset.1066947305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4201775834 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 99600899 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 10:21:41 PM UTC 24 |
| Finished | Sep 09 10:21:44 PM UTC 24 |
| Peak memory | 220608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4201775834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.4201775834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2147711242 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 14196479 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:21:37 PM UTC 24 |
| Finished | Sep 09 10:21:39 PM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147711242 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.2147711242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2627590346 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 214519199 ps |
| CPU time | 3.82 seconds |
| Started | Sep 09 10:21:35 PM UTC 24 |
| Finished | Sep 09 10:21:40 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 27590346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pa ssthru_mem_tl_intg_err.2627590346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3505249936 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 71274485 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 10:21:41 PM UTC 24 |
| Finished | Sep 09 10:21:43 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3505249936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c trl_same_csr_outstanding.3505249936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3231666879 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 81647540 ps |
| CPU time | 2.54 seconds |
| Started | Sep 09 10:21:36 PM UTC 24 |
| Finished | Sep 09 10:21:40 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231666879 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.3231666879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2868146737 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 101608078 ps |
| CPU time | 2.4 seconds |
| Started | Sep 09 10:21:37 PM UTC 24 |
| Finished | Sep 09 10:21:41 PM UTC 24 |
| Peak memory | 221600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28681 46737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_in tg_err.2868146737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4246834885 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 158487628 ps |
| CPU time | 1.69 seconds |
| Started | Sep 09 10:22:18 PM UTC 24 |
| Finished | Sep 09 10:22:20 PM UTC 24 |
| Peak memory | 222332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4246834885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.4246834885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.676696747 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 18072641 ps |
| CPU time | 0.84 seconds |
| Started | Sep 09 10:22:16 PM UTC 24 |
| Finished | Sep 09 10:22:18 PM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676696747 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.676696747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2856853576 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 1304731390 ps |
| CPU time | 3.19 seconds |
| Started | Sep 09 10:22:16 PM UTC 24 |
| Finished | Sep 09 10:22:20 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28 56853576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p assthru_mem_tl_intg_err.2856853576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.480784910 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 20119670 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 10:22:17 PM UTC 24 |
| Finished | Sep 09 10:22:20 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=480784910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_c trl_same_csr_outstanding.480784910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3937641327 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 102391105 ps |
| CPU time | 4.12 seconds |
| Started | Sep 09 10:22:16 PM UTC 24 |
| Finished | Sep 09 10:22:21 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937641327 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.3937641327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2983751432 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 105887419 ps |
| CPU time | 1.65 seconds |
| Started | Sep 09 10:22:16 PM UTC 24 |
| Finished | Sep 09 10:22:18 PM UTC 24 |
| Peak memory | 220396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29837 51432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_i ntg_err.2983751432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1709214355 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 97357521 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 10:22:19 PM UTC 24 |
| Finished | Sep 09 10:22:21 PM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1709214355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1709214355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.513348669 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 41511775 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 10:22:18 PM UTC 24 |
| Finished | Sep 09 10:22:20 PM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513348669 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.513348669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.887441607 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 25469786 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 10:22:18 PM UTC 24 |
| Finished | Sep 09 10:22:20 PM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=887441607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_c trl_same_csr_outstanding.887441607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2114987436 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 313541760 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 10:22:18 PM UTC 24 |
| Finished | Sep 09 10:22:22 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114987436 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.2114987436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4275788854 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 152690976 ps |
| CPU time | 2.01 seconds |
| Started | Sep 09 10:22:21 PM UTC 24 |
| Finished | Sep 09 10:22:24 PM UTC 24 |
| Peak memory | 222332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4275788854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.4275788854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3667014220 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 39534071 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 10:22:21 PM UTC 24 |
| Finished | Sep 09 10:22:23 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667014220 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.3667014220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2277383935 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 455761916 ps |
| CPU time | 3.2 seconds |
| Started | Sep 09 10:22:19 PM UTC 24 |
| Finished | Sep 09 10:22:24 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 77383935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p assthru_mem_tl_intg_err.2277383935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2068634734 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 41969142 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 10:22:21 PM UTC 24 |
| Finished | Sep 09 10:22:23 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2068634734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ ctrl_same_csr_outstanding.2068634734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2788654305 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 468511569 ps |
| CPU time | 5.56 seconds |
| Started | Sep 09 10:22:19 PM UTC 24 |
| Finished | Sep 09 10:22:26 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788654305 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.2788654305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1909243250 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 141578958 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 10:22:25 PM UTC 24 |
| Finished | Sep 09 10:22:27 PM UTC 24 |
| Peak memory | 222332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1909243250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1909243250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3480173293 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 86731101 ps |
| CPU time | 1 seconds |
| Started | Sep 09 10:22:23 PM UTC 24 |
| Finished | Sep 09 10:22:25 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480173293 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.3480173293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3433331227 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 538417666 ps |
| CPU time | 2.67 seconds |
| Started | Sep 09 10:22:21 PM UTC 24 |
| Finished | Sep 09 10:22:25 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34 33331227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p assthru_mem_tl_intg_err.3433331227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.827736580 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 15782600 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 10:22:25 PM UTC 24 |
| Finished | Sep 09 10:22:27 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=827736580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_c trl_same_csr_outstanding.827736580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.941411514 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 80862412 ps |
| CPU time | 4.22 seconds |
| Started | Sep 09 10:22:23 PM UTC 24 |
| Finished | Sep 09 10:22:28 PM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941411514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.941411514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3341608703 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 161358090 ps |
| CPU time | 2.42 seconds |
| Started | Sep 09 10:22:23 PM UTC 24 |
| Finished | Sep 09 10:22:26 PM UTC 24 |
| Peak memory | 221712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33416 08703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i ntg_err.3341608703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337086266 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 116268100 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 10:22:26 PM UTC 24 |
| Finished | Sep 09 10:22:29 PM UTC 24 |
| Peak memory | 210044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1337086266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1337086266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2543995015 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 45738937 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 10:22:25 PM UTC 24 |
| Finished | Sep 09 10:22:27 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543995015 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.2543995015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1515794291 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1290693842 ps |
| CPU time | 4.65 seconds |
| Started | Sep 09 10:22:25 PM UTC 24 |
| Finished | Sep 09 10:22:31 PM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 15794291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_p assthru_mem_tl_intg_err.1515794291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.213704949 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 17242217 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 10:22:26 PM UTC 24 |
| Finished | Sep 09 10:22:29 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=213704949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_c trl_same_csr_outstanding.213704949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.995981997 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 27686146 ps |
| CPU time | 2.66 seconds |
| Started | Sep 09 10:22:25 PM UTC 24 |
| Finished | Sep 09 10:22:29 PM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995981997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.995981997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1674600737 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 432064821 ps |
| CPU time | 1.88 seconds |
| Started | Sep 09 10:22:25 PM UTC 24 |
| Finished | Sep 09 10:22:28 PM UTC 24 |
| Peak memory | 220396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16746 00737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i ntg_err.1674600737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.70324659 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 113216223 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 10:22:29 PM UTC 24 |
| Finished | Sep 09 10:22:31 PM UTC 24 |
| Peak memory | 220280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=70324659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.70324659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2834917884 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 18143668 ps |
| CPU time | 1 seconds |
| Started | Sep 09 10:22:28 PM UTC 24 |
| Finished | Sep 09 10:22:31 PM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834917884 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.2834917884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.412487010 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 753017273 ps |
| CPU time | 8.13 seconds |
| Started | Sep 09 10:22:26 PM UTC 24 |
| Finished | Sep 09 10:22:36 PM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 2487010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_pa ssthru_mem_tl_intg_err.412487010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.565552817 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 49516810 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 10:22:29 PM UTC 24 |
| Finished | Sep 09 10:22:31 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=565552817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_c trl_same_csr_outstanding.565552817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4096285204 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 24333463 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 10:22:28 PM UTC 24 |
| Finished | Sep 09 10:22:33 PM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096285204 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.4096285204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3744330987 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 345518347 ps |
| CPU time | 4.08 seconds |
| Started | Sep 09 10:22:28 PM UTC 24 |
| Finished | Sep 09 10:22:34 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37443 30987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i ntg_err.3744330987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.823581477 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 30290266 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 10:22:31 PM UTC 24 |
| Finished | Sep 09 10:22:33 PM UTC 24 |
| Peak memory | 220280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=823581477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.823581477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3360729590 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 27161173 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 10:22:30 PM UTC 24 |
| Finished | Sep 09 10:22:32 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360729590 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.3360729590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3969793356 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 751277807 ps |
| CPU time | 4.62 seconds |
| Started | Sep 09 10:22:29 PM UTC 24 |
| Finished | Sep 09 10:22:34 PM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 69793356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p assthru_mem_tl_intg_err.3969793356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3998881038 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 22899515 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 10:22:30 PM UTC 24 |
| Finished | Sep 09 10:22:33 PM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3998881038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ ctrl_same_csr_outstanding.3998881038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.357883179 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 126565677 ps |
| CPU time | 4.64 seconds |
| Started | Sep 09 10:22:30 PM UTC 24 |
| Finished | Sep 09 10:22:36 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357883179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.357883179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3650012847 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 567589861 ps |
| CPU time | 2.89 seconds |
| Started | Sep 09 10:22:30 PM UTC 24 |
| Finished | Sep 09 10:22:34 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36500 12847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i ntg_err.3650012847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2393899285 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 71264920 ps |
| CPU time | 2.96 seconds |
| Started | Sep 09 10:22:34 PM UTC 24 |
| Finished | Sep 09 10:22:38 PM UTC 24 |
| Peak memory | 221916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2393899285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2393899285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3441003432 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 35709218 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 10:22:32 PM UTC 24 |
| Finished | Sep 09 10:22:34 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441003432 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.3441003432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2000591216 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1917084053 ps |
| CPU time | 4.86 seconds |
| Started | Sep 09 10:22:32 PM UTC 24 |
| Finished | Sep 09 10:22:38 PM UTC 24 |
| Peak memory | 211736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 00591216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_p assthru_mem_tl_intg_err.2000591216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.851364230 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 23236498 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 10:22:34 PM UTC 24 |
| Finished | Sep 09 10:22:36 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=851364230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_c trl_same_csr_outstanding.851364230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1943022557 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 129203926 ps |
| CPU time | 5.67 seconds |
| Started | Sep 09 10:22:32 PM UTC 24 |
| Finished | Sep 09 10:22:39 PM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943022557 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.1943022557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3616723720 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2676941677 ps |
| CPU time | 3.55 seconds |
| Started | Sep 09 10:22:32 PM UTC 24 |
| Finished | Sep 09 10:22:37 PM UTC 24 |
| Peak memory | 221600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36167 23720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.3616723720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1377259260 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 255497916 ps |
| CPU time | 1.61 seconds |
| Started | Sep 09 10:22:36 PM UTC 24 |
| Finished | Sep 09 10:22:38 PM UTC 24 |
| Peak memory | 220284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1377259260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1377259260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1857352280 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 17071450 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 10:22:36 PM UTC 24 |
| Finished | Sep 09 10:22:38 PM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857352280 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1857352280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2254366961 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 434626436 ps |
| CPU time | 2.82 seconds |
| Started | Sep 09 10:22:34 PM UTC 24 |
| Finished | Sep 09 10:22:38 PM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 54366961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p assthru_mem_tl_intg_err.2254366961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1527883357 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 20522715 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 10:22:36 PM UTC 24 |
| Finished | Sep 09 10:22:37 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1527883357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ ctrl_same_csr_outstanding.1527883357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1726555958 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 139579415 ps |
| CPU time | 3.84 seconds |
| Started | Sep 09 10:22:34 PM UTC 24 |
| Finished | Sep 09 10:22:39 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726555958 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.1726555958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4268025885 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 959293927 ps |
| CPU time | 3.81 seconds |
| Started | Sep 09 10:22:35 PM UTC 24 |
| Finished | Sep 09 10:22:40 PM UTC 24 |
| Peak memory | 221664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42680 25885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i ntg_err.4268025885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3811149029 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 81901540 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 10:22:39 PM UTC 24 |
| Finished | Sep 09 10:22:42 PM UTC 24 |
| Peak memory | 221984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3811149029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3811149029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4067496075 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 43293699 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 10:22:39 PM UTC 24 |
| Finished | Sep 09 10:22:41 PM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067496075 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.4067496075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2533500673 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 866782597 ps |
| CPU time | 5.25 seconds |
| Started | Sep 09 10:22:37 PM UTC 24 |
| Finished | Sep 09 10:22:43 PM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 33500673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_p assthru_mem_tl_intg_err.2533500673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4124850759 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 23512177 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 10:22:39 PM UTC 24 |
| Finished | Sep 09 10:22:41 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4124850759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ ctrl_same_csr_outstanding.4124850759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3426705361 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 32392233 ps |
| CPU time | 4.15 seconds |
| Started | Sep 09 10:22:37 PM UTC 24 |
| Finished | Sep 09 10:22:42 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426705361 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.3426705361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2633991059 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 845152095 ps |
| CPU time | 2.76 seconds |
| Started | Sep 09 10:22:37 PM UTC 24 |
| Finished | Sep 09 10:22:41 PM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26339 91059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i ntg_err.2633991059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.883652804 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 15279839 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 10:21:47 PM UTC 24 |
| Finished | Sep 09 10:21:49 PM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88365280 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alias ing.883652804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2506689302 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 190940802 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 10:21:45 PM UTC 24 |
| Finished | Sep 09 10:21:48 PM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25066893 02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_ bash.2506689302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2414886923 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 14015044 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:21:43 PM UTC 24 |
| Finished | Sep 09 10:21:45 PM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24148869 23 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r eset.2414886923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.736508002 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 222366258 ps |
| CPU time | 2.63 seconds |
| Started | Sep 09 10:21:48 PM UTC 24 |
| Finished | Sep 09 10:21:52 PM UTC 24 |
| Peak memory | 223892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=736508002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.736508002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1832234074 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 64775820 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 10:21:45 PM UTC 24 |
| Finished | Sep 09 10:21:47 PM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832234074 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1832234074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2048310026 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1870784094 ps |
| CPU time | 6.72 seconds |
| Started | Sep 09 10:21:41 PM UTC 24 |
| Finished | Sep 09 10:21:49 PM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 48310026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa ssthru_mem_tl_intg_err.2048310026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2466554963 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 19796906 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 10:21:48 PM UTC 24 |
| Finished | Sep 09 10:21:50 PM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2466554963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c trl_same_csr_outstanding.2466554963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2488080049 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 118877381 ps |
| CPU time | 3.42 seconds |
| Started | Sep 09 10:21:42 PM UTC 24 |
| Finished | Sep 09 10:21:46 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488080049 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.2488080049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1299564260 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 254636363 ps |
| CPU time | 4.39 seconds |
| Started | Sep 09 10:21:43 PM UTC 24 |
| Finished | Sep 09 10:21:49 PM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12995 64260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_in tg_err.1299564260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1016505673 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 61536906 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 10:21:52 PM UTC 24 |
| Finished | Sep 09 10:21:54 PM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10165056 73 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia sing.1016505673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4154817081 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 47671035 ps |
| CPU time | 2.62 seconds |
| Started | Sep 09 10:21:52 PM UTC 24 |
| Finished | Sep 09 10:21:56 PM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41548170 81 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_ bash.4154817081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.640420078 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 17389395 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:21:50 PM UTC 24 |
| Finished | Sep 09 10:21:52 PM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64042007 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_re set.640420078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.393029372 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 58309958 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 10:21:55 PM UTC 24 |
| Finished | Sep 09 10:21:57 PM UTC 24 |
| Peak memory | 220284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=393029372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.393029372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.297524828 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 32803516 ps |
| CPU time | 0.87 seconds |
| Started | Sep 09 10:21:51 PM UTC 24 |
| Finished | Sep 09 10:21:53 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297524828 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.297524828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.407648355 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 220497658 ps |
| CPU time | 3.13 seconds |
| Started | Sep 09 10:21:50 PM UTC 24 |
| Finished | Sep 09 10:21:54 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 7648355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pas sthru_mem_tl_intg_err.407648355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.740044777 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 16829516 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 10:21:54 PM UTC 24 |
| Finished | Sep 09 10:21:56 PM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=740044777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ct rl_same_csr_outstanding.740044777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1624871536 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 124780915 ps |
| CPU time | 5.17 seconds |
| Started | Sep 09 10:21:50 PM UTC 24 |
| Finished | Sep 09 10:21:56 PM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624871536 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.1624871536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.818811581 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 278593594 ps |
| CPU time | 2.96 seconds |
| Started | Sep 09 10:21:50 PM UTC 24 |
| Finished | Sep 09 10:21:54 PM UTC 24 |
| Peak memory | 221612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81881 1581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_int g_err.818811581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1510513426 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 54848268 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 10:21:58 PM UTC 24 |
| Finished | Sep 09 10:22:00 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15105134 26 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia sing.1510513426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1838208697 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 569739477 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 10:21:58 PM UTC 24 |
| Finished | Sep 09 10:22:01 PM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18382086 97 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_ bash.1838208697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2063378075 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 40134116 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 10:21:56 PM UTC 24 |
| Finished | Sep 09 10:21:58 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20633780 75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_r eset.2063378075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1868186277 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 47363788 ps |
| CPU time | 1.95 seconds |
| Started | Sep 09 10:21:59 PM UTC 24 |
| Finished | Sep 09 10:22:02 PM UTC 24 |
| Peak memory | 222332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1868186277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1868186277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.606973348 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 12161336 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 10:21:56 PM UTC 24 |
| Finished | Sep 09 10:21:58 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606973348 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.606973348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3986528351 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 458649948 ps |
| CPU time | 4.65 seconds |
| Started | Sep 09 10:21:55 PM UTC 24 |
| Finished | Sep 09 10:22:00 PM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 86528351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pa ssthru_mem_tl_intg_err.3986528351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1483442190 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 53813029 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 10:21:59 PM UTC 24 |
| Finished | Sep 09 10:22:01 PM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1483442190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c trl_same_csr_outstanding.1483442190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2677053102 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 138281701 ps |
| CPU time | 7.88 seconds |
| Started | Sep 09 10:21:56 PM UTC 24 |
| Finished | Sep 09 10:22:05 PM UTC 24 |
| Peak memory | 221976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677053102 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.2677053102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1284968474 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 584840258 ps |
| CPU time | 4.45 seconds |
| Started | Sep 09 10:21:56 PM UTC 24 |
| Finished | Sep 09 10:22:02 PM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12849 68474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in tg_err.1284968474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2178894938 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 50424663 ps |
| CPU time | 3.23 seconds |
| Started | Sep 09 10:22:03 PM UTC 24 |
| Finished | Sep 09 10:22:07 PM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2178894938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2178894938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3708926011 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 14296618 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 10:22:02 PM UTC 24 |
| Finished | Sep 09 10:22:04 PM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708926011 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.3708926011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3958353877 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 105220625 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 10:22:02 PM UTC 24 |
| Finished | Sep 09 10:22:04 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3958353877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_c trl_same_csr_outstanding.3958353877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2625967648 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 130359127 ps |
| CPU time | 4.84 seconds |
| Started | Sep 09 10:22:00 PM UTC 24 |
| Finished | Sep 09 10:22:06 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625967648 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.2625967648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4086329308 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 466968261 ps |
| CPU time | 2.86 seconds |
| Started | Sep 09 10:22:02 PM UTC 24 |
| Finished | Sep 09 10:22:06 PM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40863 29308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in tg_err.4086329308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1676865583 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 61003291 ps |
| CPU time | 0.87 seconds |
| Started | Sep 09 10:22:05 PM UTC 24 |
| Finished | Sep 09 10:22:06 PM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676865583 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.1676865583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2258962248 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 801320287 ps |
| CPU time | 2.78 seconds |
| Started | Sep 09 10:22:03 PM UTC 24 |
| Finished | Sep 09 10:22:07 PM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 58962248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa ssthru_mem_tl_intg_err.2258962248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3139155205 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 27968742 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 10:22:05 PM UTC 24 |
| Finished | Sep 09 10:22:06 PM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3139155205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c trl_same_csr_outstanding.3139155205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3117577212 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 428541073 ps |
| CPU time | 5.4 seconds |
| Started | Sep 09 10:22:03 PM UTC 24 |
| Finished | Sep 09 10:22:10 PM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117577212 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3117577212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1635232833 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 116492351 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 10:22:09 PM UTC 24 |
| Finished | Sep 09 10:22:11 PM UTC 24 |
| Peak memory | 210044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1635232833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1635232833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1792919220 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 37592746 ps |
| CPU time | 0.9 seconds |
| Started | Sep 09 10:22:07 PM UTC 24 |
| Finished | Sep 09 10:22:09 PM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792919220 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.1792919220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.297930033 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 370239895 ps |
| CPU time | 2.73 seconds |
| Started | Sep 09 10:22:07 PM UTC 24 |
| Finished | Sep 09 10:22:11 PM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 7930033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pas sthru_mem_tl_intg_err.297930033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.983817203 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 33409608 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 10:22:09 PM UTC 24 |
| Finished | Sep 09 10:22:11 PM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=983817203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ct rl_same_csr_outstanding.983817203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3497656936 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 486694758 ps |
| CPU time | 3.57 seconds |
| Started | Sep 09 10:22:07 PM UTC 24 |
| Finished | Sep 09 10:22:12 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497656936 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.3497656936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.367612 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 165505111 ps |
| CPU time | 2.91 seconds |
| Started | Sep 09 10:22:07 PM UTC 24 |
| Finished | Sep 09 10:22:11 PM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36761 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_intg_err.367612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.433494158 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 37706470 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 10:22:12 PM UTC 24 |
| Finished | Sep 09 10:22:15 PM UTC 24 |
| Peak memory | 220604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=433494158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.433494158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3887367800 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 58441308 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 10:22:10 PM UTC 24 |
| Finished | Sep 09 10:22:12 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887367800 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.3887367800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3296115355 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 840350193 ps |
| CPU time | 3.02 seconds |
| Started | Sep 09 10:22:09 PM UTC 24 |
| Finished | Sep 09 10:22:13 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 96115355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa ssthru_mem_tl_intg_err.3296115355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.376052990 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 22998693 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:22:12 PM UTC 24 |
| Finished | Sep 09 10:22:14 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=376052990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ct rl_same_csr_outstanding.376052990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2746939514 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 105065049 ps |
| CPU time | 3.58 seconds |
| Started | Sep 09 10:22:09 PM UTC 24 |
| Finished | Sep 09 10:22:14 PM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746939514 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.2746939514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1948737806 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 35177815 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 10:22:14 PM UTC 24 |
| Finished | Sep 09 10:22:17 PM UTC 24 |
| Peak memory | 220604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1948737806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1948737806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2457440130 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 17443740 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 10:22:14 PM UTC 24 |
| Finished | Sep 09 10:22:16 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457440130 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.2457440130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2758755680 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 240388761 ps |
| CPU time | 3.23 seconds |
| Started | Sep 09 10:22:12 PM UTC 24 |
| Finished | Sep 09 10:22:17 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 58755680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa ssthru_mem_tl_intg_err.2758755680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3792933379 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 24303549 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:22:14 PM UTC 24 |
| Finished | Sep 09 10:22:16 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3792933379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c trl_same_csr_outstanding.3792933379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2666260611 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 264540071 ps |
| CPU time | 3.25 seconds |
| Started | Sep 09 10:22:12 PM UTC 24 |
| Finished | Sep 09 10:22:17 PM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666260611 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.2666260611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.618356102 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 704862483 ps |
| CPU time | 2.67 seconds |
| Started | Sep 09 10:22:12 PM UTC 24 |
| Finished | Sep 09 10:22:16 PM UTC 24 |
| Peak memory | 221596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61835 6102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_int g_err.618356102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2866180426 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10791973148 ps |
| CPU time | 371.55 seconds |
| Started | Sep 09 09:10:21 PM UTC 24 |
| Finished | Sep 09 09:16:40 PM UTC 24 |
| Peak memory | 376664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866180426 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_ key_req.2866180426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.600035732 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1471322065 ps |
| CPU time | 42.44 seconds |
| Started | Sep 09 09:10:20 PM UTC 24 |
| Finished | Sep 09 09:11:11 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600035732 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.600035732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1818885802 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 27493525039 ps |
| CPU time | 1221.75 seconds |
| Started | Sep 09 09:10:21 PM UTC 24 |
| Finished | Sep 09 09:30:58 PM UTC 24 |
| Peak memory | 385048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818885802 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.1818885802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3788315624 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 763673596 ps |
| CPU time | 5.82 seconds |
| Started | Sep 09 09:10:23 PM UTC 24 |
| Finished | Sep 09 09:10:30 PM UTC 24 |
| Peak memory | 213632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788315624 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.3788315624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.313159108 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 53405151945 ps |
| CPU time | 1668.98 seconds |
| Started | Sep 09 09:10:20 PM UTC 24 |
| Finished | Sep 09 09:38:34 PM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313159108 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.313159108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2986180222 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 289095024 ps |
| CPU time | 14.13 seconds |
| Started | Sep 09 09:10:20 PM UTC 24 |
| Finished | Sep 09 09:10:43 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986180222 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.2986180222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1615950680 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 100101442551 ps |
| CPU time | 535.91 seconds |
| Started | Sep 09 09:10:20 PM UTC 24 |
| Finished | Sep 09 09:19:30 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615950680 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce ss_b2b.1615950680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2878247368 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 432080109 ps |
| CPU time | 1.82 seconds |
| Started | Sep 09 09:10:26 PM UTC 24 |
| Finished | Sep 09 09:10:35 PM UTC 24 |
| Peak memory | 248864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878247368 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2878247368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2209821397 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 90476841 ps |
| CPU time | 1.69 seconds |
| Started | Sep 09 09:10:19 PM UTC 24 |
| Finished | Sep 09 09:10:25 PM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209821397 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2209821397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3622218497 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 50894512471 ps |
| CPU time | 1164.31 seconds |
| Started | Sep 09 09:10:26 PM UTC 24 |
| Finished | Sep 09 09:30:09 PM UTC 24 |
| Peak memory | 384852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362221849 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.3622218497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1092004785 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 88038016 ps |
| CPU time | 1.95 seconds |
| Started | Sep 09 09:10:21 PM UTC 24 |
| Finished | Sep 09 09:10:26 PM UTC 24 |
| Peak memory | 224284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1092004785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th roughput_w_partial_write.1092004785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2483560248 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 15492568477 ps |
| CPU time | 857.6 seconds |
| Started | Sep 09 09:10:29 PM UTC 24 |
| Finished | Sep 09 09:25:00 PM UTC 24 |
| Peak memory | 381096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483560248 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_ key_req.2483560248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2110107342 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 44436189 ps |
| CPU time | 0.84 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:10:41 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110107342 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2110107342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.3899411072 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1019919522 ps |
| CPU time | 68.66 seconds |
| Started | Sep 09 09:10:26 PM UTC 24 |
| Finished | Sep 09 09:11:43 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899411072 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.3899411072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.545366550 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4546022344 ps |
| CPU time | 757.35 seconds |
| Started | Sep 09 09:10:30 PM UTC 24 |
| Finished | Sep 09 09:23:23 PM UTC 24 |
| Peak memory | 385200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545366550 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.545366550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3337937262 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 665418735 ps |
| CPU time | 5.48 seconds |
| Started | Sep 09 09:10:27 PM UTC 24 |
| Finished | Sep 09 09:10:34 PM UTC 24 |
| Peak memory | 247524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 337937262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max _throughput.3337937262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3545050505 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 42157889 ps |
| CPU time | 3.03 seconds |
| Started | Sep 09 09:10:34 PM UTC 24 |
| Finished | Sep 09 09:10:42 PM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545050505 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.3545050505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.319085447 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 334525689 ps |
| CPU time | 6.01 seconds |
| Started | Sep 09 09:10:31 PM UTC 24 |
| Finished | Sep 09 09:10:40 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319085447 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.319085447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3811976361 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 40136723939 ps |
| CPU time | 994.38 seconds |
| Started | Sep 09 09:10:26 PM UTC 24 |
| Finished | Sep 09 09:27:18 PM UTC 24 |
| Peak memory | 376640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811976361 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.3811976361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.614406105 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2480884591 ps |
| CPU time | 19.07 seconds |
| Started | Sep 09 09:10:27 PM UTC 24 |
| Finished | Sep 09 09:10:49 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614406105 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.614406105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1805460459 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 17489188306 ps |
| CPU time | 451.72 seconds |
| Started | Sep 09 09:10:27 PM UTC 24 |
| Finished | Sep 09 09:18:06 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805460459 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce ss_b2b.1805460459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1052427550 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 34996997 ps |
| CPU time | 0.79 seconds |
| Started | Sep 09 09:10:31 PM UTC 24 |
| Finished | Sep 09 09:10:34 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052427550 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1052427550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.321091544 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 7960142936 ps |
| CPU time | 1134.79 seconds |
| Started | Sep 09 09:10:31 PM UTC 24 |
| Finished | Sep 09 09:29:39 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321091544 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.321091544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3175299739 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 333999169 ps |
| CPU time | 3.41 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:10:44 PM UTC 24 |
| Peak memory | 250096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175299739 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3175299739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.2340072786 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 314411723 ps |
| CPU time | 31.46 seconds |
| Started | Sep 09 09:10:26 PM UTC 24 |
| Finished | Sep 09 09:11:05 PM UTC 24 |
| Peak memory | 316968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340072786 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2340072786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3568320179 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 9805120950 ps |
| CPU time | 2029.81 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:44:49 PM UTC 24 |
| Peak memory | 395184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356832017 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.3568320179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2606281646 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2042746983 ps |
| CPU time | 208.95 seconds |
| Started | Sep 09 09:10:26 PM UTC 24 |
| Finished | Sep 09 09:14:05 PM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606281646 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2606281646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.940405019 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 267735899 ps |
| CPU time | 8.43 seconds |
| Started | Sep 09 09:10:27 PM UTC 24 |
| Finished | Sep 09 09:10:37 PM UTC 24 |
| Peak memory | 263972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 940405019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_thr oughput_w_partial_write.940405019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2104717394 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 13098872431 ps |
| CPU time | 709.17 seconds |
| Started | Sep 09 09:19:35 PM UTC 24 |
| Finished | Sep 09 09:31:32 PM UTC 24 |
| Peak memory | 382896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104717394 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during _key_req.2104717394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.4085673293 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 15893776 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:20:18 PM UTC 24 |
| Finished | Sep 09 09:20:20 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085673293 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.4085673293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1592092985 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 367281059 ps |
| CPU time | 31.94 seconds |
| Started | Sep 09 09:19:02 PM UTC 24 |
| Finished | Sep 09 09:19:36 PM UTC 24 |
| Peak memory | 214092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592092985 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.1592092985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.4186329777 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 231296335 ps |
| CPU time | 4.71 seconds |
| Started | Sep 09 09:19:33 PM UTC 24 |
| Finished | Sep 09 09:19:39 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186329777 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.4186329777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1505436592 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 168461329 ps |
| CPU time | 115.09 seconds |
| Started | Sep 09 09:19:29 PM UTC 24 |
| Finished | Sep 09 09:21:26 PM UTC 24 |
| Peak memory | 381104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 505436592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma x_throughput.1505436592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.357768202 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 182802986 ps |
| CPU time | 4.78 seconds |
| Started | Sep 09 09:20:03 PM UTC 24 |
| Finished | Sep 09 09:20:09 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357768202 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.357768202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.4213096830 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1349990368 ps |
| CPU time | 10.5 seconds |
| Started | Sep 09 09:19:58 PM UTC 24 |
| Finished | Sep 09 09:20:10 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213096830 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.4213096830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.161478041 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 13408735946 ps |
| CPU time | 965.13 seconds |
| Started | Sep 09 09:19:02 PM UTC 24 |
| Finished | Sep 09 09:35:18 PM UTC 24 |
| Peak memory | 387060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161478041 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.161478041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.4236200780 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3403723686 ps |
| CPU time | 23.62 seconds |
| Started | Sep 09 09:19:06 PM UTC 24 |
| Finished | Sep 09 09:19:31 PM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236200780 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.4236200780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1231460475 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6921803227 ps |
| CPU time | 301.5 seconds |
| Started | Sep 09 09:19:19 PM UTC 24 |
| Finished | Sep 09 09:24:25 PM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231460475 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc ess_b2b.1231460475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.233133149 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 74059610 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:19:55 PM UTC 24 |
| Finished | Sep 09 09:19:57 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233133149 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.233133149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.385634691 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 43026068809 ps |
| CPU time | 418.21 seconds |
| Started | Sep 09 09:19:40 PM UTC 24 |
| Finished | Sep 09 09:26:43 PM UTC 24 |
| Peak memory | 370488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385634691 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.385634691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.3893397048 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1222549656 ps |
| CPU time | 18.61 seconds |
| Started | Sep 09 09:18:59 PM UTC 24 |
| Finished | Sep 09 09:19:19 PM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893397048 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3893397048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1011846952 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 30417129212 ps |
| CPU time | 2973.04 seconds |
| Started | Sep 09 09:20:10 PM UTC 24 |
| Finished | Sep 09 10:10:15 PM UTC 24 |
| Peak memory | 396836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101184695 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.1011846952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1436107430 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4530480624 ps |
| CPU time | 232.94 seconds |
| Started | Sep 09 09:20:10 PM UTC 24 |
| Finished | Sep 09 09:24:07 PM UTC 24 |
| Peak memory | 344044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436107430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1436107430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3261900505 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5991159677 ps |
| CPU time | 331.32 seconds |
| Started | Sep 09 09:19:04 PM UTC 24 |
| Finished | Sep 09 09:24:40 PM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261900505 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3261900505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.212527155 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 98645059 ps |
| CPU time | 28.8 seconds |
| Started | Sep 09 09:19:32 PM UTC 24 |
| Finished | Sep 09 09:20:02 PM UTC 24 |
| Peak memory | 299180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 212527155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_th roughput_w_partial_write.212527155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.674853391 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1710675927 ps |
| CPU time | 489.56 seconds |
| Started | Sep 09 09:22:19 PM UTC 24 |
| Finished | Sep 09 09:30:34 PM UTC 24 |
| Peak memory | 380784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674853391 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_ key_req.674853391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2847064910 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 34333075 ps |
| CPU time | 0.86 seconds |
| Started | Sep 09 09:22:39 PM UTC 24 |
| Finished | Sep 09 09:22:41 PM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847064910 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2847064910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.1792639259 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 5386913544 ps |
| CPU time | 74.67 seconds |
| Started | Sep 09 09:21:27 PM UTC 24 |
| Finished | Sep 09 09:22:44 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792639259 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.1792639259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.133649093 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3836723104 ps |
| CPU time | 111.45 seconds |
| Started | Sep 09 09:22:19 PM UTC 24 |
| Finished | Sep 09 09:24:13 PM UTC 24 |
| Peak memory | 323428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133649093 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.133649093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1126275172 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1929073331 ps |
| CPU time | 9.43 seconds |
| Started | Sep 09 09:22:08 PM UTC 24 |
| Finished | Sep 09 09:22:18 PM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126275172 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.1126275172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1742384955 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 210369464 ps |
| CPU time | 44.97 seconds |
| Started | Sep 09 09:21:51 PM UTC 24 |
| Finished | Sep 09 09:22:37 PM UTC 24 |
| Peak memory | 323440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 742384955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ma x_throughput.1742384955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.4287731312 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 637967962 ps |
| CPU time | 8 seconds |
| Started | Sep 09 09:22:30 PM UTC 24 |
| Finished | Sep 09 09:22:40 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287731312 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.4287731312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1429069961 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 188349456 ps |
| CPU time | 9.73 seconds |
| Started | Sep 09 09:22:28 PM UTC 24 |
| Finished | Sep 09 09:22:39 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429069961 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.1429069961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1217143595 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 15874648244 ps |
| CPU time | 1252.8 seconds |
| Started | Sep 09 09:21:13 PM UTC 24 |
| Finished | Sep 09 09:42:20 PM UTC 24 |
| Peak memory | 380856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217143595 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.1217143595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1016732374 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 669103984 ps |
| CPU time | 2.73 seconds |
| Started | Sep 09 09:21:46 PM UTC 24 |
| Finished | Sep 09 09:21:50 PM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016732374 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.1016732374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2079221857 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4163594079 ps |
| CPU time | 359.82 seconds |
| Started | Sep 09 09:21:49 PM UTC 24 |
| Finished | Sep 09 09:27:53 PM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079221857 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc ess_b2b.2079221857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.2545211646 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 30366964 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:22:27 PM UTC 24 |
| Finished | Sep 09 09:22:29 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545211646 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2545211646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.694163084 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 8906782817 ps |
| CPU time | 648.78 seconds |
| Started | Sep 09 09:22:23 PM UTC 24 |
| Finished | Sep 09 09:33:19 PM UTC 24 |
| Peak memory | 386948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694163084 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.694163084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1223457767 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 500212262 ps |
| CPU time | 82.08 seconds |
| Started | Sep 09 09:20:22 PM UTC 24 |
| Finished | Sep 09 09:21:45 PM UTC 24 |
| Peak memory | 350276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223457767 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1223457767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3614462202 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 17540716814 ps |
| CPU time | 1278.49 seconds |
| Started | Sep 09 09:22:38 PM UTC 24 |
| Finished | Sep 09 09:44:10 PM UTC 24 |
| Peak memory | 386948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361446220 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.3614462202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3053253435 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2677060132 ps |
| CPU time | 638.12 seconds |
| Started | Sep 09 09:22:35 PM UTC 24 |
| Finished | Sep 09 09:33:20 PM UTC 24 |
| Peak memory | 395244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053253435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3053253435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2829571314 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 15395642437 ps |
| CPU time | 464.37 seconds |
| Started | Sep 09 09:21:29 PM UTC 24 |
| Finished | Sep 09 09:29:19 PM UTC 24 |
| Peak memory | 214052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829571314 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.2829571314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.4098071231 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 35863366 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 09:22:05 PM UTC 24 |
| Finished | Sep 09 09:22:07 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4098071231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t hroughput_w_partial_write.4098071231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.302026163 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 5475126623 ps |
| CPU time | 953.54 seconds |
| Started | Sep 09 09:23:23 PM UTC 24 |
| Finished | Sep 09 09:39:27 PM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302026163 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_ key_req.302026163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2022347893 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 64703604 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:23:52 PM UTC 24 |
| Finished | Sep 09 09:23:54 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022347893 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2022347893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1442423627 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3193895114 ps |
| CPU time | 60.61 seconds |
| Started | Sep 09 09:22:42 PM UTC 24 |
| Finished | Sep 09 09:23:44 PM UTC 24 |
| Peak memory | 213788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442423627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.1442423627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3566666946 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 6501192401 ps |
| CPU time | 447.74 seconds |
| Started | Sep 09 09:23:24 PM UTC 24 |
| Finished | Sep 09 09:30:58 PM UTC 24 |
| Peak memory | 374772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566666946 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.3566666946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.521597060 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 185499429 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 09:23:20 PM UTC 24 |
| Finished | Sep 09 09:23:22 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521597060 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.521597060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1415152620 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 107441212 ps |
| CPU time | 34.73 seconds |
| Started | Sep 09 09:22:55 PM UTC 24 |
| Finished | Sep 09 09:23:31 PM UTC 24 |
| Peak memory | 317552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 415152620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma x_throughput.1415152620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.763449593 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 503804578 ps |
| CPU time | 4.77 seconds |
| Started | Sep 09 09:23:45 PM UTC 24 |
| Finished | Sep 09 09:23:51 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763449593 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.763449593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1037104760 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 670696531 ps |
| CPU time | 8.99 seconds |
| Started | Sep 09 09:23:40 PM UTC 24 |
| Finished | Sep 09 09:23:50 PM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037104760 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.1037104760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3565295286 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 65293750236 ps |
| CPU time | 1029.97 seconds |
| Started | Sep 09 09:22:41 PM UTC 24 |
| Finished | Sep 09 09:40:03 PM UTC 24 |
| Peak memory | 382768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565295286 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.3565295286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1787035287 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 287352370 ps |
| CPU time | 50.85 seconds |
| Started | Sep 09 09:22:44 PM UTC 24 |
| Finished | Sep 09 09:23:37 PM UTC 24 |
| Peak memory | 335632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787035287 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.1787035287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.628986309 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 8450891475 ps |
| CPU time | 356.8 seconds |
| Started | Sep 09 09:22:49 PM UTC 24 |
| Finished | Sep 09 09:28:51 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628986309 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acce ss_b2b.628986309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.943208832 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 31279902 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:23:37 PM UTC 24 |
| Finished | Sep 09 09:23:39 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943208832 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.943208832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.2966009345 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 9613292942 ps |
| CPU time | 804.7 seconds |
| Started | Sep 09 09:23:31 PM UTC 24 |
| Finished | Sep 09 09:37:05 PM UTC 24 |
| Peak memory | 376664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966009345 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2966009345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.4094416535 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 115290000 ps |
| CPU time | 11.06 seconds |
| Started | Sep 09 09:22:40 PM UTC 24 |
| Finished | Sep 09 09:22:52 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094416535 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.4094416535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.490408098 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 34035057661 ps |
| CPU time | 2613.08 seconds |
| Started | Sep 09 09:23:52 PM UTC 24 |
| Finished | Sep 09 10:07:51 PM UTC 24 |
| Peak memory | 399036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490408098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.490408098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.343775476 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3488805395 ps |
| CPU time | 70.64 seconds |
| Started | Sep 09 09:23:49 PM UTC 24 |
| Finished | Sep 09 09:25:02 PM UTC 24 |
| Peak memory | 325872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343775476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.343775476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3688242320 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4438356388 ps |
| CPU time | 234.12 seconds |
| Started | Sep 09 09:22:43 PM UTC 24 |
| Finished | Sep 09 09:26:41 PM UTC 24 |
| Peak memory | 214156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688242320 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.3688242320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2414948059 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 151020759 ps |
| CPU time | 93.34 seconds |
| Started | Sep 09 09:23:03 PM UTC 24 |
| Finished | Sep 09 09:24:38 PM UTC 24 |
| Peak memory | 381032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2414948059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t hroughput_w_partial_write.2414948059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1531109314 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 27630174743 ps |
| CPU time | 906.23 seconds |
| Started | Sep 09 09:24:48 PM UTC 24 |
| Finished | Sep 09 09:40:03 PM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531109314 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during _key_req.1531109314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3896889330 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 37957348 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:25:02 PM UTC 24 |
| Finished | Sep 09 09:25:04 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896889330 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3896889330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.1206322420 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2121137052 ps |
| CPU time | 47.33 seconds |
| Started | Sep 09 09:24:08 PM UTC 24 |
| Finished | Sep 09 09:24:57 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206322420 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.1206322420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1378140055 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2648263467 ps |
| CPU time | 125.04 seconds |
| Started | Sep 09 09:24:50 PM UTC 24 |
| Finished | Sep 09 09:26:57 PM UTC 24 |
| Peak memory | 309112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378140055 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.1378140055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2822946643 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2977530648 ps |
| CPU time | 9.6 seconds |
| Started | Sep 09 09:24:48 PM UTC 24 |
| Finished | Sep 09 09:24:58 PM UTC 24 |
| Peak memory | 214196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822946643 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.2822946643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1860173967 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 631221651 ps |
| CPU time | 16.71 seconds |
| Started | Sep 09 09:24:41 PM UTC 24 |
| Finished | Sep 09 09:24:59 PM UTC 24 |
| Peak memory | 270140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 860173967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ma x_throughput.1860173967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2949803178 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 174266077 ps |
| CPU time | 6.9 seconds |
| Started | Sep 09 09:25:00 PM UTC 24 |
| Finished | Sep 09 09:25:08 PM UTC 24 |
| Peak memory | 224436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949803178 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2949803178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.151615012 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 374931420 ps |
| CPU time | 7.95 seconds |
| Started | Sep 09 09:24:59 PM UTC 24 |
| Finished | Sep 09 09:25:08 PM UTC 24 |
| Peak memory | 224328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151615012 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.151615012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.2578999568 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 16977562184 ps |
| CPU time | 534.01 seconds |
| Started | Sep 09 09:24:04 PM UTC 24 |
| Finished | Sep 09 09:33:04 PM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578999568 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.2578999568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.506614139 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 306706371 ps |
| CPU time | 19.22 seconds |
| Started | Sep 09 09:24:26 PM UTC 24 |
| Finished | Sep 09 09:24:47 PM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506614139 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.506614139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3378173043 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 8099615424 ps |
| CPU time | 180.02 seconds |
| Started | Sep 09 09:24:39 PM UTC 24 |
| Finished | Sep 09 09:27:43 PM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378173043 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc ess_b2b.3378173043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.1534244339 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 75743743 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:24:58 PM UTC 24 |
| Finished | Sep 09 09:25:00 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534244339 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1534244339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.891035501 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 111002955100 ps |
| CPU time | 979.14 seconds |
| Started | Sep 09 09:24:52 PM UTC 24 |
| Finished | Sep 09 09:41:21 PM UTC 24 |
| Peak memory | 385268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891035501 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.891035501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3355964096 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 489075433 ps |
| CPU time | 7.02 seconds |
| Started | Sep 09 09:23:55 PM UTC 24 |
| Finished | Sep 09 09:24:03 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355964096 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3355964096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2832191205 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 41730886139 ps |
| CPU time | 2208.6 seconds |
| Started | Sep 09 09:25:01 PM UTC 24 |
| Finished | Sep 09 10:02:12 PM UTC 24 |
| Peak memory | 389292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283219120 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.2832191205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2074697183 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6441526695 ps |
| CPU time | 402.43 seconds |
| Started | Sep 09 09:24:14 PM UTC 24 |
| Finished | Sep 09 09:31:02 PM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074697183 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2074697183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3403555370 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 755819351 ps |
| CPU time | 3.26 seconds |
| Started | Sep 09 09:24:46 PM UTC 24 |
| Finished | Sep 09 09:24:51 PM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3403555370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t hroughput_w_partial_write.3403555370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.1412097372 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 999014069 ps |
| CPU time | 232.74 seconds |
| Started | Sep 09 09:26:07 PM UTC 24 |
| Finished | Sep 09 09:30:03 PM UTC 24 |
| Peak memory | 385124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412097372 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during _key_req.1412097372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.771959798 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 13970678 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:26:48 PM UTC 24 |
| Finished | Sep 09 09:26:50 PM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771959798 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.771959798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.788661305 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3644723167 ps |
| CPU time | 21.54 seconds |
| Started | Sep 09 09:25:09 PM UTC 24 |
| Finished | Sep 09 09:25:31 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788661305 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.788661305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3913132301 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2229073986 ps |
| CPU time | 967.16 seconds |
| Started | Sep 09 09:26:07 PM UTC 24 |
| Finished | Sep 09 09:42:24 PM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913132301 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.3913132301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3280838797 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 778269666 ps |
| CPU time | 5.59 seconds |
| Started | Sep 09 09:25:59 PM UTC 24 |
| Finished | Sep 09 09:26:06 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280838797 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.3280838797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4206832941 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 257862245 ps |
| CPU time | 15.97 seconds |
| Started | Sep 09 09:25:41 PM UTC 24 |
| Finished | Sep 09 09:25:58 PM UTC 24 |
| Peak memory | 270188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 206832941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma x_throughput.4206832941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3718208016 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 62389209 ps |
| CPU time | 4.39 seconds |
| Started | Sep 09 09:26:42 PM UTC 24 |
| Finished | Sep 09 09:26:47 PM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718208016 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.3718208016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2683853975 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 96968626 ps |
| CPU time | 7.72 seconds |
| Started | Sep 09 09:26:34 PM UTC 24 |
| Finished | Sep 09 09:26:42 PM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683853975 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2683853975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.2035543299 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 183062459 ps |
| CPU time | 8.74 seconds |
| Started | Sep 09 09:25:32 PM UTC 24 |
| Finished | Sep 09 09:25:42 PM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035543299 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.2035543299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1281076079 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 130480646818 ps |
| CPU time | 635.18 seconds |
| Started | Sep 09 09:25:36 PM UTC 24 |
| Finished | Sep 09 09:36:19 PM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281076079 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acc ess_b2b.1281076079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.816392358 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 82694446 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 09:26:31 PM UTC 24 |
| Finished | Sep 09 09:26:33 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816392358 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.816392358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3021665662 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1243163550 ps |
| CPU time | 122.51 seconds |
| Started | Sep 09 09:26:28 PM UTC 24 |
| Finished | Sep 09 09:28:33 PM UTC 24 |
| Peak memory | 368428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021665662 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3021665662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.1433954639 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 132773490 ps |
| CPU time | 3.16 seconds |
| Started | Sep 09 09:25:05 PM UTC 24 |
| Finished | Sep 09 09:25:10 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433954639 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1433954639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.409501213 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 7872317835 ps |
| CPU time | 1665.68 seconds |
| Started | Sep 09 09:26:44 PM UTC 24 |
| Finished | Sep 09 09:54:46 PM UTC 24 |
| Peak memory | 385276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409501213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.409501213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.91537955 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1238082181 ps |
| CPU time | 308.88 seconds |
| Started | Sep 09 09:26:43 PM UTC 24 |
| Finished | Sep 09 09:31:56 PM UTC 24 |
| Peak memory | 388964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91537955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.91537955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3573461968 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 9595180393 ps |
| CPU time | 247.85 seconds |
| Started | Sep 09 09:25:11 PM UTC 24 |
| Finished | Sep 09 09:29:22 PM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573461968 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.3573461968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2951389199 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 90584250 ps |
| CPU time | 23.37 seconds |
| Started | Sep 09 09:25:42 PM UTC 24 |
| Finished | Sep 09 09:26:07 PM UTC 24 |
| Peak memory | 286888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2951389199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_t hroughput_w_partial_write.2951389199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2864434269 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3012899787 ps |
| CPU time | 456.13 seconds |
| Started | Sep 09 09:27:40 PM UTC 24 |
| Finished | Sep 09 09:35:22 PM UTC 24 |
| Peak memory | 384864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864434269 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during _key_req.2864434269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.631389783 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 20593956 ps |
| CPU time | 0.9 seconds |
| Started | Sep 09 09:28:08 PM UTC 24 |
| Finished | Sep 09 09:28:09 PM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631389783 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.631389783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.508978817 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 534290401 ps |
| CPU time | 40.8 seconds |
| Started | Sep 09 09:26:56 PM UTC 24 |
| Finished | Sep 09 09:27:39 PM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508978817 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.508978817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.3480750001 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 15121789430 ps |
| CPU time | 1082.72 seconds |
| Started | Sep 09 09:27:43 PM UTC 24 |
| Finished | Sep 09 09:45:58 PM UTC 24 |
| Peak memory | 386952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480750001 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.3480750001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1331669048 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 553882491 ps |
| CPU time | 8.71 seconds |
| Started | Sep 09 09:27:40 PM UTC 24 |
| Finished | Sep 09 09:27:50 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331669048 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.1331669048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2405813255 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 124925436 ps |
| CPU time | 75.56 seconds |
| Started | Sep 09 09:27:31 PM UTC 24 |
| Finished | Sep 09 09:28:48 PM UTC 24 |
| Peak memory | 372592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 405813255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma x_throughput.2405813255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.4164045471 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 224968237 ps |
| CPU time | 4.3 seconds |
| Started | Sep 09 09:27:50 PM UTC 24 |
| Finished | Sep 09 09:27:56 PM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164045471 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.4164045471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1845236826 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 587886144 ps |
| CPU time | 15.15 seconds |
| Started | Sep 09 09:27:50 PM UTC 24 |
| Finished | Sep 09 09:28:07 PM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845236826 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.1845236826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.4214255790 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2822185501 ps |
| CPU time | 73.43 seconds |
| Started | Sep 09 09:26:54 PM UTC 24 |
| Finished | Sep 09 09:28:09 PM UTC 24 |
| Peak memory | 300924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214255790 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.4214255790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.981267456 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 173936221 ps |
| CPU time | 67.27 seconds |
| Started | Sep 09 09:27:03 PM UTC 24 |
| Finished | Sep 09 09:28:12 PM UTC 24 |
| Peak memory | 331888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981267456 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.981267456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.237966964 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 76535269802 ps |
| CPU time | 525.64 seconds |
| Started | Sep 09 09:27:19 PM UTC 24 |
| Finished | Sep 09 09:36:11 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237966964 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acce ss_b2b.237966964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.59476790 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 98791170 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:27:47 PM UTC 24 |
| Finished | Sep 09 09:27:50 PM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59476790 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.59476790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1017286281 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1831653465 ps |
| CPU time | 491.89 seconds |
| Started | Sep 09 09:27:47 PM UTC 24 |
| Finished | Sep 09 09:36:05 PM UTC 24 |
| Peak memory | 384812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017286281 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1017286281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2087360386 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1389703418 ps |
| CPU time | 10.2 seconds |
| Started | Sep 09 09:26:51 PM UTC 24 |
| Finished | Sep 09 09:27:02 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087360386 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2087360386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.470819251 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 46083338944 ps |
| CPU time | 2530.17 seconds |
| Started | Sep 09 09:27:56 PM UTC 24 |
| Finished | Sep 09 10:10:32 PM UTC 24 |
| Peak memory | 388792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470819251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.470819251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3430337268 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2515709053 ps |
| CPU time | 246.41 seconds |
| Started | Sep 09 09:27:54 PM UTC 24 |
| Finished | Sep 09 09:32:05 PM UTC 24 |
| Peak memory | 340264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430337268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3430337268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3327887103 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3295832456 ps |
| CPU time | 420.64 seconds |
| Started | Sep 09 09:26:58 PM UTC 24 |
| Finished | Sep 09 09:34:05 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327887103 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.3327887103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2164370006 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 63402239 ps |
| CPU time | 8.77 seconds |
| Started | Sep 09 09:27:36 PM UTC 24 |
| Finished | Sep 09 09:27:46 PM UTC 24 |
| Peak memory | 247652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2164370006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.2164370006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3380237107 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9342428741 ps |
| CPU time | 591.5 seconds |
| Started | Sep 09 09:29:01 PM UTC 24 |
| Finished | Sep 09 09:39:00 PM UTC 24 |
| Peak memory | 376752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380237107 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during _key_req.3380237107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3514425255 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 14296203 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:29:30 PM UTC 24 |
| Finished | Sep 09 09:29:32 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514425255 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3514425255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.581373596 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5144677642 ps |
| CPU time | 61.99 seconds |
| Started | Sep 09 09:28:13 PM UTC 24 |
| Finished | Sep 09 09:29:17 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581373596 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.581373596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1924762074 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1358745078 ps |
| CPU time | 292.77 seconds |
| Started | Sep 09 09:29:02 PM UTC 24 |
| Finished | Sep 09 09:33:59 PM UTC 24 |
| Peak memory | 372608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924762074 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.1924762074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.322602605 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 11770142123 ps |
| CPU time | 13.35 seconds |
| Started | Sep 09 09:28:52 PM UTC 24 |
| Finished | Sep 09 09:29:07 PM UTC 24 |
| Peak memory | 214196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322602605 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.322602605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2754648777 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 395769187 ps |
| CPU time | 47.2 seconds |
| Started | Sep 09 09:28:49 PM UTC 24 |
| Finished | Sep 09 09:29:38 PM UTC 24 |
| Peak memory | 323436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 754648777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ma x_throughput.2754648777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.364287233 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 391235981 ps |
| CPU time | 8.43 seconds |
| Started | Sep 09 09:29:20 PM UTC 24 |
| Finished | Sep 09 09:29:30 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364287233 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.364287233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.269515052 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1339659921 ps |
| CPU time | 8.3 seconds |
| Started | Sep 09 09:29:20 PM UTC 24 |
| Finished | Sep 09 09:29:30 PM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269515052 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.269515052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3063453695 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 46706765731 ps |
| CPU time | 903.49 seconds |
| Started | Sep 09 09:28:11 PM UTC 24 |
| Finished | Sep 09 09:43:25 PM UTC 24 |
| Peak memory | 379060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063453695 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3063453695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2885238991 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 125662615 ps |
| CPU time | 25.47 seconds |
| Started | Sep 09 09:28:34 PM UTC 24 |
| Finished | Sep 09 09:29:01 PM UTC 24 |
| Peak memory | 292724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885238991 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.2885238991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2072394221 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 14544879320 ps |
| CPU time | 483.45 seconds |
| Started | Sep 09 09:28:38 PM UTC 24 |
| Finished | Sep 09 09:36:48 PM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072394221 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acc ess_b2b.2072394221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2755269724 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 25713797 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:29:17 PM UTC 24 |
| Finished | Sep 09 09:29:19 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755269724 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2755269724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3036916762 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 12265990166 ps |
| CPU time | 871.53 seconds |
| Started | Sep 09 09:29:08 PM UTC 24 |
| Finished | Sep 09 09:43:49 PM UTC 24 |
| Peak memory | 383156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036916762 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3036916762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.1370032017 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 141728850 ps |
| CPU time | 12.78 seconds |
| Started | Sep 09 09:28:11 PM UTC 24 |
| Finished | Sep 09 09:28:25 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370032017 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1370032017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1026794865 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 25830102865 ps |
| CPU time | 1413.37 seconds |
| Started | Sep 09 09:29:23 PM UTC 24 |
| Finished | Sep 09 09:53:12 PM UTC 24 |
| Peak memory | 376752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102679486 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.1026794865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4159157004 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1490945939 ps |
| CPU time | 81.38 seconds |
| Started | Sep 09 09:29:22 PM UTC 24 |
| Finished | Sep 09 09:30:46 PM UTC 24 |
| Peak memory | 300856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159157004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.4159157004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1739926304 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 8283165345 ps |
| CPU time | 257.58 seconds |
| Started | Sep 09 09:28:26 PM UTC 24 |
| Finished | Sep 09 09:32:48 PM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739926304 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.1739926304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3680738103 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 158381512 ps |
| CPU time | 75.09 seconds |
| Started | Sep 09 09:28:49 PM UTC 24 |
| Finished | Sep 09 09:30:06 PM UTC 24 |
| Peak memory | 378992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3680738103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t hroughput_w_partial_write.3680738103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.171084812 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 18864708145 ps |
| CPU time | 1278.48 seconds |
| Started | Sep 09 09:30:10 PM UTC 24 |
| Finished | Sep 09 09:51:42 PM UTC 24 |
| Peak memory | 384916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171084812 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_ key_req.171084812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2394647991 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 46740261 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:30:35 PM UTC 24 |
| Finished | Sep 09 09:30:37 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394647991 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2394647991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.1016538276 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 10189673301 ps |
| CPU time | 31.62 seconds |
| Started | Sep 09 09:29:38 PM UTC 24 |
| Finished | Sep 09 09:30:11 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016538276 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.1016538276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.458022187 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1880119481 ps |
| CPU time | 131.69 seconds |
| Started | Sep 09 09:30:10 PM UTC 24 |
| Finished | Sep 09 09:32:25 PM UTC 24 |
| Peak memory | 370736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458022187 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.458022187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3689675112 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2521600370 ps |
| CPU time | 7.43 seconds |
| Started | Sep 09 09:30:07 PM UTC 24 |
| Finished | Sep 09 09:30:16 PM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689675112 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.3689675112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2987403960 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 449692937 ps |
| CPU time | 10.89 seconds |
| Started | Sep 09 09:30:04 PM UTC 24 |
| Finished | Sep 09 09:30:16 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 987403960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma x_throughput.2987403960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1534906358 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 195586583 ps |
| CPU time | 5.25 seconds |
| Started | Sep 09 09:30:20 PM UTC 24 |
| Finished | Sep 09 09:30:26 PM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534906358 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.1534906358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2610499095 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2615077176 ps |
| CPU time | 18.43 seconds |
| Started | Sep 09 09:30:17 PM UTC 24 |
| Finished | Sep 09 09:30:36 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610499095 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.2610499095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3137739766 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5444965244 ps |
| CPU time | 294.51 seconds |
| Started | Sep 09 09:29:34 PM UTC 24 |
| Finished | Sep 09 09:34:32 PM UTC 24 |
| Peak memory | 309096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137739766 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.3137739766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.403127870 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4137801829 ps |
| CPU time | 25.27 seconds |
| Started | Sep 09 09:29:40 PM UTC 24 |
| Finished | Sep 09 09:30:06 PM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403127870 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.403127870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.530751028 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 60291206918 ps |
| CPU time | 444.12 seconds |
| Started | Sep 09 09:30:00 PM UTC 24 |
| Finished | Sep 09 09:37:30 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530751028 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acce ss_b2b.530751028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3002706252 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 51534757 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:30:17 PM UTC 24 |
| Finished | Sep 09 09:30:19 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002706252 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3002706252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.1151608707 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6426910304 ps |
| CPU time | 324.55 seconds |
| Started | Sep 09 09:30:11 PM UTC 24 |
| Finished | Sep 09 09:35:40 PM UTC 24 |
| Peak memory | 384820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151608707 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1151608707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3330453018 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1247517273 ps |
| CPU time | 58.77 seconds |
| Started | Sep 09 09:29:31 PM UTC 24 |
| Finished | Sep 09 09:30:31 PM UTC 24 |
| Peak memory | 333508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330453018 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3330453018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2547725640 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 33527506293 ps |
| CPU time | 2495.4 seconds |
| Started | Sep 09 09:30:32 PM UTC 24 |
| Finished | Sep 09 10:12:34 PM UTC 24 |
| Peak memory | 388808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254772564 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.2547725640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2144515062 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 10510896657 ps |
| CPU time | 799.75 seconds |
| Started | Sep 09 09:30:27 PM UTC 24 |
| Finished | Sep 09 09:43:56 PM UTC 24 |
| Peak memory | 370672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144515062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2144515062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1289327973 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 19159420408 ps |
| CPU time | 525.71 seconds |
| Started | Sep 09 09:29:39 PM UTC 24 |
| Finished | Sep 09 09:38:31 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289327973 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.1289327973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.3789397005 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 132871190 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 09:30:07 PM UTC 24 |
| Finished | Sep 09 09:30:10 PM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3789397005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_t hroughput_w_partial_write.3789397005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.45156020 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3964197703 ps |
| CPU time | 151.53 seconds |
| Started | Sep 09 09:31:08 PM UTC 24 |
| Finished | Sep 09 09:33:43 PM UTC 24 |
| Peak memory | 329896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45156020 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during_k ey_req.45156020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3848487336 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 50567472 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:31:57 PM UTC 24 |
| Finished | Sep 09 09:31:59 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848487336 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3848487336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.4172357089 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3588472112 ps |
| CPU time | 95.81 seconds |
| Started | Sep 09 09:30:45 PM UTC 24 |
| Finished | Sep 09 09:32:23 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172357089 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.4172357089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1501507016 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 6609675118 ps |
| CPU time | 685.2 seconds |
| Started | Sep 09 09:31:10 PM UTC 24 |
| Finished | Sep 09 09:42:42 PM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501507016 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.1501507016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.180280203 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 236455097 ps |
| CPU time | 5.35 seconds |
| Started | Sep 09 09:31:02 PM UTC 24 |
| Finished | Sep 09 09:31:09 PM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180280203 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.180280203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2798146542 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 64063237 ps |
| CPU time | 8.56 seconds |
| Started | Sep 09 09:30:58 PM UTC 24 |
| Finished | Sep 09 09:31:08 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 798146542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ma x_throughput.2798146542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3870240194 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 176254157 ps |
| CPU time | 6.31 seconds |
| Started | Sep 09 09:31:49 PM UTC 24 |
| Finished | Sep 09 09:31:56 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870240194 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.3870240194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2459391344 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 181394022 ps |
| CPU time | 13.26 seconds |
| Started | Sep 09 09:31:39 PM UTC 24 |
| Finished | Sep 09 09:31:53 PM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459391344 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.2459391344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.732561552 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 167213148005 ps |
| CPU time | 1448.28 seconds |
| Started | Sep 09 09:30:38 PM UTC 24 |
| Finished | Sep 09 09:55:02 PM UTC 24 |
| Peak memory | 385216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732561552 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.732561552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.448440564 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 431886495 ps |
| CPU time | 45.97 seconds |
| Started | Sep 09 09:30:47 PM UTC 24 |
| Finished | Sep 09 09:31:35 PM UTC 24 |
| Peak memory | 317276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448440564 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.448440564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3014138773 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 58647069176 ps |
| CPU time | 512.49 seconds |
| Started | Sep 09 09:30:54 PM UTC 24 |
| Finished | Sep 09 09:39:34 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014138773 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc ess_b2b.3014138773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.905699319 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 88000513 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:31:36 PM UTC 24 |
| Finished | Sep 09 09:31:38 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905699319 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.905699319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1478221616 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 26731169623 ps |
| CPU time | 341.56 seconds |
| Started | Sep 09 09:31:33 PM UTC 24 |
| Finished | Sep 09 09:37:19 PM UTC 24 |
| Peak memory | 385204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478221616 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1478221616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.278743172 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3607803488 ps |
| CPU time | 14.67 seconds |
| Started | Sep 09 09:30:37 PM UTC 24 |
| Finished | Sep 09 09:30:53 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278743172 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.278743172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3299034055 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 27833890515 ps |
| CPU time | 4266.38 seconds |
| Started | Sep 09 09:31:57 PM UTC 24 |
| Finished | Sep 09 10:43:46 PM UTC 24 |
| Peak memory | 396984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329903405 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.3299034055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2314208480 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4774743273 ps |
| CPU time | 243.16 seconds |
| Started | Sep 09 09:31:54 PM UTC 24 |
| Finished | Sep 09 09:36:01 PM UTC 24 |
| Peak memory | 375020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314208480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2314208480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2952644899 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2980656850 ps |
| CPU time | 405.31 seconds |
| Started | Sep 09 09:30:45 PM UTC 24 |
| Finished | Sep 09 09:37:36 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952644899 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2952644899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.4089755360 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 213875488 ps |
| CPU time | 47.07 seconds |
| Started | Sep 09 09:30:59 PM UTC 24 |
| Finished | Sep 09 09:31:48 PM UTC 24 |
| Peak memory | 319336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4089755360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t hroughput_w_partial_write.4089755360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2580670353 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 6677226600 ps |
| CPU time | 76.74 seconds |
| Started | Sep 09 09:33:05 PM UTC 24 |
| Finished | Sep 09 09:34:24 PM UTC 24 |
| Peak memory | 296872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580670353 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during _key_req.2580670353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.4000522855 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 15621821 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 09:33:41 PM UTC 24 |
| Finished | Sep 09 09:33:43 PM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000522855 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.4000522855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1435516054 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3078167945 ps |
| CPU time | 22.37 seconds |
| Started | Sep 09 09:32:08 PM UTC 24 |
| Finished | Sep 09 09:32:32 PM UTC 24 |
| Peak memory | 213968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435516054 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1435516054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.3600587933 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 20923872881 ps |
| CPU time | 1472.61 seconds |
| Started | Sep 09 09:33:15 PM UTC 24 |
| Finished | Sep 09 09:58:04 PM UTC 24 |
| Peak memory | 378820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600587933 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.3600587933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.2275356124 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1593933794 ps |
| CPU time | 8.1 seconds |
| Started | Sep 09 09:33:05 PM UTC 24 |
| Finished | Sep 09 09:33:14 PM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275356124 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.2275356124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2023547865 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 111938204 ps |
| CPU time | 50.59 seconds |
| Started | Sep 09 09:32:39 PM UTC 24 |
| Finished | Sep 09 09:33:32 PM UTC 24 |
| Peak memory | 321648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 023547865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma x_throughput.2023547865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3313705778 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 54677209 ps |
| CPU time | 4.39 seconds |
| Started | Sep 09 09:33:28 PM UTC 24 |
| Finished | Sep 09 09:33:33 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313705778 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.3313705778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.407673571 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2828727093 ps |
| CPU time | 14.13 seconds |
| Started | Sep 09 09:33:25 PM UTC 24 |
| Finished | Sep 09 09:33:40 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407673571 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.407673571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3784232903 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 31517172358 ps |
| CPU time | 1560.34 seconds |
| Started | Sep 09 09:32:05 PM UTC 24 |
| Finished | Sep 09 09:58:22 PM UTC 24 |
| Peak memory | 386924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784232903 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.3784232903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.953898863 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 177795407 ps |
| CPU time | 11.13 seconds |
| Started | Sep 09 09:32:26 PM UTC 24 |
| Finished | Sep 09 09:32:38 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953898863 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.953898863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.455044078 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 15856418100 ps |
| CPU time | 364.44 seconds |
| Started | Sep 09 09:32:33 PM UTC 24 |
| Finished | Sep 09 09:38:42 PM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455044078 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acce ss_b2b.455044078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1593968033 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 103363711 ps |
| CPU time | 1.34 seconds |
| Started | Sep 09 09:33:21 PM UTC 24 |
| Finished | Sep 09 09:33:24 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593968033 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1593968033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.3514832241 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 24107634829 ps |
| CPU time | 482.35 seconds |
| Started | Sep 09 09:33:20 PM UTC 24 |
| Finished | Sep 09 09:41:28 PM UTC 24 |
| Peak memory | 378804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514832241 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3514832241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2352681630 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 123932348 ps |
| CPU time | 84.81 seconds |
| Started | Sep 09 09:32:00 PM UTC 24 |
| Finished | Sep 09 09:33:27 PM UTC 24 |
| Peak memory | 366452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352681630 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2352681630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3450822083 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 11357350089 ps |
| CPU time | 3908.4 seconds |
| Started | Sep 09 09:33:34 PM UTC 24 |
| Finished | Sep 09 10:39:22 PM UTC 24 |
| Peak memory | 386744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345082208 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.3450822083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4213548291 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3777298208 ps |
| CPU time | 198.36 seconds |
| Started | Sep 09 09:33:33 PM UTC 24 |
| Finished | Sep 09 09:36:54 PM UTC 24 |
| Peak memory | 368544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213548291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.4213548291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3355416804 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 18397613824 ps |
| CPU time | 365.92 seconds |
| Started | Sep 09 09:32:24 PM UTC 24 |
| Finished | Sep 09 09:38:35 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355416804 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.3355416804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1337181601 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 109373970 ps |
| CPU time | 15.43 seconds |
| Started | Sep 09 09:32:48 PM UTC 24 |
| Finished | Sep 09 09:33:05 PM UTC 24 |
| Peak memory | 268136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1337181601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_t hroughput_w_partial_write.1337181601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3853609360 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7606552683 ps |
| CPU time | 379.66 seconds |
| Started | Sep 09 09:10:37 PM UTC 24 |
| Finished | Sep 09 09:17:03 PM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853609360 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_ key_req.3853609360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3311357645 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 65869507 ps |
| CPU time | 0.83 seconds |
| Started | Sep 09 09:10:40 PM UTC 24 |
| Finished | Sep 09 09:10:42 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311357645 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3311357645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.3785620898 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 762821805 ps |
| CPU time | 17.66 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:10:58 PM UTC 24 |
| Peak memory | 213796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785620898 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.3785620898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.2343055856 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 169425367784 ps |
| CPU time | 940.71 seconds |
| Started | Sep 09 09:10:37 PM UTC 24 |
| Finished | Sep 09 09:26:28 PM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343055856 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.2343055856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3583095074 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2273162054 ps |
| CPU time | 7.36 seconds |
| Started | Sep 09 09:10:37 PM UTC 24 |
| Finished | Sep 09 09:10:46 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583095074 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.3583095074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3868587788 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 180737317 ps |
| CPU time | 24.2 seconds |
| Started | Sep 09 09:10:37 PM UTC 24 |
| Finished | Sep 09 09:11:03 PM UTC 24 |
| Peak memory | 303204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 868587788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max _throughput.3868587788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.298775725 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 138038821 ps |
| CPU time | 6.44 seconds |
| Started | Sep 09 09:10:38 PM UTC 24 |
| Finished | Sep 09 09:10:47 PM UTC 24 |
| Peak memory | 224108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298775725 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.298775725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3261758678 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 93577862 ps |
| CPU time | 5.05 seconds |
| Started | Sep 09 09:10:38 PM UTC 24 |
| Finished | Sep 09 09:10:45 PM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261758678 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.3261758678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4228351973 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 37941613431 ps |
| CPU time | 698.69 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:22:27 PM UTC 24 |
| Peak memory | 372628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228351973 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.4228351973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2238566811 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 279985643 ps |
| CPU time | 5.82 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:10:47 PM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238566811 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.2238566811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2162942139 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 56689511761 ps |
| CPU time | 432.26 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:17:55 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162942139 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce ss_b2b.2162942139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3785724838 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 104577302 ps |
| CPU time | 0.81 seconds |
| Started | Sep 09 09:10:37 PM UTC 24 |
| Finished | Sep 09 09:10:40 PM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785724838 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3785724838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.790878511 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 16474410744 ps |
| CPU time | 1078.72 seconds |
| Started | Sep 09 09:10:37 PM UTC 24 |
| Finished | Sep 09 09:28:48 PM UTC 24 |
| Peak memory | 384956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790878511 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.790878511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2397604078 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 25743676138 ps |
| CPU time | 1563.04 seconds |
| Started | Sep 09 09:10:39 PM UTC 24 |
| Finished | Sep 09 09:36:57 PM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239760407 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.2397604078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3827696189 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 7160708049 ps |
| CPU time | 244.01 seconds |
| Started | Sep 09 09:10:36 PM UTC 24 |
| Finished | Sep 09 09:14:45 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827696189 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.3827696189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4158933013 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 379430869 ps |
| CPU time | 27.51 seconds |
| Started | Sep 09 09:10:37 PM UTC 24 |
| Finished | Sep 09 09:11:06 PM UTC 24 |
| Peak memory | 313192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4158933013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th roughput_w_partial_write.4158933013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.4270607617 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 15167226265 ps |
| CPU time | 1189.66 seconds |
| Started | Sep 09 09:34:52 PM UTC 24 |
| Finished | Sep 09 09:54:55 PM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270607617 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during _key_req.4270607617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2159190354 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 50541694 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 09:35:42 PM UTC 24 |
| Finished | Sep 09 09:35:44 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159190354 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.2159190354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3859227990 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 18924906140 ps |
| CPU time | 71.9 seconds |
| Started | Sep 09 09:33:57 PM UTC 24 |
| Finished | Sep 09 09:35:11 PM UTC 24 |
| Peak memory | 214136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859227990 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3859227990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3138505096 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 12772740027 ps |
| CPU time | 1331.79 seconds |
| Started | Sep 09 09:35:04 PM UTC 24 |
| Finished | Sep 09 09:57:30 PM UTC 24 |
| Peak memory | 385268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138505096 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.3138505096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1316062386 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 753460781 ps |
| CPU time | 13.12 seconds |
| Started | Sep 09 09:34:37 PM UTC 24 |
| Finished | Sep 09 09:34:51 PM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316062386 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.1316062386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3832649895 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 95532800 ps |
| CPU time | 36.52 seconds |
| Started | Sep 09 09:34:25 PM UTC 24 |
| Finished | Sep 09 09:35:03 PM UTC 24 |
| Peak memory | 304936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 832649895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ma x_throughput.3832649895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1025030429 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 137984508 ps |
| CPU time | 6.42 seconds |
| Started | Sep 09 09:35:23 PM UTC 24 |
| Finished | Sep 09 09:35:31 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025030429 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.1025030429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3696136510 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 266789757 ps |
| CPU time | 11.24 seconds |
| Started | Sep 09 09:35:21 PM UTC 24 |
| Finished | Sep 09 09:35:34 PM UTC 24 |
| Peak memory | 224076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696136510 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.3696136510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2323810075 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2706226056 ps |
| CPU time | 653.86 seconds |
| Started | Sep 09 09:33:44 PM UTC 24 |
| Finished | Sep 09 09:44:45 PM UTC 24 |
| Peak memory | 376676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323810075 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.2323810075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.965504768 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 866049490 ps |
| CPU time | 15.96 seconds |
| Started | Sep 09 09:34:06 PM UTC 24 |
| Finished | Sep 09 09:34:24 PM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965504768 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.965504768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2182951011 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 136739830724 ps |
| CPU time | 367.31 seconds |
| Started | Sep 09 09:34:25 PM UTC 24 |
| Finished | Sep 09 09:40:37 PM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182951011 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc ess_b2b.2182951011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2211691433 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 36982384 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 09:35:18 PM UTC 24 |
| Finished | Sep 09 09:35:20 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211691433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2211691433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.342666958 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 62311327918 ps |
| CPU time | 924.54 seconds |
| Started | Sep 09 09:35:12 PM UTC 24 |
| Finished | Sep 09 09:50:47 PM UTC 24 |
| Peak memory | 378808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342666958 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.342666958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.177361107 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1033879524 ps |
| CPU time | 12.19 seconds |
| Started | Sep 09 09:33:43 PM UTC 24 |
| Finished | Sep 09 09:33:56 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177361107 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.177361107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1023669151 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 35383655225 ps |
| CPU time | 2045.25 seconds |
| Started | Sep 09 09:35:35 PM UTC 24 |
| Finished | Sep 09 10:10:01 PM UTC 24 |
| Peak memory | 387000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102366915 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.1023669151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3516718923 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4758873222 ps |
| CPU time | 132.66 seconds |
| Started | Sep 09 09:35:32 PM UTC 24 |
| Finished | Sep 09 09:37:46 PM UTC 24 |
| Peak memory | 389356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516718923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3516718923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.4010657560 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 28880009680 ps |
| CPU time | 349.01 seconds |
| Started | Sep 09 09:33:59 PM UTC 24 |
| Finished | Sep 09 09:39:54 PM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010657560 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.4010657560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1051983095 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 66025794 ps |
| CPU time | 2.32 seconds |
| Started | Sep 09 09:34:33 PM UTC 24 |
| Finished | Sep 09 09:34:36 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1051983095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t hroughput_w_partial_write.1051983095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2210868602 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 9295321934 ps |
| CPU time | 965.9 seconds |
| Started | Sep 09 09:36:49 PM UTC 24 |
| Finished | Sep 09 09:53:05 PM UTC 24 |
| Peak memory | 386984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210868602 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during _key_req.2210868602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3837271988 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 38068748 ps |
| CPU time | 0.86 seconds |
| Started | Sep 09 09:37:13 PM UTC 24 |
| Finished | Sep 09 09:37:15 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837271988 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.3837271988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.229347887 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 237638000 ps |
| CPU time | 19.27 seconds |
| Started | Sep 09 09:36:02 PM UTC 24 |
| Finished | Sep 09 09:36:23 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229347887 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.229347887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2058542405 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 12762920112 ps |
| CPU time | 1255.12 seconds |
| Started | Sep 09 09:36:51 PM UTC 24 |
| Finished | Sep 09 09:57:59 PM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058542405 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.2058542405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1049688101 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1121882860 ps |
| CPU time | 5.68 seconds |
| Started | Sep 09 09:36:43 PM UTC 24 |
| Finished | Sep 09 09:36:49 PM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049688101 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.1049688101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1635541306 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 475526489 ps |
| CPU time | 12.31 seconds |
| Started | Sep 09 09:36:23 PM UTC 24 |
| Finished | Sep 09 09:36:37 PM UTC 24 |
| Peak memory | 272216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 635541306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma x_throughput.1635541306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.332816276 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 369375395 ps |
| CPU time | 4.42 seconds |
| Started | Sep 09 09:37:06 PM UTC 24 |
| Finished | Sep 09 09:37:12 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332816276 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.332816276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.962959164 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2731584957 ps |
| CPU time | 9.75 seconds |
| Started | Sep 09 09:37:01 PM UTC 24 |
| Finished | Sep 09 09:37:12 PM UTC 24 |
| Peak memory | 224156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962959164 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.962959164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2900291404 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3459143163 ps |
| CPU time | 28.04 seconds |
| Started | Sep 09 09:36:12 PM UTC 24 |
| Finished | Sep 09 09:36:42 PM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900291404 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2900291404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2801702846 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4318819462 ps |
| CPU time | 225.26 seconds |
| Started | Sep 09 09:36:19 PM UTC 24 |
| Finished | Sep 09 09:40:08 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801702846 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc ess_b2b.2801702846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1863845429 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 71296457 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:36:58 PM UTC 24 |
| Finished | Sep 09 09:37:00 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863845429 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1863845429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.2682582157 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 30840619253 ps |
| CPU time | 509.74 seconds |
| Started | Sep 09 09:36:55 PM UTC 24 |
| Finished | Sep 09 09:45:31 PM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682582157 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2682582157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.2532691193 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 187429669 ps |
| CPU time | 9.51 seconds |
| Started | Sep 09 09:35:45 PM UTC 24 |
| Finished | Sep 09 09:35:56 PM UTC 24 |
| Peak memory | 245888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532691193 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2532691193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.946112314 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 365712679319 ps |
| CPU time | 2467.33 seconds |
| Started | Sep 09 09:37:12 PM UTC 24 |
| Finished | Sep 09 10:18:45 PM UTC 24 |
| Peak memory | 388724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946112314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.946112314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1495145813 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1888444790 ps |
| CPU time | 531.6 seconds |
| Started | Sep 09 09:37:08 PM UTC 24 |
| Finished | Sep 09 09:46:06 PM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495145813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1495145813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.109253055 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1689301902 ps |
| CPU time | 160.13 seconds |
| Started | Sep 09 09:36:06 PM UTC 24 |
| Finished | Sep 09 09:38:49 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109253055 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.109253055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1723115096 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 95151246 ps |
| CPU time | 28.14 seconds |
| Started | Sep 09 09:36:37 PM UTC 24 |
| Finished | Sep 09 09:37:07 PM UTC 24 |
| Peak memory | 297132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1723115096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_t hroughput_w_partial_write.1723115096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3776163367 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3343333451 ps |
| CPU time | 1309.36 seconds |
| Started | Sep 09 09:38:40 PM UTC 24 |
| Finished | Sep 09 10:00:43 PM UTC 24 |
| Peak memory | 385192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776163367 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during _key_req.3776163367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.734490805 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 27898831 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 09:39:00 PM UTC 24 |
| Finished | Sep 09 09:39:02 PM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734490805 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.734490805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.4213032519 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 14995390133 ps |
| CPU time | 79.38 seconds |
| Started | Sep 09 09:37:31 PM UTC 24 |
| Finished | Sep 09 09:38:52 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213032519 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.4213032519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3080352338 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 8581951261 ps |
| CPU time | 725.44 seconds |
| Started | Sep 09 09:38:43 PM UTC 24 |
| Finished | Sep 09 09:50:56 PM UTC 24 |
| Peak memory | 382824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080352338 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.3080352338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1129640332 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 663173893 ps |
| CPU time | 7.16 seconds |
| Started | Sep 09 09:38:36 PM UTC 24 |
| Finished | Sep 09 09:38:45 PM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129640332 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.1129640332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2107206017 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 89100203 ps |
| CPU time | 29.36 seconds |
| Started | Sep 09 09:38:32 PM UTC 24 |
| Finished | Sep 09 09:39:03 PM UTC 24 |
| Peak memory | 296816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 107206017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ma x_throughput.2107206017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.197105194 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 162672750 ps |
| CPU time | 7.22 seconds |
| Started | Sep 09 09:38:53 PM UTC 24 |
| Finished | Sep 09 09:39:01 PM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197105194 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.197105194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.751641701 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 74944062 ps |
| CPU time | 5.55 seconds |
| Started | Sep 09 09:38:53 PM UTC 24 |
| Finished | Sep 09 09:39:00 PM UTC 24 |
| Peak memory | 224152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751641701 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.751641701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2807599680 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 42923413691 ps |
| CPU time | 995.21 seconds |
| Started | Sep 09 09:37:20 PM UTC 24 |
| Finished | Sep 09 09:54:06 PM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807599680 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.2807599680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1663482957 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1202817201 ps |
| CPU time | 24.48 seconds |
| Started | Sep 09 09:37:47 PM UTC 24 |
| Finished | Sep 09 09:38:13 PM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663482957 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.1663482957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1275071796 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 8616223070 ps |
| CPU time | 184.14 seconds |
| Started | Sep 09 09:38:13 PM UTC 24 |
| Finished | Sep 09 09:41:20 PM UTC 24 |
| Peak memory | 214092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275071796 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc ess_b2b.1275071796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3433205277 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 47301694 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:38:50 PM UTC 24 |
| Finished | Sep 09 09:38:52 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433205277 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3433205277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.610281883 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 68560924739 ps |
| CPU time | 382.86 seconds |
| Started | Sep 09 09:38:46 PM UTC 24 |
| Finished | Sep 09 09:45:14 PM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610281883 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.610281883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.193951106 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 654057634 ps |
| CPU time | 101.09 seconds |
| Started | Sep 09 09:37:16 PM UTC 24 |
| Finished | Sep 09 09:39:00 PM UTC 24 |
| Peak memory | 372604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193951106 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.193951106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2530587229 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 32808440327 ps |
| CPU time | 1086.85 seconds |
| Started | Sep 09 09:39:00 PM UTC 24 |
| Finished | Sep 09 09:57:19 PM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253058722 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.2530587229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.4189095273 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 15484137362 ps |
| CPU time | 437.69 seconds |
| Started | Sep 09 09:37:37 PM UTC 24 |
| Finished | Sep 09 09:45:00 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189095273 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.4189095273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.220346404 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 163910947 ps |
| CPU time | 2.66 seconds |
| Started | Sep 09 09:38:35 PM UTC 24 |
| Finished | Sep 09 09:38:39 PM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 220346404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_th roughput_w_partial_write.220346404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.1945605220 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3313306597 ps |
| CPU time | 395.05 seconds |
| Started | Sep 09 09:40:03 PM UTC 24 |
| Finished | Sep 09 09:46:43 PM UTC 24 |
| Peak memory | 378804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945605220 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during _key_req.1945605220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1046131320 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 16932737 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:40:21 PM UTC 24 |
| Finished | Sep 09 09:40:23 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046131320 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1046131320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.468071665 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2383808140 ps |
| CPU time | 78.06 seconds |
| Started | Sep 09 09:39:04 PM UTC 24 |
| Finished | Sep 09 09:40:24 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468071665 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.468071665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.418096561 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2455343754 ps |
| CPU time | 650.93 seconds |
| Started | Sep 09 09:40:04 PM UTC 24 |
| Finished | Sep 09 09:51:03 PM UTC 24 |
| Peak memory | 376252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418096561 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.418096561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.325477788 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1343021907 ps |
| CPU time | 11.1 seconds |
| Started | Sep 09 09:39:55 PM UTC 24 |
| Finished | Sep 09 09:40:07 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325477788 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.325477788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1551841530 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 86868576 ps |
| CPU time | 15.77 seconds |
| Started | Sep 09 09:39:44 PM UTC 24 |
| Finished | Sep 09 09:40:01 PM UTC 24 |
| Peak memory | 272308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 551841530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma x_throughput.1551841530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3552763389 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 176986679 ps |
| CPU time | 7.42 seconds |
| Started | Sep 09 09:40:11 PM UTC 24 |
| Finished | Sep 09 09:40:20 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552763389 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3552763389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2630642231 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 456901992 ps |
| CPU time | 9.48 seconds |
| Started | Sep 09 09:40:09 PM UTC 24 |
| Finished | Sep 09 09:40:20 PM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630642231 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2630642231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2987336713 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 9077571842 ps |
| CPU time | 126.62 seconds |
| Started | Sep 09 09:39:04 PM UTC 24 |
| Finished | Sep 09 09:41:12 PM UTC 24 |
| Peak memory | 340144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987336713 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2987336713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2348372207 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 545772748 ps |
| CPU time | 45.74 seconds |
| Started | Sep 09 09:39:29 PM UTC 24 |
| Finished | Sep 09 09:40:16 PM UTC 24 |
| Peak memory | 313208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348372207 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2348372207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.384217945 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 7151832793 ps |
| CPU time | 228.13 seconds |
| Started | Sep 09 09:39:35 PM UTC 24 |
| Finished | Sep 09 09:43:27 PM UTC 24 |
| Peak memory | 213996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384217945 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acce ss_b2b.384217945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2001855985 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 25948621 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:40:08 PM UTC 24 |
| Finished | Sep 09 09:40:11 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001855985 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2001855985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3274609636 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 56448779511 ps |
| CPU time | 482.63 seconds |
| Started | Sep 09 09:40:04 PM UTC 24 |
| Finished | Sep 09 09:48:12 PM UTC 24 |
| Peak memory | 359972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274609636 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3274609636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.894395012 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 648045921 ps |
| CPU time | 92.72 seconds |
| Started | Sep 09 09:39:02 PM UTC 24 |
| Finished | Sep 09 09:40:37 PM UTC 24 |
| Peak memory | 379000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894395012 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.894395012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1089157095 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 373921730125 ps |
| CPU time | 3079.67 seconds |
| Started | Sep 09 09:40:21 PM UTC 24 |
| Finished | Sep 09 10:32:12 PM UTC 24 |
| Peak memory | 386744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108915709 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.1089157095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2343519180 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 12892666453 ps |
| CPU time | 304.02 seconds |
| Started | Sep 09 09:40:17 PM UTC 24 |
| Finished | Sep 09 09:45:26 PM UTC 24 |
| Peak memory | 391340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343519180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2343519180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.8431242 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2529966392 ps |
| CPU time | 300.4 seconds |
| Started | Sep 09 09:39:28 PM UTC 24 |
| Finished | Sep 09 09:44:32 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8431242 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.8431242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.795491459 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 519888968 ps |
| CPU time | 41.85 seconds |
| Started | Sep 09 09:39:52 PM UTC 24 |
| Finished | Sep 09 09:40:36 PM UTC 24 |
| Peak memory | 335652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 795491459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_th roughput_w_partial_write.795491459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.667294772 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 4041736482 ps |
| CPU time | 1034.14 seconds |
| Started | Sep 09 09:41:12 PM UTC 24 |
| Finished | Sep 09 09:58:38 PM UTC 24 |
| Peak memory | 378740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667294772 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during_ key_req.667294772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.420933570 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 44314987 ps |
| CPU time | 0.86 seconds |
| Started | Sep 09 09:41:35 PM UTC 24 |
| Finished | Sep 09 09:41:37 PM UTC 24 |
| Peak memory | 213288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420933570 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.420933570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.954255799 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2356108247 ps |
| CPU time | 31.86 seconds |
| Started | Sep 09 09:40:37 PM UTC 24 |
| Finished | Sep 09 09:41:11 PM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954255799 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.954255799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3752632197 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 4059800169 ps |
| CPU time | 160.57 seconds |
| Started | Sep 09 09:41:13 PM UTC 24 |
| Finished | Sep 09 09:43:56 PM UTC 24 |
| Peak memory | 370880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752632197 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.3752632197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.3202409033 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1138836430 ps |
| CPU time | 9.36 seconds |
| Started | Sep 09 09:41:11 PM UTC 24 |
| Finished | Sep 09 09:41:21 PM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202409033 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.3202409033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3291765266 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 286562554 ps |
| CPU time | 82.71 seconds |
| Started | Sep 09 09:41:07 PM UTC 24 |
| Finished | Sep 09 09:42:31 PM UTC 24 |
| Peak memory | 381044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 291765266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ma x_throughput.3291765266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2990879557 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 347605860 ps |
| CPU time | 6.78 seconds |
| Started | Sep 09 09:41:25 PM UTC 24 |
| Finished | Sep 09 09:41:33 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990879557 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.2990879557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2921792528 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 921542623 ps |
| CPU time | 13.06 seconds |
| Started | Sep 09 09:41:22 PM UTC 24 |
| Finished | Sep 09 09:41:37 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921792528 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.2921792528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2759816192 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 18746592290 ps |
| CPU time | 597.84 seconds |
| Started | Sep 09 09:40:25 PM UTC 24 |
| Finished | Sep 09 09:50:31 PM UTC 24 |
| Peak memory | 358264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759816192 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.2759816192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2661497016 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 313559736 ps |
| CPU time | 28.91 seconds |
| Started | Sep 09 09:40:38 PM UTC 24 |
| Finished | Sep 09 09:41:09 PM UTC 24 |
| Peak memory | 284856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661497016 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.2661497016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.295412052 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 50577264066 ps |
| CPU time | 325.1 seconds |
| Started | Sep 09 09:40:55 PM UTC 24 |
| Finished | Sep 09 09:46:25 PM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295412052 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acce ss_b2b.295412052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1546555393 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 97825212 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:41:22 PM UTC 24 |
| Finished | Sep 09 09:41:24 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546555393 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1546555393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.1923300790 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 13528455882 ps |
| CPU time | 421.15 seconds |
| Started | Sep 09 09:41:21 PM UTC 24 |
| Finished | Sep 09 09:48:27 PM UTC 24 |
| Peak memory | 348344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923300790 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1923300790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3371272487 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3901027005 ps |
| CPU time | 44.22 seconds |
| Started | Sep 09 09:40:24 PM UTC 24 |
| Finished | Sep 09 09:41:10 PM UTC 24 |
| Peak memory | 300880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371272487 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3371272487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3382432619 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3734249188 ps |
| CPU time | 410.2 seconds |
| Started | Sep 09 09:41:34 PM UTC 24 |
| Finished | Sep 09 09:48:29 PM UTC 24 |
| Peak memory | 383152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338243261 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.3382432619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3884791200 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2212436144 ps |
| CPU time | 64.02 seconds |
| Started | Sep 09 09:41:30 PM UTC 24 |
| Finished | Sep 09 09:42:35 PM UTC 24 |
| Peak memory | 327660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884791200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3884791200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3810015719 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 8764657078 ps |
| CPU time | 257.25 seconds |
| Started | Sep 09 09:40:38 PM UTC 24 |
| Finished | Sep 09 09:45:00 PM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810015719 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.3810015719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2001229438 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 426722487 ps |
| CPU time | 22.88 seconds |
| Started | Sep 09 09:41:10 PM UTC 24 |
| Finished | Sep 09 09:41:34 PM UTC 24 |
| Peak memory | 282344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2001229438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t hroughput_w_partial_write.2001229438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2963156753 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 15222785033 ps |
| CPU time | 1364.14 seconds |
| Started | Sep 09 09:43:01 PM UTC 24 |
| Finished | Sep 09 10:06:00 PM UTC 24 |
| Peak memory | 386912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963156753 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during _key_req.2963156753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.708746486 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 44366178 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 09:43:45 PM UTC 24 |
| Finished | Sep 09 09:43:47 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708746486 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.708746486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.4105975159 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 7116368451 ps |
| CPU time | 35.82 seconds |
| Started | Sep 09 09:42:21 PM UTC 24 |
| Finished | Sep 09 09:42:59 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105975159 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.4105975159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.2875148017 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 38690220976 ps |
| CPU time | 449.66 seconds |
| Started | Sep 09 09:43:05 PM UTC 24 |
| Finished | Sep 09 09:50:41 PM UTC 24 |
| Peak memory | 384888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875148017 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.2875148017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3241591976 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 309277838 ps |
| CPU time | 3.21 seconds |
| Started | Sep 09 09:43:00 PM UTC 24 |
| Finished | Sep 09 09:43:04 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241591976 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.3241591976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2439492664 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 215194405 ps |
| CPU time | 47.94 seconds |
| Started | Sep 09 09:42:43 PM UTC 24 |
| Finished | Sep 09 09:43:32 PM UTC 24 |
| Peak memory | 338096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 439492664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma x_throughput.2439492664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3326789898 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 101613385 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 09:43:29 PM UTC 24 |
| Finished | Sep 09 09:43:34 PM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326789898 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.3326789898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1953032347 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 686899602 ps |
| CPU time | 15.61 seconds |
| Started | Sep 09 09:43:28 PM UTC 24 |
| Finished | Sep 09 09:43:45 PM UTC 24 |
| Peak memory | 224144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953032347 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1953032347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.12418174 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 647613410 ps |
| CPU time | 166.98 seconds |
| Started | Sep 09 09:41:37 PM UTC 24 |
| Finished | Sep 09 09:44:27 PM UTC 24 |
| Peak memory | 356080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12418174 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.12418174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3579564349 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 570436926 ps |
| CPU time | 27.09 seconds |
| Started | Sep 09 09:42:32 PM UTC 24 |
| Finished | Sep 09 09:43:00 PM UTC 24 |
| Peak memory | 282488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579564349 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3579564349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1983428827 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2592443427 ps |
| CPU time | 204.58 seconds |
| Started | Sep 09 09:42:37 PM UTC 24 |
| Finished | Sep 09 09:46:05 PM UTC 24 |
| Peak memory | 214200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983428827 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc ess_b2b.1983428827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.4022841632 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 44204029 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:43:26 PM UTC 24 |
| Finished | Sep 09 09:43:28 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022841632 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4022841632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.3075453366 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 73124038364 ps |
| CPU time | 1322.49 seconds |
| Started | Sep 09 09:43:21 PM UTC 24 |
| Finished | Sep 09 10:05:38 PM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075453366 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3075453366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.994011801 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 150276733 ps |
| CPU time | 64.43 seconds |
| Started | Sep 09 09:41:37 PM UTC 24 |
| Finished | Sep 09 09:42:43 PM UTC 24 |
| Peak memory | 378740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994011801 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.994011801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.3054304969 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 39575276438 ps |
| CPU time | 3236.6 seconds |
| Started | Sep 09 09:43:35 PM UTC 24 |
| Finished | Sep 09 10:38:06 PM UTC 24 |
| Peak memory | 388708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305430496 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.3054304969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3313788166 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 7942103572 ps |
| CPU time | 25.68 seconds |
| Started | Sep 09 09:43:33 PM UTC 24 |
| Finished | Sep 09 09:44:00 PM UTC 24 |
| Peak memory | 226528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313788166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3313788166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.461395862 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1923692807 ps |
| CPU time | 230.39 seconds |
| Started | Sep 09 09:42:25 PM UTC 24 |
| Finished | Sep 09 09:46:20 PM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461395862 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.461395862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.4259677203 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 106458396 ps |
| CPU time | 34.44 seconds |
| Started | Sep 09 09:42:44 PM UTC 24 |
| Finished | Sep 09 09:43:20 PM UTC 24 |
| Peak memory | 302876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4259677203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t hroughput_w_partial_write.4259677203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3075608904 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 3313245658 ps |
| CPU time | 918.93 seconds |
| Started | Sep 09 09:44:34 PM UTC 24 |
| Finished | Sep 09 10:00:02 PM UTC 24 |
| Peak memory | 383152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075608904 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during _key_req.3075608904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2978783037 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 14813336 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:45:00 PM UTC 24 |
| Finished | Sep 09 09:45:02 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978783037 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2978783037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.384922497 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 10510492424 ps |
| CPU time | 41.41 seconds |
| Started | Sep 09 09:43:57 PM UTC 24 |
| Finished | Sep 09 09:44:40 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384922497 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.384922497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3134745577 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 9117329707 ps |
| CPU time | 590.41 seconds |
| Started | Sep 09 09:44:37 PM UTC 24 |
| Finished | Sep 09 09:54:34 PM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134745577 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.3134745577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.4275044690 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 805707378 ps |
| CPU time | 7.82 seconds |
| Started | Sep 09 09:44:27 PM UTC 24 |
| Finished | Sep 09 09:44:36 PM UTC 24 |
| Peak memory | 213772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275044690 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.4275044690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.962177819 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 163660494 ps |
| CPU time | 91.41 seconds |
| Started | Sep 09 09:44:10 PM UTC 24 |
| Finished | Sep 09 09:45:43 PM UTC 24 |
| Peak memory | 380708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 62177819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_max _throughput.962177819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1538839850 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 364120756 ps |
| CPU time | 4.99 seconds |
| Started | Sep 09 09:44:50 PM UTC 24 |
| Finished | Sep 09 09:44:56 PM UTC 24 |
| Peak memory | 224296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538839850 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.1538839850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1955125212 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 244047518 ps |
| CPU time | 6.68 seconds |
| Started | Sep 09 09:44:49 PM UTC 24 |
| Finished | Sep 09 09:44:57 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955125212 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.1955125212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3901673994 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 17845268330 ps |
| CPU time | 1419.78 seconds |
| Started | Sep 09 09:43:50 PM UTC 24 |
| Finished | Sep 09 10:07:45 PM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901673994 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3901673994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2115433352 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 385114527 ps |
| CPU time | 87.6 seconds |
| Started | Sep 09 09:44:01 PM UTC 24 |
| Finished | Sep 09 09:45:30 PM UTC 24 |
| Peak memory | 362228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115433352 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.2115433352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1856822327 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 13833010563 ps |
| CPU time | 415.87 seconds |
| Started | Sep 09 09:44:06 PM UTC 24 |
| Finished | Sep 09 09:51:07 PM UTC 24 |
| Peak memory | 214288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856822327 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc ess_b2b.1856822327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3275750895 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 28407679 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 09:44:46 PM UTC 24 |
| Finished | Sep 09 09:44:48 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275750895 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3275750895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3389576996 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1598933202 ps |
| CPU time | 125.76 seconds |
| Started | Sep 09 09:44:41 PM UTC 24 |
| Finished | Sep 09 09:46:49 PM UTC 24 |
| Peak memory | 352372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389576996 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3389576996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.2994389713 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 839320413 ps |
| CPU time | 16 seconds |
| Started | Sep 09 09:43:48 PM UTC 24 |
| Finished | Sep 09 09:44:06 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994389713 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2994389713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1022864160 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 4446273085 ps |
| CPU time | 1052.48 seconds |
| Started | Sep 09 09:44:57 PM UTC 24 |
| Finished | Sep 09 10:02:41 PM UTC 24 |
| Peak memory | 385148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102286416 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.1022864160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3616228984 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1493436795 ps |
| CPU time | 189.67 seconds |
| Started | Sep 09 09:44:57 PM UTC 24 |
| Finished | Sep 09 09:48:10 PM UTC 24 |
| Peak memory | 325548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616228984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3616228984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3446782160 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 9769092769 ps |
| CPU time | 240.11 seconds |
| Started | Sep 09 09:43:57 PM UTC 24 |
| Finished | Sep 09 09:48:01 PM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446782160 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.3446782160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3404011949 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 141795446 ps |
| CPU time | 87.03 seconds |
| Started | Sep 09 09:44:11 PM UTC 24 |
| Finished | Sep 09 09:45:40 PM UTC 24 |
| Peak memory | 370464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3404011949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t hroughput_w_partial_write.3404011949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.520419535 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3044143621 ps |
| CPU time | 967.44 seconds |
| Started | Sep 09 09:45:40 PM UTC 24 |
| Finished | Sep 09 10:01:58 PM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520419535 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_ key_req.520419535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3069545018 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 44234376 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:46:07 PM UTC 24 |
| Finished | Sep 09 09:46:09 PM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069545018 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3069545018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.49311216 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 7006495770 ps |
| CPU time | 64.07 seconds |
| Started | Sep 09 09:45:15 PM UTC 24 |
| Finished | Sep 09 09:46:21 PM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49311216 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.49311216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.2935670603 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 136763845677 ps |
| CPU time | 1158.02 seconds |
| Started | Sep 09 09:45:44 PM UTC 24 |
| Finished | Sep 09 10:05:15 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935670603 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.2935670603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3117701141 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2557862071 ps |
| CPU time | 6.88 seconds |
| Started | Sep 09 09:45:38 PM UTC 24 |
| Finished | Sep 09 09:45:47 PM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117701141 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.3117701141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.864961557 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 89328919 ps |
| CPU time | 3.92 seconds |
| Started | Sep 09 09:45:32 PM UTC 24 |
| Finished | Sep 09 09:45:37 PM UTC 24 |
| Peak memory | 231268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 64961557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_max _throughput.864961557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3051926013 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 217547452 ps |
| CPU time | 6.53 seconds |
| Started | Sep 09 09:45:59 PM UTC 24 |
| Finished | Sep 09 09:46:07 PM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051926013 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.3051926013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1173305832 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 459560981 ps |
| CPU time | 14.54 seconds |
| Started | Sep 09 09:45:51 PM UTC 24 |
| Finished | Sep 09 09:46:06 PM UTC 24 |
| Peak memory | 224392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173305832 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.1173305832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1916872282 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2861709135 ps |
| CPU time | 377.6 seconds |
| Started | Sep 09 09:45:04 PM UTC 24 |
| Finished | Sep 09 09:51:26 PM UTC 24 |
| Peak memory | 385160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916872282 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.1916872282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3963781182 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 46612004 ps |
| CPU time | 2.73 seconds |
| Started | Sep 09 09:45:31 PM UTC 24 |
| Finished | Sep 09 09:45:35 PM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963781182 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.3963781182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3152435591 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 6802917172 ps |
| CPU time | 218.73 seconds |
| Started | Sep 09 09:45:31 PM UTC 24 |
| Finished | Sep 09 09:49:13 PM UTC 24 |
| Peak memory | 213936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152435591 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acc ess_b2b.3152435591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2254657144 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 95664596 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:45:48 PM UTC 24 |
| Finished | Sep 09 09:45:50 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254657144 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2254657144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.383776964 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 10329035055 ps |
| CPU time | 448.13 seconds |
| Started | Sep 09 09:45:46 PM UTC 24 |
| Finished | Sep 09 09:53:20 PM UTC 24 |
| Peak memory | 368572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383776964 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.383776964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.2197726735 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 297470078 ps |
| CPU time | 28.86 seconds |
| Started | Sep 09 09:45:01 PM UTC 24 |
| Finished | Sep 09 09:45:32 PM UTC 24 |
| Peak memory | 286584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197726735 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2197726735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.2717358523 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 28480466147 ps |
| CPU time | 1379.21 seconds |
| Started | Sep 09 09:46:07 PM UTC 24 |
| Finished | Sep 09 10:09:20 PM UTC 24 |
| Peak memory | 381172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271735852 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.2717358523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3312759603 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 5906763303 ps |
| CPU time | 176.88 seconds |
| Started | Sep 09 09:45:27 PM UTC 24 |
| Finished | Sep 09 09:48:27 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312759603 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.3312759603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3222114947 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 75959956 ps |
| CPU time | 8.7 seconds |
| Started | Sep 09 09:45:35 PM UTC 24 |
| Finished | Sep 09 09:45:45 PM UTC 24 |
| Peak memory | 264040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3222114947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t hroughput_w_partial_write.3222114947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1062694171 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 8057423695 ps |
| CPU time | 797.48 seconds |
| Started | Sep 09 09:46:49 PM UTC 24 |
| Finished | Sep 09 10:00:16 PM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062694171 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during _key_req.1062694171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1765722778 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 37775626 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:48:04 PM UTC 24 |
| Finished | Sep 09 09:48:07 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765722778 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1765722778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1425170361 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 16387736908 ps |
| CPU time | 70.52 seconds |
| Started | Sep 09 09:46:20 PM UTC 24 |
| Finished | Sep 09 09:47:33 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425170361 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.1425170361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.4195052790 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 46576768041 ps |
| CPU time | 1010.99 seconds |
| Started | Sep 09 09:46:55 PM UTC 24 |
| Finished | Sep 09 10:03:57 PM UTC 24 |
| Peak memory | 380860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195052790 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.4195052790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2556557277 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1845361527 ps |
| CPU time | 7.78 seconds |
| Started | Sep 09 09:46:44 PM UTC 24 |
| Finished | Sep 09 09:46:53 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556557277 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.2556557277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3436974950 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 414984762 ps |
| CPU time | 10.6 seconds |
| Started | Sep 09 09:46:29 PM UTC 24 |
| Finished | Sep 09 09:46:41 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 436974950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ma x_throughput.3436974950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.448946516 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 192054135 ps |
| CPU time | 7.29 seconds |
| Started | Sep 09 09:47:54 PM UTC 24 |
| Finished | Sep 09 09:48:03 PM UTC 24 |
| Peak memory | 223964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448946516 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.448946516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2010331819 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 366103399 ps |
| CPU time | 14.74 seconds |
| Started | Sep 09 09:47:37 PM UTC 24 |
| Finished | Sep 09 09:47:53 PM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010331819 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.2010331819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2471162461 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1971016252 ps |
| CPU time | 283.7 seconds |
| Started | Sep 09 09:46:10 PM UTC 24 |
| Finished | Sep 09 09:50:58 PM UTC 24 |
| Peak memory | 372592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471162461 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.2471162461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1771616163 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 378300324 ps |
| CPU time | 95.22 seconds |
| Started | Sep 09 09:46:26 PM UTC 24 |
| Finished | Sep 09 09:48:03 PM UTC 24 |
| Peak memory | 364328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771616163 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.1771616163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.885867389 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 21138679821 ps |
| CPU time | 496.17 seconds |
| Started | Sep 09 09:46:27 PM UTC 24 |
| Finished | Sep 09 09:54:51 PM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885867389 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acce ss_b2b.885867389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.448760570 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 28269224 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 09:47:34 PM UTC 24 |
| Finished | Sep 09 09:47:36 PM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448760570 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.448760570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.2367865921 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7829027547 ps |
| CPU time | 243.08 seconds |
| Started | Sep 09 09:47:28 PM UTC 24 |
| Finished | Sep 09 09:51:34 PM UTC 24 |
| Peak memory | 384852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367865921 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2367865921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2012348338 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1165587680 ps |
| CPU time | 16.92 seconds |
| Started | Sep 09 09:46:07 PM UTC 24 |
| Finished | Sep 09 09:46:25 PM UTC 24 |
| Peak memory | 213784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012348338 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2012348338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3246213488 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 33412340614 ps |
| CPU time | 2209.54 seconds |
| Started | Sep 09 09:48:03 PM UTC 24 |
| Finished | Sep 09 10:25:17 PM UTC 24 |
| Peak memory | 385436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324621348 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.3246213488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3655418459 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 10150300643 ps |
| CPU time | 238.83 seconds |
| Started | Sep 09 09:46:22 PM UTC 24 |
| Finished | Sep 09 09:50:24 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655418459 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.3655418459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1576108798 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 408027228 ps |
| CPU time | 43.6 seconds |
| Started | Sep 09 09:46:42 PM UTC 24 |
| Finished | Sep 09 09:47:27 PM UTC 24 |
| Peak memory | 308964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1576108798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t hroughput_w_partial_write.1576108798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3050737401 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 17710230854 ps |
| CPU time | 1109.25 seconds |
| Started | Sep 09 09:48:40 PM UTC 24 |
| Finished | Sep 09 10:07:22 PM UTC 24 |
| Peak memory | 384944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050737401 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.3050737401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1963068464 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 27548066 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:49:30 PM UTC 24 |
| Finished | Sep 09 09:49:33 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963068464 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1963068464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.348769257 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 4179974584 ps |
| CPU time | 53.3 seconds |
| Started | Sep 09 09:48:14 PM UTC 24 |
| Finished | Sep 09 09:49:09 PM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348769257 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.348769257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.2322124812 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 843026931 ps |
| CPU time | 223.01 seconds |
| Started | Sep 09 09:48:47 PM UTC 24 |
| Finished | Sep 09 09:52:33 PM UTC 24 |
| Peak memory | 358184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322124812 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.2322124812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2985955906 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 65878905 ps |
| CPU time | 2.25 seconds |
| Started | Sep 09 09:48:36 PM UTC 24 |
| Finished | Sep 09 09:48:40 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985955906 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.2985955906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1524570752 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 168583562 ps |
| CPU time | 4.81 seconds |
| Started | Sep 09 09:48:29 PM UTC 24 |
| Finished | Sep 09 09:48:35 PM UTC 24 |
| Peak memory | 231180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 524570752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma x_throughput.1524570752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.255242117 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 231116638 ps |
| CPU time | 8.27 seconds |
| Started | Sep 09 09:49:17 PM UTC 24 |
| Finished | Sep 09 09:49:27 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255242117 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.255242117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3474472039 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1876398093 ps |
| CPU time | 7.54 seconds |
| Started | Sep 09 09:49:14 PM UTC 24 |
| Finished | Sep 09 09:49:23 PM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474472039 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.3474472039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3131626278 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2354824883 ps |
| CPU time | 694.32 seconds |
| Started | Sep 09 09:48:11 PM UTC 24 |
| Finished | Sep 09 09:59:52 PM UTC 24 |
| Peak memory | 382896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131626278 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.3131626278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1480794842 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4362336893 ps |
| CPU time | 16.42 seconds |
| Started | Sep 09 09:48:28 PM UTC 24 |
| Finished | Sep 09 09:48:46 PM UTC 24 |
| Peak memory | 213952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480794842 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.1480794842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.990864239 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 53850994618 ps |
| CPU time | 360.57 seconds |
| Started | Sep 09 09:48:29 PM UTC 24 |
| Finished | Sep 09 09:54:34 PM UTC 24 |
| Peak memory | 213788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990864239 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acce ss_b2b.990864239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1769114865 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 180560243 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:49:14 PM UTC 24 |
| Finished | Sep 09 09:49:16 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769114865 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1769114865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.399695443 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 12805569472 ps |
| CPU time | 683.78 seconds |
| Started | Sep 09 09:49:10 PM UTC 24 |
| Finished | Sep 09 10:00:42 PM UTC 24 |
| Peak memory | 387004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399695443 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.399695443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.883776338 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 4862583419 ps |
| CPU time | 124.34 seconds |
| Started | Sep 09 09:48:07 PM UTC 24 |
| Finished | Sep 09 09:50:14 PM UTC 24 |
| Peak memory | 379068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883776338 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.883776338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3272548965 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 49939577322 ps |
| CPU time | 3816.48 seconds |
| Started | Sep 09 09:49:27 PM UTC 24 |
| Finished | Sep 09 10:53:43 PM UTC 24 |
| Peak memory | 388792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327254896 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.3272548965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.148326823 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1119969990 ps |
| CPU time | 289.18 seconds |
| Started | Sep 09 09:49:23 PM UTC 24 |
| Finished | Sep 09 09:54:17 PM UTC 24 |
| Peak memory | 385200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148326823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.148326823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.575721753 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 4630435576 ps |
| CPU time | 455.19 seconds |
| Started | Sep 09 09:48:28 PM UTC 24 |
| Finished | Sep 09 09:56:09 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575721753 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.575721753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1710653780 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 484090911 ps |
| CPU time | 41.56 seconds |
| Started | Sep 09 09:48:30 PM UTC 24 |
| Finished | Sep 09 09:49:13 PM UTC 24 |
| Peak memory | 313196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1710653780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t hroughput_w_partial_write.1710653780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.62213506 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 22354867072 ps |
| CPU time | 686.42 seconds |
| Started | Sep 09 09:10:44 PM UTC 24 |
| Finished | Sep 09 09:22:19 PM UTC 24 |
| Peak memory | 381100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62213506 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_ke y_req.62213506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.47574410 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 13222181 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:10:50 PM UTC 24 |
| Finished | Sep 09 09:10:52 PM UTC 24 |
| Peak memory | 212652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47574410 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.47574410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3481390231 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 6389397087 ps |
| CPU time | 41.44 seconds |
| Started | Sep 09 09:10:42 PM UTC 24 |
| Finished | Sep 09 09:11:25 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481390231 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3481390231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1339178499 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 4709743945 ps |
| CPU time | 166.45 seconds |
| Started | Sep 09 09:10:44 PM UTC 24 |
| Finished | Sep 09 09:13:34 PM UTC 24 |
| Peak memory | 354176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339178499 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.1339178499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3760682196 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 305149403 ps |
| CPU time | 2.03 seconds |
| Started | Sep 09 09:10:44 PM UTC 24 |
| Finished | Sep 09 09:10:47 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760682196 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.3760682196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2486585474 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 159629369 ps |
| CPU time | 17.17 seconds |
| Started | Sep 09 09:10:43 PM UTC 24 |
| Finished | Sep 09 09:11:01 PM UTC 24 |
| Peak memory | 272156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 486585474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max _throughput.2486585474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1830646854 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 62384094 ps |
| CPU time | 4.82 seconds |
| Started | Sep 09 09:10:48 PM UTC 24 |
| Finished | Sep 09 09:10:54 PM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830646854 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1830646854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2095965203 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 286754529 ps |
| CPU time | 6.81 seconds |
| Started | Sep 09 09:10:47 PM UTC 24 |
| Finished | Sep 09 09:10:55 PM UTC 24 |
| Peak memory | 223964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095965203 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.2095965203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2802364510 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 315401125 ps |
| CPU time | 12.59 seconds |
| Started | Sep 09 09:10:43 PM UTC 24 |
| Finished | Sep 09 09:10:57 PM UTC 24 |
| Peak memory | 213720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802364510 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.2802364510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1079560564 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 45953582 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 09:10:47 PM UTC 24 |
| Finished | Sep 09 09:10:49 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079560564 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1079560564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1781995622 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 24968966741 ps |
| CPU time | 1119.82 seconds |
| Started | Sep 09 09:10:46 PM UTC 24 |
| Finished | Sep 09 09:29:37 PM UTC 24 |
| Peak memory | 386948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781995622 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1781995622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.479821963 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 249698971 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 09:10:49 PM UTC 24 |
| Finished | Sep 09 09:10:53 PM UTC 24 |
| Peak memory | 250096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479821963 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.479821963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3015655161 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 462849360 ps |
| CPU time | 42.47 seconds |
| Started | Sep 09 09:10:41 PM UTC 24 |
| Finished | Sep 09 09:11:25 PM UTC 24 |
| Peak memory | 315204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015655161 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3015655161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2965906509 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 11045822714 ps |
| CPU time | 3025.92 seconds |
| Started | Sep 09 09:10:48 PM UTC 24 |
| Finished | Sep 09 10:01:45 PM UTC 24 |
| Peak memory | 390712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296590650 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.2965906509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.30144720 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8082723407 ps |
| CPU time | 127.78 seconds |
| Started | Sep 09 09:10:48 PM UTC 24 |
| Finished | Sep 09 09:12:58 PM UTC 24 |
| Peak memory | 370928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30144720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.30144720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3371773755 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 55275922096 ps |
| CPU time | 324.77 seconds |
| Started | Sep 09 09:10:42 PM UTC 24 |
| Finished | Sep 09 09:16:11 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371773755 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3371773755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.2101813107 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 150976457 ps |
| CPU time | 106.74 seconds |
| Started | Sep 09 09:10:44 PM UTC 24 |
| Finished | Sep 09 09:12:33 PM UTC 24 |
| Peak memory | 380816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2101813107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th roughput_w_partial_write.2101813107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.434835106 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3004048908 ps |
| CPU time | 652.2 seconds |
| Started | Sep 09 09:50:59 PM UTC 24 |
| Finished | Sep 09 10:01:58 PM UTC 24 |
| Peak memory | 384864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434835106 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_ key_req.434835106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.852773564 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 21318733 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:51:28 PM UTC 24 |
| Finished | Sep 09 09:51:29 PM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852773564 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.852773564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2177538265 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2526872251 ps |
| CPU time | 70.47 seconds |
| Started | Sep 09 09:50:10 PM UTC 24 |
| Finished | Sep 09 09:51:22 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177538265 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2177538265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3041450529 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 93993001314 ps |
| CPU time | 446.73 seconds |
| Started | Sep 09 09:51:04 PM UTC 24 |
| Finished | Sep 09 09:58:36 PM UTC 24 |
| Peak memory | 346296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041450529 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.3041450529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2039332478 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 877944815 ps |
| CPU time | 9.16 seconds |
| Started | Sep 09 09:50:57 PM UTC 24 |
| Finished | Sep 09 09:51:07 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039332478 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.2039332478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3889428898 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 453581646 ps |
| CPU time | 63.28 seconds |
| Started | Sep 09 09:50:41 PM UTC 24 |
| Finished | Sep 09 09:51:47 PM UTC 24 |
| Peak memory | 350328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 889428898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma x_throughput.3889428898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3840501210 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 99465679 ps |
| CPU time | 4.88 seconds |
| Started | Sep 09 09:51:20 PM UTC 24 |
| Finished | Sep 09 09:51:26 PM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840501210 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.3840501210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.2897518953 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 95241471 ps |
| CPU time | 7.26 seconds |
| Started | Sep 09 09:51:11 PM UTC 24 |
| Finished | Sep 09 09:51:19 PM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897518953 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.2897518953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2571779936 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 19526122044 ps |
| CPU time | 309.79 seconds |
| Started | Sep 09 09:49:38 PM UTC 24 |
| Finished | Sep 09 09:54:51 PM UTC 24 |
| Peak memory | 387032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571779936 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2571779936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2152849361 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2371832706 ps |
| CPU time | 78.72 seconds |
| Started | Sep 09 09:50:25 PM UTC 24 |
| Finished | Sep 09 09:51:46 PM UTC 24 |
| Peak memory | 378808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152849361 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.2152849361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.878699610 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 142045860365 ps |
| CPU time | 425.51 seconds |
| Started | Sep 09 09:50:31 PM UTC 24 |
| Finished | Sep 09 09:57:43 PM UTC 24 |
| Peak memory | 214000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878699610 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acce ss_b2b.878699610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1104647050 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 47532258 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:51:08 PM UTC 24 |
| Finished | Sep 09 09:51:10 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104647050 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1104647050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.1253882696 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3493491364 ps |
| CPU time | 1267.81 seconds |
| Started | Sep 09 09:51:08 PM UTC 24 |
| Finished | Sep 09 10:12:30 PM UTC 24 |
| Peak memory | 385268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253882696 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1253882696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.2854257476 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 177960398 ps |
| CPU time | 1.83 seconds |
| Started | Sep 09 09:49:34 PM UTC 24 |
| Finished | Sep 09 09:49:36 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854257476 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2854257476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3545533067 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 13304340009 ps |
| CPU time | 3726.26 seconds |
| Started | Sep 09 09:51:27 PM UTC 24 |
| Finished | Sep 09 10:54:12 PM UTC 24 |
| Peak memory | 396912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354553306 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.3545533067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.274324790 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1428337832 ps |
| CPU time | 59.33 seconds |
| Started | Sep 09 09:51:23 PM UTC 24 |
| Finished | Sep 09 09:52:24 PM UTC 24 |
| Peak memory | 301172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274324790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.274324790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1654344804 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 3376551888 ps |
| CPU time | 357.7 seconds |
| Started | Sep 09 09:50:15 PM UTC 24 |
| Finished | Sep 09 09:56:18 PM UTC 24 |
| Peak memory | 214236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654344804 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.1654344804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.380598590 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1238231646 ps |
| CPU time | 37.82 seconds |
| Started | Sep 09 09:50:48 PM UTC 24 |
| Finished | Sep 09 09:51:27 PM UTC 24 |
| Peak memory | 309040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 380598590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_th roughput_w_partial_write.380598590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1359680248 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 3002771458 ps |
| CPU time | 403.72 seconds |
| Started | Sep 09 09:52:05 PM UTC 24 |
| Finished | Sep 09 09:58:54 PM UTC 24 |
| Peak memory | 378696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359680248 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during _key_req.1359680248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3015658138 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 37233139 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:53:06 PM UTC 24 |
| Finished | Sep 09 09:53:08 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015658138 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3015658138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3888699475 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2892189853 ps |
| CPU time | 76.02 seconds |
| Started | Sep 09 09:51:31 PM UTC 24 |
| Finished | Sep 09 09:52:49 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888699475 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.3888699475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1714012802 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 19759900059 ps |
| CPU time | 1163.98 seconds |
| Started | Sep 09 09:52:11 PM UTC 24 |
| Finished | Sep 09 10:11:47 PM UTC 24 |
| Peak memory | 384960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714012802 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.1714012802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3780905918 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 346937275 ps |
| CPU time | 3.05 seconds |
| Started | Sep 09 09:52:00 PM UTC 24 |
| Finished | Sep 09 09:52:04 PM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780905918 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.3780905918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.3266449849 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 48986901 ps |
| CPU time | 6.06 seconds |
| Started | Sep 09 09:51:47 PM UTC 24 |
| Finished | Sep 09 09:51:54 PM UTC 24 |
| Peak memory | 233324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 266449849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma x_throughput.3266449849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3545375178 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 240043786 ps |
| CPU time | 3.77 seconds |
| Started | Sep 09 09:52:50 PM UTC 24 |
| Finished | Sep 09 09:52:55 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545375178 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.3545375178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.3408891406 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 564173859 ps |
| CPU time | 10.72 seconds |
| Started | Sep 09 09:52:38 PM UTC 24 |
| Finished | Sep 09 09:52:49 PM UTC 24 |
| Peak memory | 224076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408891406 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.3408891406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2860756827 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 157162539073 ps |
| CPU time | 1484.21 seconds |
| Started | Sep 09 09:51:31 PM UTC 24 |
| Finished | Sep 09 10:16:31 PM UTC 24 |
| Peak memory | 384944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860756827 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.2860756827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.4162689660 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2021755959 ps |
| CPU time | 25.84 seconds |
| Started | Sep 09 09:51:43 PM UTC 24 |
| Finished | Sep 09 09:52:10 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162689660 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.4162689660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3170375959 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 29432325420 ps |
| CPU time | 222.22 seconds |
| Started | Sep 09 09:51:46 PM UTC 24 |
| Finished | Sep 09 09:55:32 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170375959 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc ess_b2b.3170375959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.375749268 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 53555661 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:52:33 PM UTC 24 |
| Finished | Sep 09 09:52:36 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375749268 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.375749268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.205151714 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 38775772156 ps |
| CPU time | 760.33 seconds |
| Started | Sep 09 09:52:25 PM UTC 24 |
| Finished | Sep 09 10:05:14 PM UTC 24 |
| Peak memory | 383164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205151714 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.205151714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.802655723 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 51550955 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 09:51:28 PM UTC 24 |
| Finished | Sep 09 09:51:30 PM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802655723 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.802655723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.749415198 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 47243314458 ps |
| CPU time | 2964.63 seconds |
| Started | Sep 09 09:52:56 PM UTC 24 |
| Finished | Sep 09 10:42:50 PM UTC 24 |
| Peak memory | 390832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749415198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.749415198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.907898651 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 10397671595 ps |
| CPU time | 58.11 seconds |
| Started | Sep 09 09:52:52 PM UTC 24 |
| Finished | Sep 09 09:53:52 PM UTC 24 |
| Peak memory | 231360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907898651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.907898651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1437369582 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2105072933 ps |
| CPU time | 214.28 seconds |
| Started | Sep 09 09:51:35 PM UTC 24 |
| Finished | Sep 09 09:55:12 PM UTC 24 |
| Peak memory | 213764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437369582 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.1437369582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3347046328 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 73188799 ps |
| CPU time | 2.44 seconds |
| Started | Sep 09 09:51:55 PM UTC 24 |
| Finished | Sep 09 09:51:59 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3347046328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t hroughput_w_partial_write.3347046328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3079446454 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3177071421 ps |
| CPU time | 721.23 seconds |
| Started | Sep 09 09:54:29 PM UTC 24 |
| Finished | Sep 09 10:06:38 PM UTC 24 |
| Peak memory | 377008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079446454 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.3079446454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4133522399 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 14219493 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:54:52 PM UTC 24 |
| Finished | Sep 09 09:54:55 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133522399 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.4133522399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.2405904925 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 6177120813 ps |
| CPU time | 47.16 seconds |
| Started | Sep 09 09:53:13 PM UTC 24 |
| Finished | Sep 09 09:54:01 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405904925 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.2405904925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.617559435 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3894025937 ps |
| CPU time | 157.16 seconds |
| Started | Sep 09 09:54:35 PM UTC 24 |
| Finished | Sep 09 09:57:14 PM UTC 24 |
| Peak memory | 352172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617559435 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.617559435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3928335491 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 11228851012 ps |
| CPU time | 9.01 seconds |
| Started | Sep 09 09:54:17 PM UTC 24 |
| Finished | Sep 09 09:54:27 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928335491 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.3928335491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3228956014 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 136870188 ps |
| CPU time | 120.46 seconds |
| Started | Sep 09 09:54:06 PM UTC 24 |
| Finished | Sep 09 09:56:09 PM UTC 24 |
| Peak memory | 381040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 228956014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma x_throughput.3228956014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2837114071 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 356274076 ps |
| CPU time | 6.4 seconds |
| Started | Sep 09 09:54:51 PM UTC 24 |
| Finished | Sep 09 09:54:59 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837114071 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2837114071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1987671825 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1229824828 ps |
| CPU time | 12.19 seconds |
| Started | Sep 09 09:54:50 PM UTC 24 |
| Finished | Sep 09 09:55:03 PM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987671825 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.1987671825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2272267985 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 8907335163 ps |
| CPU time | 424.73 seconds |
| Started | Sep 09 09:53:09 PM UTC 24 |
| Finished | Sep 09 10:00:19 PM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272267985 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.2272267985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1832548102 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 877703703 ps |
| CPU time | 21.26 seconds |
| Started | Sep 09 09:53:53 PM UTC 24 |
| Finished | Sep 09 09:54:16 PM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832548102 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1832548102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3164219447 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 24355841803 ps |
| CPU time | 620.25 seconds |
| Started | Sep 09 09:54:02 PM UTC 24 |
| Finished | Sep 09 10:04:30 PM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164219447 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acc ess_b2b.3164219447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.178033601 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 58354495 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:54:47 PM UTC 24 |
| Finished | Sep 09 09:54:49 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178033601 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.178033601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.718442799 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 4000814001 ps |
| CPU time | 312.33 seconds |
| Started | Sep 09 09:54:36 PM UTC 24 |
| Finished | Sep 09 09:59:52 PM UTC 24 |
| Peak memory | 379064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718442799 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.718442799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.3940776752 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 556328938 ps |
| CPU time | 101.89 seconds |
| Started | Sep 09 09:53:06 PM UTC 24 |
| Finished | Sep 09 09:54:50 PM UTC 24 |
| Peak memory | 378740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940776752 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3940776752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1738208334 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 75965310872 ps |
| CPU time | 2899.48 seconds |
| Started | Sep 09 09:54:52 PM UTC 24 |
| Finished | Sep 09 10:43:42 PM UTC 24 |
| Peak memory | 395248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173820833 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.1738208334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2200547361 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2832576423 ps |
| CPU time | 187.98 seconds |
| Started | Sep 09 09:54:52 PM UTC 24 |
| Finished | Sep 09 09:58:03 PM UTC 24 |
| Peak memory | 388912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200547361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2200547361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3311624279 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2103379659 ps |
| CPU time | 243.11 seconds |
| Started | Sep 09 09:53:21 PM UTC 24 |
| Finished | Sep 09 09:57:27 PM UTC 24 |
| Peak memory | 214096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311624279 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.3311624279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3256877809 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 99759381 ps |
| CPU time | 34.14 seconds |
| Started | Sep 09 09:54:16 PM UTC 24 |
| Finished | Sep 09 09:54:52 PM UTC 24 |
| Peak memory | 296732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3256877809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t hroughput_w_partial_write.3256877809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2525060211 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 9987705998 ps |
| CPU time | 400.78 seconds |
| Started | Sep 09 09:55:33 PM UTC 24 |
| Finished | Sep 09 10:02:18 PM UTC 24 |
| Peak memory | 358308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525060211 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during _key_req.2525060211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1214723309 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 45430526 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:56:28 PM UTC 24 |
| Finished | Sep 09 09:56:30 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214723309 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1214723309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.636217601 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 879309796 ps |
| CPU time | 20.14 seconds |
| Started | Sep 09 09:55:00 PM UTC 24 |
| Finished | Sep 09 09:55:21 PM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636217601 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.636217601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3006576277 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 22855364844 ps |
| CPU time | 1029.04 seconds |
| Started | Sep 09 09:55:33 PM UTC 24 |
| Finished | Sep 09 10:12:53 PM UTC 24 |
| Peak memory | 384952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006576277 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3006576277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1812621137 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1675795778 ps |
| CPU time | 7.78 seconds |
| Started | Sep 09 09:55:22 PM UTC 24 |
| Finished | Sep 09 09:55:31 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812621137 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.1812621137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2078252135 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 110135346 ps |
| CPU time | 71.38 seconds |
| Started | Sep 09 09:55:13 PM UTC 24 |
| Finished | Sep 09 09:56:27 PM UTC 24 |
| Peak memory | 335732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 078252135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma x_throughput.2078252135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2765349320 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 64554760 ps |
| CPU time | 3.87 seconds |
| Started | Sep 09 09:56:18 PM UTC 24 |
| Finished | Sep 09 09:56:23 PM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765349320 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.2765349320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3221042441 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 228372268 ps |
| CPU time | 7.59 seconds |
| Started | Sep 09 09:56:13 PM UTC 24 |
| Finished | Sep 09 09:56:22 PM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221042441 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.3221042441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2341283379 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 12223459883 ps |
| CPU time | 556.76 seconds |
| Started | Sep 09 09:54:56 PM UTC 24 |
| Finished | Sep 09 10:04:20 PM UTC 24 |
| Peak memory | 379020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341283379 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.2341283379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3272387274 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 115251694 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 09:55:04 PM UTC 24 |
| Finished | Sep 09 09:55:09 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272387274 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.3272387274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1353567774 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 16573357646 ps |
| CPU time | 462 seconds |
| Started | Sep 09 09:55:10 PM UTC 24 |
| Finished | Sep 09 10:02:59 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353567774 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc ess_b2b.1353567774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.1775079158 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 83430156 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:56:10 PM UTC 24 |
| Finished | Sep 09 09:56:12 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775079158 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1775079158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2599703307 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 106333537828 ps |
| CPU time | 774.49 seconds |
| Started | Sep 09 09:56:10 PM UTC 24 |
| Finished | Sep 09 10:09:13 PM UTC 24 |
| Peak memory | 376688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599703307 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2599703307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.841337619 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1533101781 ps |
| CPU time | 16.91 seconds |
| Started | Sep 09 09:54:56 PM UTC 24 |
| Finished | Sep 09 09:55:14 PM UTC 24 |
| Peak memory | 214148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841337619 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.841337619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1553347281 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 98119229142 ps |
| CPU time | 3016.2 seconds |
| Started | Sep 09 09:56:25 PM UTC 24 |
| Finished | Sep 09 10:47:14 PM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155334728 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.1553347281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1043672333 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1311624381 ps |
| CPU time | 323.02 seconds |
| Started | Sep 09 09:56:22 PM UTC 24 |
| Finished | Sep 09 10:01:50 PM UTC 24 |
| Peak memory | 374636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043672333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1043672333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2709059962 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 7095506996 ps |
| CPU time | 414.04 seconds |
| Started | Sep 09 09:55:03 PM UTC 24 |
| Finished | Sep 09 10:02:03 PM UTC 24 |
| Peak memory | 214028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709059962 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.2709059962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2208445407 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 305189125 ps |
| CPU time | 125.74 seconds |
| Started | Sep 09 09:55:15 PM UTC 24 |
| Finished | Sep 09 09:57:24 PM UTC 24 |
| Peak memory | 380712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2208445407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_t hroughput_w_partial_write.2208445407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.528406555 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 12371316404 ps |
| CPU time | 1109.58 seconds |
| Started | Sep 09 09:57:53 PM UTC 24 |
| Finished | Sep 09 10:16:35 PM UTC 24 |
| Peak memory | 387244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528406555 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during_ key_req.528406555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3114775733 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 13619897 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 09:58:35 PM UTC 24 |
| Finished | Sep 09 09:58:37 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114775733 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3114775733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1853655059 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1072206732 ps |
| CPU time | 72.36 seconds |
| Started | Sep 09 09:57:20 PM UTC 24 |
| Finished | Sep 09 09:58:35 PM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853655059 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1853655059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3732756586 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 9514046185 ps |
| CPU time | 899.61 seconds |
| Started | Sep 09 09:58:00 PM UTC 24 |
| Finished | Sep 09 10:13:10 PM UTC 24 |
| Peak memory | 374584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732756586 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.3732756586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.411313311 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 54851220 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 09:57:49 PM UTC 24 |
| Finished | Sep 09 09:57:52 PM UTC 24 |
| Peak memory | 212568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411313311 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.411313311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.4148079790 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 126133857 ps |
| CPU time | 73.24 seconds |
| Started | Sep 09 09:57:31 PM UTC 24 |
| Finished | Sep 09 09:58:46 PM UTC 24 |
| Peak memory | 351928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 148079790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ma x_throughput.4148079790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4208028836 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 244471491 ps |
| CPU time | 4.01 seconds |
| Started | Sep 09 09:58:18 PM UTC 24 |
| Finished | Sep 09 09:58:23 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208028836 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.4208028836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.534313306 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 243550936 ps |
| CPU time | 7.95 seconds |
| Started | Sep 09 09:58:08 PM UTC 24 |
| Finished | Sep 09 09:58:17 PM UTC 24 |
| Peak memory | 224128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534313306 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.534313306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.4263753586 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 39883556365 ps |
| CPU time | 755.04 seconds |
| Started | Sep 09 09:57:15 PM UTC 24 |
| Finished | Sep 09 10:09:59 PM UTC 24 |
| Peak memory | 374964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263753586 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.4263753586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.4112026991 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3019930674 ps |
| CPU time | 19.23 seconds |
| Started | Sep 09 09:57:28 PM UTC 24 |
| Finished | Sep 09 09:57:48 PM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112026991 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.4112026991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2322728310 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 15600422730 ps |
| CPU time | 244.28 seconds |
| Started | Sep 09 09:57:31 PM UTC 24 |
| Finished | Sep 09 10:01:39 PM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322728310 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc ess_b2b.2322728310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1744243108 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 44007561 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 09:58:05 PM UTC 24 |
| Finished | Sep 09 09:58:07 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744243108 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1744243108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.3564107416 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 8135448881 ps |
| CPU time | 490.8 seconds |
| Started | Sep 09 09:58:05 PM UTC 24 |
| Finished | Sep 09 10:06:21 PM UTC 24 |
| Peak memory | 382900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564107416 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3564107416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.718736490 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 449704409 ps |
| CPU time | 57.98 seconds |
| Started | Sep 09 09:56:31 PM UTC 24 |
| Finished | Sep 09 09:57:30 PM UTC 24 |
| Peak memory | 325420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718736490 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.718736490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3317356975 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 156516140551 ps |
| CPU time | 2393 seconds |
| Started | Sep 09 09:58:24 PM UTC 24 |
| Finished | Sep 09 10:38:43 PM UTC 24 |
| Peak memory | 395352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331735697 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.3317356975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.380539447 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2100265056 ps |
| CPU time | 544.64 seconds |
| Started | Sep 09 09:58:23 PM UTC 24 |
| Finished | Sep 09 10:07:34 PM UTC 24 |
| Peak memory | 391088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380539447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.380539447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.358119673 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5435296547 ps |
| CPU time | 345.67 seconds |
| Started | Sep 09 09:57:25 PM UTC 24 |
| Finished | Sep 09 10:03:15 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358119673 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.358119673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3382442869 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 399174034 ps |
| CPU time | 51.64 seconds |
| Started | Sep 09 09:57:43 PM UTC 24 |
| Finished | Sep 09 09:58:36 PM UTC 24 |
| Peak memory | 315244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3382442869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t hroughput_w_partial_write.3382442869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2759387703 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 9881372619 ps |
| CPU time | 688.79 seconds |
| Started | Sep 09 09:59:11 PM UTC 24 |
| Finished | Sep 09 10:10:48 PM UTC 24 |
| Peak memory | 385136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759387703 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during _key_req.2759387703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1870677901 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 19876904 ps |
| CPU time | 0.87 seconds |
| Started | Sep 09 10:00:15 PM UTC 24 |
| Finished | Sep 09 10:00:17 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870677901 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1870677901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.654941677 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 17790253686 ps |
| CPU time | 62.96 seconds |
| Started | Sep 09 09:58:39 PM UTC 24 |
| Finished | Sep 09 09:59:43 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654941677 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.654941677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2425138881 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 35801089143 ps |
| CPU time | 831.59 seconds |
| Started | Sep 09 09:59:45 PM UTC 24 |
| Finished | Sep 09 10:13:46 PM UTC 24 |
| Peak memory | 378804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425138881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.2425138881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2971045724 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1551232051 ps |
| CPU time | 7.76 seconds |
| Started | Sep 09 09:59:01 PM UTC 24 |
| Finished | Sep 09 09:59:10 PM UTC 24 |
| Peak memory | 228184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971045724 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.2971045724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.4190732053 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 142976265 ps |
| CPU time | 2.57 seconds |
| Started | Sep 09 09:58:55 PM UTC 24 |
| Finished | Sep 09 09:58:59 PM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 190732053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma x_throughput.4190732053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.794136120 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 176873603 ps |
| CPU time | 7.83 seconds |
| Started | Sep 09 10:00:01 PM UTC 24 |
| Finished | Sep 09 10:00:14 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794136120 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.794136120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3705131799 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 73779055 ps |
| CPU time | 5.71 seconds |
| Started | Sep 09 09:59:57 PM UTC 24 |
| Finished | Sep 09 10:00:04 PM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705131799 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.3705131799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.444336542 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 79058556519 ps |
| CPU time | 659.24 seconds |
| Started | Sep 09 09:58:37 PM UTC 24 |
| Finished | Sep 09 10:09:44 PM UTC 24 |
| Peak memory | 384860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444336542 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.444336542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3537918213 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2133913166 ps |
| CPU time | 13.09 seconds |
| Started | Sep 09 09:58:46 PM UTC 24 |
| Finished | Sep 09 09:59:00 PM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537918213 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.3537918213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1859805241 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4730525648 ps |
| CPU time | 338.45 seconds |
| Started | Sep 09 09:58:47 PM UTC 24 |
| Finished | Sep 09 10:04:30 PM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859805241 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acc ess_b2b.1859805241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.420987371 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 31350607 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:59:54 PM UTC 24 |
| Finished | Sep 09 09:59:56 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420987371 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.420987371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.870474593 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 14161285423 ps |
| CPU time | 774.11 seconds |
| Started | Sep 09 09:59:53 PM UTC 24 |
| Finished | Sep 09 10:12:56 PM UTC 24 |
| Peak memory | 387256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870474593 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.870474593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.2610089752 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 125636319 ps |
| CPU time | 6.4 seconds |
| Started | Sep 09 09:58:37 PM UTC 24 |
| Finished | Sep 09 09:58:45 PM UTC 24 |
| Peak memory | 231152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610089752 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2610089752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.944264035 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 32970484599 ps |
| CPU time | 1365.42 seconds |
| Started | Sep 09 10:00:06 PM UTC 24 |
| Finished | Sep 09 10:23:06 PM UTC 24 |
| Peak memory | 382560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944264035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.944264035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.886750404 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1051367658 ps |
| CPU time | 163.36 seconds |
| Started | Sep 09 10:00:06 PM UTC 24 |
| Finished | Sep 09 10:02:52 PM UTC 24 |
| Peak memory | 370364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886750404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.886750404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.65011831 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 14407601826 ps |
| CPU time | 326.99 seconds |
| Started | Sep 09 09:58:39 PM UTC 24 |
| Finished | Sep 09 10:04:10 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65011831 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.65011831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.2754837881 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 122960427 ps |
| CPU time | 58.98 seconds |
| Started | Sep 09 09:58:59 PM UTC 24 |
| Finished | Sep 09 10:00:00 PM UTC 24 |
| Peak memory | 338024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2754837881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t hroughput_w_partial_write.2754837881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.829769418 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 14061575046 ps |
| CPU time | 684.89 seconds |
| Started | Sep 09 10:01:51 PM UTC 24 |
| Finished | Sep 09 10:13:23 PM UTC 24 |
| Peak memory | 387240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829769418 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during_ key_req.829769418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1215097939 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 12436251 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 10:02:14 PM UTC 24 |
| Finished | Sep 09 10:02:16 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215097939 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1215097939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.1584466305 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 12715139767 ps |
| CPU time | 61.13 seconds |
| Started | Sep 09 10:00:21 PM UTC 24 |
| Finished | Sep 09 10:01:23 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584466305 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.1584466305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3859849920 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 11694388991 ps |
| CPU time | 1217 seconds |
| Started | Sep 09 10:01:56 PM UTC 24 |
| Finished | Sep 09 10:22:26 PM UTC 24 |
| Peak memory | 370872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859849920 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.3859849920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3821115819 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1449104467 ps |
| CPU time | 7.8 seconds |
| Started | Sep 09 10:01:47 PM UTC 24 |
| Finished | Sep 09 10:01:55 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821115819 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.3821115819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.304774957 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 150600925 ps |
| CPU time | 101.18 seconds |
| Started | Sep 09 10:01:24 PM UTC 24 |
| Finished | Sep 09 10:03:07 PM UTC 24 |
| Peak memory | 374952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 04774957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max _throughput.304774957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2054313326 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 270427284 ps |
| CPU time | 6.64 seconds |
| Started | Sep 09 10:02:03 PM UTC 24 |
| Finished | Sep 09 10:02:11 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054313326 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.2054313326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1441629238 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2711471061 ps |
| CPU time | 16.12 seconds |
| Started | Sep 09 10:02:02 PM UTC 24 |
| Finished | Sep 09 10:02:19 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441629238 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.1441629238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3681949898 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 12470133410 ps |
| CPU time | 932.68 seconds |
| Started | Sep 09 10:00:19 PM UTC 24 |
| Finished | Sep 09 10:16:01 PM UTC 24 |
| Peak memory | 382824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681949898 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.3681949898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.626235253 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1233916176 ps |
| CPU time | 92.54 seconds |
| Started | Sep 09 10:00:43 PM UTC 24 |
| Finished | Sep 09 10:02:17 PM UTC 24 |
| Peak memory | 362280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626235253 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.626235253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1533747924 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 52778049511 ps |
| CPU time | 391.04 seconds |
| Started | Sep 09 10:00:44 PM UTC 24 |
| Finished | Sep 09 10:07:20 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533747924 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acc ess_b2b.1533747924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3369861007 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 25743291 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 10:01:59 PM UTC 24 |
| Finished | Sep 09 10:02:01 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369861007 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3369861007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.253848266 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1287517225 ps |
| CPU time | 626.31 seconds |
| Started | Sep 09 10:01:59 PM UTC 24 |
| Finished | Sep 09 10:12:32 PM UTC 24 |
| Peak memory | 385012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253848266 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.253848266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2486699420 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2662082463 ps |
| CPU time | 17.24 seconds |
| Started | Sep 09 10:00:17 PM UTC 24 |
| Finished | Sep 09 10:00:36 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486699420 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2486699420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1526237369 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 190737796878 ps |
| CPU time | 2382.33 seconds |
| Started | Sep 09 10:02:11 PM UTC 24 |
| Finished | Sep 09 10:42:19 PM UTC 24 |
| Peak memory | 388780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152623736 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.1526237369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.735791624 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3646369886 ps |
| CPU time | 190.28 seconds |
| Started | Sep 09 10:02:11 PM UTC 24 |
| Finished | Sep 09 10:05:25 PM UTC 24 |
| Peak memory | 374900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735791624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.735791624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1556291714 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 26311627375 ps |
| CPU time | 261.59 seconds |
| Started | Sep 09 10:00:37 PM UTC 24 |
| Finished | Sep 09 10:05:02 PM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556291714 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.1556291714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.1409263495 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1471670040 ps |
| CPU time | 29.62 seconds |
| Started | Sep 09 10:01:39 PM UTC 24 |
| Finished | Sep 09 10:02:10 PM UTC 24 |
| Peak memory | 298852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1409263495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t hroughput_w_partial_write.1409263495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.85595924 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 11178884559 ps |
| CPU time | 715.73 seconds |
| Started | Sep 09 10:03:09 PM UTC 24 |
| Finished | Sep 09 10:15:12 PM UTC 24 |
| Peak memory | 382836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85595924 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_k ey_req.85595924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3452974924 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 13217257 ps |
| CPU time | 0.86 seconds |
| Started | Sep 09 10:03:43 PM UTC 24 |
| Finished | Sep 09 10:03:45 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452974924 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3452974924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2739523876 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2486543486 ps |
| CPU time | 43.83 seconds |
| Started | Sep 09 10:02:19 PM UTC 24 |
| Finished | Sep 09 10:03:04 PM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739523876 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.2739523876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3576558151 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5648342334 ps |
| CPU time | 393.93 seconds |
| Started | Sep 09 10:03:14 PM UTC 24 |
| Finished | Sep 09 10:09:53 PM UTC 24 |
| Peak memory | 372672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576558151 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.3576558151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1830905414 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5313657441 ps |
| CPU time | 7.81 seconds |
| Started | Sep 09 10:03:05 PM UTC 24 |
| Finished | Sep 09 10:03:13 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830905414 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.1830905414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.440476951 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 353046335 ps |
| CPU time | 18.56 seconds |
| Started | Sep 09 10:02:53 PM UTC 24 |
| Finished | Sep 09 10:03:13 PM UTC 24 |
| Peak memory | 272236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 40476951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max _throughput.440476951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3424748792 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 95732904 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 10:03:21 PM UTC 24 |
| Finished | Sep 09 10:03:26 PM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424748792 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.3424748792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2278290942 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 239150642 ps |
| CPU time | 8.53 seconds |
| Started | Sep 09 10:03:19 PM UTC 24 |
| Finished | Sep 09 10:03:29 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278290942 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.2278290942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2273209983 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 75392660941 ps |
| CPU time | 792.15 seconds |
| Started | Sep 09 10:02:19 PM UTC 24 |
| Finished | Sep 09 10:15:40 PM UTC 24 |
| Peak memory | 362340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273209983 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.2273209983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3084895482 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 324533725 ps |
| CPU time | 76.83 seconds |
| Started | Sep 09 10:02:23 PM UTC 24 |
| Finished | Sep 09 10:03:42 PM UTC 24 |
| Peak memory | 354088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084895482 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3084895482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2643929709 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 25967677743 ps |
| CPU time | 411.7 seconds |
| Started | Sep 09 10:02:42 PM UTC 24 |
| Finished | Sep 09 10:09:39 PM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643929709 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc ess_b2b.2643929709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2880415904 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 76867971 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:03:16 PM UTC 24 |
| Finished | Sep 09 10:03:18 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880415904 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2880415904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.3098958543 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 7636330104 ps |
| CPU time | 442.42 seconds |
| Started | Sep 09 10:03:14 PM UTC 24 |
| Finished | Sep 09 10:10:41 PM UTC 24 |
| Peak memory | 354232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098958543 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3098958543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.671712182 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 162503336 ps |
| CPU time | 3.58 seconds |
| Started | Sep 09 10:02:17 PM UTC 24 |
| Finished | Sep 09 10:02:22 PM UTC 24 |
| Peak memory | 220144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671712182 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.671712182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3041966019 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 42343203622 ps |
| CPU time | 2056.04 seconds |
| Started | Sep 09 10:03:30 PM UTC 24 |
| Finished | Sep 09 10:38:07 PM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304196601 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.3041966019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3916084187 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2079516129 ps |
| CPU time | 144.06 seconds |
| Started | Sep 09 10:03:27 PM UTC 24 |
| Finished | Sep 09 10:05:54 PM UTC 24 |
| Peak memory | 366828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916084187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3916084187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3615577962 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2148427823 ps |
| CPU time | 257.21 seconds |
| Started | Sep 09 10:02:20 PM UTC 24 |
| Finished | Sep 09 10:06:41 PM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615577962 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.3615577962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1059062283 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 190972035 ps |
| CPU time | 19.75 seconds |
| Started | Sep 09 10:02:59 PM UTC 24 |
| Finished | Sep 09 10:03:20 PM UTC 24 |
| Peak memory | 298856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1059062283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t hroughput_w_partial_write.1059062283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1824759307 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1110589002 ps |
| CPU time | 41.84 seconds |
| Started | Sep 09 10:04:37 PM UTC 24 |
| Finished | Sep 09 10:05:20 PM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824759307 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during _key_req.1824759307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.2052390872 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 15834299 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:05:21 PM UTC 24 |
| Finished | Sep 09 10:05:23 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052390872 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.2052390872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2792460650 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1736452887 ps |
| CPU time | 28.75 seconds |
| Started | Sep 09 10:04:01 PM UTC 24 |
| Finished | Sep 09 10:04:31 PM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792460650 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.2792460650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.3085360304 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 812104727 ps |
| CPU time | 18.5 seconds |
| Started | Sep 09 10:04:41 PM UTC 24 |
| Finished | Sep 09 10:05:01 PM UTC 24 |
| Peak memory | 235384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085360304 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.3085360304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.957547942 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1625568251 ps |
| CPU time | 5.23 seconds |
| Started | Sep 09 10:04:34 PM UTC 24 |
| Finished | Sep 09 10:04:40 PM UTC 24 |
| Peak memory | 214128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957547942 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.957547942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.750098734 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 185954457 ps |
| CPU time | 4.49 seconds |
| Started | Sep 09 10:04:30 PM UTC 24 |
| Finished | Sep 09 10:04:36 PM UTC 24 |
| Peak memory | 231200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 50098734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_max _throughput.750098734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.622066719 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 66017757 ps |
| CPU time | 5.95 seconds |
| Started | Sep 09 10:05:15 PM UTC 24 |
| Finished | Sep 09 10:05:22 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622066719 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.622066719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3610694760 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 264969669 ps |
| CPU time | 10.27 seconds |
| Started | Sep 09 10:05:06 PM UTC 24 |
| Finished | Sep 09 10:05:18 PM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610694760 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.3610694760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2751319722 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1619808483 ps |
| CPU time | 120.58 seconds |
| Started | Sep 09 10:03:58 PM UTC 24 |
| Finished | Sep 09 10:06:01 PM UTC 24 |
| Peak memory | 335660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751319722 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.2751319722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1638146764 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 484541891 ps |
| CPU time | 11.28 seconds |
| Started | Sep 09 10:04:20 PM UTC 24 |
| Finished | Sep 09 10:04:33 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638146764 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.1638146764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2318820363 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4522936727 ps |
| CPU time | 398.44 seconds |
| Started | Sep 09 10:04:30 PM UTC 24 |
| Finished | Sep 09 10:11:15 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318820363 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc ess_b2b.2318820363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4277515154 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 36083073 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 10:05:03 PM UTC 24 |
| Finished | Sep 09 10:05:05 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277515154 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.4277515154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1857151165 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2920876464 ps |
| CPU time | 340.68 seconds |
| Started | Sep 09 10:05:01 PM UTC 24 |
| Finished | Sep 09 10:10:46 PM UTC 24 |
| Peak memory | 379060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857151165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1857151165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.292996375 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4236233375 ps |
| CPU time | 12.46 seconds |
| Started | Sep 09 10:03:46 PM UTC 24 |
| Finished | Sep 09 10:04:00 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292996375 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.292996375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3805173229 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 176693380925 ps |
| CPU time | 2814.22 seconds |
| Started | Sep 09 10:05:19 PM UTC 24 |
| Finished | Sep 09 10:52:43 PM UTC 24 |
| Peak memory | 388688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380517322 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.3805173229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.1157397592 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 9662225017 ps |
| CPU time | 304.12 seconds |
| Started | Sep 09 10:04:11 PM UTC 24 |
| Finished | Sep 09 10:09:20 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157397592 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.1157397592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.4139965749 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 740680488 ps |
| CPU time | 52.27 seconds |
| Started | Sep 09 10:04:33 PM UTC 24 |
| Finished | Sep 09 10:05:26 PM UTC 24 |
| Peak memory | 329576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4139965749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t hroughput_w_partial_write.4139965749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3142590005 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1483859486 ps |
| CPU time | 231.43 seconds |
| Started | Sep 09 10:06:02 PM UTC 24 |
| Finished | Sep 09 10:09:56 PM UTC 24 |
| Peak memory | 384800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142590005 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during _key_req.3142590005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3787943041 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 29536388 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 10:06:39 PM UTC 24 |
| Finished | Sep 09 10:06:41 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787943041 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3787943041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.422857030 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 14448875365 ps |
| CPU time | 102.45 seconds |
| Started | Sep 09 10:05:26 PM UTC 24 |
| Finished | Sep 09 10:07:11 PM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422857030 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.422857030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2266750938 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 2505090904 ps |
| CPU time | 149.81 seconds |
| Started | Sep 09 10:06:03 PM UTC 24 |
| Finished | Sep 09 10:08:35 PM UTC 24 |
| Peak memory | 311144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266750938 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.2266750938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2012378678 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1885305553 ps |
| CPU time | 7.65 seconds |
| Started | Sep 09 10:06:02 PM UTC 24 |
| Finished | Sep 09 10:06:11 PM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012378678 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2012378678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1747252280 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 94419842 ps |
| CPU time | 6.11 seconds |
| Started | Sep 09 10:05:54 PM UTC 24 |
| Finished | Sep 09 10:06:02 PM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 747252280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ma x_throughput.1747252280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3141647631 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1149115676 ps |
| CPU time | 8.86 seconds |
| Started | Sep 09 10:06:22 PM UTC 24 |
| Finished | Sep 09 10:06:32 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141647631 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.3141647631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.428429223 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 784124447 ps |
| CPU time | 16.37 seconds |
| Started | Sep 09 10:06:14 PM UTC 24 |
| Finished | Sep 09 10:06:32 PM UTC 24 |
| Peak memory | 213736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428429223 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.428429223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.2989547444 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 20419456504 ps |
| CPU time | 541.13 seconds |
| Started | Sep 09 10:05:24 PM UTC 24 |
| Finished | Sep 09 10:14:32 PM UTC 24 |
| Peak memory | 356528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989547444 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.2989547444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3796759325 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2205218884 ps |
| CPU time | 24.88 seconds |
| Started | Sep 09 10:05:27 PM UTC 24 |
| Finished | Sep 09 10:05:54 PM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796759325 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.3796759325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2724399852 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 45597555172 ps |
| CPU time | 404.73 seconds |
| Started | Sep 09 10:05:39 PM UTC 24 |
| Finished | Sep 09 10:12:30 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724399852 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acc ess_b2b.2724399852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.848423605 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 260108059 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 10:06:11 PM UTC 24 |
| Finished | Sep 09 10:06:13 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848423605 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.848423605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.540123460 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2833219205 ps |
| CPU time | 406.55 seconds |
| Started | Sep 09 10:06:03 PM UTC 24 |
| Finished | Sep 09 10:12:54 PM UTC 24 |
| Peak memory | 385204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540123460 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.540123460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.54951120 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 161996295 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 10:05:23 PM UTC 24 |
| Finished | Sep 09 10:05:26 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54951120 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.54951120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.329932868 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 3629766865 ps |
| CPU time | 885.83 seconds |
| Started | Sep 09 10:06:34 PM UTC 24 |
| Finished | Sep 09 10:21:31 PM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329932868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.329932868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3675050585 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3346490146 ps |
| CPU time | 175.27 seconds |
| Started | Sep 09 10:05:26 PM UTC 24 |
| Finished | Sep 09 10:08:25 PM UTC 24 |
| Peak memory | 214152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675050585 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3675050585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.94709307 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 229114371 ps |
| CPU time | 6.31 seconds |
| Started | Sep 09 10:05:55 PM UTC 24 |
| Finished | Sep 09 10:06:02 PM UTC 24 |
| Peak memory | 241504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 94709307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_thr oughput_w_partial_write.94709307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1655956275 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 24106228597 ps |
| CPU time | 449.96 seconds |
| Started | Sep 09 09:11:07 PM UTC 24 |
| Finished | Sep 09 09:18:42 PM UTC 24 |
| Peak memory | 378728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655956275 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_ key_req.1655956275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.636387911 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 20952605 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:11:26 PM UTC 24 |
| Finished | Sep 09 09:11:28 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636387911 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.636387911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.31719165 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1814389200 ps |
| CPU time | 43.52 seconds |
| Started | Sep 09 09:10:54 PM UTC 24 |
| Finished | Sep 09 09:11:39 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31719165 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.31719165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.377050909 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 17793406788 ps |
| CPU time | 913.27 seconds |
| Started | Sep 09 09:11:07 PM UTC 24 |
| Finished | Sep 09 09:26:30 PM UTC 24 |
| Peak memory | 384784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377050909 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.377050909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1987961467 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 410004169 ps |
| CPU time | 7.23 seconds |
| Started | Sep 09 09:11:06 PM UTC 24 |
| Finished | Sep 09 09:11:14 PM UTC 24 |
| Peak memory | 224360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987961467 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.1987961467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2267499285 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 68737781 ps |
| CPU time | 1.92 seconds |
| Started | Sep 09 09:11:03 PM UTC 24 |
| Finished | Sep 09 09:11:06 PM UTC 24 |
| Peak memory | 222652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 267499285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max _throughput.2267499285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3593086463 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 329295009 ps |
| CPU time | 3.57 seconds |
| Started | Sep 09 09:11:15 PM UTC 24 |
| Finished | Sep 09 09:11:20 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593086463 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.3593086463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1284661351 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 932828027 ps |
| CPU time | 9.24 seconds |
| Started | Sep 09 09:11:15 PM UTC 24 |
| Finished | Sep 09 09:11:25 PM UTC 24 |
| Peak memory | 224128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284661351 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.1284661351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1795157371 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 9252773678 ps |
| CPU time | 311.4 seconds |
| Started | Sep 09 09:10:54 PM UTC 24 |
| Finished | Sep 09 09:16:10 PM UTC 24 |
| Peak memory | 383232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795157371 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.1795157371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2121088413 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1083301782 ps |
| CPU time | 7.55 seconds |
| Started | Sep 09 09:10:57 PM UTC 24 |
| Finished | Sep 09 09:11:06 PM UTC 24 |
| Peak memory | 213748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121088413 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.2121088413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.89521126 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 103141341315 ps |
| CPU time | 869.92 seconds |
| Started | Sep 09 09:11:00 PM UTC 24 |
| Finished | Sep 09 09:25:40 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89521126 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access _b2b.89521126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.596300728 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 29687393 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:11:12 PM UTC 24 |
| Finished | Sep 09 09:11:14 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596300728 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.596300728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.2002990910 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 983189229 ps |
| CPU time | 160.61 seconds |
| Started | Sep 09 09:11:07 PM UTC 24 |
| Finished | Sep 09 09:13:50 PM UTC 24 |
| Peak memory | 350072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002990910 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2002990910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2727333033 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 630106812 ps |
| CPU time | 2.88 seconds |
| Started | Sep 09 09:11:20 PM UTC 24 |
| Finished | Sep 09 09:11:24 PM UTC 24 |
| Peak memory | 250096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727333033 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2727333033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.634252403 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 596492269 ps |
| CPU time | 67.72 seconds |
| Started | Sep 09 09:10:53 PM UTC 24 |
| Finished | Sep 09 09:12:03 PM UTC 24 |
| Peak memory | 364732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634252403 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.634252403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.263518829 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 6769771245 ps |
| CPU time | 2306.69 seconds |
| Started | Sep 09 09:11:18 PM UTC 24 |
| Finished | Sep 09 09:50:09 PM UTC 24 |
| Peak memory | 385244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263518829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.263518829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1842910800 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2673259650 ps |
| CPU time | 292.52 seconds |
| Started | Sep 09 09:10:55 PM UTC 24 |
| Finished | Sep 09 09:15:52 PM UTC 24 |
| Peak memory | 214236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842910800 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.1842910800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2993900907 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 236642528 ps |
| CPU time | 30.61 seconds |
| Started | Sep 09 09:11:04 PM UTC 24 |
| Finished | Sep 09 09:11:36 PM UTC 24 |
| Peak memory | 300836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2993900907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th roughput_w_partial_write.2993900907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3968027683 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 971263673 ps |
| CPU time | 15.36 seconds |
| Started | Sep 09 10:07:51 PM UTC 24 |
| Finished | Sep 09 10:08:08 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968027683 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during _key_req.3968027683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3760542537 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 32589252 ps |
| CPU time | 0.87 seconds |
| Started | Sep 09 10:08:36 PM UTC 24 |
| Finished | Sep 09 10:08:38 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760542537 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3760542537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.3296938871 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1565212645 ps |
| CPU time | 22.59 seconds |
| Started | Sep 09 10:07:05 PM UTC 24 |
| Finished | Sep 09 10:07:29 PM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296938871 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.3296938871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.583152750 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 13798890914 ps |
| CPU time | 853.22 seconds |
| Started | Sep 09 10:07:53 PM UTC 24 |
| Finished | Sep 09 10:22:16 PM UTC 24 |
| Peak memory | 368476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583152750 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.583152750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2944015366 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 969218415 ps |
| CPU time | 11.65 seconds |
| Started | Sep 09 10:07:46 PM UTC 24 |
| Finished | Sep 09 10:07:59 PM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944015366 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.2944015366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.533093017 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 131599693 ps |
| CPU time | 76.77 seconds |
| Started | Sep 09 10:07:30 PM UTC 24 |
| Finished | Sep 09 10:08:49 PM UTC 24 |
| Peak memory | 376684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 33093017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max _throughput.533093017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3016241034 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 746934001 ps |
| CPU time | 7.12 seconds |
| Started | Sep 09 10:08:26 PM UTC 24 |
| Finished | Sep 09 10:08:34 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016241034 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.3016241034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.99580461 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 191078478 ps |
| CPU time | 11.62 seconds |
| Started | Sep 09 10:08:12 PM UTC 24 |
| Finished | Sep 09 10:08:25 PM UTC 24 |
| Peak memory | 224004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99580461 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.99580461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1251141288 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2612857435 ps |
| CPU time | 637.71 seconds |
| Started | Sep 09 10:06:42 PM UTC 24 |
| Finished | Sep 09 10:17:27 PM UTC 24 |
| Peak memory | 386968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251141288 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1251141288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.464625067 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 761152675 ps |
| CPU time | 93.1 seconds |
| Started | Sep 09 10:07:21 PM UTC 24 |
| Finished | Sep 09 10:08:56 PM UTC 24 |
| Peak memory | 360508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464625067 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.464625067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1097775855 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 57262634629 ps |
| CPU time | 411.1 seconds |
| Started | Sep 09 10:07:23 PM UTC 24 |
| Finished | Sep 09 10:14:19 PM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097775855 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc ess_b2b.1097775855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2154890589 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 91862287 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:08:09 PM UTC 24 |
| Finished | Sep 09 10:08:11 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154890589 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2154890589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2634343921 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 12154365546 ps |
| CPU time | 798.39 seconds |
| Started | Sep 09 10:07:59 PM UTC 24 |
| Finished | Sep 09 10:21:27 PM UTC 24 |
| Peak memory | 387204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634343921 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2634343921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.1428851209 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 457419643 ps |
| CPU time | 68.25 seconds |
| Started | Sep 09 10:06:42 PM UTC 24 |
| Finished | Sep 09 10:07:52 PM UTC 24 |
| Peak memory | 335676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428851209 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1428851209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.415729008 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 25431411481 ps |
| CPU time | 1373.74 seconds |
| Started | Sep 09 10:08:35 PM UTC 24 |
| Finished | Sep 09 10:31:45 PM UTC 24 |
| Peak memory | 380796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415729008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.415729008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.57563002 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 695104895 ps |
| CPU time | 92.22 seconds |
| Started | Sep 09 10:08:26 PM UTC 24 |
| Finished | Sep 09 10:10:00 PM UTC 24 |
| Peak memory | 368820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57563002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.57563002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2694270510 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2948482320 ps |
| CPU time | 265.84 seconds |
| Started | Sep 09 10:07:11 PM UTC 24 |
| Finished | Sep 09 10:11:41 PM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694270510 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.2694270510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3768782825 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 154036483 ps |
| CPU time | 105.65 seconds |
| Started | Sep 09 10:07:35 PM UTC 24 |
| Finished | Sep 09 10:09:23 PM UTC 24 |
| Peak memory | 381032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3768782825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_t hroughput_w_partial_write.3768782825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3321343530 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1890240358 ps |
| CPU time | 93.09 seconds |
| Started | Sep 09 10:09:36 PM UTC 24 |
| Finished | Sep 09 10:11:12 PM UTC 24 |
| Peak memory | 348008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321343530 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during _key_req.3321343530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.591330158 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 35642373 ps |
| CPU time | 0.84 seconds |
| Started | Sep 09 10:09:56 PM UTC 24 |
| Finished | Sep 09 10:09:58 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591330158 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.591330158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.2687426630 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3104390766 ps |
| CPU time | 61.18 seconds |
| Started | Sep 09 10:08:57 PM UTC 24 |
| Finished | Sep 09 10:09:59 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687426630 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.2687426630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.3165720093 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 2258361819 ps |
| CPU time | 137.63 seconds |
| Started | Sep 09 10:09:40 PM UTC 24 |
| Finished | Sep 09 10:12:00 PM UTC 24 |
| Peak memory | 309076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165720093 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.3165720093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3913288230 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3170185266 ps |
| CPU time | 8.2 seconds |
| Started | Sep 09 10:09:29 PM UTC 24 |
| Finished | Sep 09 10:09:39 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913288230 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.3913288230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2791155873 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 179098068 ps |
| CPU time | 6.03 seconds |
| Started | Sep 09 10:09:21 PM UTC 24 |
| Finished | Sep 09 10:09:28 PM UTC 24 |
| Peak memory | 235312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 791155873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma x_throughput.2791155873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2170642828 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 108133021 ps |
| CPU time | 6.83 seconds |
| Started | Sep 09 10:09:48 PM UTC 24 |
| Finished | Sep 09 10:09:56 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170642828 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.2170642828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2345458509 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 95997295 ps |
| CPU time | 6.45 seconds |
| Started | Sep 09 10:09:46 PM UTC 24 |
| Finished | Sep 09 10:09:53 PM UTC 24 |
| Peak memory | 224148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345458509 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.2345458509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2755718323 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 19443694079 ps |
| CPU time | 721.4 seconds |
| Started | Sep 09 10:08:49 PM UTC 24 |
| Finished | Sep 09 10:20:59 PM UTC 24 |
| Peak memory | 383160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755718323 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2755718323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.298595082 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 464384813 ps |
| CPU time | 20.51 seconds |
| Started | Sep 09 10:09:14 PM UTC 24 |
| Finished | Sep 09 10:09:36 PM UTC 24 |
| Peak memory | 292956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298595082 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.298595082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3567305232 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 52005807588 ps |
| CPU time | 277.81 seconds |
| Started | Sep 09 10:09:21 PM UTC 24 |
| Finished | Sep 09 10:14:03 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567305232 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc ess_b2b.3567305232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1260068448 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 145926454 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 10:09:45 PM UTC 24 |
| Finished | Sep 09 10:09:47 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260068448 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1260068448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.3616736909 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 11747368042 ps |
| CPU time | 704.65 seconds |
| Started | Sep 09 10:09:41 PM UTC 24 |
| Finished | Sep 09 10:21:34 PM UTC 24 |
| Peak memory | 381176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616736909 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3616736909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.3018653415 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1132969225 ps |
| CPU time | 63.89 seconds |
| Started | Sep 09 10:08:39 PM UTC 24 |
| Finished | Sep 09 10:09:45 PM UTC 24 |
| Peak memory | 335612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018653415 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3018653415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1332778061 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 121011586997 ps |
| CPU time | 1395.73 seconds |
| Started | Sep 09 10:09:54 PM UTC 24 |
| Finished | Sep 09 10:33:25 PM UTC 24 |
| Peak memory | 386924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133277806 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.1332778061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3326083756 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 6808714657 ps |
| CPU time | 71.51 seconds |
| Started | Sep 09 10:09:54 PM UTC 24 |
| Finished | Sep 09 10:11:07 PM UTC 24 |
| Peak memory | 362476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326083756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3326083756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3255824733 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 6347924375 ps |
| CPU time | 188.25 seconds |
| Started | Sep 09 10:09:06 PM UTC 24 |
| Finished | Sep 09 10:12:17 PM UTC 24 |
| Peak memory | 214304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255824733 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.3255824733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.1270502426 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 153370018 ps |
| CPU time | 48.66 seconds |
| Started | Sep 09 10:09:23 PM UTC 24 |
| Finished | Sep 09 10:10:13 PM UTC 24 |
| Peak memory | 329836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1270502426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t hroughput_w_partial_write.1270502426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.403640743 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 22415409280 ps |
| CPU time | 685.46 seconds |
| Started | Sep 09 10:10:30 PM UTC 24 |
| Finished | Sep 09 10:22:03 PM UTC 24 |
| Peak memory | 387244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403640743 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during_ key_req.403640743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1111467543 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 58746861 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 10:11:09 PM UTC 24 |
| Finished | Sep 09 10:11:11 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111467543 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1111467543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.1991653064 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 7265012472 ps |
| CPU time | 82.77 seconds |
| Started | Sep 09 10:10:00 PM UTC 24 |
| Finished | Sep 09 10:11:24 PM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991653064 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.1991653064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.4022830780 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 23650775364 ps |
| CPU time | 472.41 seconds |
| Started | Sep 09 10:10:34 PM UTC 24 |
| Finished | Sep 09 10:18:32 PM UTC 24 |
| Peak memory | 380852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022830780 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.4022830780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2705902947 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 831234066 ps |
| CPU time | 10.83 seconds |
| Started | Sep 09 10:10:16 PM UTC 24 |
| Finished | Sep 09 10:10:28 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705902947 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.2705902947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2971010977 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 160220906 ps |
| CPU time | 83.03 seconds |
| Started | Sep 09 10:10:07 PM UTC 24 |
| Finished | Sep 09 10:11:32 PM UTC 24 |
| Peak memory | 346156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 971010977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma x_throughput.2971010977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3361089675 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 92873782 ps |
| CPU time | 4.03 seconds |
| Started | Sep 09 10:10:50 PM UTC 24 |
| Finished | Sep 09 10:10:55 PM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361089675 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.3361089675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.603039759 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1190574385 ps |
| CPU time | 6.46 seconds |
| Started | Sep 09 10:10:49 PM UTC 24 |
| Finished | Sep 09 10:10:56 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603039759 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.603039759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2061779396 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 7216489639 ps |
| CPU time | 795.76 seconds |
| Started | Sep 09 10:09:59 PM UTC 24 |
| Finished | Sep 09 10:23:22 PM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061779396 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.2061779396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1736020365 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 90990050 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 10:10:01 PM UTC 24 |
| Finished | Sep 09 10:10:06 PM UTC 24 |
| Peak memory | 220020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736020365 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.1736020365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1871668001 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 48809619580 ps |
| CPU time | 342.44 seconds |
| Started | Sep 09 10:10:02 PM UTC 24 |
| Finished | Sep 09 10:15:49 PM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871668001 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acc ess_b2b.1871668001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1077291730 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 29503598 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 10:10:47 PM UTC 24 |
| Finished | Sep 09 10:10:49 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077291730 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1077291730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.786276155 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4956553186 ps |
| CPU time | 639.65 seconds |
| Started | Sep 09 10:10:42 PM UTC 24 |
| Finished | Sep 09 10:21:29 PM UTC 24 |
| Peak memory | 387004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786276155 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.786276155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2805625474 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 165253985 ps |
| CPU time | 99.62 seconds |
| Started | Sep 09 10:09:57 PM UTC 24 |
| Finished | Sep 09 10:11:39 PM UTC 24 |
| Peak memory | 380712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805625474 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2805625474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.2390460804 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 44379134172 ps |
| CPU time | 2308.11 seconds |
| Started | Sep 09 10:10:57 PM UTC 24 |
| Finished | Sep 09 10:49:50 PM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239046080 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.2390460804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.638771865 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1593565206 ps |
| CPU time | 99.23 seconds |
| Started | Sep 09 10:10:56 PM UTC 24 |
| Finished | Sep 09 10:12:38 PM UTC 24 |
| Peak memory | 331620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638771865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.638771865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1852697704 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 17886321709 ps |
| CPU time | 326.01 seconds |
| Started | Sep 09 10:10:01 PM UTC 24 |
| Finished | Sep 09 10:15:31 PM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852697704 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1852697704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1706210277 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 574453934 ps |
| CPU time | 74.32 seconds |
| Started | Sep 09 10:10:14 PM UTC 24 |
| Finished | Sep 09 10:11:31 PM UTC 24 |
| Peak memory | 372848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1706210277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.1706210277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2637683954 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 3479462438 ps |
| CPU time | 885.89 seconds |
| Started | Sep 09 10:11:41 PM UTC 24 |
| Finished | Sep 09 10:26:36 PM UTC 24 |
| Peak memory | 385128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637683954 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during _key_req.2637683954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1713110763 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 14459531 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 10:12:09 PM UTC 24 |
| Finished | Sep 09 10:12:11 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713110763 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1713110763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.2319155651 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2473752464 ps |
| CPU time | 43.96 seconds |
| Started | Sep 09 10:11:16 PM UTC 24 |
| Finished | Sep 09 10:12:01 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319155651 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.2319155651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2287156237 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 77694942425 ps |
| CPU time | 1802.23 seconds |
| Started | Sep 09 10:11:42 PM UTC 24 |
| Finished | Sep 09 10:42:02 PM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287156237 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.2287156237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1389906937 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 910651756 ps |
| CPU time | 17.66 seconds |
| Started | Sep 09 10:11:40 PM UTC 24 |
| Finished | Sep 09 10:11:58 PM UTC 24 |
| Peak memory | 213832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389906937 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.1389906937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1519506062 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1328361679 ps |
| CPU time | 28.11 seconds |
| Started | Sep 09 10:11:34 PM UTC 24 |
| Finished | Sep 09 10:12:04 PM UTC 24 |
| Peak memory | 319224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 519506062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma x_throughput.1519506062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2092809139 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 108130685 ps |
| CPU time | 4.34 seconds |
| Started | Sep 09 10:12:02 PM UTC 24 |
| Finished | Sep 09 10:12:08 PM UTC 24 |
| Peak memory | 224288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092809139 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.2092809139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2142138685 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 186916632 ps |
| CPU time | 13.31 seconds |
| Started | Sep 09 10:12:00 PM UTC 24 |
| Finished | Sep 09 10:12:15 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142138685 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.2142138685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1410474523 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 21587179068 ps |
| CPU time | 1271.29 seconds |
| Started | Sep 09 10:11:13 PM UTC 24 |
| Finished | Sep 09 10:32:38 PM UTC 24 |
| Peak memory | 382824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410474523 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.1410474523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.147741103 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 92428558 ps |
| CPU time | 4.35 seconds |
| Started | Sep 09 10:11:31 PM UTC 24 |
| Finished | Sep 09 10:11:37 PM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147741103 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.147741103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1922981670 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 39405599750 ps |
| CPU time | 313.92 seconds |
| Started | Sep 09 10:11:33 PM UTC 24 |
| Finished | Sep 09 10:16:52 PM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922981670 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc ess_b2b.1922981670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3171834019 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 107093743 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 10:11:59 PM UTC 24 |
| Finished | Sep 09 10:12:01 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171834019 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3171834019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3994574194 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2854397021 ps |
| CPU time | 703.25 seconds |
| Started | Sep 09 10:11:48 PM UTC 24 |
| Finished | Sep 09 10:23:40 PM UTC 24 |
| Peak memory | 370552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994574194 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3994574194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.940280886 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1467846454 ps |
| CPU time | 20.39 seconds |
| Started | Sep 09 10:11:12 PM UTC 24 |
| Finished | Sep 09 10:11:33 PM UTC 24 |
| Peak memory | 213788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940280886 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.940280886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.947897980 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 37622372037 ps |
| CPU time | 1789.25 seconds |
| Started | Sep 09 10:12:05 PM UTC 24 |
| Finished | Sep 09 10:42:13 PM UTC 24 |
| Peak memory | 386872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947897980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.947897980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3873149771 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 5008464089 ps |
| CPU time | 36.21 seconds |
| Started | Sep 09 10:12:02 PM UTC 24 |
| Finished | Sep 09 10:12:40 PM UTC 24 |
| Peak memory | 264504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873149771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3873149771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3877537361 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 33305712027 ps |
| CPU time | 241.02 seconds |
| Started | Sep 09 10:11:25 PM UTC 24 |
| Finished | Sep 09 10:15:30 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877537361 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.3877537361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.775878018 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 136591967 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 10:11:38 PM UTC 24 |
| Finished | Sep 09 10:11:40 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 775878018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_th roughput_w_partial_write.775878018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2829481399 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 3848918680 ps |
| CPU time | 1057.8 seconds |
| Started | Sep 09 10:12:41 PM UTC 24 |
| Finished | Sep 09 10:30:31 PM UTC 24 |
| Peak memory | 380840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829481399 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during _key_req.2829481399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.3719840425 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 22181489 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 10:13:03 PM UTC 24 |
| Finished | Sep 09 10:13:05 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719840425 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.3719840425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.2242354919 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4911014248 ps |
| CPU time | 63.5 seconds |
| Started | Sep 09 10:12:16 PM UTC 24 |
| Finished | Sep 09 10:13:21 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242354919 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.2242354919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.2018120165 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 10648096204 ps |
| CPU time | 547.17 seconds |
| Started | Sep 09 10:12:41 PM UTC 24 |
| Finished | Sep 09 10:21:54 PM UTC 24 |
| Peak memory | 366520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018120165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.2018120165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.564977466 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 857870813 ps |
| CPU time | 12.21 seconds |
| Started | Sep 09 10:12:39 PM UTC 24 |
| Finished | Sep 09 10:12:52 PM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564977466 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.564977466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.630240982 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 54092708 ps |
| CPU time | 5.38 seconds |
| Started | Sep 09 10:12:34 PM UTC 24 |
| Finished | Sep 09 10:12:40 PM UTC 24 |
| Peak memory | 247716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 30240982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_max _throughput.630240982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.93930650 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1804231459 ps |
| CPU time | 7.75 seconds |
| Started | Sep 09 10:12:56 PM UTC 24 |
| Finished | Sep 09 10:13:05 PM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93930650 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.93930650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2167063010 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1571489577 ps |
| CPU time | 7.66 seconds |
| Started | Sep 09 10:12:54 PM UTC 24 |
| Finished | Sep 09 10:13:02 PM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167063010 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.2167063010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3734171877 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 14244252841 ps |
| CPU time | 552.17 seconds |
| Started | Sep 09 10:12:15 PM UTC 24 |
| Finished | Sep 09 10:21:34 PM UTC 24 |
| Peak memory | 372916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734171877 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.3734171877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.416431195 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 937977800 ps |
| CPU time | 8.38 seconds |
| Started | Sep 09 10:12:30 PM UTC 24 |
| Finished | Sep 09 10:12:40 PM UTC 24 |
| Peak memory | 214136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416431195 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.416431195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.241921726 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3601721033 ps |
| CPU time | 246.96 seconds |
| Started | Sep 09 10:12:31 PM UTC 24 |
| Finished | Sep 09 10:16:41 PM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241921726 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acce ss_b2b.241921726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3268081142 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 44479641 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 10:12:54 PM UTC 24 |
| Finished | Sep 09 10:12:56 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268081142 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3268081142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.839150513 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 15616321629 ps |
| CPU time | 167.4 seconds |
| Started | Sep 09 10:12:41 PM UTC 24 |
| Finished | Sep 09 10:15:31 PM UTC 24 |
| Peak memory | 343948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839150513 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.839150513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.3189864413 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 87133529 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 10:12:12 PM UTC 24 |
| Finished | Sep 09 10:12:15 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189864413 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3189864413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1910551708 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 184530654979 ps |
| CPU time | 2393.73 seconds |
| Started | Sep 09 10:12:57 PM UTC 24 |
| Finished | Sep 09 10:53:16 PM UTC 24 |
| Peak memory | 388720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191055170 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.1910551708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.117672941 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 525054593 ps |
| CPU time | 26.51 seconds |
| Started | Sep 09 10:12:57 PM UTC 24 |
| Finished | Sep 09 10:13:25 PM UTC 24 |
| Peak memory | 262388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117672941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.117672941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2495862566 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 12757464368 ps |
| CPU time | 298.86 seconds |
| Started | Sep 09 10:12:18 PM UTC 24 |
| Finished | Sep 09 10:17:21 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495862566 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.2495862566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3701342779 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 277793657 ps |
| CPU time | 91.32 seconds |
| Started | Sep 09 10:12:35 PM UTC 24 |
| Finished | Sep 09 10:14:08 PM UTC 24 |
| Peak memory | 374508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3701342779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t hroughput_w_partial_write.3701342779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3108846126 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3025311312 ps |
| CPU time | 758.19 seconds |
| Started | Sep 09 10:14:03 PM UTC 24 |
| Finished | Sep 09 10:26:51 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108846126 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during _key_req.3108846126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3941304770 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 32113305 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 10:14:33 PM UTC 24 |
| Finished | Sep 09 10:14:35 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941304770 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3941304770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2132387275 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 21690444647 ps |
| CPU time | 97.89 seconds |
| Started | Sep 09 10:13:11 PM UTC 24 |
| Finished | Sep 09 10:14:51 PM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132387275 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.2132387275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3710209918 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 10574441802 ps |
| CPU time | 142.17 seconds |
| Started | Sep 09 10:14:04 PM UTC 24 |
| Finished | Sep 09 10:16:29 PM UTC 24 |
| Peak memory | 362348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710209918 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3710209918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3986218046 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 761094957 ps |
| CPU time | 14.29 seconds |
| Started | Sep 09 10:13:53 PM UTC 24 |
| Finished | Sep 09 10:14:09 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986218046 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.3986218046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.388683727 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 243759500 ps |
| CPU time | 68.17 seconds |
| Started | Sep 09 10:13:37 PM UTC 24 |
| Finished | Sep 09 10:14:47 PM UTC 24 |
| Peak memory | 352104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 88683727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_max _throughput.388683727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2971705894 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 104290553 ps |
| CPU time | 4.57 seconds |
| Started | Sep 09 10:14:20 PM UTC 24 |
| Finished | Sep 09 10:14:25 PM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971705894 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.2971705894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2126928267 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 448267798 ps |
| CPU time | 13.12 seconds |
| Started | Sep 09 10:14:13 PM UTC 24 |
| Finished | Sep 09 10:14:27 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126928267 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2126928267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1559401058 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 68515372622 ps |
| CPU time | 1058.36 seconds |
| Started | Sep 09 10:13:06 PM UTC 24 |
| Finished | Sep 09 10:30:56 PM UTC 24 |
| Peak memory | 382900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559401058 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.1559401058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2953568932 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 784897236 ps |
| CPU time | 11.56 seconds |
| Started | Sep 09 10:13:24 PM UTC 24 |
| Finished | Sep 09 10:13:37 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953568932 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.2953568932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1261486416 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 10461530361 ps |
| CPU time | 277.42 seconds |
| Started | Sep 09 10:13:26 PM UTC 24 |
| Finished | Sep 09 10:18:08 PM UTC 24 |
| Peak memory | 213960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261486416 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acc ess_b2b.1261486416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1232433372 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 73088884 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 10:14:10 PM UTC 24 |
| Finished | Sep 09 10:14:12 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232433372 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1232433372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.1877162159 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 13593136611 ps |
| CPU time | 532.85 seconds |
| Started | Sep 09 10:14:10 PM UTC 24 |
| Finished | Sep 09 10:23:09 PM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877162159 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1877162159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.2749734976 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 643167564 ps |
| CPU time | 98.72 seconds |
| Started | Sep 09 10:13:05 PM UTC 24 |
| Finished | Sep 09 10:14:46 PM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749734976 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2749734976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1221839982 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5771882284 ps |
| CPU time | 1034.28 seconds |
| Started | Sep 09 10:14:28 PM UTC 24 |
| Finished | Sep 09 10:31:54 PM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122183998 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.1221839982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1264957365 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 6610651088 ps |
| CPU time | 450.01 seconds |
| Started | Sep 09 10:14:26 PM UTC 24 |
| Finished | Sep 09 10:22:02 PM UTC 24 |
| Peak memory | 389104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264957365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1264957365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1167531042 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 36816032459 ps |
| CPU time | 342.33 seconds |
| Started | Sep 09 10:13:23 PM UTC 24 |
| Finished | Sep 09 10:19:10 PM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167531042 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1167531042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3562435597 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 158887793 ps |
| CPU time | 3.85 seconds |
| Started | Sep 09 10:13:47 PM UTC 24 |
| Finished | Sep 09 10:13:52 PM UTC 24 |
| Peak memory | 231160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3562435597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t hroughput_w_partial_write.3562435597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3038830289 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 558225044 ps |
| CPU time | 51.63 seconds |
| Started | Sep 09 10:15:31 PM UTC 24 |
| Finished | Sep 09 10:16:25 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038830289 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during _key_req.3038830289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1107416695 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 13581061 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 10:15:50 PM UTC 24 |
| Finished | Sep 09 10:15:52 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107416695 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1107416695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3585080222 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 12103427112 ps |
| CPU time | 58.93 seconds |
| Started | Sep 09 10:14:47 PM UTC 24 |
| Finished | Sep 09 10:15:48 PM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585080222 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.3585080222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.4078706829 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 7372930474 ps |
| CPU time | 317.99 seconds |
| Started | Sep 09 10:15:33 PM UTC 24 |
| Finished | Sep 09 10:20:55 PM UTC 24 |
| Peak memory | 370616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078706829 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.4078706829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.4276168050 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2086966849 ps |
| CPU time | 10.28 seconds |
| Started | Sep 09 10:15:30 PM UTC 24 |
| Finished | Sep 09 10:15:42 PM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276168050 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.4276168050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.964221763 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 77738063 ps |
| CPU time | 16.45 seconds |
| Started | Sep 09 10:15:13 PM UTC 24 |
| Finished | Sep 09 10:15:31 PM UTC 24 |
| Peak memory | 280424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 64221763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_max _throughput.964221763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3061174391 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 399106236 ps |
| CPU time | 7.6 seconds |
| Started | Sep 09 10:15:41 PM UTC 24 |
| Finished | Sep 09 10:15:50 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061174391 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.3061174391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2456782711 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 6540947218 ps |
| CPU time | 16.74 seconds |
| Started | Sep 09 10:15:40 PM UTC 24 |
| Finished | Sep 09 10:15:58 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456782711 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.2456782711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3439578778 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 5939618247 ps |
| CPU time | 39.87 seconds |
| Started | Sep 09 10:14:47 PM UTC 24 |
| Finished | Sep 09 10:15:29 PM UTC 24 |
| Peak memory | 213952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439578778 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.3439578778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.2110947288 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 962075155 ps |
| CPU time | 16.18 seconds |
| Started | Sep 09 10:14:55 PM UTC 24 |
| Finished | Sep 09 10:15:12 PM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110947288 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.2110947288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2345041098 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 18507423058 ps |
| CPU time | 309.47 seconds |
| Started | Sep 09 10:15:13 PM UTC 24 |
| Finished | Sep 09 10:20:27 PM UTC 24 |
| Peak memory | 213960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345041098 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc ess_b2b.2345041098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.1761888428 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 125368419 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 10:15:37 PM UTC 24 |
| Finished | Sep 09 10:15:39 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761888428 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1761888428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.255987593 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 14689568245 ps |
| CPU time | 965.87 seconds |
| Started | Sep 09 10:15:33 PM UTC 24 |
| Finished | Sep 09 10:31:49 PM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255987593 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.255987593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.4098967354 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 229082787 ps |
| CPU time | 16.19 seconds |
| Started | Sep 09 10:14:36 PM UTC 24 |
| Finished | Sep 09 10:14:54 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098967354 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.4098967354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3406168259 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 48622073289 ps |
| CPU time | 539.93 seconds |
| Started | Sep 09 10:15:49 PM UTC 24 |
| Finished | Sep 09 10:24:56 PM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340616825 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.3406168259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.966654362 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2305740586 ps |
| CPU time | 142.91 seconds |
| Started | Sep 09 10:15:43 PM UTC 24 |
| Finished | Sep 09 10:18:09 PM UTC 24 |
| Peak memory | 372720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966654362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.966654362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.709532240 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4057485080 ps |
| CPU time | 184.15 seconds |
| Started | Sep 09 10:14:53 PM UTC 24 |
| Finished | Sep 09 10:18:00 PM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709532240 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.709532240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1986744544 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 56014284 ps |
| CPU time | 5.59 seconds |
| Started | Sep 09 10:15:29 PM UTC 24 |
| Finished | Sep 09 10:15:36 PM UTC 24 |
| Peak memory | 241584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1986744544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t hroughput_w_partial_write.1986744544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2608954777 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 15112651365 ps |
| CPU time | 481.73 seconds |
| Started | Sep 09 10:16:35 PM UTC 24 |
| Finished | Sep 09 10:24:43 PM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608954777 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during _key_req.2608954777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3624111378 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 16074669 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 10:17:12 PM UTC 24 |
| Finished | Sep 09 10:17:14 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624111378 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3624111378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3896832821 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4725359719 ps |
| CPU time | 26.49 seconds |
| Started | Sep 09 10:15:59 PM UTC 24 |
| Finished | Sep 09 10:16:26 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896832821 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.3896832821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.2821555068 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 12872893554 ps |
| CPU time | 395.93 seconds |
| Started | Sep 09 10:16:36 PM UTC 24 |
| Finished | Sep 09 10:23:17 PM UTC 24 |
| Peak memory | 370612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821555068 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.2821555068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3430740508 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 283296960 ps |
| CPU time | 2.74 seconds |
| Started | Sep 09 10:16:31 PM UTC 24 |
| Finished | Sep 09 10:16:35 PM UTC 24 |
| Peak memory | 214076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430740508 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.3430740508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4205045334 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 517191884 ps |
| CPU time | 116.56 seconds |
| Started | Sep 09 10:16:27 PM UTC 24 |
| Finished | Sep 09 10:18:26 PM UTC 24 |
| Peak memory | 380780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 205045334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ma x_throughput.4205045334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1763208424 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 683079278 ps |
| CPU time | 6.22 seconds |
| Started | Sep 09 10:16:56 PM UTC 24 |
| Finished | Sep 09 10:17:03 PM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763208424 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.1763208424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1830001823 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 379320954 ps |
| CPU time | 7.96 seconds |
| Started | Sep 09 10:16:54 PM UTC 24 |
| Finished | Sep 09 10:17:03 PM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830001823 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.1830001823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1878813311 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 4140439393 ps |
| CPU time | 460.86 seconds |
| Started | Sep 09 10:15:53 PM UTC 24 |
| Finished | Sep 09 10:23:40 PM UTC 24 |
| Peak memory | 384816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878813311 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.1878813311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3464367745 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 140464749 ps |
| CPU time | 38.16 seconds |
| Started | Sep 09 10:16:14 PM UTC 24 |
| Finished | Sep 09 10:16:53 PM UTC 24 |
| Peak memory | 315328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464367745 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.3464367745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3391494028 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 4663423626 ps |
| CPU time | 345.89 seconds |
| Started | Sep 09 10:16:26 PM UTC 24 |
| Finished | Sep 09 10:22:17 PM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391494028 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc ess_b2b.3391494028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.3713514445 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 107383105 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 10:16:53 PM UTC 24 |
| Finished | Sep 09 10:16:55 PM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713514445 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3713514445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2263242000 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1570771412 ps |
| CPU time | 28.03 seconds |
| Started | Sep 09 10:16:42 PM UTC 24 |
| Finished | Sep 09 10:17:11 PM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263242000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2263242000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3320963967 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 944133754 ps |
| CPU time | 21.68 seconds |
| Started | Sep 09 10:15:50 PM UTC 24 |
| Finished | Sep 09 10:16:13 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320963967 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3320963967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.4015427557 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 67858964748 ps |
| CPU time | 2018.54 seconds |
| Started | Sep 09 10:17:04 PM UTC 24 |
| Finished | Sep 09 10:51:04 PM UTC 24 |
| Peak memory | 395356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401542755 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.4015427557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1428448754 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 523844873 ps |
| CPU time | 59.42 seconds |
| Started | Sep 09 10:17:04 PM UTC 24 |
| Finished | Sep 09 10:18:05 PM UTC 24 |
| Peak memory | 305008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428448754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1428448754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1454096682 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 38650550461 ps |
| CPU time | 308.86 seconds |
| Started | Sep 09 10:16:03 PM UTC 24 |
| Finished | Sep 09 10:21:16 PM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454096682 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.1454096682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3553001250 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 544915875 ps |
| CPU time | 74.27 seconds |
| Started | Sep 09 10:16:30 PM UTC 24 |
| Finished | Sep 09 10:17:46 PM UTC 24 |
| Peak memory | 354096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3553001250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t hroughput_w_partial_write.3553001250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1400945161 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 4136899571 ps |
| CPU time | 1118.03 seconds |
| Started | Sep 09 10:18:09 PM UTC 24 |
| Finished | Sep 09 10:37:00 PM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400945161 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during _key_req.1400945161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2612052289 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 26012617 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 10:18:49 PM UTC 24 |
| Finished | Sep 09 10:18:51 PM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612052289 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2612052289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1639107375 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2703547180 ps |
| CPU time | 70.11 seconds |
| Started | Sep 09 10:17:28 PM UTC 24 |
| Finished | Sep 09 10:18:40 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639107375 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1639107375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1203793411 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 12818707454 ps |
| CPU time | 1004.08 seconds |
| Started | Sep 09 10:18:25 PM UTC 24 |
| Finished | Sep 09 10:35:20 PM UTC 24 |
| Peak memory | 384956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203793411 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1203793411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2625643400 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 5438053740 ps |
| CPU time | 13.56 seconds |
| Started | Sep 09 10:18:09 PM UTC 24 |
| Finished | Sep 09 10:18:24 PM UTC 24 |
| Peak memory | 228592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625643400 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2625643400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.734813585 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 543703583 ps |
| CPU time | 91.13 seconds |
| Started | Sep 09 10:18:01 PM UTC 24 |
| Finished | Sep 09 10:19:35 PM UTC 24 |
| Peak memory | 381036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 34813585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max _throughput.734813585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2522105454 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 91348143 ps |
| CPU time | 6.24 seconds |
| Started | Sep 09 10:18:41 PM UTC 24 |
| Finished | Sep 09 10:18:48 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522105454 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2522105454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3448875890 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 466855561 ps |
| CPU time | 6.69 seconds |
| Started | Sep 09 10:18:36 PM UTC 24 |
| Finished | Sep 09 10:18:44 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448875890 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.3448875890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1825429657 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 8962542690 ps |
| CPU time | 158.68 seconds |
| Started | Sep 09 10:17:22 PM UTC 24 |
| Finished | Sep 09 10:20:04 PM UTC 24 |
| Peak memory | 315232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825429657 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.1825429657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.58996153 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 107272729 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 10:17:47 PM UTC 24 |
| Finished | Sep 09 10:17:49 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58996153 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.58996153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3674048597 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 82539233258 ps |
| CPU time | 533.33 seconds |
| Started | Sep 09 10:17:50 PM UTC 24 |
| Finished | Sep 09 10:26:50 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674048597 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc ess_b2b.3674048597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.826900573 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 28146377 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 10:18:33 PM UTC 24 |
| Finished | Sep 09 10:18:35 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826900573 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.826900573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.353715702 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 8736979821 ps |
| CPU time | 1369.67 seconds |
| Started | Sep 09 10:18:27 PM UTC 24 |
| Finished | Sep 09 10:41:31 PM UTC 24 |
| Peak memory | 387000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353715702 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.353715702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.569779026 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3633042164 ps |
| CPU time | 18.52 seconds |
| Started | Sep 09 10:17:15 PM UTC 24 |
| Finished | Sep 09 10:17:35 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569779026 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.569779026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3501297551 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 1709444534 ps |
| CPU time | 79.19 seconds |
| Started | Sep 09 10:18:46 PM UTC 24 |
| Finished | Sep 09 10:20:07 PM UTC 24 |
| Peak memory | 308924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350129755 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.3501297551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3272937204 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 13917808890 ps |
| CPU time | 870.04 seconds |
| Started | Sep 09 10:18:45 PM UTC 24 |
| Finished | Sep 09 10:33:25 PM UTC 24 |
| Peak memory | 393124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272937204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3272937204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1739102532 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 6103812173 ps |
| CPU time | 334.66 seconds |
| Started | Sep 09 10:17:36 PM UTC 24 |
| Finished | Sep 09 10:23:15 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739102532 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.1739102532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3499532581 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 179655083 ps |
| CPU time | 110.47 seconds |
| Started | Sep 09 10:18:06 PM UTC 24 |
| Finished | Sep 09 10:19:59 PM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3499532581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t hroughput_w_partial_write.3499532581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1873558233 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 16248364899 ps |
| CPU time | 687.13 seconds |
| Started | Sep 09 10:20:28 PM UTC 24 |
| Finished | Sep 09 10:32:03 PM UTC 24 |
| Peak memory | 380768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873558233 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during _key_req.1873558233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2932519812 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 14222300 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 10:21:17 PM UTC 24 |
| Finished | Sep 09 10:21:19 PM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932519812 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2932519812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2873990135 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3459470489 ps |
| CPU time | 35.36 seconds |
| Started | Sep 09 10:19:11 PM UTC 24 |
| Finished | Sep 09 10:19:47 PM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873990135 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2873990135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.609653942 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 12969710796 ps |
| CPU time | 968.22 seconds |
| Started | Sep 09 10:20:37 PM UTC 24 |
| Finished | Sep 09 10:36:56 PM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609653942 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.609653942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1686802988 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 722333824 ps |
| CPU time | 14.81 seconds |
| Started | Sep 09 10:20:21 PM UTC 24 |
| Finished | Sep 09 10:20:36 PM UTC 24 |
| Peak memory | 228136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686802988 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.1686802988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1402509826 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1278865681 ps |
| CPU time | 108.19 seconds |
| Started | Sep 09 10:20:04 PM UTC 24 |
| Finished | Sep 09 10:21:55 PM UTC 24 |
| Peak memory | 378740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 402509826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma x_throughput.1402509826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1838633904 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1130697389 ps |
| CPU time | 8.64 seconds |
| Started | Sep 09 10:21:00 PM UTC 24 |
| Finished | Sep 09 10:21:10 PM UTC 24 |
| Peak memory | 224344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838633904 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.1838633904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.813530312 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 141381832 ps |
| CPU time | 5.74 seconds |
| Started | Sep 09 10:20:59 PM UTC 24 |
| Finished | Sep 09 10:21:06 PM UTC 24 |
| Peak memory | 213784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813530312 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.813530312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2456461404 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 8521579679 ps |
| CPU time | 499.09 seconds |
| Started | Sep 09 10:19:09 PM UTC 24 |
| Finished | Sep 09 10:27:34 PM UTC 24 |
| Peak memory | 378800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456461404 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.2456461404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2005777907 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1737074210 ps |
| CPU time | 46.5 seconds |
| Started | Sep 09 10:19:48 PM UTC 24 |
| Finished | Sep 09 10:20:36 PM UTC 24 |
| Peak memory | 303224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005777907 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.2005777907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3590437443 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3751769510 ps |
| CPU time | 290.94 seconds |
| Started | Sep 09 10:20:00 PM UTC 24 |
| Finished | Sep 09 10:24:56 PM UTC 24 |
| Peak memory | 213832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590437443 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc ess_b2b.3590437443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4284312104 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 47481512 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 10:20:56 PM UTC 24 |
| Finished | Sep 09 10:20:58 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284312104 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4284312104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.4100026363 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 58419515395 ps |
| CPU time | 836.6 seconds |
| Started | Sep 09 10:20:38 PM UTC 24 |
| Finished | Sep 09 10:34:44 PM UTC 24 |
| Peak memory | 385272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100026363 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.4100026363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.2341390979 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 191971718 ps |
| CPU time | 13.74 seconds |
| Started | Sep 09 10:18:52 PM UTC 24 |
| Finished | Sep 09 10:19:07 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341390979 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2341390979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.391351432 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 86969597035 ps |
| CPU time | 4531.91 seconds |
| Started | Sep 09 10:21:11 PM UTC 24 |
| Finished | Sep 09 11:37:34 PM UTC 24 |
| Peak memory | 388660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391351432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.391351432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2794051669 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2719501974 ps |
| CPU time | 197.85 seconds |
| Started | Sep 09 10:21:06 PM UTC 24 |
| Finished | Sep 09 10:24:27 PM UTC 24 |
| Peak memory | 366696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794051669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.2794051669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.433048016 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 12738828165 ps |
| CPU time | 270.38 seconds |
| Started | Sep 09 10:19:36 PM UTC 24 |
| Finished | Sep 09 10:24:10 PM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433048016 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.433048016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1868918915 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 256318910 ps |
| CPU time | 9.99 seconds |
| Started | Sep 09 10:20:08 PM UTC 24 |
| Finished | Sep 09 10:20:19 PM UTC 24 |
| Peak memory | 257828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1868918915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t hroughput_w_partial_write.1868918915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.4146288596 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1724514754 ps |
| CPU time | 106.53 seconds |
| Started | Sep 09 09:11:53 PM UTC 24 |
| Finished | Sep 09 09:13:41 PM UTC 24 |
| Peak memory | 366432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146288596 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_ key_req.4146288596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.419036092 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 42105345 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:12:36 PM UTC 24 |
| Finished | Sep 09 09:12:38 PM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419036092 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.419036092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.1486887568 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 17164339543 ps |
| CPU time | 86.22 seconds |
| Started | Sep 09 09:11:27 PM UTC 24 |
| Finished | Sep 09 09:12:55 PM UTC 24 |
| Peak memory | 214208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486887568 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.1486887568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.4074005925 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 42599409146 ps |
| CPU time | 925.72 seconds |
| Started | Sep 09 09:11:55 PM UTC 24 |
| Finished | Sep 09 09:27:30 PM UTC 24 |
| Peak memory | 385204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074005925 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.4074005925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1059285046 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1552566068 ps |
| CPU time | 7.01 seconds |
| Started | Sep 09 09:11:43 PM UTC 24 |
| Finished | Sep 09 09:11:51 PM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059285046 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.1059285046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1523693010 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 247646052 ps |
| CPU time | 71.61 seconds |
| Started | Sep 09 09:11:36 PM UTC 24 |
| Finished | Sep 09 09:12:50 PM UTC 24 |
| Peak memory | 362348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 523693010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max _throughput.1523693010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2604970390 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 98910249 ps |
| CPU time | 4.83 seconds |
| Started | Sep 09 09:12:29 PM UTC 24 |
| Finished | Sep 09 09:12:35 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604970390 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.2604970390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1757834211 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 899406199 ps |
| CPU time | 9.22 seconds |
| Started | Sep 09 09:12:24 PM UTC 24 |
| Finished | Sep 09 09:12:34 PM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757834211 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.1757834211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.250760612 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 8772109785 ps |
| CPU time | 579.47 seconds |
| Started | Sep 09 09:11:26 PM UTC 24 |
| Finished | Sep 09 09:21:12 PM UTC 24 |
| Peak memory | 374576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250760612 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.250760612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2044062702 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1160835621 ps |
| CPU time | 23.73 seconds |
| Started | Sep 09 09:11:29 PM UTC 24 |
| Finished | Sep 09 09:11:54 PM UTC 24 |
| Peak memory | 213820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044062702 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.2044062702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1514488528 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 223107015944 ps |
| CPU time | 521.02 seconds |
| Started | Sep 09 09:11:30 PM UTC 24 |
| Finished | Sep 09 09:20:18 PM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514488528 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce ss_b2b.1514488528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1454686611 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 44650919 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:12:21 PM UTC 24 |
| Finished | Sep 09 09:12:23 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454686611 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1454686611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1556956999 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 104089218270 ps |
| CPU time | 1650.4 seconds |
| Started | Sep 09 09:12:04 PM UTC 24 |
| Finished | Sep 09 09:39:52 PM UTC 24 |
| Peak memory | 378732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556956999 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1556956999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3981941544 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 87637244 ps |
| CPU time | 2.48 seconds |
| Started | Sep 09 09:11:26 PM UTC 24 |
| Finished | Sep 09 09:11:29 PM UTC 24 |
| Peak memory | 213780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981941544 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3981941544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1999725843 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 9703291190 ps |
| CPU time | 116.75 seconds |
| Started | Sep 09 09:12:35 PM UTC 24 |
| Finished | Sep 09 09:14:34 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199972584 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.1999725843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2366680536 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10562107183 ps |
| CPU time | 168.72 seconds |
| Started | Sep 09 09:12:34 PM UTC 24 |
| Finished | Sep 09 09:15:26 PM UTC 24 |
| Peak memory | 329712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366680536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2366680536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.492496625 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 9516946915 ps |
| CPU time | 278.79 seconds |
| Started | Sep 09 09:11:29 PM UTC 24 |
| Finished | Sep 09 09:16:12 PM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492496625 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.492496625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1189573496 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 113911037 ps |
| CPU time | 38.45 seconds |
| Started | Sep 09 09:11:40 PM UTC 24 |
| Finished | Sep 09 09:12:20 PM UTC 24 |
| Peak memory | 300912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1189573496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th roughput_w_partial_write.1189573496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2688866998 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 20806990469 ps |
| CPU time | 848.01 seconds |
| Started | Sep 09 09:13:28 PM UTC 24 |
| Finished | Sep 09 09:27:46 PM UTC 24 |
| Peak memory | 380964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688866998 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_ key_req.2688866998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2154648964 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 21752938 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:13:54 PM UTC 24 |
| Finished | Sep 09 09:13:56 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154648964 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.2154648964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.3135491504 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 6059567152 ps |
| CPU time | 35.22 seconds |
| Started | Sep 09 09:12:51 PM UTC 24 |
| Finished | Sep 09 09:13:27 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135491504 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.3135491504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.1991223220 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1577230069 ps |
| CPU time | 791.45 seconds |
| Started | Sep 09 09:13:34 PM UTC 24 |
| Finished | Sep 09 09:26:56 PM UTC 24 |
| Peak memory | 384888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991223220 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.1991223220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1674122976 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 696630591 ps |
| CPU time | 11.72 seconds |
| Started | Sep 09 09:13:26 PM UTC 24 |
| Finished | Sep 09 09:13:39 PM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674122976 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.1674122976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1208757771 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 135835310 ps |
| CPU time | 76.66 seconds |
| Started | Sep 09 09:13:00 PM UTC 24 |
| Finished | Sep 09 09:14:18 PM UTC 24 |
| Peak memory | 381032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 208757771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max _throughput.1208757771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3892754558 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 765742589 ps |
| CPU time | 8.53 seconds |
| Started | Sep 09 09:13:44 PM UTC 24 |
| Finished | Sep 09 09:13:53 PM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892754558 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.3892754558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1551208010 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 261575179 ps |
| CPU time | 10.55 seconds |
| Started | Sep 09 09:13:41 PM UTC 24 |
| Finished | Sep 09 09:13:53 PM UTC 24 |
| Peak memory | 224388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551208010 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.1551208010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1894929295 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 6651049030 ps |
| CPU time | 353.1 seconds |
| Started | Sep 09 09:12:42 PM UTC 24 |
| Finished | Sep 09 09:18:41 PM UTC 24 |
| Peak memory | 376832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894929295 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.1894929295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1136073962 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4726653680 ps |
| CPU time | 28.06 seconds |
| Started | Sep 09 09:12:56 PM UTC 24 |
| Finished | Sep 09 09:13:25 PM UTC 24 |
| Peak memory | 214136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136073962 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1136073962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.859392777 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 18832295413 ps |
| CPU time | 567.61 seconds |
| Started | Sep 09 09:12:59 PM UTC 24 |
| Finished | Sep 09 09:22:34 PM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859392777 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acces s_b2b.859392777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1621729615 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 29092043 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 09:13:40 PM UTC 24 |
| Finished | Sep 09 09:13:43 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621729615 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1621729615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3235179266 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 984249873 ps |
| CPU time | 18.78 seconds |
| Started | Sep 09 09:12:39 PM UTC 24 |
| Finished | Sep 09 09:12:59 PM UTC 24 |
| Peak memory | 213760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235179266 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3235179266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1336085888 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 42003427184 ps |
| CPU time | 3572.14 seconds |
| Started | Sep 09 09:13:54 PM UTC 24 |
| Finished | Sep 09 10:14:04 PM UTC 24 |
| Peak memory | 388664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133608588 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.1336085888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1616014695 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 245770190 ps |
| CPU time | 124.51 seconds |
| Started | Sep 09 09:13:51 PM UTC 24 |
| Finished | Sep 09 09:15:58 PM UTC 24 |
| Peak memory | 374704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616014695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1616014695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1114705842 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 6437123277 ps |
| CPU time | 167.2 seconds |
| Started | Sep 09 09:12:55 PM UTC 24 |
| Finished | Sep 09 09:15:45 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114705842 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1114705842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3600756137 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 483348723 ps |
| CPU time | 70.97 seconds |
| Started | Sep 09 09:13:21 PM UTC 24 |
| Finished | Sep 09 09:14:34 PM UTC 24 |
| Peak memory | 354088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3600756137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th roughput_w_partial_write.3600756137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3448221775 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2079928419 ps |
| CPU time | 443.7 seconds |
| Started | Sep 09 09:14:54 PM UTC 24 |
| Finished | Sep 09 09:22:23 PM UTC 24 |
| Peak memory | 382824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448221775 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_ key_req.3448221775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.300616777 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 38730315 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 09:15:54 PM UTC 24 |
| Finished | Sep 09 09:15:55 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300616777 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.300616777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.185938757 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1619802208 ps |
| CPU time | 46.97 seconds |
| Started | Sep 09 09:14:13 PM UTC 24 |
| Finished | Sep 09 09:15:02 PM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185938757 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.185938757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2888435516 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 10272876576 ps |
| CPU time | 1013.43 seconds |
| Started | Sep 09 09:15:03 PM UTC 24 |
| Finished | Sep 09 09:32:08 PM UTC 24 |
| Peak memory | 382900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888435516 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2888435516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.24540069 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 403635339 ps |
| CPU time | 2.91 seconds |
| Started | Sep 09 09:14:49 PM UTC 24 |
| Finished | Sep 09 09:14:53 PM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24540069 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.24540069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.4248490663 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 185008326 ps |
| CPU time | 6.02 seconds |
| Started | Sep 09 09:14:40 PM UTC 24 |
| Finished | Sep 09 09:14:48 PM UTC 24 |
| Peak memory | 235620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 248490663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max _throughput.4248490663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.4253218211 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 174625845 ps |
| CPU time | 7.2 seconds |
| Started | Sep 09 09:15:43 PM UTC 24 |
| Finished | Sep 09 09:15:51 PM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253218211 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.4253218211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2450176771 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 516383255 ps |
| CPU time | 8.32 seconds |
| Started | Sep 09 09:15:33 PM UTC 24 |
| Finished | Sep 09 09:15:43 PM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450176771 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.2450176771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1664487000 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 64638119281 ps |
| CPU time | 273.66 seconds |
| Started | Sep 09 09:14:05 PM UTC 24 |
| Finished | Sep 09 09:18:43 PM UTC 24 |
| Peak memory | 368572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664487000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.1664487000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.302515045 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 51533377 ps |
| CPU time | 3.54 seconds |
| Started | Sep 09 09:14:35 PM UTC 24 |
| Finished | Sep 09 09:14:40 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302515045 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.302515045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.451580525 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 60640191851 ps |
| CPU time | 485.99 seconds |
| Started | Sep 09 09:14:35 PM UTC 24 |
| Finished | Sep 09 09:22:48 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451580525 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acces s_b2b.451580525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3998981451 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 28305599 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 09:15:30 PM UTC 24 |
| Finished | Sep 09 09:15:32 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998981451 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3998981451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.921728178 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 51401232587 ps |
| CPU time | 719.63 seconds |
| Started | Sep 09 09:15:27 PM UTC 24 |
| Finished | Sep 09 09:27:35 PM UTC 24 |
| Peak memory | 387260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921728178 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.921728178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.1382965388 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3918563976 ps |
| CPU time | 14.17 seconds |
| Started | Sep 09 09:13:57 PM UTC 24 |
| Finished | Sep 09 09:14:12 PM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382965388 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1382965388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3638840873 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 38734493551 ps |
| CPU time | 1679.61 seconds |
| Started | Sep 09 09:15:52 PM UTC 24 |
| Finished | Sep 09 09:44:09 PM UTC 24 |
| Peak memory | 386984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363884087 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.3638840873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.645329847 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1300353236 ps |
| CPU time | 225.41 seconds |
| Started | Sep 09 09:15:45 PM UTC 24 |
| Finished | Sep 09 09:19:34 PM UTC 24 |
| Peak memory | 370532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645329847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.645329847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1342887638 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2185526486 ps |
| CPU time | 281.57 seconds |
| Started | Sep 09 09:14:19 PM UTC 24 |
| Finished | Sep 09 09:19:05 PM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342887638 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.1342887638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.60779966 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 110063896 ps |
| CPU time | 42.17 seconds |
| Started | Sep 09 09:14:46 PM UTC 24 |
| Finished | Sep 09 09:15:29 PM UTC 24 |
| Peak memory | 313196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 60779966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_thro ughput_w_partial_write.60779966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3793766325 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 43376740151 ps |
| CPU time | 762.29 seconds |
| Started | Sep 09 09:16:30 PM UTC 24 |
| Finished | Sep 09 09:29:21 PM UTC 24 |
| Peak memory | 385192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793766325 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_ key_req.3793766325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.314547012 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 22241145 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:16:55 PM UTC 24 |
| Finished | Sep 09 09:16:57 PM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314547012 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.314547012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.4268061715 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 6678250335 ps |
| CPU time | 46.39 seconds |
| Started | Sep 09 09:15:58 PM UTC 24 |
| Finished | Sep 09 09:16:46 PM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268061715 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.4268061715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1175961175 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2452279676 ps |
| CPU time | 7.99 seconds |
| Started | Sep 09 09:16:35 PM UTC 24 |
| Finished | Sep 09 09:16:44 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175961175 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1175961175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4251137596 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 824937486 ps |
| CPU time | 10.85 seconds |
| Started | Sep 09 09:16:21 PM UTC 24 |
| Finished | Sep 09 09:16:34 PM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251137596 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.4251137596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2600746777 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 194879052 ps |
| CPU time | 6.11 seconds |
| Started | Sep 09 09:16:13 PM UTC 24 |
| Finished | Sep 09 09:16:20 PM UTC 24 |
| Peak memory | 235624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 600746777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max _throughput.2600746777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.494025594 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 161158950 ps |
| CPU time | 3.3 seconds |
| Started | Sep 09 09:16:47 PM UTC 24 |
| Finished | Sep 09 09:16:51 PM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494025594 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.494025594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3993857617 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 277995916 ps |
| CPU time | 12.16 seconds |
| Started | Sep 09 09:16:46 PM UTC 24 |
| Finished | Sep 09 09:16:59 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993857617 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3993857617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.4132283460 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 34358197607 ps |
| CPU time | 1931.46 seconds |
| Started | Sep 09 09:15:56 PM UTC 24 |
| Finished | Sep 09 09:48:29 PM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132283460 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.4132283460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.118898088 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 86504160 ps |
| CPU time | 2.68 seconds |
| Started | Sep 09 09:16:11 PM UTC 24 |
| Finished | Sep 09 09:16:15 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118898088 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.118898088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2164985865 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 8983375574 ps |
| CPU time | 385.08 seconds |
| Started | Sep 09 09:16:12 PM UTC 24 |
| Finished | Sep 09 09:22:42 PM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164985865 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce ss_b2b.2164985865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3040587805 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 28371305 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:16:45 PM UTC 24 |
| Finished | Sep 09 09:16:47 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040587805 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3040587805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1238104586 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 6141750922 ps |
| CPU time | 482.05 seconds |
| Started | Sep 09 09:16:41 PM UTC 24 |
| Finished | Sep 09 09:24:49 PM UTC 24 |
| Peak memory | 382904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238104586 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1238104586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.320247600 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 23012495 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:15:55 PM UTC 24 |
| Finished | Sep 09 09:15:57 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320247600 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.320247600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1857400860 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 78545525403 ps |
| CPU time | 4814.73 seconds |
| Started | Sep 09 09:16:52 PM UTC 24 |
| Finished | Sep 09 10:37:53 PM UTC 24 |
| Peak memory | 388792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185740086 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.1857400860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3138655241 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8633400809 ps |
| CPU time | 133.49 seconds |
| Started | Sep 09 09:16:48 PM UTC 24 |
| Finished | Sep 09 09:19:04 PM UTC 24 |
| Peak memory | 315320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138655241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3138655241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3696431993 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3943388946 ps |
| CPU time | 205.8 seconds |
| Started | Sep 09 09:15:59 PM UTC 24 |
| Finished | Sep 09 09:19:28 PM UTC 24 |
| Peak memory | 213944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696431993 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.3696431993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3506164052 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 480332347 ps |
| CPU time | 43.34 seconds |
| Started | Sep 09 09:16:15 PM UTC 24 |
| Finished | Sep 09 09:17:00 PM UTC 24 |
| Peak memory | 333864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3506164052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th roughput_w_partial_write.3506164052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.573784911 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 26276156018 ps |
| CPU time | 1337.99 seconds |
| Started | Sep 09 09:18:21 PM UTC 24 |
| Finished | Sep 09 09:40:54 PM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573784911 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_k ey_req.573784911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3993865637 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 14268015 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:18:59 PM UTC 24 |
| Finished | Sep 09 09:19:01 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993865637 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.3993865637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.77053247 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3543629373 ps |
| CPU time | 74.32 seconds |
| Started | Sep 09 09:17:00 PM UTC 24 |
| Finished | Sep 09 09:18:16 PM UTC 24 |
| Peak memory | 214132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77053247 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.77053247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1959803228 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4743610195 ps |
| CPU time | 203.64 seconds |
| Started | Sep 09 09:18:21 PM UTC 24 |
| Finished | Sep 09 09:21:48 PM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959803228 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.1959803228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1805623759 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 120464075 ps |
| CPU time | 2.13 seconds |
| Started | Sep 09 09:18:17 PM UTC 24 |
| Finished | Sep 09 09:18:20 PM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805623759 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.1805623759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3462537617 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 275672320 ps |
| CPU time | 28.47 seconds |
| Started | Sep 09 09:17:56 PM UTC 24 |
| Finished | Sep 09 09:18:26 PM UTC 24 |
| Peak memory | 297060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 462537617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max _throughput.3462537617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.625949867 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 850141129 ps |
| CPU time | 8.1 seconds |
| Started | Sep 09 09:18:48 PM UTC 24 |
| Finished | Sep 09 09:18:57 PM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625949867 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.625949867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2854098147 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 709842757 ps |
| CPU time | 8.55 seconds |
| Started | Sep 09 09:18:47 PM UTC 24 |
| Finished | Sep 09 09:18:57 PM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854098147 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.2854098147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1312980658 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5650114974 ps |
| CPU time | 373.93 seconds |
| Started | Sep 09 09:17:00 PM UTC 24 |
| Finished | Sep 09 09:23:19 PM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312980658 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.1312980658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3480593497 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1043290798 ps |
| CPU time | 9.32 seconds |
| Started | Sep 09 09:17:12 PM UTC 24 |
| Finished | Sep 09 09:17:22 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480593497 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.3480593497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3197091029 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5102563956 ps |
| CPU time | 380.64 seconds |
| Started | Sep 09 09:17:23 PM UTC 24 |
| Finished | Sep 09 09:23:48 PM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197091029 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acce ss_b2b.3197091029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3258516257 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 33614558 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 09:18:47 PM UTC 24 |
| Finished | Sep 09 09:18:49 PM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258516257 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3258516257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4108952521 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 52376710232 ps |
| CPU time | 684.61 seconds |
| Started | Sep 09 09:18:26 PM UTC 24 |
| Finished | Sep 09 09:29:59 PM UTC 24 |
| Peak memory | 384952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108952521 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.4108952521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.4078398459 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 794072499 ps |
| CPU time | 11.71 seconds |
| Started | Sep 09 09:16:58 PM UTC 24 |
| Finished | Sep 09 09:17:11 PM UTC 24 |
| Peak memory | 245496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078398459 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.4078398459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.993601732 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 32450467109 ps |
| CPU time | 396.17 seconds |
| Started | Sep 09 09:18:54 PM UTC 24 |
| Finished | Sep 09 09:25:35 PM UTC 24 |
| Peak memory | 362424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993601732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.993601732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.261414614 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3184704450 ps |
| CPU time | 319.13 seconds |
| Started | Sep 09 09:17:03 PM UTC 24 |
| Finished | Sep 09 09:22:27 PM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261414614 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.261414614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3873073081 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 931287779 ps |
| CPU time | 104.6 seconds |
| Started | Sep 09 09:18:07 PM UTC 24 |
| Finished | Sep 09 09:19:54 PM UTC 24 |
| Peak memory | 380780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3873073081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th roughput_w_partial_write.3873073081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
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