| T556 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3780905918 |
|
|
Sep 09 09:52:00 PM UTC 24 |
Sep 09 09:52:04 PM UTC 24 |
346937275 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.4162689660 |
|
|
Sep 09 09:51:43 PM UTC 24 |
Sep 09 09:52:10 PM UTC 24 |
2021755959 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.274324790 |
|
|
Sep 09 09:51:23 PM UTC 24 |
Sep 09 09:52:24 PM UTC 24 |
1428337832 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.2322124812 |
|
|
Sep 09 09:48:47 PM UTC 24 |
Sep 09 09:52:33 PM UTC 24 |
843026931 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.375749268 |
|
|
Sep 09 09:52:33 PM UTC 24 |
Sep 09 09:52:36 PM UTC 24 |
53555661 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3888699475 |
|
|
Sep 09 09:51:31 PM UTC 24 |
Sep 09 09:52:49 PM UTC 24 |
2892189853 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.3408891406 |
|
|
Sep 09 09:52:38 PM UTC 24 |
Sep 09 09:52:49 PM UTC 24 |
564173859 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3545375178 |
|
|
Sep 09 09:52:50 PM UTC 24 |
Sep 09 09:52:55 PM UTC 24 |
240043786 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2210868602 |
|
|
Sep 09 09:36:49 PM UTC 24 |
Sep 09 09:53:05 PM UTC 24 |
9295321934 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3015658138 |
|
|
Sep 09 09:53:06 PM UTC 24 |
Sep 09 09:53:08 PM UTC 24 |
37233139 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1026794865 |
|
|
Sep 09 09:29:23 PM UTC 24 |
Sep 09 09:53:12 PM UTC 24 |
25830102865 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.383776964 |
|
|
Sep 09 09:45:46 PM UTC 24 |
Sep 09 09:53:20 PM UTC 24 |
10329035055 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.907898651 |
|
|
Sep 09 09:52:52 PM UTC 24 |
Sep 09 09:53:52 PM UTC 24 |
10397671595 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.2405904925 |
|
|
Sep 09 09:53:13 PM UTC 24 |
Sep 09 09:54:01 PM UTC 24 |
6177120813 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2807599680 |
|
|
Sep 09 09:37:20 PM UTC 24 |
Sep 09 09:54:06 PM UTC 24 |
42923413691 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1832548102 |
|
|
Sep 09 09:53:53 PM UTC 24 |
Sep 09 09:54:16 PM UTC 24 |
877703703 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.148326823 |
|
|
Sep 09 09:49:23 PM UTC 24 |
Sep 09 09:54:17 PM UTC 24 |
1119969990 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3928335491 |
|
|
Sep 09 09:54:17 PM UTC 24 |
Sep 09 09:54:27 PM UTC 24 |
11228851012 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3134745577 |
|
|
Sep 09 09:44:37 PM UTC 24 |
Sep 09 09:54:34 PM UTC 24 |
9117329707 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.990864239 |
|
|
Sep 09 09:48:29 PM UTC 24 |
Sep 09 09:54:34 PM UTC 24 |
53850994618 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.409501213 |
|
|
Sep 09 09:26:44 PM UTC 24 |
Sep 09 09:54:46 PM UTC 24 |
7872317835 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.178033601 |
|
|
Sep 09 09:54:47 PM UTC 24 |
Sep 09 09:54:49 PM UTC 24 |
58354495 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.3940776752 |
|
|
Sep 09 09:53:06 PM UTC 24 |
Sep 09 09:54:50 PM UTC 24 |
556328938 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.885867389 |
|
|
Sep 09 09:46:27 PM UTC 24 |
Sep 09 09:54:51 PM UTC 24 |
21138679821 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2571779936 |
|
|
Sep 09 09:49:38 PM UTC 24 |
Sep 09 09:54:51 PM UTC 24 |
19526122044 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3256877809 |
|
|
Sep 09 09:54:16 PM UTC 24 |
Sep 09 09:54:52 PM UTC 24 |
99759381 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4133522399 |
|
|
Sep 09 09:54:52 PM UTC 24 |
Sep 09 09:54:55 PM UTC 24 |
14219493 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.4270607617 |
|
|
Sep 09 09:34:52 PM UTC 24 |
Sep 09 09:54:55 PM UTC 24 |
15167226265 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2837114071 |
|
|
Sep 09 09:54:51 PM UTC 24 |
Sep 09 09:54:59 PM UTC 24 |
356274076 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.732561552 |
|
|
Sep 09 09:30:38 PM UTC 24 |
Sep 09 09:55:02 PM UTC 24 |
167213148005 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1987671825 |
|
|
Sep 09 09:54:50 PM UTC 24 |
Sep 09 09:55:03 PM UTC 24 |
1229824828 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3272387274 |
|
|
Sep 09 09:55:04 PM UTC 24 |
Sep 09 09:55:09 PM UTC 24 |
115251694 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1437369582 |
|
|
Sep 09 09:51:35 PM UTC 24 |
Sep 09 09:55:12 PM UTC 24 |
2105072933 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.636217601 |
|
|
Sep 09 09:55:00 PM UTC 24 |
Sep 09 09:55:21 PM UTC 24 |
879309796 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1812621137 |
|
|
Sep 09 09:55:22 PM UTC 24 |
Sep 09 09:55:31 PM UTC 24 |
1675795778 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3170375959 |
|
|
Sep 09 09:51:46 PM UTC 24 |
Sep 09 09:55:32 PM UTC 24 |
29432325420 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.575721753 |
|
|
Sep 09 09:48:28 PM UTC 24 |
Sep 09 09:56:09 PM UTC 24 |
4630435576 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3228956014 |
|
|
Sep 09 09:54:06 PM UTC 24 |
Sep 09 09:56:09 PM UTC 24 |
136870188 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.1775079158 |
|
|
Sep 09 09:56:10 PM UTC 24 |
Sep 09 09:56:12 PM UTC 24 |
83430156 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1654344804 |
|
|
Sep 09 09:50:15 PM UTC 24 |
Sep 09 09:56:18 PM UTC 24 |
3376551888 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3221042441 |
|
|
Sep 09 09:56:13 PM UTC 24 |
Sep 09 09:56:22 PM UTC 24 |
228372268 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2765349320 |
|
|
Sep 09 09:56:18 PM UTC 24 |
Sep 09 09:56:23 PM UTC 24 |
64554760 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2078252135 |
|
|
Sep 09 09:55:13 PM UTC 24 |
Sep 09 09:56:27 PM UTC 24 |
110135346 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1214723309 |
|
|
Sep 09 09:56:28 PM UTC 24 |
Sep 09 09:56:30 PM UTC 24 |
45430526 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.617559435 |
|
|
Sep 09 09:54:35 PM UTC 24 |
Sep 09 09:57:14 PM UTC 24 |
3894025937 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2530587229 |
|
|
Sep 09 09:39:00 PM UTC 24 |
Sep 09 09:57:19 PM UTC 24 |
32808440327 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2208445407 |
|
|
Sep 09 09:55:15 PM UTC 24 |
Sep 09 09:57:24 PM UTC 24 |
305189125 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3311624279 |
|
|
Sep 09 09:53:21 PM UTC 24 |
Sep 09 09:57:27 PM UTC 24 |
2103379659 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3138505096 |
|
|
Sep 09 09:35:04 PM UTC 24 |
Sep 09 09:57:30 PM UTC 24 |
12772740027 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.718736490 |
|
|
Sep 09 09:56:31 PM UTC 24 |
Sep 09 09:57:30 PM UTC 24 |
449704409 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.878699610 |
|
|
Sep 09 09:50:31 PM UTC 24 |
Sep 09 09:57:43 PM UTC 24 |
142045860365 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.4112026991 |
|
|
Sep 09 09:57:28 PM UTC 24 |
Sep 09 09:57:48 PM UTC 24 |
3019930674 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.411313311 |
|
|
Sep 09 09:57:49 PM UTC 24 |
Sep 09 09:57:52 PM UTC 24 |
54851220 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2058542405 |
|
|
Sep 09 09:36:51 PM UTC 24 |
Sep 09 09:57:59 PM UTC 24 |
12762920112 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2200547361 |
|
|
Sep 09 09:54:52 PM UTC 24 |
Sep 09 09:58:03 PM UTC 24 |
2832576423 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.3600587933 |
|
|
Sep 09 09:33:15 PM UTC 24 |
Sep 09 09:58:04 PM UTC 24 |
20923872881 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1744243108 |
|
|
Sep 09 09:58:05 PM UTC 24 |
Sep 09 09:58:07 PM UTC 24 |
44007561 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.534313306 |
|
|
Sep 09 09:58:08 PM UTC 24 |
Sep 09 09:58:17 PM UTC 24 |
243550936 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3784232903 |
|
|
Sep 09 09:32:05 PM UTC 24 |
Sep 09 09:58:22 PM UTC 24 |
31517172358 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4208028836 |
|
|
Sep 09 09:58:18 PM UTC 24 |
Sep 09 09:58:23 PM UTC 24 |
244471491 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1853655059 |
|
|
Sep 09 09:57:20 PM UTC 24 |
Sep 09 09:58:35 PM UTC 24 |
1072206732 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3041450529 |
|
|
Sep 09 09:51:04 PM UTC 24 |
Sep 09 09:58:36 PM UTC 24 |
93993001314 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3382442869 |
|
|
Sep 09 09:57:43 PM UTC 24 |
Sep 09 09:58:36 PM UTC 24 |
399174034 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3114775733 |
|
|
Sep 09 09:58:35 PM UTC 24 |
Sep 09 09:58:37 PM UTC 24 |
13619897 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.667294772 |
|
|
Sep 09 09:41:12 PM UTC 24 |
Sep 09 09:58:38 PM UTC 24 |
4041736482 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.2610089752 |
|
|
Sep 09 09:58:37 PM UTC 24 |
Sep 09 09:58:45 PM UTC 24 |
125636319 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.4148079790 |
|
|
Sep 09 09:57:31 PM UTC 24 |
Sep 09 09:58:46 PM UTC 24 |
126133857 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1359680248 |
|
|
Sep 09 09:52:05 PM UTC 24 |
Sep 09 09:58:54 PM UTC 24 |
3002771458 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.4190732053 |
|
|
Sep 09 09:58:55 PM UTC 24 |
Sep 09 09:58:59 PM UTC 24 |
142976265 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3537918213 |
|
|
Sep 09 09:58:46 PM UTC 24 |
Sep 09 09:59:00 PM UTC 24 |
2133913166 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2971045724 |
|
|
Sep 09 09:59:01 PM UTC 24 |
Sep 09 09:59:10 PM UTC 24 |
1551232051 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.654941677 |
|
|
Sep 09 09:58:39 PM UTC 24 |
Sep 09 09:59:43 PM UTC 24 |
17790253686 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.718442799 |
|
|
Sep 09 09:54:36 PM UTC 24 |
Sep 09 09:59:52 PM UTC 24 |
4000814001 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3131626278 |
|
|
Sep 09 09:48:11 PM UTC 24 |
Sep 09 09:59:52 PM UTC 24 |
2354824883 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.420987371 |
|
|
Sep 09 09:59:54 PM UTC 24 |
Sep 09 09:59:56 PM UTC 24 |
31350607 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.2754837881 |
|
|
Sep 09 09:58:59 PM UTC 24 |
Sep 09 10:00:00 PM UTC 24 |
122960427 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3075608904 |
|
|
Sep 09 09:44:34 PM UTC 24 |
Sep 09 10:00:02 PM UTC 24 |
3313245658 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3705131799 |
|
|
Sep 09 09:59:57 PM UTC 24 |
Sep 09 10:00:04 PM UTC 24 |
73779055 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.794136120 |
|
|
Sep 09 10:00:01 PM UTC 24 |
Sep 09 10:00:14 PM UTC 24 |
176873603 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1062694171 |
|
|
Sep 09 09:46:49 PM UTC 24 |
Sep 09 10:00:16 PM UTC 24 |
8057423695 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1870677901 |
|
|
Sep 09 10:00:15 PM UTC 24 |
Sep 09 10:00:17 PM UTC 24 |
19876904 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2272267985 |
|
|
Sep 09 09:53:09 PM UTC 24 |
Sep 09 10:00:19 PM UTC 24 |
8907335163 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2486699420 |
|
|
Sep 09 10:00:17 PM UTC 24 |
Sep 09 10:00:36 PM UTC 24 |
2662082463 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.399695443 |
|
|
Sep 09 09:49:10 PM UTC 24 |
Sep 09 10:00:42 PM UTC 24 |
12805569472 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3776163367 |
|
|
Sep 09 09:38:40 PM UTC 24 |
Sep 09 10:00:43 PM UTC 24 |
3343333451 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.1584466305 |
|
|
Sep 09 10:00:21 PM UTC 24 |
Sep 09 10:01:23 PM UTC 24 |
12715139767 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2322728310 |
|
|
Sep 09 09:57:31 PM UTC 24 |
Sep 09 10:01:39 PM UTC 24 |
15600422730 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2965906509 |
|
|
Sep 09 09:10:48 PM UTC 24 |
Sep 09 10:01:45 PM UTC 24 |
11045822714 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1043672333 |
|
|
Sep 09 09:56:22 PM UTC 24 |
Sep 09 10:01:50 PM UTC 24 |
1311624381 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3821115819 |
|
|
Sep 09 10:01:47 PM UTC 24 |
Sep 09 10:01:55 PM UTC 24 |
1449104467 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.520419535 |
|
|
Sep 09 09:45:40 PM UTC 24 |
Sep 09 10:01:58 PM UTC 24 |
3044143621 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.434835106 |
|
|
Sep 09 09:50:59 PM UTC 24 |
Sep 09 10:01:58 PM UTC 24 |
3004048908 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3369861007 |
|
|
Sep 09 10:01:59 PM UTC 24 |
Sep 09 10:02:01 PM UTC 24 |
25743291 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2709059962 |
|
|
Sep 09 09:55:03 PM UTC 24 |
Sep 09 10:02:03 PM UTC 24 |
7095506996 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.1409263495 |
|
|
Sep 09 10:01:39 PM UTC 24 |
Sep 09 10:02:10 PM UTC 24 |
1471670040 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2054313326 |
|
|
Sep 09 10:02:03 PM UTC 24 |
Sep 09 10:02:11 PM UTC 24 |
270427284 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2832191205 |
|
|
Sep 09 09:25:01 PM UTC 24 |
Sep 09 10:02:12 PM UTC 24 |
41730886139 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1215097939 |
|
|
Sep 09 10:02:14 PM UTC 24 |
Sep 09 10:02:16 PM UTC 24 |
12436251 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.626235253 |
|
|
Sep 09 10:00:43 PM UTC 24 |
Sep 09 10:02:17 PM UTC 24 |
1233916176 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2525060211 |
|
|
Sep 09 09:55:33 PM UTC 24 |
Sep 09 10:02:18 PM UTC 24 |
9987705998 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1441629238 |
|
|
Sep 09 10:02:02 PM UTC 24 |
Sep 09 10:02:19 PM UTC 24 |
2711471061 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.671712182 |
|
|
Sep 09 10:02:17 PM UTC 24 |
Sep 09 10:02:22 PM UTC 24 |
162503336 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1022864160 |
|
|
Sep 09 09:44:57 PM UTC 24 |
Sep 09 10:02:41 PM UTC 24 |
4446273085 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.886750404 |
|
|
Sep 09 10:00:06 PM UTC 24 |
Sep 09 10:02:52 PM UTC 24 |
1051367658 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1353567774 |
|
|
Sep 09 09:55:10 PM UTC 24 |
Sep 09 10:02:59 PM UTC 24 |
16573357646 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2739523876 |
|
|
Sep 09 10:02:19 PM UTC 24 |
Sep 09 10:03:04 PM UTC 24 |
2486543486 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.304774957 |
|
|
Sep 09 10:01:24 PM UTC 24 |
Sep 09 10:03:07 PM UTC 24 |
150600925 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.440476951 |
|
|
Sep 09 10:02:53 PM UTC 24 |
Sep 09 10:03:13 PM UTC 24 |
353046335 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1830905414 |
|
|
Sep 09 10:03:05 PM UTC 24 |
Sep 09 10:03:13 PM UTC 24 |
5313657441 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.358119673 |
|
|
Sep 09 09:57:25 PM UTC 24 |
Sep 09 10:03:15 PM UTC 24 |
5435296547 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2880415904 |
|
|
Sep 09 10:03:16 PM UTC 24 |
Sep 09 10:03:18 PM UTC 24 |
76867971 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1059062283 |
|
|
Sep 09 10:02:59 PM UTC 24 |
Sep 09 10:03:20 PM UTC 24 |
190972035 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3424748792 |
|
|
Sep 09 10:03:21 PM UTC 24 |
Sep 09 10:03:26 PM UTC 24 |
95732904 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2278290942 |
|
|
Sep 09 10:03:19 PM UTC 24 |
Sep 09 10:03:29 PM UTC 24 |
239150642 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3084895482 |
|
|
Sep 09 10:02:23 PM UTC 24 |
Sep 09 10:03:42 PM UTC 24 |
324533725 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3452974924 |
|
|
Sep 09 10:03:43 PM UTC 24 |
Sep 09 10:03:45 PM UTC 24 |
13217257 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.4195052790 |
|
|
Sep 09 09:46:55 PM UTC 24 |
Sep 09 10:03:57 PM UTC 24 |
46576768041 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.292996375 |
|
|
Sep 09 10:03:46 PM UTC 24 |
Sep 09 10:04:00 PM UTC 24 |
4236233375 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.65011831 |
|
|
Sep 09 09:58:39 PM UTC 24 |
Sep 09 10:04:10 PM UTC 24 |
14407601826 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2341283379 |
|
|
Sep 09 09:54:56 PM UTC 24 |
Sep 09 10:04:20 PM UTC 24 |
12223459883 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1859805241 |
|
|
Sep 09 09:58:47 PM UTC 24 |
Sep 09 10:04:30 PM UTC 24 |
4730525648 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3164219447 |
|
|
Sep 09 09:54:02 PM UTC 24 |
Sep 09 10:04:30 PM UTC 24 |
24355841803 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2792460650 |
|
|
Sep 09 10:04:01 PM UTC 24 |
Sep 09 10:04:31 PM UTC 24 |
1736452887 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1638146764 |
|
|
Sep 09 10:04:20 PM UTC 24 |
Sep 09 10:04:33 PM UTC 24 |
484541891 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.750098734 |
|
|
Sep 09 10:04:30 PM UTC 24 |
Sep 09 10:04:36 PM UTC 24 |
185954457 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.957547942 |
|
|
Sep 09 10:04:34 PM UTC 24 |
Sep 09 10:04:40 PM UTC 24 |
1625568251 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.3085360304 |
|
|
Sep 09 10:04:41 PM UTC 24 |
Sep 09 10:05:01 PM UTC 24 |
812104727 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1556291714 |
|
|
Sep 09 10:00:37 PM UTC 24 |
Sep 09 10:05:02 PM UTC 24 |
26311627375 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4277515154 |
|
|
Sep 09 10:05:03 PM UTC 24 |
Sep 09 10:05:05 PM UTC 24 |
36083073 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.205151714 |
|
|
Sep 09 09:52:25 PM UTC 24 |
Sep 09 10:05:14 PM UTC 24 |
38775772156 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.2935670603 |
|
|
Sep 09 09:45:44 PM UTC 24 |
Sep 09 10:05:15 PM UTC 24 |
136763845677 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3610694760 |
|
|
Sep 09 10:05:06 PM UTC 24 |
Sep 09 10:05:18 PM UTC 24 |
264969669 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1824759307 |
|
|
Sep 09 10:04:37 PM UTC 24 |
Sep 09 10:05:20 PM UTC 24 |
1110589002 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.622066719 |
|
|
Sep 09 10:05:15 PM UTC 24 |
Sep 09 10:05:22 PM UTC 24 |
66017757 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.2052390872 |
|
|
Sep 09 10:05:21 PM UTC 24 |
Sep 09 10:05:23 PM UTC 24 |
15834299 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.735791624 |
|
|
Sep 09 10:02:11 PM UTC 24 |
Sep 09 10:05:25 PM UTC 24 |
3646369886 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.54951120 |
|
|
Sep 09 10:05:23 PM UTC 24 |
Sep 09 10:05:26 PM UTC 24 |
161996295 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.4139965749 |
|
|
Sep 09 10:04:33 PM UTC 24 |
Sep 09 10:05:26 PM UTC 24 |
740680488 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.3075453366 |
|
|
Sep 09 09:43:21 PM UTC 24 |
Sep 09 10:05:38 PM UTC 24 |
73124038364 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3796759325 |
|
|
Sep 09 10:05:27 PM UTC 24 |
Sep 09 10:05:54 PM UTC 24 |
2205218884 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3916084187 |
|
|
Sep 09 10:03:27 PM UTC 24 |
Sep 09 10:05:54 PM UTC 24 |
2079516129 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2963156753 |
|
|
Sep 09 09:43:01 PM UTC 24 |
Sep 09 10:06:00 PM UTC 24 |
15222785033 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2751319722 |
|
|
Sep 09 10:03:58 PM UTC 24 |
Sep 09 10:06:01 PM UTC 24 |
1619808483 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1747252280 |
|
|
Sep 09 10:05:54 PM UTC 24 |
Sep 09 10:06:02 PM UTC 24 |
94419842 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.94709307 |
|
|
Sep 09 10:05:55 PM UTC 24 |
Sep 09 10:06:02 PM UTC 24 |
229114371 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2012378678 |
|
|
Sep 09 10:06:02 PM UTC 24 |
Sep 09 10:06:11 PM UTC 24 |
1885305553 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.848423605 |
|
|
Sep 09 10:06:11 PM UTC 24 |
Sep 09 10:06:13 PM UTC 24 |
260108059 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.3564107416 |
|
|
Sep 09 09:58:05 PM UTC 24 |
Sep 09 10:06:21 PM UTC 24 |
8135448881 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.428429223 |
|
|
Sep 09 10:06:14 PM UTC 24 |
Sep 09 10:06:32 PM UTC 24 |
784124447 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3141647631 |
|
|
Sep 09 10:06:22 PM UTC 24 |
Sep 09 10:06:32 PM UTC 24 |
1149115676 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3079446454 |
|
|
Sep 09 09:54:29 PM UTC 24 |
Sep 09 10:06:38 PM UTC 24 |
3177071421 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3615577962 |
|
|
Sep 09 10:02:20 PM UTC 24 |
Sep 09 10:06:41 PM UTC 24 |
2148427823 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3787943041 |
|
|
Sep 09 10:06:39 PM UTC 24 |
Sep 09 10:06:41 PM UTC 24 |
29536388 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.422857030 |
|
|
Sep 09 10:05:26 PM UTC 24 |
Sep 09 10:07:11 PM UTC 24 |
14448875365 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1533747924 |
|
|
Sep 09 10:00:44 PM UTC 24 |
Sep 09 10:07:20 PM UTC 24 |
52778049511 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3050737401 |
|
|
Sep 09 09:48:40 PM UTC 24 |
Sep 09 10:07:22 PM UTC 24 |
17710230854 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.3296938871 |
|
|
Sep 09 10:07:05 PM UTC 24 |
Sep 09 10:07:29 PM UTC 24 |
1565212645 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.380539447 |
|
|
Sep 09 09:58:23 PM UTC 24 |
Sep 09 10:07:34 PM UTC 24 |
2100265056 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3901673994 |
|
|
Sep 09 09:43:50 PM UTC 24 |
Sep 09 10:07:45 PM UTC 24 |
17845268330 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.490408098 |
|
|
Sep 09 09:23:52 PM UTC 24 |
Sep 09 10:07:51 PM UTC 24 |
34035057661 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.1428851209 |
|
|
Sep 09 10:06:42 PM UTC 24 |
Sep 09 10:07:52 PM UTC 24 |
457419643 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2944015366 |
|
|
Sep 09 10:07:46 PM UTC 24 |
Sep 09 10:07:59 PM UTC 24 |
969218415 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3968027683 |
|
|
Sep 09 10:07:51 PM UTC 24 |
Sep 09 10:08:08 PM UTC 24 |
971263673 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2154890589 |
|
|
Sep 09 10:08:09 PM UTC 24 |
Sep 09 10:08:11 PM UTC 24 |
91862287 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3675050585 |
|
|
Sep 09 10:05:26 PM UTC 24 |
Sep 09 10:08:25 PM UTC 24 |
3346490146 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.99580461 |
|
|
Sep 09 10:08:12 PM UTC 24 |
Sep 09 10:08:25 PM UTC 24 |
191078478 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3016241034 |
|
|
Sep 09 10:08:26 PM UTC 24 |
Sep 09 10:08:34 PM UTC 24 |
746934001 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2266750938 |
|
|
Sep 09 10:06:03 PM UTC 24 |
Sep 09 10:08:35 PM UTC 24 |
2505090904 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3760542537 |
|
|
Sep 09 10:08:36 PM UTC 24 |
Sep 09 10:08:38 PM UTC 24 |
32589252 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.533093017 |
|
|
Sep 09 10:07:30 PM UTC 24 |
Sep 09 10:08:49 PM UTC 24 |
131599693 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.464625067 |
|
|
Sep 09 10:07:21 PM UTC 24 |
Sep 09 10:08:56 PM UTC 24 |
761152675 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2599703307 |
|
|
Sep 09 09:56:10 PM UTC 24 |
Sep 09 10:09:13 PM UTC 24 |
106333537828 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.1157397592 |
|
|
Sep 09 10:04:11 PM UTC 24 |
Sep 09 10:09:20 PM UTC 24 |
9662225017 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.2717358523 |
|
|
Sep 09 09:46:07 PM UTC 24 |
Sep 09 10:09:20 PM UTC 24 |
28480466147 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3768782825 |
|
|
Sep 09 10:07:35 PM UTC 24 |
Sep 09 10:09:23 PM UTC 24 |
154036483 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2791155873 |
|
|
Sep 09 10:09:21 PM UTC 24 |
Sep 09 10:09:28 PM UTC 24 |
179098068 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.298595082 |
|
|
Sep 09 10:09:14 PM UTC 24 |
Sep 09 10:09:36 PM UTC 24 |
464384813 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3913288230 |
|
|
Sep 09 10:09:29 PM UTC 24 |
Sep 09 10:09:39 PM UTC 24 |
3170185266 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2643929709 |
|
|
Sep 09 10:02:42 PM UTC 24 |
Sep 09 10:09:39 PM UTC 24 |
25967677743 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.444336542 |
|
|
Sep 09 09:58:37 PM UTC 24 |
Sep 09 10:09:44 PM UTC 24 |
79058556519 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.3018653415 |
|
|
Sep 09 10:08:39 PM UTC 24 |
Sep 09 10:09:45 PM UTC 24 |
1132969225 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1260068448 |
|
|
Sep 09 10:09:45 PM UTC 24 |
Sep 09 10:09:47 PM UTC 24 |
145926454 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3576558151 |
|
|
Sep 09 10:03:14 PM UTC 24 |
Sep 09 10:09:53 PM UTC 24 |
5648342334 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2345458509 |
|
|
Sep 09 10:09:46 PM UTC 24 |
Sep 09 10:09:53 PM UTC 24 |
95997295 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2170642828 |
|
|
Sep 09 10:09:48 PM UTC 24 |
Sep 09 10:09:56 PM UTC 24 |
108133021 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3142590005 |
|
|
Sep 09 10:06:02 PM UTC 24 |
Sep 09 10:09:56 PM UTC 24 |
1483859486 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.591330158 |
|
|
Sep 09 10:09:56 PM UTC 24 |
Sep 09 10:09:58 PM UTC 24 |
35642373 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.4263753586 |
|
|
Sep 09 09:57:15 PM UTC 24 |
Sep 09 10:09:59 PM UTC 24 |
39883556365 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.2687426630 |
|
|
Sep 09 10:08:57 PM UTC 24 |
Sep 09 10:09:59 PM UTC 24 |
3104390766 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.57563002 |
|
|
Sep 09 10:08:26 PM UTC 24 |
Sep 09 10:10:00 PM UTC 24 |
695104895 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1023669151 |
|
|
Sep 09 09:35:35 PM UTC 24 |
Sep 09 10:10:01 PM UTC 24 |
35383655225 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1736020365 |
|
|
Sep 09 10:10:01 PM UTC 24 |
Sep 09 10:10:06 PM UTC 24 |
90990050 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.1270502426 |
|
|
Sep 09 10:09:23 PM UTC 24 |
Sep 09 10:10:13 PM UTC 24 |
153370018 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1011846952 |
|
|
Sep 09 09:20:10 PM UTC 24 |
Sep 09 10:10:15 PM UTC 24 |
30417129212 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2705902947 |
|
|
Sep 09 10:10:16 PM UTC 24 |
Sep 09 10:10:28 PM UTC 24 |
831234066 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.470819251 |
|
|
Sep 09 09:27:56 PM UTC 24 |
Sep 09 10:10:32 PM UTC 24 |
46083338944 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.3098958543 |
|
|
Sep 09 10:03:14 PM UTC 24 |
Sep 09 10:10:41 PM UTC 24 |
7636330104 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1857151165 |
|
|
Sep 09 10:05:01 PM UTC 24 |
Sep 09 10:10:46 PM UTC 24 |
2920876464 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2759387703 |
|
|
Sep 09 09:59:11 PM UTC 24 |
Sep 09 10:10:48 PM UTC 24 |
9881372619 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1077291730 |
|
|
Sep 09 10:10:47 PM UTC 24 |
Sep 09 10:10:49 PM UTC 24 |
29503598 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3361089675 |
|
|
Sep 09 10:10:50 PM UTC 24 |
Sep 09 10:10:55 PM UTC 24 |
92873782 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.603039759 |
|
|
Sep 09 10:10:49 PM UTC 24 |
Sep 09 10:10:56 PM UTC 24 |
1190574385 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3326083756 |
|
|
Sep 09 10:09:54 PM UTC 24 |
Sep 09 10:11:07 PM UTC 24 |
6808714657 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1111467543 |
|
|
Sep 09 10:11:09 PM UTC 24 |
Sep 09 10:11:11 PM UTC 24 |
58746861 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3321343530 |
|
|
Sep 09 10:09:36 PM UTC 24 |
Sep 09 10:11:12 PM UTC 24 |
1890240358 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2318820363 |
|
|
Sep 09 10:04:30 PM UTC 24 |
Sep 09 10:11:15 PM UTC 24 |
4522936727 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.1991653064 |
|
|
Sep 09 10:10:00 PM UTC 24 |
Sep 09 10:11:24 PM UTC 24 |
7265012472 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1706210277 |
|
|
Sep 09 10:10:14 PM UTC 24 |
Sep 09 10:11:31 PM UTC 24 |
574453934 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2971010977 |
|
|
Sep 09 10:10:07 PM UTC 24 |
Sep 09 10:11:32 PM UTC 24 |
160220906 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.940280886 |
|
|
Sep 09 10:11:12 PM UTC 24 |
Sep 09 10:11:33 PM UTC 24 |
1467846454 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.147741103 |
|
|
Sep 09 10:11:31 PM UTC 24 |
Sep 09 10:11:37 PM UTC 24 |
92428558 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2805625474 |
|
|
Sep 09 10:09:57 PM UTC 24 |
Sep 09 10:11:39 PM UTC 24 |
165253985 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.775878018 |
|
|
Sep 09 10:11:38 PM UTC 24 |
Sep 09 10:11:40 PM UTC 24 |
136591967 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2694270510 |
|
|
Sep 09 10:07:11 PM UTC 24 |
Sep 09 10:11:41 PM UTC 24 |
2948482320 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1714012802 |
|
|
Sep 09 09:52:11 PM UTC 24 |
Sep 09 10:11:47 PM UTC 24 |
19759900059 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1389906937 |
|
|
Sep 09 10:11:40 PM UTC 24 |
Sep 09 10:11:58 PM UTC 24 |
910651756 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.3165720093 |
|
|
Sep 09 10:09:40 PM UTC 24 |
Sep 09 10:12:00 PM UTC 24 |
2258361819 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3171834019 |
|
|
Sep 09 10:11:59 PM UTC 24 |
Sep 09 10:12:01 PM UTC 24 |
107093743 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.2319155651 |
|
|
Sep 09 10:11:16 PM UTC 24 |
Sep 09 10:12:01 PM UTC 24 |
2473752464 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1519506062 |
|
|
Sep 09 10:11:34 PM UTC 24 |
Sep 09 10:12:04 PM UTC 24 |
1328361679 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2092809139 |
|
|
Sep 09 10:12:02 PM UTC 24 |
Sep 09 10:12:08 PM UTC 24 |
108130685 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1713110763 |
|
|
Sep 09 10:12:09 PM UTC 24 |
Sep 09 10:12:11 PM UTC 24 |
14459531 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.3189864413 |
|
|
Sep 09 10:12:12 PM UTC 24 |
Sep 09 10:12:15 PM UTC 24 |
87133529 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2142138685 |
|
|
Sep 09 10:12:00 PM UTC 24 |
Sep 09 10:12:15 PM UTC 24 |
186916632 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3255824733 |
|
|
Sep 09 10:09:06 PM UTC 24 |
Sep 09 10:12:17 PM UTC 24 |
6347924375 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2724399852 |
|
|
Sep 09 10:05:39 PM UTC 24 |
Sep 09 10:12:30 PM UTC 24 |
45597555172 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.1253882696 |
|
|
Sep 09 09:51:08 PM UTC 24 |
Sep 09 10:12:30 PM UTC 24 |
3493491364 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.253848266 |
|
|
Sep 09 10:01:59 PM UTC 24 |
Sep 09 10:12:32 PM UTC 24 |
1287517225 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2547725640 |
|
|
Sep 09 09:30:32 PM UTC 24 |
Sep 09 10:12:34 PM UTC 24 |
33527506293 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.638771865 |
|
|
Sep 09 10:10:56 PM UTC 24 |
Sep 09 10:12:38 PM UTC 24 |
1593565206 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.630240982 |
|
|
Sep 09 10:12:34 PM UTC 24 |
Sep 09 10:12:40 PM UTC 24 |
54092708 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3873149771 |
|
|
Sep 09 10:12:02 PM UTC 24 |
Sep 09 10:12:40 PM UTC 24 |
5008464089 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.416431195 |
|
|
Sep 09 10:12:30 PM UTC 24 |
Sep 09 10:12:40 PM UTC 24 |
937977800 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.564977466 |
|
|
Sep 09 10:12:39 PM UTC 24 |
Sep 09 10:12:52 PM UTC 24 |
857870813 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3006576277 |
|
|
Sep 09 09:55:33 PM UTC 24 |
Sep 09 10:12:53 PM UTC 24 |
22855364844 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.540123460 |
|
|
Sep 09 10:06:03 PM UTC 24 |
Sep 09 10:12:54 PM UTC 24 |
2833219205 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3268081142 |
|
|
Sep 09 10:12:54 PM UTC 24 |
Sep 09 10:12:56 PM UTC 24 |
44479641 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.870474593 |
|
|
Sep 09 09:59:53 PM UTC 24 |
Sep 09 10:12:56 PM UTC 24 |
14161285423 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2167063010 |
|
|
Sep 09 10:12:54 PM UTC 24 |
Sep 09 10:13:02 PM UTC 24 |
1571489577 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.93930650 |
|
|
Sep 09 10:12:56 PM UTC 24 |
Sep 09 10:13:05 PM UTC 24 |
1804231459 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.3719840425 |
|
|
Sep 09 10:13:03 PM UTC 24 |
Sep 09 10:13:05 PM UTC 24 |
22181489 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3732756586 |
|
|
Sep 09 09:58:00 PM UTC 24 |
Sep 09 10:13:10 PM UTC 24 |
9514046185 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.2242354919 |
|
|
Sep 09 10:12:16 PM UTC 24 |
Sep 09 10:13:21 PM UTC 24 |
4911014248 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.829769418 |
|
|
Sep 09 10:01:51 PM UTC 24 |
Sep 09 10:13:23 PM UTC 24 |
14061575046 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.117672941 |
|
|
Sep 09 10:12:57 PM UTC 24 |
Sep 09 10:13:25 PM UTC 24 |
525054593 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2953568932 |
|
|
Sep 09 10:13:24 PM UTC 24 |
Sep 09 10:13:37 PM UTC 24 |
784897236 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2425138881 |
|
|
Sep 09 09:59:45 PM UTC 24 |
Sep 09 10:13:46 PM UTC 24 |
35801089143 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3562435597 |
|
|
Sep 09 10:13:47 PM UTC 24 |
Sep 09 10:13:52 PM UTC 24 |
158887793 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3567305232 |
|
|
Sep 09 10:09:21 PM UTC 24 |
Sep 09 10:14:03 PM UTC 24 |
52005807588 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1336085888 |
|
|
Sep 09 09:13:54 PM UTC 24 |
Sep 09 10:14:04 PM UTC 24 |
42003427184 ps |