| T312 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1732780013 |
|
|
Sep 11 08:52:29 AM UTC 24 |
Sep 11 08:56:42 AM UTC 24 |
4523904778 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.174094164 |
|
|
Sep 11 08:56:42 AM UTC 24 |
Sep 11 08:56:44 AM UTC 24 |
27502575 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3654964183 |
|
|
Sep 11 08:55:13 AM UTC 24 |
Sep 11 08:56:47 AM UTC 24 |
423781456 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.2705744376 |
|
|
Sep 11 08:56:45 AM UTC 24 |
Sep 11 08:56:59 AM UTC 24 |
190031373 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.623657111 |
|
|
Sep 11 08:55:27 AM UTC 24 |
Sep 11 08:57:04 AM UTC 24 |
27533471151 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2498418563 |
|
|
Sep 11 08:55:21 AM UTC 24 |
Sep 11 08:57:26 AM UTC 24 |
3928589008 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2356121686 |
|
|
Sep 11 08:56:47 AM UTC 24 |
Sep 11 08:57:30 AM UTC 24 |
1884211160 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2408695854 |
|
|
Sep 11 08:57:27 AM UTC 24 |
Sep 11 08:57:32 AM UTC 24 |
274789438 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3946328710 |
|
|
Sep 11 08:50:17 AM UTC 24 |
Sep 11 08:57:32 AM UTC 24 |
11923392339 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.3781163973 |
|
|
Sep 11 08:56:11 AM UTC 24 |
Sep 11 08:57:34 AM UTC 24 |
4289869305 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2665254474 |
|
|
Sep 11 08:52:46 AM UTC 24 |
Sep 11 08:57:35 AM UTC 24 |
3631351391 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.718493698 |
|
|
Sep 11 08:52:23 AM UTC 24 |
Sep 11 08:57:38 AM UTC 24 |
737875229 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2469166627 |
|
|
Sep 11 08:57:35 AM UTC 24 |
Sep 11 08:57:42 AM UTC 24 |
803361351 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.3282879317 |
|
|
Sep 11 08:55:44 AM UTC 24 |
Sep 11 08:57:48 AM UTC 24 |
974499665 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3414350761 |
|
|
Sep 11 08:57:33 AM UTC 24 |
Sep 11 08:57:48 AM UTC 24 |
79494044 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.3592701293 |
|
|
Sep 11 08:57:00 AM UTC 24 |
Sep 11 08:57:51 AM UTC 24 |
4267899211 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1844627803 |
|
|
Sep 11 08:57:49 AM UTC 24 |
Sep 11 08:57:51 AM UTC 24 |
102935745 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2998479240 |
|
|
Sep 11 08:42:10 AM UTC 24 |
Sep 11 08:57:56 AM UTC 24 |
2594456277 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2651546553 |
|
|
Sep 11 08:57:52 AM UTC 24 |
Sep 11 08:57:57 AM UTC 24 |
343845581 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1743875476 |
|
|
Sep 11 08:57:58 AM UTC 24 |
Sep 11 08:58:00 AM UTC 24 |
15114216 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2917284066 |
|
|
Sep 11 08:57:50 AM UTC 24 |
Sep 11 08:58:03 AM UTC 24 |
696344207 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4199868264 |
|
|
Sep 11 08:50:43 AM UTC 24 |
Sep 11 08:58:07 AM UTC 24 |
134190080268 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.3332157693 |
|
|
Sep 11 08:58:01 AM UTC 24 |
Sep 11 08:58:26 AM UTC 24 |
975406850 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1326027462 |
|
|
Sep 11 08:55:26 AM UTC 24 |
Sep 11 08:58:42 AM UTC 24 |
24617223776 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2069807755 |
|
|
Sep 11 08:55:41 AM UTC 24 |
Sep 11 08:58:48 AM UTC 24 |
1906938736 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.2101467458 |
|
|
Sep 11 08:50:04 AM UTC 24 |
Sep 11 08:58:50 AM UTC 24 |
1385199592 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2495747398 |
|
|
Sep 11 08:58:43 AM UTC 24 |
Sep 11 08:58:51 AM UTC 24 |
124160914 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1376599275 |
|
|
Sep 11 08:57:33 AM UTC 24 |
Sep 11 08:58:56 AM UTC 24 |
167631989 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.311236217 |
|
|
Sep 11 08:58:51 AM UTC 24 |
Sep 11 08:59:00 AM UTC 24 |
206474330 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1576335616 |
|
|
Sep 11 08:58:56 AM UTC 24 |
Sep 11 08:59:04 AM UTC 24 |
520428740 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3753368163 |
|
|
Sep 11 08:50:24 AM UTC 24 |
Sep 11 08:59:05 AM UTC 24 |
4092851439 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3292101672 |
|
|
Sep 11 08:53:44 AM UTC 24 |
Sep 11 08:59:26 AM UTC 24 |
3605100901 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1833621198 |
|
|
Sep 11 08:58:09 AM UTC 24 |
Sep 11 08:59:27 AM UTC 24 |
4040075698 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3503656502 |
|
|
Sep 11 08:59:27 AM UTC 24 |
Sep 11 08:59:29 AM UTC 24 |
89994251 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1553496744 |
|
|
Sep 11 08:59:30 AM UTC 24 |
Sep 11 08:59:36 AM UTC 24 |
112611825 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.202053280 |
|
|
Sep 11 08:59:28 AM UTC 24 |
Sep 11 08:59:41 AM UTC 24 |
469041233 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1278986238 |
|
|
Sep 11 08:51:32 AM UTC 24 |
Sep 11 08:59:42 AM UTC 24 |
81957558708 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.595934956 |
|
|
Sep 11 08:59:43 AM UTC 24 |
Sep 11 08:59:45 AM UTC 24 |
15627467 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1005095768 |
|
|
Sep 11 09:00:47 AM UTC 24 |
Sep 11 09:00:55 AM UTC 24 |
367823563 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2415493860 |
|
|
Sep 11 08:52:43 AM UTC 24 |
Sep 11 08:59:47 AM UTC 24 |
32472136436 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3187858356 |
|
|
Sep 11 08:42:25 AM UTC 24 |
Sep 11 08:59:52 AM UTC 24 |
27101740481 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2567528762 |
|
|
Sep 11 08:45:41 AM UTC 24 |
Sep 11 08:59:58 AM UTC 24 |
1972222826 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1828405852 |
|
|
Sep 11 08:58:51 AM UTC 24 |
Sep 11 08:59:58 AM UTC 24 |
157500238 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2653409032 |
|
|
Sep 11 08:54:22 AM UTC 24 |
Sep 11 09:00:00 AM UTC 24 |
6744297797 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.82362795 |
|
|
Sep 11 08:55:30 AM UTC 24 |
Sep 11 09:00:04 AM UTC 24 |
5722776843 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1467790206 |
|
|
Sep 11 08:59:59 AM UTC 24 |
Sep 11 09:00:08 AM UTC 24 |
203017157 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.47119691 |
|
|
Sep 11 09:00:08 AM UTC 24 |
Sep 11 09:00:18 AM UTC 24 |
561359540 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.3405325091 |
|
|
Sep 11 08:40:24 AM UTC 24 |
Sep 11 09:00:19 AM UTC 24 |
17738151801 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3571616657 |
|
|
Sep 11 08:40:47 AM UTC 24 |
Sep 11 09:00:30 AM UTC 24 |
2614872740 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1453725334 |
|
|
Sep 11 09:00:07 AM UTC 24 |
Sep 11 09:00:36 AM UTC 24 |
92921291 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2398390886 |
|
|
Sep 11 09:00:37 AM UTC 24 |
Sep 11 09:00:39 AM UTC 24 |
52802745 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.935577731 |
|
|
Sep 11 09:00:00 AM UTC 24 |
Sep 11 09:00:47 AM UTC 24 |
422407759 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.1529036182 |
|
|
Sep 11 09:00:40 AM UTC 24 |
Sep 11 09:00:51 AM UTC 24 |
540329661 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1452530059 |
|
|
Sep 11 08:57:05 AM UTC 24 |
Sep 11 09:00:53 AM UTC 24 |
2340842611 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1268624246 |
|
|
Sep 11 09:00:56 AM UTC 24 |
Sep 11 09:00:58 AM UTC 24 |
28197568 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.3412055540 |
|
|
Sep 11 08:59:47 AM UTC 24 |
Sep 11 09:01:24 AM UTC 24 |
576716182 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.785186496 |
|
|
Sep 11 08:59:49 AM UTC 24 |
Sep 11 09:01:28 AM UTC 24 |
7545541933 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.3623159130 |
|
|
Sep 11 09:01:00 AM UTC 24 |
Sep 11 09:01:36 AM UTC 24 |
3355381555 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.646098863 |
|
|
Sep 11 09:01:37 AM UTC 24 |
Sep 11 09:01:41 AM UTC 24 |
61679286 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2027383723 |
|
|
Sep 11 08:59:48 AM UTC 24 |
Sep 11 09:01:42 AM UTC 24 |
1047590427 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.257167688 |
|
|
Sep 11 09:01:25 AM UTC 24 |
Sep 11 09:01:48 AM UTC 24 |
1277476958 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.3083061106 |
|
|
Sep 11 08:55:04 AM UTC 24 |
Sep 11 09:02:06 AM UTC 24 |
7969912737 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1130201090 |
|
|
Sep 11 08:57:31 AM UTC 24 |
Sep 11 09:02:17 AM UTC 24 |
14078308069 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.2573023858 |
|
|
Sep 11 09:02:07 AM UTC 24 |
Sep 11 09:02:23 AM UTC 24 |
5393976307 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3020895675 |
|
|
Sep 11 09:00:52 AM UTC 24 |
Sep 11 09:02:44 AM UTC 24 |
397674296 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2271655025 |
|
|
Sep 11 08:54:34 AM UTC 24 |
Sep 11 09:02:48 AM UTC 24 |
201813208690 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.926473682 |
|
|
Sep 11 09:02:49 AM UTC 24 |
Sep 11 09:02:51 AM UTC 24 |
52359282 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1549119007 |
|
|
Sep 11 09:02:52 AM UTC 24 |
Sep 11 09:03:04 AM UTC 24 |
281604066 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3410333851 |
|
|
Sep 11 09:01:42 AM UTC 24 |
Sep 11 09:03:10 AM UTC 24 |
135264344 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1863098008 |
|
|
Sep 11 09:03:04 AM UTC 24 |
Sep 11 09:03:14 AM UTC 24 |
435915374 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.502069712 |
|
|
Sep 11 08:58:27 AM UTC 24 |
Sep 11 09:03:18 AM UTC 24 |
26411879043 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.4122457052 |
|
|
Sep 11 09:03:19 AM UTC 24 |
Sep 11 09:03:21 AM UTC 24 |
40428394 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.3377474419 |
|
|
Sep 11 08:53:15 AM UTC 24 |
Sep 11 09:03:25 AM UTC 24 |
6787695827 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.4042907508 |
|
|
Sep 11 09:01:48 AM UTC 24 |
Sep 11 09:03:25 AM UTC 24 |
165359934 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3956547081 |
|
|
Sep 11 09:01:29 AM UTC 24 |
Sep 11 09:03:29 AM UTC 24 |
1029523902 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.988930490 |
|
|
Sep 11 09:03:22 AM UTC 24 |
Sep 11 09:03:36 AM UTC 24 |
810336304 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2514817224 |
|
|
Sep 11 08:51:08 AM UTC 24 |
Sep 11 09:03:46 AM UTC 24 |
13581265991 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3048536893 |
|
|
Sep 11 08:59:53 AM UTC 24 |
Sep 11 09:03:54 AM UTC 24 |
45856340439 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.3730139087 |
|
|
Sep 11 08:40:25 AM UTC 24 |
Sep 11 09:04:11 AM UTC 24 |
20606111344 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.893972058 |
|
|
Sep 11 09:03:54 AM UTC 24 |
Sep 11 09:04:14 AM UTC 24 |
269949644 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2901443031 |
|
|
Sep 11 08:48:09 AM UTC 24 |
Sep 11 09:04:20 AM UTC 24 |
63420239230 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.4010354040 |
|
|
Sep 11 08:53:20 AM UTC 24 |
Sep 11 09:04:23 AM UTC 24 |
12096016060 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3903408627 |
|
|
Sep 11 09:04:15 AM UTC 24 |
Sep 11 09:04:24 AM UTC 24 |
1668101981 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1781215870 |
|
|
Sep 11 08:59:06 AM UTC 24 |
Sep 11 09:04:38 AM UTC 24 |
7149068951 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.641798362 |
|
|
Sep 11 09:04:37 AM UTC 24 |
Sep 11 09:04:39 AM UTC 24 |
82677145 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2664807016 |
|
|
Sep 11 08:59:36 AM UTC 24 |
Sep 11 09:04:45 AM UTC 24 |
8268843023 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.384961088 |
|
|
Sep 11 09:04:40 AM UTC 24 |
Sep 11 09:04:49 AM UTC 24 |
338981775 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.128938185 |
|
|
Sep 11 08:57:38 AM UTC 24 |
Sep 11 09:04:51 AM UTC 24 |
6774727572 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2378020814 |
|
|
Sep 11 08:40:56 AM UTC 24 |
Sep 11 09:04:52 AM UTC 24 |
43376937866 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2333012445 |
|
|
Sep 11 09:04:39 AM UTC 24 |
Sep 11 09:04:53 AM UTC 24 |
443806662 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.172936254 |
|
|
Sep 11 09:04:52 AM UTC 24 |
Sep 11 09:04:54 AM UTC 24 |
38709033 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.1248578376 |
|
|
Sep 11 08:48:03 AM UTC 24 |
Sep 11 09:05:00 AM UTC 24 |
13724441545 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.4108715769 |
|
|
Sep 11 09:04:53 AM UTC 24 |
Sep 11 09:05:00 AM UTC 24 |
353595654 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3897464263 |
|
|
Sep 11 09:03:26 AM UTC 24 |
Sep 11 09:05:01 AM UTC 24 |
3763399598 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1378169926 |
|
|
Sep 11 09:05:01 AM UTC 24 |
Sep 11 09:05:09 AM UTC 24 |
95910885 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4093577823 |
|
|
Sep 11 09:03:36 AM UTC 24 |
Sep 11 09:05:15 AM UTC 24 |
578249726 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.4227555591 |
|
|
Sep 11 09:05:16 AM UTC 24 |
Sep 11 09:05:26 AM UTC 24 |
235181153 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.408472979 |
|
|
Sep 11 09:05:27 AM UTC 24 |
Sep 11 09:05:31 AM UTC 24 |
319181254 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3130328636 |
|
|
Sep 11 08:50:05 AM UTC 24 |
Sep 11 09:05:35 AM UTC 24 |
3568852085 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2438501193 |
|
|
Sep 11 09:04:56 AM UTC 24 |
Sep 11 09:05:40 AM UTC 24 |
2392034565 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.10411299 |
|
|
Sep 11 09:05:40 AM UTC 24 |
Sep 11 09:05:42 AM UTC 24 |
125517544 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1080691767 |
|
|
Sep 11 09:01:42 AM UTC 24 |
Sep 11 09:05:48 AM UTC 24 |
30191237586 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2422193286 |
|
|
Sep 11 09:05:43 AM UTC 24 |
Sep 11 09:05:52 AM UTC 24 |
905100626 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3420167818 |
|
|
Sep 11 09:05:49 AM UTC 24 |
Sep 11 09:05:54 AM UTC 24 |
92946633 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2315099018 |
|
|
Sep 11 08:40:24 AM UTC 24 |
Sep 11 09:05:56 AM UTC 24 |
13990999126 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3051531971 |
|
|
Sep 11 08:58:49 AM UTC 24 |
Sep 11 09:05:58 AM UTC 24 |
16052972843 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3842923803 |
|
|
Sep 11 09:05:57 AM UTC 24 |
Sep 11 09:05:59 AM UTC 24 |
68961771 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.4007766810 |
|
|
Sep 11 09:05:10 AM UTC 24 |
Sep 11 09:06:00 AM UTC 24 |
225947074 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2469007599 |
|
|
Sep 11 09:04:13 AM UTC 24 |
Sep 11 09:06:08 AM UTC 24 |
303706294 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3021531265 |
|
|
Sep 11 09:03:10 AM UTC 24 |
Sep 11 09:06:23 AM UTC 24 |
1399092739 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3232956256 |
|
|
Sep 11 09:04:46 AM UTC 24 |
Sep 11 09:06:31 AM UTC 24 |
550658084 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2531500233 |
|
|
Sep 11 09:00:18 AM UTC 24 |
Sep 11 09:06:36 AM UTC 24 |
1503189023 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2729649195 |
|
|
Sep 11 09:06:37 AM UTC 24 |
Sep 11 09:06:41 AM UTC 24 |
166580645 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3194166956 |
|
|
Sep 11 09:05:59 AM UTC 24 |
Sep 11 09:06:59 AM UTC 24 |
551013529 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1651895996 |
|
|
Sep 11 09:05:01 AM UTC 24 |
Sep 11 09:07:04 AM UTC 24 |
1044912549 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.577509366 |
|
|
Sep 11 09:07:00 AM UTC 24 |
Sep 11 09:07:06 AM UTC 24 |
282918635 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2820065353 |
|
|
Sep 11 08:47:18 AM UTC 24 |
Sep 11 09:07:10 AM UTC 24 |
3207486550 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2962797433 |
|
|
Sep 11 09:06:42 AM UTC 24 |
Sep 11 09:07:10 AM UTC 24 |
358210729 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3622802512 |
|
|
Sep 11 09:07:11 AM UTC 24 |
Sep 11 09:07:13 AM UTC 24 |
73545582 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1047149943 |
|
|
Sep 11 09:07:14 AM UTC 24 |
Sep 11 09:07:22 AM UTC 24 |
95183725 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1719363096 |
|
|
Sep 11 08:59:59 AM UTC 24 |
Sep 11 09:07:24 AM UTC 24 |
65738818016 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2106585385 |
|
|
Sep 11 09:07:24 AM UTC 24 |
Sep 11 09:07:30 AM UTC 24 |
112625808 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1694171837 |
|
|
Sep 11 09:06:24 AM UTC 24 |
Sep 11 09:07:33 AM UTC 24 |
1179003673 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1591695419 |
|
|
Sep 11 09:06:01 AM UTC 24 |
Sep 11 09:07:36 AM UTC 24 |
9498759450 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.285093898 |
|
|
Sep 11 09:07:34 AM UTC 24 |
Sep 11 09:07:37 AM UTC 24 |
55284772 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3082946787 |
|
|
Sep 11 09:00:20 AM UTC 24 |
Sep 11 09:07:49 AM UTC 24 |
7070521556 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2401689204 |
|
|
Sep 11 08:53:08 AM UTC 24 |
Sep 11 09:07:54 AM UTC 24 |
33429858433 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2054201505 |
|
|
Sep 11 08:50:55 AM UTC 24 |
Sep 11 09:08:06 AM UTC 24 |
69014113514 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2218731437 |
|
|
Sep 11 09:07:37 AM UTC 24 |
Sep 11 09:08:08 AM UTC 24 |
1236297248 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3952553216 |
|
|
Sep 11 09:08:07 AM UTC 24 |
Sep 11 09:08:18 AM UTC 24 |
151499581 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.4210948154 |
|
|
Sep 11 08:51:58 AM UTC 24 |
Sep 11 09:08:24 AM UTC 24 |
16092265742 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2947473175 |
|
|
Sep 11 09:07:49 AM UTC 24 |
Sep 11 09:08:25 AM UTC 24 |
810180430 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.4214570433 |
|
|
Sep 11 08:46:59 AM UTC 24 |
Sep 11 09:08:26 AM UTC 24 |
27994567827 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3190605780 |
|
|
Sep 11 08:54:03 AM UTC 24 |
Sep 11 09:08:30 AM UTC 24 |
32953382001 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3428294029 |
|
|
Sep 11 09:08:26 AM UTC 24 |
Sep 11 09:08:40 AM UTC 24 |
985957338 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2537431516 |
|
|
Sep 11 08:50:04 AM UTC 24 |
Sep 11 09:08:56 AM UTC 24 |
2948577977 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2266837687 |
|
|
Sep 11 09:08:57 AM UTC 24 |
Sep 11 09:09:00 AM UTC 24 |
66745326 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.953757001 |
|
|
Sep 11 09:09:01 AM UTC 24 |
Sep 11 09:09:12 AM UTC 24 |
2543769368 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2085776959 |
|
|
Sep 11 09:08:20 AM UTC 24 |
Sep 11 09:09:18 AM UTC 24 |
123196724 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4078048939 |
|
|
Sep 11 09:09:13 AM UTC 24 |
Sep 11 09:09:21 AM UTC 24 |
346286007 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.64031141 |
|
|
Sep 11 09:03:30 AM UTC 24 |
Sep 11 09:09:31 AM UTC 24 |
12857221186 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2887112932 |
|
|
Sep 11 09:09:32 AM UTC 24 |
Sep 11 09:09:34 AM UTC 24 |
12310925 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.3109500455 |
|
|
Sep 11 09:08:40 AM UTC 24 |
Sep 11 09:09:39 AM UTC 24 |
145872191 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.1099727537 |
|
|
Sep 11 09:09:35 AM UTC 24 |
Sep 11 09:09:41 AM UTC 24 |
164802640 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.817051212 |
|
|
Sep 11 09:07:10 AM UTC 24 |
Sep 11 09:09:50 AM UTC 24 |
12030828970 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4105893006 |
|
|
Sep 11 09:07:25 AM UTC 24 |
Sep 11 09:09:59 AM UTC 24 |
4587391845 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3908076881 |
|
|
Sep 11 09:08:25 AM UTC 24 |
Sep 11 09:10:05 AM UTC 24 |
294464695 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1429602813 |
|
|
Sep 11 08:57:35 AM UTC 24 |
Sep 11 09:10:11 AM UTC 24 |
16000561831 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1235893164 |
|
|
Sep 11 09:02:45 AM UTC 24 |
Sep 11 09:10:15 AM UTC 24 |
47907668037 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1464463530 |
|
|
Sep 11 09:09:41 AM UTC 24 |
Sep 11 09:10:17 AM UTC 24 |
7122854787 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.4209078625 |
|
|
Sep 11 09:01:05 AM UTC 24 |
Sep 11 09:10:18 AM UTC 24 |
2012337266 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3443538543 |
|
|
Sep 11 09:10:17 AM UTC 24 |
Sep 11 09:10:21 AM UTC 24 |
382404246 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2206309965 |
|
|
Sep 11 09:10:00 AM UTC 24 |
Sep 11 09:10:22 AM UTC 24 |
626093158 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3984058400 |
|
|
Sep 11 09:09:19 AM UTC 24 |
Sep 11 09:10:31 AM UTC 24 |
7945314969 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1244763962 |
|
|
Sep 11 09:05:02 AM UTC 24 |
Sep 11 09:10:34 AM UTC 24 |
22212733924 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1318667720 |
|
|
Sep 11 09:10:32 AM UTC 24 |
Sep 11 09:10:34 AM UTC 24 |
44352456 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3392014136 |
|
|
Sep 11 09:10:12 AM UTC 24 |
Sep 11 09:10:39 AM UTC 24 |
297937764 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3315088894 |
|
|
Sep 11 09:10:35 AM UTC 24 |
Sep 11 09:10:40 AM UTC 24 |
128555740 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1541491656 |
|
|
Sep 11 09:10:35 AM UTC 24 |
Sep 11 09:10:43 AM UTC 24 |
394853481 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2279687312 |
|
|
Sep 11 09:06:32 AM UTC 24 |
Sep 11 09:10:44 AM UTC 24 |
11282229012 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2918449877 |
|
|
Sep 11 09:10:43 AM UTC 24 |
Sep 11 09:10:45 AM UTC 24 |
57324953 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1852526630 |
|
|
Sep 11 09:06:09 AM UTC 24 |
Sep 11 09:10:56 AM UTC 24 |
11583504458 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1033184216 |
|
|
Sep 11 09:10:16 AM UTC 24 |
Sep 11 09:11:08 AM UTC 24 |
560378969 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2611327065 |
|
|
Sep 11 09:07:06 AM UTC 24 |
Sep 11 09:11:08 AM UTC 24 |
8587336099 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.920114550 |
|
|
Sep 11 09:10:45 AM UTC 24 |
Sep 11 09:11:13 AM UTC 24 |
568015994 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2183239895 |
|
|
Sep 11 09:11:09 AM UTC 24 |
Sep 11 09:11:21 AM UTC 24 |
367199399 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3777148638 |
|
|
Sep 11 09:03:26 AM UTC 24 |
Sep 11 09:11:38 AM UTC 24 |
12522631534 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.1292485252 |
|
|
Sep 11 09:10:56 AM UTC 24 |
Sep 11 09:11:47 AM UTC 24 |
2081944903 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.4280467820 |
|
|
Sep 11 09:05:36 AM UTC 24 |
Sep 11 09:11:56 AM UTC 24 |
7241505052 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1758239388 |
|
|
Sep 11 09:11:47 AM UTC 24 |
Sep 11 09:12:01 AM UTC 24 |
1277173787 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1437388691 |
|
|
Sep 11 09:11:39 AM UTC 24 |
Sep 11 09:12:13 AM UTC 24 |
201776170 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.2099941516 |
|
|
Sep 11 09:12:14 AM UTC 24 |
Sep 11 09:12:22 AM UTC 24 |
55894852 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3945774750 |
|
|
Sep 11 09:12:23 AM UTC 24 |
Sep 11 09:12:25 AM UTC 24 |
31140904 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2471214568 |
|
|
Sep 11 09:07:55 AM UTC 24 |
Sep 11 09:12:27 AM UTC 24 |
5424943674 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.575553041 |
|
|
Sep 11 09:12:28 AM UTC 24 |
Sep 11 09:12:32 AM UTC 24 |
167331291 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1508696366 |
|
|
Sep 11 09:08:27 AM UTC 24 |
Sep 11 09:12:38 AM UTC 24 |
4070716947 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3574025344 |
|
|
Sep 11 09:12:26 AM UTC 24 |
Sep 11 09:12:38 AM UTC 24 |
138174740 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3956869238 |
|
|
Sep 11 09:12:39 AM UTC 24 |
Sep 11 09:12:41 AM UTC 24 |
24130611 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1841466878 |
|
|
Sep 11 09:03:47 AM UTC 24 |
Sep 11 09:12:47 AM UTC 24 |
62991218192 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.323126132 |
|
|
Sep 11 09:12:42 AM UTC 24 |
Sep 11 09:12:49 AM UTC 24 |
278832294 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2688475576 |
|
|
Sep 11 09:11:21 AM UTC 24 |
Sep 11 09:13:16 AM UTC 24 |
194360144 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.525541869 |
|
|
Sep 11 08:45:30 AM UTC 24 |
Sep 11 09:13:24 AM UTC 24 |
27825225270 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.4089341989 |
|
|
Sep 11 09:00:31 AM UTC 24 |
Sep 11 09:13:29 AM UTC 24 |
11867122005 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1513014400 |
|
|
Sep 11 09:13:24 AM UTC 24 |
Sep 11 09:13:50 AM UTC 24 |
6118246741 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.239105615 |
|
|
Sep 11 09:13:49 AM UTC 24 |
Sep 11 09:13:51 AM UTC 24 |
38482265 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3354781285 |
|
|
Sep 11 09:10:40 AM UTC 24 |
Sep 11 09:14:03 AM UTC 24 |
2243824259 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2522119433 |
|
|
Sep 11 09:05:53 AM UTC 24 |
Sep 11 09:14:08 AM UTC 24 |
4327624804 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.920522578 |
|
|
Sep 11 09:13:51 AM UTC 24 |
Sep 11 09:14:09 AM UTC 24 |
2595855918 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3761684880 |
|
|
Sep 11 09:14:09 AM UTC 24 |
Sep 11 09:14:12 AM UTC 24 |
30307710 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.3541382423 |
|
|
Sep 11 09:04:24 AM UTC 24 |
Sep 11 09:14:14 AM UTC 24 |
25341292914 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2794099901 |
|
|
Sep 11 09:14:12 AM UTC 24 |
Sep 11 09:14:20 AM UTC 24 |
284652036 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2956167725 |
|
|
Sep 11 09:14:15 AM UTC 24 |
Sep 11 09:14:22 AM UTC 24 |
91270026 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3418877581 |
|
|
Sep 11 09:08:10 AM UTC 24 |
Sep 11 09:14:25 AM UTC 24 |
44406016394 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.2622611720 |
|
|
Sep 11 09:14:26 AM UTC 24 |
Sep 11 09:14:28 AM UTC 24 |
75331404 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1807456113 |
|
|
Sep 11 09:12:50 AM UTC 24 |
Sep 11 09:14:30 AM UTC 24 |
5431027276 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1400272835 |
|
|
Sep 11 09:09:51 AM UTC 24 |
Sep 11 09:14:33 AM UTC 24 |
38489972269 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.837428687 |
|
|
Sep 11 09:14:29 AM UTC 24 |
Sep 11 09:14:36 AM UTC 24 |
121101495 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.60400312 |
|
|
Sep 11 09:14:21 AM UTC 24 |
Sep 11 09:15:05 AM UTC 24 |
2759241442 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3349048204 |
|
|
Sep 11 09:10:19 AM UTC 24 |
Sep 11 09:15:08 AM UTC 24 |
2042501862 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3977004000 |
|
|
Sep 11 09:15:06 AM UTC 24 |
Sep 11 09:15:10 AM UTC 24 |
210953484 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.395537133 |
|
|
Sep 11 09:13:29 AM UTC 24 |
Sep 11 09:15:10 AM UTC 24 |
690610558 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1250368992 |
|
|
Sep 11 09:10:06 AM UTC 24 |
Sep 11 09:15:28 AM UTC 24 |
16368612048 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1393374698 |
|
|
Sep 11 09:15:29 AM UTC 24 |
Sep 11 09:15:35 AM UTC 24 |
301296110 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.978658535 |
|
|
Sep 11 09:04:54 AM UTC 24 |
Sep 11 09:15:45 AM UTC 24 |
35534233532 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3429807450 |
|
|
Sep 11 09:15:11 AM UTC 24 |
Sep 11 09:15:47 AM UTC 24 |
96261607 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.4284030128 |
|
|
Sep 11 09:14:33 AM UTC 24 |
Sep 11 09:15:47 AM UTC 24 |
3556804236 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.2954381145 |
|
|
Sep 11 09:15:49 AM UTC 24 |
Sep 11 09:15:51 AM UTC 24 |
54045279 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.750931157 |
|
|
Sep 11 09:15:52 AM UTC 24 |
Sep 11 09:16:00 AM UTC 24 |
192169266 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2501229251 |
|
|
Sep 11 09:15:12 AM UTC 24 |
Sep 11 09:16:01 AM UTC 24 |
878848371 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3812375695 |
|
|
Sep 11 08:47:10 AM UTC 24 |
Sep 11 09:16:03 AM UTC 24 |
54322171636 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1179436872 |
|
|
Sep 11 09:00:53 AM UTC 24 |
Sep 11 09:16:04 AM UTC 24 |
47008559819 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.4253723012 |
|
|
Sep 11 09:16:05 AM UTC 24 |
Sep 11 09:16:07 AM UTC 24 |
15395169 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2531221016 |
|
|
Sep 11 09:16:02 AM UTC 24 |
Sep 11 09:16:08 AM UTC 24 |
224719719 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.173749325 |
|
|
Sep 11 09:05:31 AM UTC 24 |
Sep 11 09:16:19 AM UTC 24 |
2898313472 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.432721816 |
|
|
Sep 11 09:13:17 AM UTC 24 |
Sep 11 09:16:21 AM UTC 24 |
2147504792 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2217512668 |
|
|
Sep 11 09:11:09 AM UTC 24 |
Sep 11 09:16:33 AM UTC 24 |
9657675766 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.617223787 |
|
|
Sep 11 08:56:17 AM UTC 24 |
Sep 11 09:16:35 AM UTC 24 |
85680413698 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1268105969 |
|
|
Sep 11 08:52:25 AM UTC 24 |
Sep 11 09:16:44 AM UTC 24 |
79916313999 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2502144920 |
|
|
Sep 11 08:59:00 AM UTC 24 |
Sep 11 09:16:52 AM UTC 24 |
3046752141 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.921973877 |
|
|
Sep 11 09:16:53 AM UTC 24 |
Sep 11 09:16:57 AM UTC 24 |
421855246 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2000096156 |
|
|
Sep 11 09:16:19 AM UTC 24 |
Sep 11 09:16:59 AM UTC 24 |
9067501990 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.685568768 |
|
|
Sep 11 09:16:08 AM UTC 24 |
Sep 11 09:16:59 AM UTC 24 |
492722913 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.3220177183 |
|
|
Sep 11 08:59:07 AM UTC 24 |
Sep 11 09:17:06 AM UTC 24 |
12335795056 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2365382804 |
|
|
Sep 11 09:07:05 AM UTC 24 |
Sep 11 09:17:10 AM UTC 24 |
3738428307 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1064509036 |
|
|
Sep 11 09:16:58 AM UTC 24 |
Sep 11 09:17:10 AM UTC 24 |
1967919142 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1356115195 |
|
|
Sep 11 09:16:35 AM UTC 24 |
Sep 11 09:17:11 AM UTC 24 |
453054673 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.900532559 |
|
|
Sep 11 09:17:11 AM UTC 24 |
Sep 11 09:17:13 AM UTC 24 |
56023536 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3547707778 |
|
|
Sep 11 09:17:13 AM UTC 24 |
Sep 11 09:17:22 AM UTC 24 |
175589307 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.507160416 |
|
|
Sep 11 09:16:45 AM UTC 24 |
Sep 11 09:17:23 AM UTC 24 |
362526204 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3695730142 |
|
|
Sep 11 09:17:24 AM UTC 24 |
Sep 11 09:17:26 AM UTC 24 |
13859648 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.803819418 |
|
|
Sep 11 08:55:58 AM UTC 24 |
Sep 11 09:17:27 AM UTC 24 |
24716077324 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.636589996 |
|
|
Sep 11 08:58:04 AM UTC 24 |
Sep 11 09:17:27 AM UTC 24 |
54279145575 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1940121697 |
|
|
Sep 11 09:11:15 AM UTC 24 |
Sep 11 09:17:29 AM UTC 24 |
37054744238 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.785459106 |
|
|
Sep 11 09:17:11 AM UTC 24 |
Sep 11 09:17:34 AM UTC 24 |
5939893735 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2709050981 |
|
|
Sep 11 09:17:27 AM UTC 24 |
Sep 11 09:17:38 AM UTC 24 |
324245867 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4188627264 |
|
|
Sep 11 09:15:36 AM UTC 24 |
Sep 11 09:17:41 AM UTC 24 |
1226733341 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2785118671 |
|
|
Sep 11 08:40:46 AM UTC 24 |
Sep 11 09:17:43 AM UTC 24 |
19706182153 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.245362356 |
|
|
Sep 11 09:16:02 AM UTC 24 |
Sep 11 09:17:46 AM UTC 24 |
1833239030 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2564280905 |
|
|
Sep 11 08:55:02 AM UTC 24 |
Sep 11 09:17:46 AM UTC 24 |
13508884877 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.1555237272 |
|
|
Sep 11 09:04:24 AM UTC 24 |
Sep 11 09:17:53 AM UTC 24 |
25104637605 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.3760828165 |
|
|
Sep 11 08:57:43 AM UTC 24 |
Sep 11 09:17:54 AM UTC 24 |
14506062006 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2003130663 |
|
|
Sep 11 09:17:43 AM UTC 24 |
Sep 11 09:17:55 AM UTC 24 |
252260094 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2868442078 |
|
|
Sep 11 09:13:25 AM UTC 24 |
Sep 11 09:17:58 AM UTC 24 |
3502898693 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1861704938 |
|
|
Sep 11 09:17:56 AM UTC 24 |
Sep 11 09:17:58 AM UTC 24 |
50083636 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2632405437 |
|
|
Sep 11 09:17:46 AM UTC 24 |
Sep 11 09:18:00 AM UTC 24 |
2742949398 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1676208293 |
|
|
Sep 11 09:17:35 AM UTC 24 |
Sep 11 09:18:02 AM UTC 24 |
6642218103 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.2442433500 |
|
|
Sep 11 09:17:59 AM UTC 24 |
Sep 11 09:18:03 AM UTC 24 |
186137260 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2641931024 |
|
|
Sep 11 09:18:04 AM UTC 24 |
Sep 11 09:18:06 AM UTC 24 |
14526175 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1932207757 |
|
|
Sep 11 09:17:59 AM UTC 24 |
Sep 11 09:18:08 AM UTC 24 |
237091249 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1442930548 |
|
|
Sep 11 09:17:28 AM UTC 24 |
Sep 11 09:18:10 AM UTC 24 |
8772641402 ps |