| T553 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.4222306891 |
|
|
Sep 11 09:16:08 AM UTC 24 |
Sep 11 09:18:11 AM UTC 24 |
1332437224 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3379032112 |
|
|
Sep 11 09:09:39 AM UTC 24 |
Sep 11 09:18:17 AM UTC 24 |
2000704969 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.413488945 |
|
|
Sep 11 09:18:08 AM UTC 24 |
Sep 11 09:18:19 AM UTC 24 |
367588214 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.707087367 |
|
|
Sep 11 08:49:09 AM UTC 24 |
Sep 11 09:18:24 AM UTC 24 |
27740636487 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2882956546 |
|
|
Sep 11 09:14:37 AM UTC 24 |
Sep 11 09:18:38 AM UTC 24 |
9455387804 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.408442858 |
|
|
Sep 11 09:06:00 AM UTC 24 |
Sep 11 09:18:40 AM UTC 24 |
2685490181 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2836639849 |
|
|
Sep 11 09:17:42 AM UTC 24 |
Sep 11 09:18:46 AM UTC 24 |
249817648 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1298219826 |
|
|
Sep 11 09:18:18 AM UTC 24 |
Sep 11 09:18:46 AM UTC 24 |
3714810958 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.842880345 |
|
|
Sep 11 09:18:42 AM UTC 24 |
Sep 11 09:18:55 AM UTC 24 |
3244682870 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.2894334464 |
|
|
Sep 11 09:18:11 AM UTC 24 |
Sep 11 09:18:55 AM UTC 24 |
9078698608 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.668273841 |
|
|
Sep 11 09:17:07 AM UTC 24 |
Sep 11 09:18:57 AM UTC 24 |
2984157551 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2749943805 |
|
|
Sep 11 09:18:56 AM UTC 24 |
Sep 11 09:18:58 AM UTC 24 |
86595134 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.464947609 |
|
|
Sep 11 09:15:09 AM UTC 24 |
Sep 11 09:19:02 AM UTC 24 |
8676149553 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3741154255 |
|
|
Sep 11 09:18:38 AM UTC 24 |
Sep 11 09:19:05 AM UTC 24 |
166493327 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2301616331 |
|
|
Sep 11 09:18:59 AM UTC 24 |
Sep 11 09:19:07 AM UTC 24 |
80784517 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1395407635 |
|
|
Sep 11 09:19:07 AM UTC 24 |
Sep 11 09:19:09 AM UTC 24 |
17213465 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3417069983 |
|
|
Sep 11 09:18:58 AM UTC 24 |
Sep 11 09:19:12 AM UTC 24 |
1698660892 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.885980782 |
|
|
Sep 11 09:19:11 AM UTC 24 |
Sep 11 09:19:25 AM UTC 24 |
529938642 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2373338570 |
|
|
Sep 11 09:18:25 AM UTC 24 |
Sep 11 09:20:05 AM UTC 24 |
516193625 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.477182068 |
|
|
Sep 11 09:19:26 AM UTC 24 |
Sep 11 09:20:17 AM UTC 24 |
9184575742 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.688394917 |
|
|
Sep 11 08:59:41 AM UTC 24 |
Sep 11 09:20:25 AM UTC 24 |
41608670139 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2877733868 |
|
|
Sep 11 09:20:18 AM UTC 24 |
Sep 11 09:20:32 AM UTC 24 |
1126997295 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3359517970 |
|
|
Sep 11 09:17:30 AM UTC 24 |
Sep 11 09:20:45 AM UTC 24 |
10168675650 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3163387797 |
|
|
Sep 11 09:17:39 AM UTC 24 |
Sep 11 09:20:55 AM UTC 24 |
2066043661 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1888923592 |
|
|
Sep 11 09:20:56 AM UTC 24 |
Sep 11 09:21:03 AM UTC 24 |
566317895 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3443701270 |
|
|
Sep 11 08:52:00 AM UTC 24 |
Sep 11 09:21:18 AM UTC 24 |
79498792900 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.4146367183 |
|
|
Sep 11 09:08:31 AM UTC 24 |
Sep 11 09:21:23 AM UTC 24 |
12644416607 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1589344305 |
|
|
Sep 11 09:20:33 AM UTC 24 |
Sep 11 09:21:27 AM UTC 24 |
110134981 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.435573818 |
|
|
Sep 11 09:21:27 AM UTC 24 |
Sep 11 09:21:30 AM UTC 24 |
49286542 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3939538753 |
|
|
Sep 11 09:18:12 AM UTC 24 |
Sep 11 09:21:36 AM UTC 24 |
3859084919 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.794502990 |
|
|
Sep 11 09:10:23 AM UTC 24 |
Sep 11 09:21:37 AM UTC 24 |
28506529436 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.4143625706 |
|
|
Sep 11 09:21:35 AM UTC 24 |
Sep 11 09:21:40 AM UTC 24 |
197228572 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.952708905 |
|
|
Sep 11 09:21:19 AM UTC 24 |
Sep 11 09:21:41 AM UTC 24 |
321500763 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.568746729 |
|
|
Sep 11 09:21:41 AM UTC 24 |
Sep 11 09:21:43 AM UTC 24 |
41713919 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1658725586 |
|
|
Sep 11 09:21:31 AM UTC 24 |
Sep 11 09:21:47 AM UTC 24 |
3594279406 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2943836711 |
|
|
Sep 11 09:05:28 AM UTC 24 |
Sep 11 09:21:48 AM UTC 24 |
16685096873 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.188783783 |
|
|
Sep 11 09:21:42 AM UTC 24 |
Sep 11 09:21:51 AM UTC 24 |
1369258450 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3264908370 |
|
|
Sep 11 09:11:57 AM UTC 24 |
Sep 11 09:21:58 AM UTC 24 |
30914940840 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3961916502 |
|
|
Sep 11 09:12:02 AM UTC 24 |
Sep 11 09:22:01 AM UTC 24 |
9947297167 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3103658727 |
|
|
Sep 11 09:17:14 AM UTC 24 |
Sep 11 09:22:04 AM UTC 24 |
1711524299 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4224346115 |
|
|
Sep 11 09:18:01 AM UTC 24 |
Sep 11 09:22:05 AM UTC 24 |
559355196 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3144683566 |
|
|
Sep 11 09:21:52 AM UTC 24 |
Sep 11 09:22:07 AM UTC 24 |
606811873 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2077140118 |
|
|
Sep 11 09:22:06 AM UTC 24 |
Sep 11 09:22:10 AM UTC 24 |
379564647 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.4120564105 |
|
|
Sep 11 09:22:05 AM UTC 24 |
Sep 11 09:22:11 AM UTC 24 |
95724235 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2831391510 |
|
|
Sep 11 09:20:47 AM UTC 24 |
Sep 11 09:22:32 AM UTC 24 |
151447007 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2783986869 |
|
|
Sep 11 09:22:33 AM UTC 24 |
Sep 11 09:22:35 AM UTC 24 |
78784910 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.295566323 |
|
|
Sep 11 08:41:14 AM UTC 24 |
Sep 11 09:22:37 AM UTC 24 |
107273592333 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2195483702 |
|
|
Sep 11 09:22:38 AM UTC 24 |
Sep 11 09:22:42 AM UTC 24 |
102349553 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3442861489 |
|
|
Sep 11 09:22:36 AM UTC 24 |
Sep 11 09:22:44 AM UTC 24 |
118123122 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1008373143 |
|
|
Sep 11 09:14:31 AM UTC 24 |
Sep 11 09:22:54 AM UTC 24 |
9211114223 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.2119526163 |
|
|
Sep 11 09:22:55 AM UTC 24 |
Sep 11 09:22:57 AM UTC 24 |
27424453 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2260839875 |
|
|
Sep 11 09:21:37 AM UTC 24 |
Sep 11 09:23:02 AM UTC 24 |
4515308481 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2899483090 |
|
|
Sep 11 09:16:21 AM UTC 24 |
Sep 11 09:23:02 AM UTC 24 |
3391543031 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.4256871857 |
|
|
Sep 11 09:22:58 AM UTC 24 |
Sep 11 09:23:03 AM UTC 24 |
301161461 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1285394578 |
|
|
Sep 11 09:21:47 AM UTC 24 |
Sep 11 09:23:07 AM UTC 24 |
12458864157 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2022421523 |
|
|
Sep 11 09:22:43 AM UTC 24 |
Sep 11 09:23:07 AM UTC 24 |
563359724 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1644743169 |
|
|
Sep 11 09:22:02 AM UTC 24 |
Sep 11 09:23:14 AM UTC 24 |
136307196 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2322573528 |
|
|
Sep 11 09:23:15 AM UTC 24 |
Sep 11 09:23:26 AM UTC 24 |
236258089 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.673955197 |
|
|
Sep 11 09:23:08 AM UTC 24 |
Sep 11 09:23:31 AM UTC 24 |
5001286978 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1506604747 |
|
|
Sep 11 09:23:27 AM UTC 24 |
Sep 11 09:23:32 AM UTC 24 |
52965553 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.108807903 |
|
|
Sep 11 09:23:03 AM UTC 24 |
Sep 11 09:23:33 AM UTC 24 |
3919719762 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1017799454 |
|
|
Sep 11 09:23:32 AM UTC 24 |
Sep 11 09:23:36 AM UTC 24 |
414748417 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1947300254 |
|
|
Sep 11 09:16:36 AM UTC 24 |
Sep 11 09:23:43 AM UTC 24 |
5887026581 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.770761419 |
|
|
Sep 11 09:23:45 AM UTC 24 |
Sep 11 09:23:47 AM UTC 24 |
30570451 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3869953865 |
|
|
Sep 11 09:15:46 AM UTC 24 |
Sep 11 09:23:53 AM UTC 24 |
1915934680 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2660344233 |
|
|
Sep 11 09:23:48 AM UTC 24 |
Sep 11 09:23:55 AM UTC 24 |
77014204 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.2084147533 |
|
|
Sep 11 09:23:37 AM UTC 24 |
Sep 11 09:23:58 AM UTC 24 |
1606027043 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.1642848475 |
|
|
Sep 11 09:23:54 AM UTC 24 |
Sep 11 09:23:59 AM UTC 24 |
114613474 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2572947980 |
|
|
Sep 11 09:24:00 AM UTC 24 |
Sep 11 09:24:02 AM UTC 24 |
43704854 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2603087777 |
|
|
Sep 11 09:24:03 AM UTC 24 |
Sep 11 09:24:19 AM UTC 24 |
1278693021 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2173110318 |
|
|
Sep 11 09:23:55 AM UTC 24 |
Sep 11 09:24:23 AM UTC 24 |
1485052686 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.980206398 |
|
|
Sep 11 09:16:59 AM UTC 24 |
Sep 11 09:24:33 AM UTC 24 |
25385451798 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.115211921 |
|
|
Sep 11 09:18:20 AM UTC 24 |
Sep 11 09:24:42 AM UTC 24 |
154096074246 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.4050517812 |
|
|
Sep 11 09:02:18 AM UTC 24 |
Sep 11 09:24:45 AM UTC 24 |
15849719048 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1574637382 |
|
|
Sep 11 09:24:43 AM UTC 24 |
Sep 11 09:24:51 AM UTC 24 |
400101235 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2757290542 |
|
|
Sep 11 08:51:00 AM UTC 24 |
Sep 11 09:24:57 AM UTC 24 |
53062246331 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2270939944 |
|
|
Sep 11 09:24:25 AM UTC 24 |
Sep 11 09:25:03 AM UTC 24 |
959017176 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2129661256 |
|
|
Sep 11 09:18:48 AM UTC 24 |
Sep 11 09:25:15 AM UTC 24 |
2016435613 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3999332428 |
|
|
Sep 11 09:25:04 AM UTC 24 |
Sep 11 09:25:16 AM UTC 24 |
2654823438 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2269083930 |
|
|
Sep 11 09:12:48 AM UTC 24 |
Sep 11 09:25:32 AM UTC 24 |
65678459838 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.1052529165 |
|
|
Sep 11 09:17:00 AM UTC 24 |
Sep 11 09:25:33 AM UTC 24 |
1821142582 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.28735429 |
|
|
Sep 11 09:10:22 AM UTC 24 |
Sep 11 09:25:34 AM UTC 24 |
2487441734 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.882102224 |
|
|
Sep 11 09:25:33 AM UTC 24 |
Sep 11 09:25:35 AM UTC 24 |
84385179 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.4011720053 |
|
|
Sep 11 09:25:36 AM UTC 24 |
Sep 11 09:25:40 AM UTC 24 |
79049355 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.901277211 |
|
|
Sep 11 09:25:34 AM UTC 24 |
Sep 11 09:25:41 AM UTC 24 |
154821035 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1421466608 |
|
|
Sep 11 09:24:51 AM UTC 24 |
Sep 11 09:25:44 AM UTC 24 |
129425888 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1124796310 |
|
|
Sep 11 09:04:21 AM UTC 24 |
Sep 11 09:25:46 AM UTC 24 |
3501360286 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.772201413 |
|
|
Sep 11 09:25:45 AM UTC 24 |
Sep 11 09:25:46 AM UTC 24 |
12408614 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.379030637 |
|
|
Sep 11 09:20:06 AM UTC 24 |
Sep 11 09:25:51 AM UTC 24 |
12662222854 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2686396902 |
|
|
Sep 11 09:25:47 AM UTC 24 |
Sep 11 09:25:56 AM UTC 24 |
273665649 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3958379661 |
|
|
Sep 11 09:21:49 AM UTC 24 |
Sep 11 09:26:27 AM UTC 24 |
11342957684 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.4170769884 |
|
|
Sep 11 09:26:28 AM UTC 24 |
Sep 11 09:26:35 AM UTC 24 |
888507160 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1198427557 |
|
|
Sep 11 09:13:52 AM UTC 24 |
Sep 11 09:26:37 AM UTC 24 |
6537840467 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.631570933 |
|
|
Sep 11 09:24:57 AM UTC 24 |
Sep 11 09:26:42 AM UTC 24 |
938440863 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.335829449 |
|
|
Sep 11 09:17:28 AM UTC 24 |
Sep 11 09:26:45 AM UTC 24 |
2632042182 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.3424285020 |
|
|
Sep 11 09:25:52 AM UTC 24 |
Sep 11 09:26:46 AM UTC 24 |
750812876 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.883771035 |
|
|
Sep 11 09:26:37 AM UTC 24 |
Sep 11 09:26:48 AM UTC 24 |
76021011 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3047444012 |
|
|
Sep 11 09:26:46 AM UTC 24 |
Sep 11 09:26:53 AM UTC 24 |
1006384006 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3076622024 |
|
|
Sep 11 09:17:47 AM UTC 24 |
Sep 11 09:26:55 AM UTC 24 |
30141693723 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1821725001 |
|
|
Sep 11 09:26:56 AM UTC 24 |
Sep 11 09:26:58 AM UTC 24 |
57231560 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2580343597 |
|
|
Sep 11 09:26:59 AM UTC 24 |
Sep 11 09:27:08 AM UTC 24 |
1330575548 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1383121393 |
|
|
Sep 11 09:27:09 AM UTC 24 |
Sep 11 09:27:18 AM UTC 24 |
758751140 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1448812080 |
|
|
Sep 11 09:26:43 AM UTC 24 |
Sep 11 09:27:22 AM UTC 24 |
113679664 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2655240090 |
|
|
Sep 11 09:20:26 AM UTC 24 |
Sep 11 09:27:52 AM UTC 24 |
5751268135 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.988939336 |
|
|
Sep 11 09:27:53 AM UTC 24 |
Sep 11 09:27:55 AM UTC 24 |
18881562 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2969927174 |
|
|
Sep 11 09:25:57 AM UTC 24 |
Sep 11 09:28:01 AM UTC 24 |
2146845066 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.1607957421 |
|
|
Sep 11 09:27:56 AM UTC 24 |
Sep 11 09:28:05 AM UTC 24 |
1605132596 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1929900318 |
|
|
Sep 11 09:18:03 AM UTC 24 |
Sep 11 09:28:17 AM UTC 24 |
21358556232 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1523490028 |
|
|
Sep 11 09:24:34 AM UTC 24 |
Sep 11 09:28:29 AM UTC 24 |
2482431499 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.427337403 |
|
|
Sep 11 09:22:11 AM UTC 24 |
Sep 11 09:28:37 AM UTC 24 |
5450638695 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.3358612899 |
|
|
Sep 11 09:14:09 AM UTC 24 |
Sep 11 09:28:45 AM UTC 24 |
7716065729 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.4179303000 |
|
|
Sep 11 09:14:04 AM UTC 24 |
Sep 11 09:29:09 AM UTC 24 |
11466755362 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1379852417 |
|
|
Sep 11 09:25:41 AM UTC 24 |
Sep 11 09:29:10 AM UTC 24 |
568062370 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3637548778 |
|
|
Sep 11 09:21:59 AM UTC 24 |
Sep 11 09:29:14 AM UTC 24 |
23468901086 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1790391159 |
|
|
Sep 11 09:07:37 AM UTC 24 |
Sep 11 09:29:15 AM UTC 24 |
20310765676 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1687852346 |
|
|
Sep 11 09:29:11 AM UTC 24 |
Sep 11 09:29:21 AM UTC 24 |
1111386352 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1539722966 |
|
|
Sep 11 09:02:24 AM UTC 24 |
Sep 11 09:29:25 AM UTC 24 |
14801387135 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4161815809 |
|
|
Sep 11 09:29:25 AM UTC 24 |
Sep 11 09:29:28 AM UTC 24 |
88456969 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1004297628 |
|
|
Sep 11 09:28:45 AM UTC 24 |
Sep 11 09:29:30 AM UTC 24 |
421306494 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2167962511 |
|
|
Sep 11 09:29:28 AM UTC 24 |
Sep 11 09:29:34 AM UTC 24 |
271685318 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3817442180 |
|
|
Sep 11 09:29:32 AM UTC 24 |
Sep 11 09:29:38 AM UTC 24 |
66203348 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2173557337 |
|
|
Sep 11 09:28:30 AM UTC 24 |
Sep 11 09:29:54 AM UTC 24 |
738269584 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1991058251 |
|
|
Sep 11 09:23:08 AM UTC 24 |
Sep 11 09:29:55 AM UTC 24 |
28502887501 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.222847742 |
|
|
Sep 11 09:18:48 AM UTC 24 |
Sep 11 09:29:56 AM UTC 24 |
16007162137 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.750957219 |
|
|
Sep 11 09:28:06 AM UTC 24 |
Sep 11 09:29:57 AM UTC 24 |
38567623743 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.223055759 |
|
|
Sep 11 09:29:55 AM UTC 24 |
Sep 11 09:29:57 AM UTC 24 |
18465751 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1735203531 |
|
|
Sep 11 09:23:05 AM UTC 24 |
Sep 11 09:30:00 AM UTC 24 |
71855618444 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.4082234244 |
|
|
Sep 11 09:30:00 AM UTC 24 |
Sep 11 09:30:17 AM UTC 24 |
465958255 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1870415057 |
|
|
Sep 11 09:23:33 AM UTC 24 |
Sep 11 09:30:19 AM UTC 24 |
1651211525 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2937277823 |
|
|
Sep 11 09:29:10 AM UTC 24 |
Sep 11 09:30:25 AM UTC 24 |
732134064 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3811697722 |
|
|
Sep 11 09:17:55 AM UTC 24 |
Sep 11 09:30:28 AM UTC 24 |
3833075292 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3830683032 |
|
|
Sep 11 09:30:20 AM UTC 24 |
Sep 11 09:30:35 AM UTC 24 |
100615606 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3604360855 |
|
|
Sep 11 09:30:29 AM UTC 24 |
Sep 11 09:30:41 AM UTC 24 |
2852877889 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.1807548972 |
|
|
Sep 11 09:29:58 AM UTC 24 |
Sep 11 09:30:42 AM UTC 24 |
1806120331 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3009844057 |
|
|
Sep 11 09:18:09 AM UTC 24 |
Sep 11 09:30:45 AM UTC 24 |
2117130021 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.962732773 |
|
|
Sep 11 09:30:46 AM UTC 24 |
Sep 11 09:30:48 AM UTC 24 |
81737433 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.749927774 |
|
|
Sep 11 09:30:49 AM UTC 24 |
Sep 11 09:30:55 AM UTC 24 |
983337397 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3937752021 |
|
|
Sep 11 09:30:56 AM UTC 24 |
Sep 11 09:31:04 AM UTC 24 |
336153756 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2259342063 |
|
|
Sep 11 09:29:56 AM UTC 24 |
Sep 11 09:31:05 AM UTC 24 |
967479719 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4236033765 |
|
|
Sep 11 09:27:19 AM UTC 24 |
Sep 11 09:31:36 AM UTC 24 |
2378906015 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2503200939 |
|
|
Sep 11 09:31:37 AM UTC 24 |
Sep 11 09:31:39 AM UTC 24 |
53617870 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.2629501343 |
|
|
Sep 11 09:31:40 AM UTC 24 |
Sep 11 09:31:55 AM UTC 24 |
189287869 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2466625543 |
|
|
Sep 11 09:28:18 AM UTC 24 |
Sep 11 09:32:13 AM UTC 24 |
7872418768 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.210722964 |
|
|
Sep 11 09:30:26 AM UTC 24 |
Sep 11 09:32:14 AM UTC 24 |
302240184 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.1924150486 |
|
|
Sep 11 09:18:56 AM UTC 24 |
Sep 11 09:32:16 AM UTC 24 |
5294017021 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1444823097 |
|
|
Sep 11 09:24:46 AM UTC 24 |
Sep 11 09:32:17 AM UTC 24 |
5041883562 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1758998078 |
|
|
Sep 11 09:26:36 AM UTC 24 |
Sep 11 09:32:36 AM UTC 24 |
19125488768 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1738149280 |
|
|
Sep 11 09:32:13 AM UTC 24 |
Sep 11 09:32:39 AM UTC 24 |
3490502994 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2096026534 |
|
|
Sep 11 09:32:17 AM UTC 24 |
Sep 11 09:32:43 AM UTC 24 |
1201474933 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3057655468 |
|
|
Sep 11 09:29:35 AM UTC 24 |
Sep 11 09:32:52 AM UTC 24 |
2154053197 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3307049567 |
|
|
Sep 11 09:32:44 AM UTC 24 |
Sep 11 09:32:58 AM UTC 24 |
674819605 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2994254600 |
|
|
Sep 11 09:32:37 AM UTC 24 |
Sep 11 09:33:27 AM UTC 24 |
103451169 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.2541361881 |
|
|
Sep 11 09:32:40 AM UTC 24 |
Sep 11 09:34:04 AM UTC 24 |
138337273 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.1738222434 |
|
|
Sep 11 09:34:05 AM UTC 24 |
Sep 11 09:34:07 AM UTC 24 |
119738777 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.4103360185 |
|
|
Sep 11 09:34:08 AM UTC 24 |
Sep 11 09:34:22 AM UTC 24 |
1368183676 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.216807945 |
|
|
Sep 11 09:25:48 AM UTC 24 |
Sep 11 09:34:23 AM UTC 24 |
89175627812 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.892831229 |
|
|
Sep 11 09:30:36 AM UTC 24 |
Sep 11 09:34:24 AM UTC 24 |
2781102278 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.721471229 |
|
|
Sep 11 09:34:23 AM UTC 24 |
Sep 11 09:34:28 AM UTC 24 |
91405139 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1118986857 |
|
|
Sep 11 09:34:29 AM UTC 24 |
Sep 11 09:34:31 AM UTC 24 |
26242269 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1426820815 |
|
|
Sep 11 09:12:38 AM UTC 24 |
Sep 11 09:34:53 AM UTC 24 |
27558949151 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2343873148 |
|
|
Sep 11 09:34:24 AM UTC 24 |
Sep 11 09:34:54 AM UTC 24 |
1116264251 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.800577783 |
|
|
Sep 11 09:15:47 AM UTC 24 |
Sep 11 09:35:14 AM UTC 24 |
50510837273 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2818081865 |
|
|
Sep 11 09:35:35 AM UTC 24 |
Sep 11 09:35:38 AM UTC 24 |
108660243 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1063063802 |
|
|
Sep 11 09:19:13 AM UTC 24 |
Sep 11 09:35:40 AM UTC 24 |
16475421239 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.4283263111 |
|
|
Sep 11 09:34:32 AM UTC 24 |
Sep 11 09:35:45 AM UTC 24 |
248765628 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.3014887775 |
|
|
Sep 11 09:35:41 AM UTC 24 |
Sep 11 09:35:48 AM UTC 24 |
55288802 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3097376180 |
|
|
Sep 11 09:29:15 AM UTC 24 |
Sep 11 09:35:50 AM UTC 24 |
41494996174 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3966883711 |
|
|
Sep 11 09:29:58 AM UTC 24 |
Sep 11 09:35:53 AM UTC 24 |
3170561217 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3180660475 |
|
|
Sep 11 09:34:55 AM UTC 24 |
Sep 11 09:35:54 AM UTC 24 |
1026250179 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1032359029 |
|
|
Sep 11 09:35:48 AM UTC 24 |
Sep 11 09:35:56 AM UTC 24 |
871081291 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3366646024 |
|
|
Sep 11 09:35:45 AM UTC 24 |
Sep 11 09:35:56 AM UTC 24 |
442381871 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2691339186 |
|
|
Sep 11 08:45:54 AM UTC 24 |
Sep 11 09:35:57 AM UTC 24 |
9531817889 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2740735358 |
|
|
Sep 11 09:35:57 AM UTC 24 |
Sep 11 09:35:59 AM UTC 24 |
279077212 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.3972968227 |
|
|
Sep 11 09:35:57 AM UTC 24 |
Sep 11 09:36:05 AM UTC 24 |
682175199 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2766192745 |
|
|
Sep 11 09:35:58 AM UTC 24 |
Sep 11 09:36:06 AM UTC 24 |
613849943 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3382044483 |
|
|
Sep 11 09:36:06 AM UTC 24 |
Sep 11 09:36:08 AM UTC 24 |
16701662 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3879076580 |
|
|
Sep 11 09:21:44 AM UTC 24 |
Sep 11 09:36:27 AM UTC 24 |
53234211678 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2228631430 |
|
|
Sep 11 09:36:09 AM UTC 24 |
Sep 11 09:36:27 AM UTC 24 |
3053918565 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.4172408118 |
|
|
Sep 11 09:17:53 AM UTC 24 |
Sep 11 09:36:48 AM UTC 24 |
36659962904 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2514452959 |
|
|
Sep 11 09:32:15 AM UTC 24 |
Sep 11 09:37:04 AM UTC 24 |
2911084079 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1348020991 |
|
|
Sep 11 09:21:04 AM UTC 24 |
Sep 11 09:37:07 AM UTC 24 |
18221004047 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2296214931 |
|
|
Sep 11 09:30:18 AM UTC 24 |
Sep 11 09:37:15 AM UTC 24 |
51742344487 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.78128529 |
|
|
Sep 11 09:28:38 AM UTC 24 |
Sep 11 09:37:24 AM UTC 24 |
23941687394 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2761323832 |
|
|
Sep 11 09:37:16 AM UTC 24 |
Sep 11 09:37:40 AM UTC 24 |
286421547 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.154299191 |
|
|
Sep 11 09:36:28 AM UTC 24 |
Sep 11 09:37:42 AM UTC 24 |
4756953592 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.2390623715 |
|
|
Sep 11 09:37:24 AM UTC 24 |
Sep 11 09:37:44 AM UTC 24 |
79294854 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3517786441 |
|
|
Sep 11 09:37:41 AM UTC 24 |
Sep 11 09:37:50 AM UTC 24 |
4836680462 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3041213894 |
|
|
Sep 11 09:32:18 AM UTC 24 |
Sep 11 09:37:55 AM UTC 24 |
31991466051 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3426831947 |
|
|
Sep 11 09:37:56 AM UTC 24 |
Sep 11 09:37:58 AM UTC 24 |
43412859 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.58481925 |
|
|
Sep 11 09:37:43 AM UTC 24 |
Sep 11 09:38:01 AM UTC 24 |
371617211 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2541180039 |
|
|
Sep 11 09:37:59 AM UTC 24 |
Sep 11 09:38:08 AM UTC 24 |
1603163280 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1735059298 |
|
|
Sep 11 09:38:02 AM UTC 24 |
Sep 11 09:38:09 AM UTC 24 |
176545268 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.2203852132 |
|
|
Sep 11 09:35:55 AM UTC 24 |
Sep 11 09:38:10 AM UTC 24 |
12607703583 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1181629044 |
|
|
Sep 11 09:38:10 AM UTC 24 |
Sep 11 09:38:12 AM UTC 24 |
53105279 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3565309830 |
|
|
Sep 11 09:07:31 AM UTC 24 |
Sep 11 09:38:20 AM UTC 24 |
102275209010 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.3102710157 |
|
|
Sep 11 09:21:23 AM UTC 24 |
Sep 11 09:38:22 AM UTC 24 |
15973604482 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3148693600 |
|
|
Sep 11 09:35:15 AM UTC 24 |
Sep 11 09:38:27 AM UTC 24 |
3205410118 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.358288859 |
|
|
Sep 11 09:25:33 AM UTC 24 |
Sep 11 09:38:34 AM UTC 24 |
6728017996 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2307426107 |
|
|
Sep 11 09:38:35 AM UTC 24 |
Sep 11 09:38:44 AM UTC 24 |
496293945 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3843944460 |
|
|
Sep 11 09:37:05 AM UTC 24 |
Sep 11 09:38:51 AM UTC 24 |
1290650978 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.6028709 |
|
|
Sep 11 09:30:41 AM UTC 24 |
Sep 11 09:38:59 AM UTC 24 |
6703425122 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.961001739 |
|
|
Sep 11 09:38:23 AM UTC 24 |
Sep 11 09:39:00 AM UTC 24 |
485754550 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.340102252 |
|
|
Sep 11 09:39:00 AM UTC 24 |
Sep 11 09:39:11 AM UTC 24 |
71486365 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.817011383 |
|
|
Sep 11 09:39:02 AM UTC 24 |
Sep 11 09:39:14 AM UTC 24 |
559015219 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3613241031 |
|
|
Sep 11 09:36:00 AM UTC 24 |
Sep 11 09:39:33 AM UTC 24 |
368837902 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.2686503828 |
|
|
Sep 11 09:38:51 AM UTC 24 |
Sep 11 09:39:43 AM UTC 24 |
368060803 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1324631901 |
|
|
Sep 11 09:39:41 AM UTC 24 |
Sep 11 09:39:44 AM UTC 24 |
27959219 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2262553272 |
|
|
Sep 11 09:39:45 AM UTC 24 |
Sep 11 09:39:49 AM UTC 24 |
163958068 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.2567005181 |
|
|
Sep 11 09:38:14 AM UTC 24 |
Sep 11 09:39:58 AM UTC 24 |
2353268614 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3182098497 |
|
|
Sep 11 09:39:44 AM UTC 24 |
Sep 11 09:39:58 AM UTC 24 |
423288970 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3508676921 |
|
|
Sep 11 09:39:59 AM UTC 24 |
Sep 11 09:40:01 AM UTC 24 |
46507462 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1854926353 |
|
|
Sep 11 09:23:02 AM UTC 24 |
Sep 11 09:40:02 AM UTC 24 |
4360702169 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.3851138661 |
|
|
Sep 11 09:40:02 AM UTC 24 |
Sep 11 09:40:06 AM UTC 24 |
63924970 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3430650751 |
|
|
Sep 11 09:25:16 AM UTC 24 |
Sep 11 09:40:07 AM UTC 24 |
2506246551 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1282709489 |
|
|
Sep 11 08:55:22 AM UTC 24 |
Sep 11 09:40:15 AM UTC 24 |
10746061652 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3943610760 |
|
|
Sep 11 09:40:15 AM UTC 24 |
Sep 11 09:40:30 AM UTC 24 |
527038158 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3649220165 |
|
|
Sep 11 09:36:28 AM UTC 24 |
Sep 11 09:40:40 AM UTC 24 |
2820578993 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1453016500 |
|
|
Sep 11 09:40:06 AM UTC 24 |
Sep 11 09:40:53 AM UTC 24 |
21825461872 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2543613003 |
|
|
Sep 11 09:23:33 AM UTC 24 |
Sep 11 09:40:57 AM UTC 24 |
11011319441 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2666450995 |
|
|
Sep 11 09:26:54 AM UTC 24 |
Sep 11 09:41:01 AM UTC 24 |
118855281750 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3463085970 |
|
|
Sep 11 09:24:20 AM UTC 24 |
Sep 11 09:41:07 AM UTC 24 |
132196335205 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.599905461 |
|
|
Sep 11 09:40:58 AM UTC 24 |
Sep 11 09:41:11 AM UTC 24 |
794935444 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2644011542 |
|
|
Sep 11 09:10:46 AM UTC 24 |
Sep 11 09:41:11 AM UTC 24 |
36626418325 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.2374957951 |
|
|
Sep 11 09:41:12 AM UTC 24 |
Sep 11 09:41:15 AM UTC 24 |
80592652 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1558905603 |
|
|
Sep 11 09:41:16 AM UTC 24 |
Sep 11 09:41:24 AM UTC 24 |
665774123 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.4280419646 |
|
|
Sep 11 09:41:26 AM UTC 24 |
Sep 11 09:41:30 AM UTC 24 |
159448728 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.2644918383 |
|
|
Sep 11 09:37:51 AM UTC 24 |
Sep 11 09:41:33 AM UTC 24 |
1505278237 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3089413461 |
|
|
Sep 11 09:38:09 AM UTC 24 |
Sep 11 09:41:40 AM UTC 24 |
1323880209 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.533802405 |
|
|
Sep 11 09:41:41 AM UTC 24 |
Sep 11 09:41:43 AM UTC 24 |
14107087 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3757724041 |
|
|
Sep 11 09:25:18 AM UTC 24 |
Sep 11 09:41:44 AM UTC 24 |
76302700658 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.4244833544 |
|
|
Sep 11 09:38:28 AM UTC 24 |
Sep 11 09:41:47 AM UTC 24 |
3746833191 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1627861132 |
|
|
Sep 11 09:35:39 AM UTC 24 |
Sep 11 09:41:50 AM UTC 24 |
61262864739 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2504178824 |
|
|
Sep 11 09:36:49 AM UTC 24 |
Sep 11 09:41:51 AM UTC 24 |
17387338080 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3040637175 |
|
|
Sep 11 09:41:44 AM UTC 24 |
Sep 11 09:41:51 AM UTC 24 |
136811948 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.899217219 |
|
|
Sep 11 09:40:54 AM UTC 24 |
Sep 11 09:41:58 AM UTC 24 |
285271774 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1977639759 |
|
|
Sep 11 09:22:08 AM UTC 24 |
Sep 11 09:41:59 AM UTC 24 |
6840583467 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1471956784 |
|
|
Sep 11 09:41:52 AM UTC 24 |
Sep 11 09:42:01 AM UTC 24 |
193765577 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1018578458 |
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Sep 11 09:38:45 AM UTC 24 |
Sep 11 09:42:02 AM UTC 24 |
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| T788 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3915374880 |
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Sep 11 09:40:41 AM UTC 24 |
Sep 11 09:42:04 AM UTC 24 |
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| T789 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3344998234 |
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Sep 11 09:41:48 AM UTC 24 |
Sep 11 09:42:04 AM UTC 24 |
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| T790 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.877844250 |
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Sep 11 09:09:22 AM UTC 24 |
Sep 11 09:42:12 AM UTC 24 |
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| T791 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2874423004 |
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Sep 11 09:42:02 AM UTC 24 |
Sep 11 09:42:13 AM UTC 24 |
555375928 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2553068788 |
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Sep 11 09:42:13 AM UTC 24 |
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86971810 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.185336840 |
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Sep 11 09:42:17 AM UTC 24 |
Sep 11 09:42:22 AM UTC 24 |
220780689 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2062431792 |
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Sep 11 09:42:00 AM UTC 24 |
Sep 11 09:42:26 AM UTC 24 |
167432418 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.3939102174 |
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Sep 11 09:42:14 AM UTC 24 |
Sep 11 09:42:29 AM UTC 24 |
307174770 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1386514550 |
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Sep 11 09:42:30 AM UTC 24 |
Sep 11 09:42:32 AM UTC 24 |
15241928 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3005624528 |
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Sep 11 09:42:00 AM UTC 24 |
Sep 11 09:42:32 AM UTC 24 |
202513427 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.2365008432 |
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Sep 11 09:32:58 AM UTC 24 |
Sep 11 09:42:55 AM UTC 24 |
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| T799 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.1582594513 |
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Sep 11 09:42:33 AM UTC 24 |
Sep 11 09:43:04 AM UTC 24 |
139410100 ps |