Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total test records in report: 1012

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1880959675			Sep 11 09:50:44 AM UTC 24	Sep 11 09:50:47 AM UTC 24	149647776 ps
T1002	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3821906025			Sep 11 09:50:44 AM UTC 24	Sep 11 09:50:48 AM UTC 24	1152609535 ps
T1003	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1345144501			Sep 11 09:50:44 AM UTC 24	Sep 11 09:50:48 AM UTC 24	530898948 ps
T1004	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3091842382			Sep 11 09:50:46 AM UTC 24	Sep 11 09:50:48 AM UTC 24	12752623 ps
T1005	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.809494905			Sep 11 09:50:46 AM UTC 24	Sep 11 09:50:49 AM UTC 24	37326681 ps
T1006	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1037931294			Sep 11 09:50:44 AM UTC 24	Sep 11 09:50:49 AM UTC 24	27306515 ps
T1007	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2305359445			Sep 11 09:50:48 AM UTC 24	Sep 11 09:50:50 AM UTC 24	60783981 ps
T1008	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2982974262			Sep 11 09:50:48 AM UTC 24	Sep 11 09:50:50 AM UTC 24	15833286 ps
T1009	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1885223098			Sep 11 09:50:46 AM UTC 24	Sep 11 09:50:51 AM UTC 24	483056406 ps
T1010	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2430630457			Sep 11 09:50:48 AM UTC 24	Sep 11 09:50:52 AM UTC 24	62651839 ps
T1011	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2284790332			Sep 11 09:50:48 AM UTC 24	Sep 11 09:50:52 AM UTC 24	257827906 ps
T1012	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1049616083			Sep 11 09:50:50 AM UTC 24	Sep 11 09:50:53 AM UTC 24	103693004 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.3920041419
Short name	T3
Test name
Test status
Simulation time	1650676312 ps
CPU time	10.67 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:40:35 AM UTC 24
Peak memory	274196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920041419 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3920041419
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.554310830
Short name	T22
Test name
Test status
Simulation time	194855315 ps
CPU time	7.43 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:52 AM UTC 24
Peak memory	224260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554310830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.554310830
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1631780765
Short name	T5
Test name
Test status
Simulation time	917007820 ps
CPU time	1.89 seconds
Started	Sep 11 08:40:32 AM UTC 24
Finished	Sep 11 08:40:45 AM UTC 24
Peak memory	248244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631780765 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1631780765
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2613348710
Short name	T48
Test name
Test status
Simulation time	199032757 ps
CPU time	5.34 seconds
Started	Sep 11 08:45:51 AM UTC 24
Finished	Sep 11 08:45:57 AM UTC 24
Peak memory	224036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613348710 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.2613348710
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.4089859289
Short name	T17
Test name
Test status
Simulation time	40446288697 ps
CPU time	511.07 seconds
Started	Sep 11 08:41:07 AM UTC 24
Finished	Sep 11 08:49:46 AM UTC 24
Peak memory	360368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089859289 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.4089859289
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2422747558
Short name	T8
Test name
Test status
Simulation time	1371541557 ps
CPU time	6.53 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:40:50 AM UTC 24
Peak memory	213900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422747558 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.2422747558
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.823265222
Short name	T54
Test name
Test status
Simulation time	578326940 ps
CPU time	4.31 seconds
Started	Sep 11 09:49:28 AM UTC 24
Finished	Sep 11 09:49:33 AM UTC 24
Peak memory	211420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82326 5222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_int g_err.823265222
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2506134251
Short name	T99
Test name
Test status
Simulation time	11591886435 ps
CPU time	293.75 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:45:21 AM UTC 24
Peak memory	213860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506134251 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce ss_b2b.2506134251
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4206017025
Short name	T57
Test name
Test status
Simulation time	1301934540 ps
CPU time	3.64 seconds
Started	Sep 11 09:48:56 AM UTC 24
Finished	Sep 11 09:49:01 AM UTC 24
Peak memory	211524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 06017025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa ssthru_mem_tl_intg_err.4206017025
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.4038220982
Short name	T131
Test name
Test status
Simulation time	2888648571 ps
CPU time	524.53 seconds
Started	Sep 11 08:41:06 AM UTC 24
Finished	Sep 11 08:50:04 AM UTC 24
Peak memory	378992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038220982 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.4038220982
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.910177284
Short name	T23
Test name
Test status
Simulation time	1022801024 ps
CPU time	11.35 seconds
Started	Sep 11 08:40:54 AM UTC 24
Finished	Sep 11 08:41:06 AM UTC 24
Peak memory	224156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910177284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.910177284
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.1500928957
Short name	T148
Test name
Test status
Simulation time	250414460 ps
CPU time	56.61 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:41:40 AM UTC 24
Peak memory	341988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1500928957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th roughput_w_partial_write.1500928957
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3446522283
Short name	T24
Test name
Test status
Simulation time	246772112 ps
CPU time	23.73 seconds
Started	Sep 11 08:40:46 AM UTC 24
Finished	Sep 11 08:41:12 AM UTC 24
Peak memory	224152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446522283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3446522283
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2762897532
Short name	T12
Test name
Test status
Simulation time	27776236 ps
CPU time	0.75 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:46 AM UTC 24
Peak memory	212400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762897532 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2762897532
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2901443031
Short name	T386
Test name
Test status
Simulation time	63420239230 ps
CPU time	960.49 seconds
Started	Sep 11 08:48:09 AM UTC 24
Finished	Sep 11 09:04:20 AM UTC 24
Peak memory	386992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901443031 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2901443031
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3931827762
Short name	T1
Test name
Test status
Simulation time	16611867 ps
CPU time	0.63 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:25 AM UTC 24
Peak memory	212936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931827762 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3931827762
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2513183758
Short name	T120
Test name
Test status
Simulation time	173509914 ps
CPU time	2.51 seconds
Started	Sep 11 09:50:21 AM UTC 24
Finished	Sep 11 09:50:24 AM UTC 24
Peak memory	221560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25131 83758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_i ntg_err.2513183758
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1301196289
Short name	T128
Test name
Test status
Simulation time	531834897 ps
CPU time	2.88 seconds
Started	Sep 11 09:50:25 AM UTC 24
Finished	Sep 11 09:50:29 AM UTC 24
Peak memory	221528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13011 96289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i ntg_err.1301196289
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.2641312324
Short name	T67
Test name
Test status
Simulation time	526465944 ps
CPU time	12.02 seconds
Started	Sep 11 08:40:35 AM UTC 24
Finished	Sep 11 08:40:58 AM UTC 24
Peak memory	213908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641312324 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2641312324
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3125152794
Short name	T124
Test name
Test status
Simulation time	319887394 ps
CPU time	3.42 seconds
Started	Sep 11 09:50:01 AM UTC 24
Finished	Sep 11 09:50:06 AM UTC 24
Peak memory	221712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31251 52794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in tg_err.3125152794
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3749481620
Short name	T127
Test name
Test status
Simulation time	350625632 ps
CPU time	2.31 seconds
Started	Sep 11 09:50:07 AM UTC 24
Finished	Sep 11 09:50:11 AM UTC 24
Peak memory	210992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37494 81620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in tg_err.3749481620
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.3405325091
Short name	T354
Test name
Test status
Simulation time	17738151801 ps
CPU time	1162.05 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 09:00:19 AM UTC 24
Peak memory	384888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405325091 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3405325091
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2315099018
Short name	T410
Test name
Test status
Simulation time	13990999126 ps
CPU time	1497.38 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 09:05:56 AM UTC 24
Peak memory	395164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231509901 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.2315099018
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2344524289
Short name	T208
Test name
Test status
Simulation time	3167557261 ps
CPU time	5.29 seconds
Started	Sep 11 08:46:52 AM UTC 24
Finished	Sep 11 08:46:59 AM UTC 24
Peak memory	213880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344524289 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.2344524289
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3098928928
Short name	T2
Test name
Test status
Simulation time	213164075 ps
CPU time	5.31 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:40:29 AM UTC 24
Peak memory	214188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098928928 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.3098928928
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.468182028
Short name	T101
Test name
Test status
Simulation time	32770454 ps
CPU time	1.04 seconds
Started	Sep 11 09:49:09 AM UTC 24
Finished	Sep 11 09:49:11 AM UTC 24
Peak memory	210380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46818202 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alias ing.468182028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3863386915
Short name	T100
Test name
Test status
Simulation time	458698085 ps
CPU time	2.76 seconds
Started	Sep 11 09:49:06 AM UTC 24
Finished	Sep 11 09:49:10 AM UTC 24
Peak memory	211368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38633869 15 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_ bash.3863386915
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.750659009
Short name	T58
Test name
Test status
Simulation time	57717679 ps
CPU time	0.99 seconds
Started	Sep 11 09:49:02 AM UTC 24
Finished	Sep 11 09:49:04 AM UTC 24
Peak memory	209884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75065900 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_re set.750659009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2605405981
Short name	T927
Test name
Test status
Simulation time	51922307 ps
CPU time	1.25 seconds
Started	Sep 11 09:49:11 AM UTC 24
Finished	Sep 11 09:49:13 AM UTC 24
Peak memory	210420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2605405981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2605405981
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.399492785
Short name	T68
Test name
Test status
Simulation time	43004195 ps
CPU time	0.91 seconds
Started	Sep 11 09:49:06 AM UTC 24
Finished	Sep 11 09:49:08 AM UTC 24
Peak memory	210384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399492785 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.399492785
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.144622271
Short name	T91
Test name
Test status
Simulation time	75961254 ps
CPU time	0.92 seconds
Started	Sep 11 09:49:09 AM UTC 24
Finished	Sep 11 09:49:11 AM UTC 24
Peak memory	210296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=144622271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ct rl_same_csr_outstanding.144622271
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3815635305
Short name	T114
Test name
Test status
Simulation time	234256457 ps
CPU time	5.59 seconds
Started	Sep 11 09:49:01 AM UTC 24
Finished	Sep 11 09:49:08 AM UTC 24
Peak memory	221856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815635305 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.3815635305
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1378479320
Short name	T52
Test name
Test status
Simulation time	270373494 ps
CPU time	2.57 seconds
Started	Sep 11 09:49:01 AM UTC 24
Finished	Sep 11 09:49:05 AM UTC 24
Peak memory	221660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13784 79320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_in tg_err.1378479320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.369246708
Short name	T72
Test name
Test status
Simulation time	18252732 ps
CPU time	0.97 seconds
Started	Sep 11 09:49:21 AM UTC 24
Finished	Sep 11 09:49:23 AM UTC 24
Peak memory	210236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36924670 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alias ing.369246708
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4006135341
Short name	T102
Test name
Test status
Simulation time	128474616 ps
CPU time	2 seconds
Started	Sep 11 09:49:20 AM UTC 24
Finished	Sep 11 09:49:23 AM UTC 24
Peak memory	210244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40061353 41 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_ bash.4006135341
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1807113365
Short name	T70
Test name
Test status
Simulation time	13895319 ps
CPU time	0.92 seconds
Started	Sep 11 09:49:18 AM UTC 24
Finished	Sep 11 09:49:20 AM UTC 24
Peak memory	210420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18071133 65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r eset.1807113365
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1677679361
Short name	T929
Test name
Test status
Simulation time	54606369 ps
CPU time	1.3 seconds
Started	Sep 11 09:49:23 AM UTC 24
Finished	Sep 11 09:49:26 AM UTC 24
Peak memory	220272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1677679361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1677679361
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1542955422
Short name	T71
Test name
Test status
Simulation time	27480091 ps
CPU time	0.93 seconds
Started	Sep 11 09:49:18 AM UTC 24
Finished	Sep 11 09:49:20 AM UTC 24
Peak memory	210384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542955422 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.1542955422
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3512848856
Short name	T69
Test name
Test status
Simulation time	853258300 ps
CPU time	3.91 seconds
Started	Sep 11 09:49:12 AM UTC 24
Finished	Sep 11 09:49:17 AM UTC 24
Peak memory	211264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 12848856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pa ssthru_mem_tl_intg_err.3512848856
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.184872934
Short name	T92
Test name
Test status
Simulation time	16766407 ps
CPU time	1.14 seconds
Started	Sep 11 09:49:21 AM UTC 24
Finished	Sep 11 09:49:23 AM UTC 24
Peak memory	210152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=184872934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ct rl_same_csr_outstanding.184872934
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1670846745
Short name	T928
Test name
Test status
Simulation time	111648951 ps
CPU time	4.52 seconds
Started	Sep 11 09:49:12 AM UTC 24
Finished	Sep 11 09:49:18 AM UTC 24
Peak memory	221912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670846745 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.1670846745
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2064683323
Short name	T53
Test name
Test status
Simulation time	174085841 ps
CPU time	3.69 seconds
Started	Sep 11 09:49:14 AM UTC 24
Finished	Sep 11 09:49:19 AM UTC 24
Peak memory	221580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20646 83323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_in tg_err.2064683323
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2674360027
Short name	T966
Test name
Test status
Simulation time	164311094 ps
CPU time	2.5 seconds
Started	Sep 11 09:50:19 AM UTC 24
Finished	Sep 11 09:50:23 AM UTC 24
Peak memory	221904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2674360027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2674360027
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1565855985
Short name	T963
Test name
Test status
Simulation time	121517754 ps
CPU time	0.97 seconds
Started	Sep 11 09:50:18 AM UTC 24
Finished	Sep 11 09:50:20 AM UTC 24
Peak memory	210092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565855985 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.1565855985
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2063605074
Short name	T88
Test name
Test status
Simulation time	232606700 ps
CPU time	2.89 seconds
Started	Sep 11 09:50:18 AM UTC 24
Finished	Sep 11 09:50:21 AM UTC 24
Peak memory	211328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 63605074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p assthru_mem_tl_intg_err.2063605074
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4056440270
Short name	T964
Test name
Test status
Simulation time	19295057 ps
CPU time	1.17 seconds
Started	Sep 11 09:50:19 AM UTC 24
Finished	Sep 11 09:50:22 AM UTC 24
Peak memory	210148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4056440270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ ctrl_same_csr_outstanding.4056440270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1973827751
Short name	T965
Test name
Test status
Simulation time	48910212 ps
CPU time	3.15 seconds
Started	Sep 11 09:50:18 AM UTC 24
Finished	Sep 11 09:50:22 AM UTC 24
Peak memory	211492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973827751 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.1973827751
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4178493917
Short name	T119
Test name
Test status
Simulation time	221630802 ps
CPU time	3.5 seconds
Started	Sep 11 09:50:18 AM UTC 24
Finished	Sep 11 09:50:22 AM UTC 24
Peak memory	221504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41784 93917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_i ntg_err.4178493917
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.201573811
Short name	T971
Test name
Test status
Simulation time	341582645 ps
CPU time	3.69 seconds
Started	Sep 11 09:50:24 AM UTC 24
Finished	Sep 11 09:50:28 AM UTC 24
Peak memory	221700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=201573811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.201573811
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3448913760
Short name	T968
Test name
Test status
Simulation time	21614311 ps
CPU time	1.05 seconds
Started	Sep 11 09:50:24 AM UTC 24
Finished	Sep 11 09:50:26 AM UTC 24
Peak memory	210716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448913760 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.3448913760
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1398677619
Short name	T89
Test name
Test status
Simulation time	824897733 ps
CPU time	3.39 seconds
Started	Sep 11 09:50:19 AM UTC 24
Finished	Sep 11 09:50:24 AM UTC 24
Peak memory	211340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 98677619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p assthru_mem_tl_intg_err.1398677619
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2997059177
Short name	T969
Test name
Test status
Simulation time	56341327 ps
CPU time	1.06 seconds
Started	Sep 11 09:50:24 AM UTC 24
Finished	Sep 11 09:50:26 AM UTC 24
Peak memory	210148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2997059177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ ctrl_same_csr_outstanding.2997059177
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2585096692
Short name	T967
Test name
Test status
Simulation time	152941161 ps
CPU time	4.88 seconds
Started	Sep 11 09:50:20 AM UTC 24
Finished	Sep 11 09:50:25 AM UTC 24
Peak memory	221600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585096692 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.2585096692
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1071918466
Short name	T974
Test name
Test status
Simulation time	62456750 ps
CPU time	2.99 seconds
Started	Sep 11 09:50:27 AM UTC 24
Finished	Sep 11 09:50:31 AM UTC 24
Peak memory	221916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1071918466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1071918466
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1050617585
Short name	T970
Test name
Test status
Simulation time	22351517 ps
CPU time	1.04 seconds
Started	Sep 11 09:50:25 AM UTC 24
Finished	Sep 11 09:50:27 AM UTC 24
Peak memory	210352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050617585 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.1050617585
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3282626213
Short name	T90
Test name
Test status
Simulation time	5022020323 ps
CPU time	5.18 seconds
Started	Sep 11 09:50:24 AM UTC 24
Finished	Sep 11 09:50:30 AM UTC 24
Peak memory	211672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 82626213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p assthru_mem_tl_intg_err.3282626213
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3050061249
Short name	T973
Test name
Test status
Simulation time	197372487 ps
CPU time	1.22 seconds
Started	Sep 11 09:50:27 AM UTC 24
Finished	Sep 11 09:50:29 AM UTC 24
Peak memory	210300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3050061249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ ctrl_same_csr_outstanding.3050061249
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1452965846
Short name	T972
Test name
Test status
Simulation time	399948425 ps
CPU time	4.08 seconds
Started	Sep 11 09:50:24 AM UTC 24
Finished	Sep 11 09:50:29 AM UTC 24
Peak memory	211608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452965846 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.1452965846
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.587104185
Short name	T975
Test name
Test status
Simulation time	32902661 ps
CPU time	0.89 seconds
Started	Sep 11 09:50:29 AM UTC 24
Finished	Sep 11 09:50:31 AM UTC 24
Peak memory	210092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587104185 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.587104185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2645041878
Short name	T979
Test name
Test status
Simulation time	1511187144 ps
CPU time	6.1 seconds
Started	Sep 11 09:50:27 AM UTC 24
Finished	Sep 11 09:50:34 AM UTC 24
Peak memory	211480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 45041878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p assthru_mem_tl_intg_err.2645041878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1606894986
Short name	T977
Test name
Test status
Simulation time	41653303 ps
CPU time	1.2 seconds
Started	Sep 11 09:50:31 AM UTC 24
Finished	Sep 11 09:50:33 AM UTC 24
Peak memory	210148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1606894986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ ctrl_same_csr_outstanding.1606894986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3071425753
Short name	T978
Test name
Test status
Simulation time	132904377 ps
CPU time	5.19 seconds
Started	Sep 11 09:50:27 AM UTC 24
Finished	Sep 11 09:50:33 AM UTC 24
Peak memory	221780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071425753 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.3071425753
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2696895486
Short name	T976
Test name
Test status
Simulation time	491003809 ps
CPU time	2.6 seconds
Started	Sep 11 09:50:28 AM UTC 24
Finished	Sep 11 09:50:32 AM UTC 24
Peak memory	211540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26968 95486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i ntg_err.2696895486
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.185730631
Short name	T983
Test name
Test status
Simulation time	160985752 ps
CPU time	2.29 seconds
Started	Sep 11 09:50:34 AM UTC 24
Finished	Sep 11 09:50:38 AM UTC 24
Peak memory	221956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=185730631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.185730631
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2023854698
Short name	T980
Test name
Test status
Simulation time	31571741 ps
CPU time	0.95 seconds
Started	Sep 11 09:50:32 AM UTC 24
Finished	Sep 11 09:50:35 AM UTC 24
Peak memory	210384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023854698 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.2023854698
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.757974320
Short name	T982
Test name
Test status
Simulation time	927993929 ps
CPU time	4.77 seconds
Started	Sep 11 09:50:31 AM UTC 24
Finished	Sep 11 09:50:37 AM UTC 24
Peak memory	211568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75 7974320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_pa ssthru_mem_tl_intg_err.757974320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4132286384
Short name	T981
Test name
Test status
Simulation time	42349194 ps
CPU time	0.93 seconds
Started	Sep 11 09:50:34 AM UTC 24
Finished	Sep 11 09:50:36 AM UTC 24
Peak memory	210148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4132286384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ ctrl_same_csr_outstanding.4132286384
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2181863170
Short name	T988
Test name
Test status
Simulation time	155654489 ps
CPU time	7.17 seconds
Started	Sep 11 09:50:31 AM UTC 24
Finished	Sep 11 09:50:39 AM UTC 24
Peak memory	221728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181863170 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.2181863170
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1939616087
Short name	T125
Test name
Test status
Simulation time	204591189 ps
CPU time	2.68 seconds
Started	Sep 11 09:50:32 AM UTC 24
Finished	Sep 11 09:50:37 AM UTC 24
Peak memory	211488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19396 16087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i ntg_err.1939616087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1210656393
Short name	T987
Test name
Test status
Simulation time	316962449 ps
CPU time	1.46 seconds
Started	Sep 11 09:50:37 AM UTC 24
Finished	Sep 11 09:50:39 AM UTC 24
Peak memory	220336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1210656393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1210656393
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3111921209
Short name	T984
Test name
Test status
Simulation time	21955964 ps
CPU time	0.91 seconds
Started	Sep 11 09:50:35 AM UTC 24
Finished	Sep 11 09:50:38 AM UTC 24
Peak memory	210776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111921209 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.3111921209
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2359739310
Short name	T990
Test name
Test status
Simulation time	423676388 ps
CPU time	4.82 seconds
Started	Sep 11 09:50:35 AM UTC 24
Finished	Sep 11 09:50:42 AM UTC 24
Peak memory	211552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 59739310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p assthru_mem_tl_intg_err.2359739310
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2670761185
Short name	T986
Test name
Test status
Simulation time	14554020 ps
CPU time	0.91 seconds
Started	Sep 11 09:50:37 AM UTC 24
Finished	Sep 11 09:50:39 AM UTC 24
Peak memory	210296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2670761185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ ctrl_same_csr_outstanding.2670761185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.197879529
Short name	T994
Test name
Test status
Simulation time	125724833 ps
CPU time	6.35 seconds
Started	Sep 11 09:50:35 AM UTC 24
Finished	Sep 11 09:50:43 AM UTC 24
Peak memory	221656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197879529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.197879529
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1412851676
Short name	T985
Test name
Test status
Simulation time	173253677 ps
CPU time	1.7 seconds
Started	Sep 11 09:50:35 AM UTC 24
Finished	Sep 11 09:50:38 AM UTC 24
Peak memory	220464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14128 51676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i ntg_err.1412851676
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.496283631
Short name	T992
Test name
Test status
Simulation time	34531407 ps
CPU time	1.53 seconds
Started	Sep 11 09:50:40 AM UTC 24
Finished	Sep 11 09:50:42 AM UTC 24
Peak memory	220272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=496283631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.496283631
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1985845613
Short name	T989
Test name
Test status
Simulation time	13799457 ps
CPU time	0.98 seconds
Started	Sep 11 09:50:38 AM UTC 24
Finished	Sep 11 09:50:41 AM UTC 24
Peak memory	210092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985845613 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1985845613
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3243655794
Short name	T993
Test name
Test status
Simulation time	452851636 ps
CPU time	3.19 seconds
Started	Sep 11 09:50:38 AM UTC 24
Finished	Sep 11 09:50:43 AM UTC 24
Peak memory	211328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 43655794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p assthru_mem_tl_intg_err.3243655794
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3168480337
Short name	T991
Test name
Test status
Simulation time	92985038 ps
CPU time	1.01 seconds
Started	Sep 11 09:50:40 AM UTC 24
Finished	Sep 11 09:50:42 AM UTC 24
Peak memory	210856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3168480337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ ctrl_same_csr_outstanding.3168480337
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1220564384
Short name	T1000
Test name
Test status
Simulation time	605552456 ps
CPU time	7.01 seconds
Started	Sep 11 09:50:38 AM UTC 24
Finished	Sep 11 09:50:47 AM UTC 24
Peak memory	211432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220564384 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.1220564384
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3426980668
Short name	T126
Test name
Test status
Simulation time	804082031 ps
CPU time	3.45 seconds
Started	Sep 11 09:50:38 AM UTC 24
Finished	Sep 11 09:50:43 AM UTC 24
Peak memory	221532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34269 80668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i ntg_err.3426980668
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1880959675
Short name	T1001
Test name
Test status
Simulation time	149647776 ps
CPU time	1.55 seconds
Started	Sep 11 09:50:44 AM UTC 24
Finished	Sep 11 09:50:47 AM UTC 24
Peak memory	222324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1880959675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1880959675
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2219070532
Short name	T996
Test name
Test status
Simulation time	13368297 ps
CPU time	0.96 seconds
Started	Sep 11 09:50:43 AM UTC 24
Finished	Sep 11 09:50:45 AM UTC 24
Peak memory	209588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219070532 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.2219070532
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3861251397
Short name	T995
Test name
Test status
Simulation time	227663165 ps
CPU time	2.52 seconds
Started	Sep 11 09:50:40 AM UTC 24
Finished	Sep 11 09:50:43 AM UTC 24
Peak memory	211344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 61251397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_p assthru_mem_tl_intg_err.3861251397
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2460794518
Short name	T997
Test name
Test status
Simulation time	13219720 ps
CPU time	0.98 seconds
Started	Sep 11 09:50:43 AM UTC 24
Finished	Sep 11 09:50:45 AM UTC 24
Peak memory	210380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2460794518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ ctrl_same_csr_outstanding.2460794518
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1834368899
Short name	T998
Test name
Test status
Simulation time	74770906 ps
CPU time	3.04 seconds
Started	Sep 11 09:50:41 AM UTC 24
Finished	Sep 11 09:50:45 AM UTC 24
Peak memory	211236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834368899 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.1834368899
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2255974555
Short name	T129
Test name
Test status
Simulation time	545567261 ps
CPU time	2.68 seconds
Started	Sep 11 09:50:41 AM UTC 24
Finished	Sep 11 09:50:45 AM UTC 24
Peak memory	221600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22559 74555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.2255974555
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.809494905
Short name	T1005
Test name
Test status
Simulation time	37326681 ps
CPU time	1.32 seconds
Started	Sep 11 09:50:46 AM UTC 24
Finished	Sep 11 09:50:49 AM UTC 24
Peak memory	220272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=809494905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.809494905
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3868113100
Short name	T999
Test name
Test status
Simulation time	28798682 ps
CPU time	1 seconds
Started	Sep 11 09:50:44 AM UTC 24
Finished	Sep 11 09:50:47 AM UTC 24
Peak memory	210324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868113100 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.3868113100
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3821906025
Short name	T1002
Test name
Test status
Simulation time	1152609535 ps
CPU time	2.74 seconds
Started	Sep 11 09:50:44 AM UTC 24
Finished	Sep 11 09:50:48 AM UTC 24
Peak memory	211328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 21906025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p assthru_mem_tl_intg_err.3821906025
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3091842382
Short name	T1004
Test name
Test status
Simulation time	12752623 ps
CPU time	1.03 seconds
Started	Sep 11 09:50:46 AM UTC 24
Finished	Sep 11 09:50:48 AM UTC 24
Peak memory	210148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3091842382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ ctrl_same_csr_outstanding.3091842382
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1037931294
Short name	T1006
Test name
Test status
Simulation time	27306515 ps
CPU time	3.72 seconds
Started	Sep 11 09:50:44 AM UTC 24
Finished	Sep 11 09:50:49 AM UTC 24
Peak memory	221728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037931294 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.1037931294
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1345144501
Short name	T1003
Test name
Test status
Simulation time	530898948 ps
CPU time	2.7 seconds
Started	Sep 11 09:50:44 AM UTC 24
Finished	Sep 11 09:50:48 AM UTC 24
Peak memory	221600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13451 44501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i ntg_err.1345144501
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1049616083
Short name	T1012
Test name
Test status
Simulation time	103693004 ps
CPU time	2.02 seconds
Started	Sep 11 09:50:50 AM UTC 24
Finished	Sep 11 09:50:53 AM UTC 24
Peak memory	221640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1049616083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1049616083
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2305359445
Short name	T1007
Test name
Test status
Simulation time	60783981 ps
CPU time	0.94 seconds
Started	Sep 11 09:50:48 AM UTC 24
Finished	Sep 11 09:50:50 AM UTC 24
Peak memory	210028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305359445 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.2305359445
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1885223098
Short name	T1009
Test name
Test status
Simulation time	483056406 ps
CPU time	3.82 seconds
Started	Sep 11 09:50:46 AM UTC 24
Finished	Sep 11 09:50:51 AM UTC 24
Peak memory	211480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18 85223098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_p assthru_mem_tl_intg_err.1885223098
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2982974262
Short name	T1008
Test name
Test status
Simulation time	15833286 ps
CPU time	0.94 seconds
Started	Sep 11 09:50:48 AM UTC 24
Finished	Sep 11 09:50:50 AM UTC 24
Peak memory	210024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2982974262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ ctrl_same_csr_outstanding.2982974262
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2430630457
Short name	T1010
Test name
Test status
Simulation time	62651839 ps
CPU time	2.98 seconds
Started	Sep 11 09:50:48 AM UTC 24
Finished	Sep 11 09:50:52 AM UTC 24
Peak memory	211484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430630457 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.2430630457
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2284790332
Short name	T1011
Test name
Test status
Simulation time	257827906 ps
CPU time	3.19 seconds
Started	Sep 11 09:50:48 AM UTC 24
Finished	Sep 11 09:50:52 AM UTC 24
Peak memory	221628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22847 90332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i ntg_err.2284790332
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1671768308
Short name	T932
Test name
Test status
Simulation time	40609562 ps
CPU time	0.93 seconds
Started	Sep 11 09:49:35 AM UTC 24
Finished	Sep 11 09:49:37 AM UTC 24
Peak memory	210380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16717683 08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alia sing.1671768308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3356188280
Short name	T75
Test name
Test status
Simulation time	293073479 ps
CPU time	2.06 seconds
Started	Sep 11 09:49:33 AM UTC 24
Finished	Sep 11 09:49:36 AM UTC 24
Peak memory	211352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33561882 80 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_ bash.3356188280
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.651012327
Short name	T931
Test name
Test status
Simulation time	36435866 ps
CPU time	1.02 seconds
Started	Sep 11 09:49:30 AM UTC 24
Finished	Sep 11 09:49:32 AM UTC 24
Peak memory	209880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65101232 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_re set.651012327
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3348109899
Short name	T933
Test name
Test status
Simulation time	41554031 ps
CPU time	1.66 seconds
Started	Sep 11 09:49:37 AM UTC 24
Finished	Sep 11 09:49:40 AM UTC 24
Peak memory	219784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3348109899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3348109899
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1906589055
Short name	T74
Test name
Test status
Simulation time	31288454 ps
CPU time	0.94 seconds
Started	Sep 11 09:49:31 AM UTC 24
Finished	Sep 11 09:49:33 AM UTC 24
Peak memory	210156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906589055 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1906589055
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3670137604
Short name	T73
Test name
Test status
Simulation time	770497102 ps
CPU time	3.47 seconds
Started	Sep 11 09:49:24 AM UTC 24
Finished	Sep 11 09:49:29 AM UTC 24
Peak memory	211268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 70137604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa ssthru_mem_tl_intg_err.3670137604
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1892226400
Short name	T93
Test name
Test status
Simulation time	44395626 ps
CPU time	1.15 seconds
Started	Sep 11 09:49:35 AM UTC 24
Finished	Sep 11 09:49:37 AM UTC 24
Peak memory	210352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1892226400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c trl_same_csr_outstanding.1892226400
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1265211279
Short name	T930
Test name
Test status
Simulation time	112572611 ps
CPU time	2.88 seconds
Started	Sep 11 09:49:24 AM UTC 24
Finished	Sep 11 09:49:29 AM UTC 24
Peak memory	211564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265211279 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.1265211279
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.333147965
Short name	T937
Test name
Test status
Simulation time	17362484 ps
CPU time	0.98 seconds
Started	Sep 11 09:49:45 AM UTC 24
Finished	Sep 11 09:49:47 AM UTC 24
Peak memory	210652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33314796 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alias ing.333147965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1551565294
Short name	T936
Test name
Test status
Simulation time	29508340 ps
CPU time	1.59 seconds
Started	Sep 11 09:49:44 AM UTC 24
Finished	Sep 11 09:49:46 AM UTC 24
Peak memory	210312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15515652 94 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_ bash.1551565294
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2304090643
Short name	T934
Test name
Test status
Simulation time	101313010 ps
CPU time	0.91 seconds
Started	Sep 11 09:49:42 AM UTC 24
Finished	Sep 11 09:49:44 AM UTC 24
Peak memory	210352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23040906 43 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_r eset.2304090643
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.121701392
Short name	T939
Test name
Test status
Simulation time	63176064 ps
CPU time	1.35 seconds
Started	Sep 11 09:49:47 AM UTC 24
Finished	Sep 11 09:49:50 AM UTC 24
Peak memory	220600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=121701392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.121701392
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2519102056
Short name	T94
Test name
Test status
Simulation time	43570388 ps
CPU time	0.85 seconds
Started	Sep 11 09:49:44 AM UTC 24
Finished	Sep 11 09:49:46 AM UTC 24
Peak memory	210296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519102056 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.2519102056
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2372183583
Short name	T76
Test name
Test status
Simulation time	401607833 ps
CPU time	4.41 seconds
Started	Sep 11 09:49:37 AM UTC 24
Finished	Sep 11 09:49:43 AM UTC 24
Peak memory	211556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 72183583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pa ssthru_mem_tl_intg_err.2372183583
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.844425413
Short name	T938
Test name
Test status
Simulation time	55803855 ps
CPU time	1.02 seconds
Started	Sep 11 09:49:46 AM UTC 24
Finished	Sep 11 09:49:48 AM UTC 24
Peak memory	210296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=844425413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ct rl_same_csr_outstanding.844425413
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1504428291
Short name	T935
Test name
Test status
Simulation time	577131108 ps
CPU time	6.91 seconds
Started	Sep 11 09:49:38 AM UTC 24
Finished	Sep 11 09:49:46 AM UTC 24
Peak memory	221600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504428291 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.1504428291
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3107252038
Short name	T121
Test name
Test status
Simulation time	444345287 ps
CPU time	1.66 seconds
Started	Sep 11 09:49:41 AM UTC 24
Finished	Sep 11 09:49:43 AM UTC 24
Peak memory	210156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31072 52038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in tg_err.3107252038
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2241442960
Short name	T944
Test name
Test status
Simulation time	167478376 ps
CPU time	0.99 seconds
Started	Sep 11 09:49:55 AM UTC 24
Finished	Sep 11 09:49:57 AM UTC 24
Peak memory	210440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22414429 60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia sing.2241442960
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3095350796
Short name	T945
Test name
Test status
Simulation time	309329460 ps
CPU time	2.73 seconds
Started	Sep 11 09:49:53 AM UTC 24
Finished	Sep 11 09:49:57 AM UTC 24
Peak memory	211472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30953507 96 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_ bash.3095350796
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1962245111
Short name	T941
Test name
Test status
Simulation time	39715695 ps
CPU time	1.02 seconds
Started	Sep 11 09:49:51 AM UTC 24
Finished	Sep 11 09:49:53 AM UTC 24
Peak memory	210716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19622451 11 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_r eset.1962245111
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2439454859
Short name	T946
Test name
Test status
Simulation time	129537707 ps
CPU time	1.86 seconds
Started	Sep 11 09:49:55 AM UTC 24
Finished	Sep 11 09:49:58 AM UTC 24
Peak memory	220596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2439454859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2439454859
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.503224326
Short name	T942
Test name
Test status
Simulation time	103255683 ps
CPU time	0.95 seconds
Started	Sep 11 09:49:53 AM UTC 24
Finished	Sep 11 09:49:55 AM UTC 24
Peak memory	210236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503224326 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.503224326
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3073906974
Short name	T77
Test name
Test status
Simulation time	528947579 ps
CPU time	5.03 seconds
Started	Sep 11 09:49:48 AM UTC 24
Finished	Sep 11 09:49:54 AM UTC 24
Peak memory	211640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 73906974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pa ssthru_mem_tl_intg_err.3073906974
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1711158336
Short name	T943
Test name
Test status
Simulation time	16519699 ps
CPU time	0.85 seconds
Started	Sep 11 09:49:55 AM UTC 24
Finished	Sep 11 09:49:56 AM UTC 24
Peak memory	210352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1711158336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c trl_same_csr_outstanding.1711158336
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3444468291
Short name	T940
Test name
Test status
Simulation time	288405090 ps
CPU time	3.59 seconds
Started	Sep 11 09:49:48 AM UTC 24
Finished	Sep 11 09:49:52 AM UTC 24
Peak memory	211536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444468291 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.3444468291
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.27682610
Short name	T115
Test name
Test status
Simulation time	362252776 ps
CPU time	2.47 seconds
Started	Sep 11 09:49:50 AM UTC 24
Finished	Sep 11 09:49:53 AM UTC 24
Peak memory	221736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27682 610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_intg _err.27682610
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.122638312
Short name	T949
Test name
Test status
Simulation time	49427656 ps
CPU time	3.18 seconds
Started	Sep 11 09:50:01 AM UTC 24
Finished	Sep 11 09:50:05 AM UTC 24
Peak memory	221764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=122638312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.122638312
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1866564627
Short name	T84
Test name
Test status
Simulation time	76894031 ps
CPU time	0.91 seconds
Started	Sep 11 09:49:58 AM UTC 24
Finished	Sep 11 09:50:00 AM UTC 24
Peak memory	210096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866564627 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.1866564627
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3768655390
Short name	T78
Test name
Test status
Simulation time	394463593 ps
CPU time	3.06 seconds
Started	Sep 11 09:49:56 AM UTC 24
Finished	Sep 11 09:50:00 AM UTC 24
Peak memory	211336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 68655390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa ssthru_mem_tl_intg_err.3768655390
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3022738991
Short name	T947
Test name
Test status
Simulation time	96066174 ps
CPU time	1.14 seconds
Started	Sep 11 09:49:58 AM UTC 24
Finished	Sep 11 09:50:00 AM UTC 24
Peak memory	210380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3022738991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_c trl_same_csr_outstanding.3022738991
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.453833295
Short name	T116
Test name
Test status
Simulation time	139164653 ps
CPU time	5.41 seconds
Started	Sep 11 09:49:57 AM UTC 24
Finished	Sep 11 09:50:03 AM UTC 24
Peak memory	221792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453833295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.453833295
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3786260433
Short name	T122
Test name
Test status
Simulation time	506778241 ps
CPU time	3.23 seconds
Started	Sep 11 09:49:57 AM UTC 24
Finished	Sep 11 09:50:01 AM UTC 24
Peak memory	221656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37862 60433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in tg_err.3786260433
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.958410089
Short name	T951
Test name
Test status
Simulation time	70165779 ps
CPU time	1.94 seconds
Started	Sep 11 09:50:06 AM UTC 24
Finished	Sep 11 09:50:09 AM UTC 24
Peak memory	220276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=958410089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.958410089
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1450449942
Short name	T948
Test name
Test status
Simulation time	36192236 ps
CPU time	0.97 seconds
Started	Sep 11 09:50:02 AM UTC 24
Finished	Sep 11 09:50:04 AM UTC 24
Peak memory	210092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450449942 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.1450449942
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2436769601
Short name	T79
Test name
Test status
Simulation time	693794852 ps
CPU time	3.48 seconds
Started	Sep 11 09:50:01 AM UTC 24
Finished	Sep 11 09:50:05 AM UTC 24
Peak memory	211340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24 36769601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa ssthru_mem_tl_intg_err.2436769601
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2590425003
Short name	T950
Test name
Test status
Simulation time	12983008 ps
CPU time	0.82 seconds
Started	Sep 11 09:50:04 AM UTC 24
Finished	Sep 11 09:50:06 AM UTC 24
Peak memory	210352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2590425003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c trl_same_csr_outstanding.2590425003
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3267166841
Short name	T117
Test name
Test status
Simulation time	141024176 ps
CPU time	4.94 seconds
Started	Sep 11 09:50:01 AM UTC 24
Finished	Sep 11 09:50:07 AM UTC 24
Peak memory	221856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267166841 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3267166841
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3018567669
Short name	T956
Test name
Test status
Simulation time	38875499 ps
CPU time	2.56 seconds
Started	Sep 11 09:50:09 AM UTC 24
Finished	Sep 11 09:50:12 AM UTC 24
Peak memory	221792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3018567669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3018567669
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1263165373
Short name	T952
Test name
Test status
Simulation time	16371846 ps
CPU time	1.01 seconds
Started	Sep 11 09:50:07 AM UTC 24
Finished	Sep 11 09:50:09 AM UTC 24
Peak memory	211084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263165373 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.1263165373
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.762557230
Short name	T955
Test name
Test status
Simulation time	1605697479 ps
CPU time	4.19 seconds
Started	Sep 11 09:50:06 AM UTC 24
Finished	Sep 11 09:50:11 AM UTC 24
Peak memory	211856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76 2557230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pas sthru_mem_tl_intg_err.762557230
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.731943195
Short name	T953
Test name
Test status
Simulation time	18147881 ps
CPU time	1.15 seconds
Started	Sep 11 09:50:07 AM UTC 24
Finished	Sep 11 09:50:10 AM UTC 24
Peak memory	210236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=731943195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ct rl_same_csr_outstanding.731943195
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.180237708
Short name	T954
Test name
Test status
Simulation time	249078915 ps
CPU time	3.03 seconds
Started	Sep 11 09:50:06 AM UTC 24
Finished	Sep 11 09:50:10 AM UTC 24
Peak memory	221676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180237708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.180237708
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1510142049
Short name	T85
Test name
Test status
Simulation time	77678065 ps
CPU time	0.98 seconds
Started	Sep 11 09:50:10 AM UTC 24
Finished	Sep 11 09:50:12 AM UTC 24
Peak memory	210152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510142049 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.1510142049
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3662783780
Short name	T86
Test name
Test status
Simulation time	1559693381 ps
CPU time	5 seconds
Started	Sep 11 09:50:10 AM UTC 24
Finished	Sep 11 09:50:16 AM UTC 24
Peak memory	211676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 62783780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa ssthru_mem_tl_intg_err.3662783780
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3139247242
Short name	T957
Test name
Test status
Simulation time	80104063 ps
CPU time	1.32 seconds
Started	Sep 11 09:50:12 AM UTC 24
Finished	Sep 11 09:50:14 AM UTC 24
Peak memory	210352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3139247242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c trl_same_csr_outstanding.3139247242
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.356313987
Short name	T961
Test name
Test status
Simulation time	131470080 ps
CPU time	6.06 seconds
Started	Sep 11 09:50:10 AM UTC 24
Finished	Sep 11 09:50:17 AM UTC 24
Peak memory	211428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356313987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.356313987
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1333556602
Short name	T123
Test name
Test status
Simulation time	228941392 ps
CPU time	2.51 seconds
Started	Sep 11 09:50:10 AM UTC 24
Finished	Sep 11 09:50:14 AM UTC 24
Peak memory	211472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13335 56602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in tg_err.1333556602
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1754521819
Short name	T962
Test name
Test status
Simulation time	154616491 ps
CPU time	1.42 seconds
Started	Sep 11 09:50:16 AM UTC 24
Finished	Sep 11 09:50:18 AM UTC 24
Peak memory	220596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1754521819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1754521819
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3372151308
Short name	T958
Test name
Test status
Simulation time	20899051 ps
CPU time	1 seconds
Started	Sep 11 09:50:15 AM UTC 24
Finished	Sep 11 09:50:17 AM UTC 24
Peak memory	210092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372151308 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.3372151308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2538565504
Short name	T87
Test name
Test status
Simulation time	400646006 ps
CPU time	4.77 seconds
Started	Sep 11 09:50:12 AM UTC 24
Finished	Sep 11 09:50:18 AM UTC 24
Peak memory	211480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 38565504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa ssthru_mem_tl_intg_err.2538565504
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2340853811
Short name	T959
Test name
Test status
Simulation time	33431985 ps
CPU time	1.09 seconds
Started	Sep 11 09:50:15 AM UTC 24
Finished	Sep 11 09:50:17 AM UTC 24
Peak memory	210148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2340853811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c trl_same_csr_outstanding.2340853811
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1972033176
Short name	T960
Test name
Test status
Simulation time	67093026 ps
CPU time	3.05 seconds
Started	Sep 11 09:50:13 AM UTC 24
Finished	Sep 11 09:50:17 AM UTC 24
Peak memory	221604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972033176 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.1972033176
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1420809897
Short name	T130
Test name
Test status
Simulation time	444599886 ps
CPU time	2.34 seconds
Started	Sep 11 09:50:13 AM UTC 24
Finished	Sep 11 09:50:17 AM UTC 24
Peak memory	221592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14208 09897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_in tg_err.1420809897
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3541216283
Short name	T16
Test name
Test status
Simulation time	7825868700 ps
CPU time	29.16 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:40:53 AM UTC 24
Peak memory	214192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541216283 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.3541216283
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.272773041
Short name	T146
Test name
Test status
Simulation time	14947586577 ps
CPU time	380.17 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:46:48 AM UTC 24
Peak memory	380784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272773041 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.272773041
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3880509526
Short name	T4
Test name
Test status
Simulation time	184325793 ps
CPU time	2.5 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:40:37 AM UTC 24
Peak memory	247008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880509526 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3880509526
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1321646630
Short name	T202
Test name
Test status
Simulation time	3696212407 ps
CPU time	373.03 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:46:41 AM UTC 24
Peak memory	214232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321646630 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.1321646630
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3810763741
Short name	T294
Test name
Test status
Simulation time	3339759320 ps
CPU time	868.77 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:55:22 AM UTC 24
Peak memory	380768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810763741 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_ key_req.3810763741
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.494440838
Short name	T55
Test name
Test status
Simulation time	2586556602 ps
CPU time	85.42 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:42:11 AM UTC 24
Peak memory	360356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494440838 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.494440838
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3864438553
Short name	T9
Test name
Test status
Simulation time	599804779 ps
CPU time	6.46 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:51 AM UTC 24
Peak memory	213860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864438553 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3864438553
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.4203327862
Short name	T111
Test name
Test status
Simulation time	405217546 ps
CPU time	32.08 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:41:17 AM UTC 24
Peak memory	323376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 203327862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max _throughput.4203327862
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3292160966
Short name	T21
Test name
Test status
Simulation time	432836773 ps
CPU time	3.37 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:48 AM UTC 24
Peak memory	224212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292160966 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.3292160966
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1266044941
Short name	T32
Test name
Test status
Simulation time	298300047 ps
CPU time	6.58 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:51 AM UTC 24
Peak memory	224136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266044941 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.1266044941
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2997446745
Short name	T241
Test name
Test status
Simulation time	5714137230 ps
CPU time	606.04 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:50:47 AM UTC 24
Peak memory	381100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997446745 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.2997446745
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.235683986
Short name	T153
Test name
Test status
Simulation time	1068501188 ps
CPU time	100.06 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:42:26 AM UTC 24
Peak memory	380776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235683986 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.235683986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3425769845
Short name	T207
Test name
Test status
Simulation time	4815183571 ps
CPU time	368.81 seconds
Started	Sep 11 08:40:23 AM UTC 24
Finished	Sep 11 08:46:57 AM UTC 24
Peak memory	214168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425769845 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce ss_b2b.3425769845
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3687447337
Short name	T6
Test name
Test status
Simulation time	435258119 ps
CPU time	2.81 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:48 AM UTC 24
Peak memory	250196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687447337 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3687447337
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3168922838
Short name	T33
Test name
Test status
Simulation time	480961777 ps
CPU time	7.12 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:40:52 AM UTC 24
Peak memory	249692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3168922838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th roughput_w_partial_write.3168922838
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2102806100
Short name	T302
Test name
Test status
Simulation time	8457117337 ps
CPU time	520.16 seconds
Started	Sep 11 08:46:56 AM UTC 24
Finished	Sep 11 08:55:43 AM UTC 24
Peak memory	372636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102806100 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during _key_req.2102806100
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1396126058
Short name	T214
Test name
Test status
Simulation time	22753774 ps
CPU time	0.91 seconds
Started	Sep 11 08:47:18 AM UTC 24
Finished	Sep 11 08:47:20 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396126058 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1396126058
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.3946587885
Short name	T212
Test name
Test status
Simulation time	1880535588 ps
CPU time	69.79 seconds
Started	Sep 11 08:46:05 AM UTC 24
Finished	Sep 11 08:47:17 AM UTC 24
Peak memory	213908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946587885 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.3946587885
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1374680093
Short name	T157
Test name
Test status
Simulation time	1750166478 ps
CPU time	387.72 seconds
Started	Sep 11 08:46:59 AM UTC 24
Finished	Sep 11 08:53:31 AM UTC 24
Peak memory	380704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374680093 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1374680093
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3781608472
Short name	T211
Test name
Test status
Simulation time	258128754 ps
CPU time	18.72 seconds
Started	Sep 11 08:46:49 AM UTC 24
Finished	Sep 11 08:47:09 AM UTC 24
Peak memory	280428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 781608472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma x_throughput.3781608472
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.268350998
Short name	T49
Test name
Test status
Simulation time	110991264 ps
CPU time	4.45 seconds
Started	Sep 11 08:47:03 AM UTC 24
Finished	Sep 11 08:47:08 AM UTC 24
Peak memory	224240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268350998 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.268350998
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.583755722
Short name	T213
Test name
Test status
Simulation time	695421797 ps
CPU time	14.91 seconds
Started	Sep 11 08:47:02 AM UTC 24
Finished	Sep 11 08:47:18 AM UTC 24
Peak memory	224116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583755722 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.583755722
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3652604020
Short name	T155
Test name
Test status
Simulation time	11458159722 ps
CPU time	344.04 seconds
Started	Sep 11 08:46:02 AM UTC 24
Finished	Sep 11 08:51:51 AM UTC 24
Peak memory	337764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652604020 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.3652604020
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.528517635
Short name	T204
Test name
Test status
Simulation time	4343354516 ps
CPU time	8.59 seconds
Started	Sep 11 08:46:42 AM UTC 24
Finished	Sep 11 08:46:51 AM UTC 24
Peak memory	213912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528517635 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.528517635
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4194415652
Short name	T147
Test name
Test status
Simulation time	11960145333 ps
CPU time	156.49 seconds
Started	Sep 11 08:46:46 AM UTC 24
Finished	Sep 11 08:49:25 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194415652 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc ess_b2b.4194415652
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2691385756
Short name	T210
Test name
Test status
Simulation time	80070514 ps
CPU time	1.26 seconds
Started	Sep 11 08:47:00 AM UTC 24
Finished	Sep 11 08:47:02 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691385756 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2691385756
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.4214570433
Short name	T438
Test name
Test status
Simulation time	27994567827 ps
CPU time	1274.3 seconds
Started	Sep 11 08:46:59 AM UTC 24
Finished	Sep 11 09:08:26 AM UTC 24
Peak memory	387248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214570433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.4214570433
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2568467965
Short name	T201
Test name
Test status
Simulation time	240705917 ps
CPU time	2.25 seconds
Started	Sep 11 08:46:01 AM UTC 24
Finished	Sep 11 08:46:05 AM UTC 24
Peak memory	214176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568467965 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2568467965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3812375695
Short name	T513
Test name
Test status
Simulation time	54322171636 ps
CPU time	1714.38 seconds
Started	Sep 11 08:47:10 AM UTC 24
Finished	Sep 11 09:16:03 AM UTC 24
Peak memory	386992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381237569 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.3812375695
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3823061964
Short name	T137
Test name
Test status
Simulation time	7691993622 ps
CPU time	300.38 seconds
Started	Sep 11 08:47:09 AM UTC 24
Finished	Sep 11 08:52:13 AM UTC 24
Peak memory	387312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823061964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3823061964
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.809633508
Short name	T251
Test name
Test status
Simulation time	2651448948 ps
CPU time	284.96 seconds
Started	Sep 11 08:46:15 AM UTC 24
Finished	Sep 11 08:51:04 AM UTC 24
Peak memory	214156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809633508 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.809633508
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2537052237
Short name	T206
Test name
Test status
Simulation time	190703466 ps
CPU time	5.1 seconds
Started	Sep 11 08:46:51 AM UTC 24
Finished	Sep 11 08:46:57 AM UTC 24
Peak memory	231392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2537052237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t hroughput_w_partial_write.2537052237
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.391205786
Short name	T239
Test name
Test status
Simulation time	1428549008 ps
CPU time	152.53 seconds
Started	Sep 11 08:47:57 AM UTC 24
Finished	Sep 11 08:50:32 AM UTC 24
Peak memory	337688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391205786 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_ key_req.391205786
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3524896110
Short name	T226
Test name
Test status
Simulation time	61186879 ps
CPU time	0.87 seconds
Started	Sep 11 08:49:18 AM UTC 24
Finished	Sep 11 08:49:20 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524896110 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3524896110
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2393401650
Short name	T221
Test name
Test status
Simulation time	703095470 ps
CPU time	47.26 seconds
Started	Sep 11 08:47:20 AM UTC 24
Finished	Sep 11 08:48:08 AM UTC 24
Peak memory	213832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393401650 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.2393401650
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.1248578376
Short name	T397
Test name
Test status
Simulation time	13724441545 ps
CPU time	1006.42 seconds
Started	Sep 11 08:48:03 AM UTC 24
Finished	Sep 11 09:05:00 AM UTC 24
Peak memory	384836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248578376 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.1248578376
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1489775008
Short name	T220
Test name
Test status
Simulation time	1996265872 ps
CPU time	16.28 seconds
Started	Sep 11 08:47:45 AM UTC 24
Finished	Sep 11 08:48:02 AM UTC 24
Peak memory	213840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489775008 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.1489775008
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1055526944
Short name	T219
Test name
Test status
Simulation time	76050242 ps
CPU time	19.52 seconds
Started	Sep 11 08:47:35 AM UTC 24
Finished	Sep 11 08:47:56 AM UTC 24
Peak memory	280424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 055526944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ma x_throughput.1055526944
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2029473391
Short name	T225
Test name
Test status
Simulation time	360727460 ps
CPU time	5.28 seconds
Started	Sep 11 08:48:49 AM UTC 24
Finished	Sep 11 08:48:56 AM UTC 24
Peak memory	224080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029473391 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.2029473391
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.814174179
Short name	T224
Test name
Test status
Simulation time	6564518036 ps
CPU time	20.38 seconds
Started	Sep 11 08:48:26 AM UTC 24
Finished	Sep 11 08:48:49 AM UTC 24
Peak memory	224124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814174179 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.814174179
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2820065353
Short name	T422
Test name
Test status
Simulation time	3207486550 ps
CPU time	1178.28 seconds
Started	Sep 11 08:47:18 AM UTC 24
Finished	Sep 11 09:07:10 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820065353 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.2820065353
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4223300512
Short name	T216
Test name
Test status
Simulation time	5022051557 ps
CPU time	12.66 seconds
Started	Sep 11 08:47:21 AM UTC 24
Finished	Sep 11 08:47:35 AM UTC 24
Peak memory	213968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223300512 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.4223300512
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3645857755
Short name	T256
Test name
Test status
Simulation time	3564566288 ps
CPU time	245.61 seconds
Started	Sep 11 08:47:22 AM UTC 24
Finished	Sep 11 08:51:31 AM UTC 24
Peak memory	213936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645857755 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc ess_b2b.3645857755
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.607670732
Short name	T223
Test name
Test status
Simulation time	34981246 ps
CPU time	1.22 seconds
Started	Sep 11 08:48:23 AM UTC 24
Finished	Sep 11 08:48:25 AM UTC 24
Peak memory	212528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607670732 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.607670732
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1639952103
Short name	T215
Test name
Test status
Simulation time	61757463 ps
CPU time	1.89 seconds
Started	Sep 11 08:47:18 AM UTC 24
Finished	Sep 11 08:47:21 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639952103 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1639952103
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.707087367
Short name	T556
Test name
Test status
Simulation time	27740636487 ps
CPU time	1736.98 seconds
Started	Sep 11 08:49:09 AM UTC 24
Finished	Sep 11 09:18:24 AM UTC 24
Peak memory	384944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707087367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.707087367
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.952513995
Short name	T61
Test name
Test status
Simulation time	2218951600 ps
CPU time	107.83 seconds
Started	Sep 11 08:48:58 AM UTC 24
Finished	Sep 11 08:50:48 AM UTC 24
Peak memory	313192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952513995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.952513995
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.4097062442
Short name	T268
Test name
Test status
Simulation time	6641982742 ps
CPU time	319.66 seconds
Started	Sep 11 08:47:21 AM UTC 24
Finished	Sep 11 08:52:45 AM UTC 24
Peak memory	213896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097062442 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.4097062442
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1372940621
Short name	T218
Test name
Test status
Simulation time	55065915 ps
CPU time	4.73 seconds
Started	Sep 11 08:47:38 AM UTC 24
Finished	Sep 11 08:47:44 AM UTC 24
Peak memory	231456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1372940621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t hroughput_w_partial_write.1372940621
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2537431516
Short name	T441
Test name
Test status
Simulation time	2948577977 ps
CPU time	1119 seconds
Started	Sep 11 08:50:04 AM UTC 24
Finished	Sep 11 09:08:56 AM UTC 24
Peak memory	386904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537431516 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during _key_req.2537431516
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1996452762
Short name	T236
Test name
Test status
Simulation time	58018243 ps
CPU time	0.98 seconds
Started	Sep 11 08:50:18 AM UTC 24
Finished	Sep 11 08:50:20 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996452762 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1996452762
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.3933075319
Short name	T229
Test name
Test status
Simulation time	370175226 ps
CPU time	25.16 seconds
Started	Sep 11 08:49:21 AM UTC 24
Finished	Sep 11 08:49:48 AM UTC 24
Peak memory	213836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933075319 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.3933075319
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.2101467458
Short name	T333
Test name
Test status
Simulation time	1385199592 ps
CPU time	519.12 seconds
Started	Sep 11 08:50:04 AM UTC 24
Finished	Sep 11 08:58:50 AM UTC 24
Peak memory	384884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101467458 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.2101467458
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1246980358
Short name	T231
Test name
Test status
Simulation time	1025424789 ps
CPU time	7.74 seconds
Started	Sep 11 08:49:54 AM UTC 24
Finished	Sep 11 08:50:03 AM UTC 24
Peak memory	228140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246980358 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.1246980358
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1880086979
Short name	T230
Test name
Test status
Simulation time	182243777 ps
CPU time	4.92 seconds
Started	Sep 11 08:49:46 AM UTC 24
Finished	Sep 11 08:49:52 AM UTC 24
Peak memory	235368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 880086979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma x_throughput.1880086979
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1406030503
Short name	T235
Test name
Test status
Simulation time	200021890 ps
CPU time	7.09 seconds
Started	Sep 11 08:50:09 AM UTC 24
Finished	Sep 11 08:50:17 AM UTC 24
Peak memory	224008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406030503 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.1406030503
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2344402635
Short name	T237
Test name
Test status
Simulation time	662457893 ps
CPU time	15.6 seconds
Started	Sep 11 08:50:05 AM UTC 24
Finished	Sep 11 08:50:23 AM UTC 24
Peak memory	224312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344402635 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.2344402635
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.851105613
Short name	T269
Test name
Test status
Simulation time	10312542928 ps
CPU time	201.28 seconds
Started	Sep 11 08:49:21 AM UTC 24
Finished	Sep 11 08:52:45 AM UTC 24
Peak memory	380764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851105613 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.851105613
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2509312182
Short name	T245
Test name
Test status
Simulation time	199991672 ps
CPU time	78.05 seconds
Started	Sep 11 08:49:34 AM UTC 24
Finished	Sep 11 08:50:54 AM UTC 24
Peak memory	364652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509312182 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.2509312182
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2833584904
Short name	T156
Test name
Test status
Simulation time	47259634294 ps
CPU time	294.8 seconds
Started	Sep 11 08:49:37 AM UTC 24
Finished	Sep 11 08:54:36 AM UTC 24
Peak memory	213976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833584904 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acc ess_b2b.2833584904
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.448922916
Short name	T234
Test name
Test status
Simulation time	27338648 ps
CPU time	1.2 seconds
Started	Sep 11 08:50:05 AM UTC 24
Finished	Sep 11 08:50:08 AM UTC 24
Peak memory	212408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448922916 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.448922916
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3130328636
Short name	T404
Test name
Test status
Simulation time	3568852085 ps
CPU time	918.07 seconds
Started	Sep 11 08:50:05 AM UTC 24
Finished	Sep 11 09:05:35 AM UTC 24
Peak memory	384872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130328636 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3130328636
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.2855848902
Short name	T228
Test name
Test status
Simulation time	482883354 ps
CPU time	15.11 seconds
Started	Sep 11 08:49:20 AM UTC 24
Finished	Sep 11 08:49:36 AM UTC 24
Peak memory	214112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855848902 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2855848902
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3946328710
Short name	T136
Test name
Test status
Simulation time	11923392339 ps
CPU time	429.07 seconds
Started	Sep 11 08:50:17 AM UTC 24
Finished	Sep 11 08:57:32 AM UTC 24
Peak memory	376804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394632871 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.3946328710
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1001452397
Short name	T142
Test name
Test status
Simulation time	1050293578 ps
CPU time	281.22 seconds
Started	Sep 11 08:50:12 AM UTC 24
Finished	Sep 11 08:54:57 AM UTC 24
Peak memory	380772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001452397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1001452397
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1511499186
Short name	T270
Test name
Test status
Simulation time	1998840978 ps
CPU time	207.24 seconds
Started	Sep 11 08:49:26 AM UTC 24
Finished	Sep 11 08:52:57 AM UTC 24
Peak memory	213756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511499186 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.1511499186
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.415143857
Short name	T238
Test name
Test status
Simulation time	351339647 ps
CPU time	39.31 seconds
Started	Sep 11 08:49:49 AM UTC 24
Finished	Sep 11 08:50:29 AM UTC 24
Peak memory	345956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 415143857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_th roughput_w_partial_write.415143857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2252135233
Short name	T285
Test name
Test status
Simulation time	1151407945 ps
CPU time	204.35 seconds
Started	Sep 11 08:50:53 AM UTC 24
Finished	Sep 11 08:54:21 AM UTC 24
Peak memory	331560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252135233 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during _key_req.2252135233
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.863363374
Short name	T253
Test name
Test status
Simulation time	11902723 ps
CPU time	0.93 seconds
Started	Sep 11 08:51:04 AM UTC 24
Finished	Sep 11 08:51:06 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863363374 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.863363374
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.1138788964
Short name	T248
Test name
Test status
Simulation time	5855027992 ps
CPU time	26.03 seconds
Started	Sep 11 08:50:30 AM UTC 24
Finished	Sep 11 08:50:57 AM UTC 24
Peak memory	214232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138788964 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.1138788964
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1859628957
Short name	T305
Test name
Test status
Simulation time	1646206930 ps
CPU time	311.64 seconds
Started	Sep 11 08:50:55 AM UTC 24
Finished	Sep 11 08:56:11 AM UTC 24
Peak memory	358264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859628957 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.1859628957
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.340177022
Short name	T247
Test name
Test status
Simulation time	1919965620 ps
CPU time	5.04 seconds
Started	Sep 11 08:50:49 AM UTC 24
Finished	Sep 11 08:50:55 AM UTC 24
Peak memory	214124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340177022 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.340177022
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3442599656
Short name	T246
Test name
Test status
Simulation time	167232727 ps
CPU time	5.27 seconds
Started	Sep 11 08:50:48 AM UTC 24
Finished	Sep 11 08:50:54 AM UTC 24
Peak memory	231272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 442599656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ma x_throughput.3442599656
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.988531163
Short name	T254
Test name
Test status
Simulation time	1119480158 ps
CPU time	7.82 seconds
Started	Sep 11 08:50:58 AM UTC 24
Finished	Sep 11 08:51:07 AM UTC 24
Peak memory	224012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988531163 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.988531163
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1691564108
Short name	T252
Test name
Test status
Simulation time	831237988 ps
CPU time	8.68 seconds
Started	Sep 11 08:50:56 AM UTC 24
Finished	Sep 11 08:51:06 AM UTC 24
Peak memory	224132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691564108 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.1691564108
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3753368163
Short name	T338
Test name
Test status
Simulation time	4092851439 ps
CPU time	515.41 seconds
Started	Sep 11 08:50:24 AM UTC 24
Finished	Sep 11 08:59:05 AM UTC 24
Peak memory	384940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753368163 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.3753368163
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3189091473
Short name	T242
Test name
Test status
Simulation time	8719959668 ps
CPU time	11.96 seconds
Started	Sep 11 08:50:36 AM UTC 24
Finished	Sep 11 08:50:49 AM UTC 24
Peak memory	213864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189091473 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.3189091473
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4199868264
Short name	T329
Test name
Test status
Simulation time	134190080268 ps
CPU time	438.75 seconds
Started	Sep 11 08:50:43 AM UTC 24
Finished	Sep 11 08:58:07 AM UTC 24
Peak memory	213856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199868264 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc ess_b2b.4199868264
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.1321007173
Short name	T249
Test name
Test status
Simulation time	33123697 ps
CPU time	1.17 seconds
Started	Sep 11 08:50:56 AM UTC 24
Finished	Sep 11 08:50:58 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321007173 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1321007173
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2054201505
Short name	T433
Test name
Test status
Simulation time	69014113514 ps
CPU time	1019.65 seconds
Started	Sep 11 08:50:55 AM UTC 24
Finished	Sep 11 09:08:06 AM UTC 24
Peak memory	384944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054201505 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2054201505
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2789906962
Short name	T240
Test name
Test status
Simulation time	1804400469 ps
CPU time	12.13 seconds
Started	Sep 11 08:50:21 AM UTC 24
Finished	Sep 11 08:50:35 AM UTC 24
Peak memory	213800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789906962 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2789906962
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2757290542
Short name	T626
Test name
Test status
Simulation time	53062246331 ps
CPU time	2014.84 seconds
Started	Sep 11 08:51:00 AM UTC 24
Finished	Sep 11 09:24:57 AM UTC 24
Peak memory	384888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275729054 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.2757290542
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4033532756
Short name	T62
Test name
Test status
Simulation time	1134552267 ps
CPU time	12.03 seconds
Started	Sep 11 08:50:59 AM UTC 24
Finished	Sep 11 08:51:13 AM UTC 24
Peak memory	224440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033532756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.4033532756
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.318242320
Short name	T273
Test name
Test status
Simulation time	6375896409 ps
CPU time	152 seconds
Started	Sep 11 08:50:33 AM UTC 24
Finished	Sep 11 08:53:07 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318242320 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.318242320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3234170782
Short name	T244
Test name
Test status
Simulation time	207076373 ps
CPU time	3.87 seconds
Started	Sep 11 08:50:49 AM UTC 24
Finished	Sep 11 08:50:54 AM UTC 24
Peak memory	231000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3234170782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t hroughput_w_partial_write.3234170782
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.4210948154
Short name	T436
Test name
Test status
Simulation time	16092265742 ps
CPU time	974.69 seconds
Started	Sep 11 08:51:58 AM UTC 24
Finished	Sep 11 09:08:24 AM UTC 24
Peak memory	384796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210948154 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during _key_req.4210948154
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3763101878
Short name	T265
Test name
Test status
Simulation time	22144419 ps
CPU time	0.89 seconds
Started	Sep 11 08:52:26 AM UTC 24
Finished	Sep 11 08:52:28 AM UTC 24
Peak memory	212808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763101878 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3763101878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.752313431
Short name	T259
Test name
Test status
Simulation time	626333022 ps
CPU time	47.56 seconds
Started	Sep 11 08:51:09 AM UTC 24
Finished	Sep 11 08:51:58 AM UTC 24
Peak memory	213788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752313431 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.752313431
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3443701270
Short name	T578
Test name
Test status
Simulation time	79498792900 ps
CPU time	1741.06 seconds
Started	Sep 11 08:52:00 AM UTC 24
Finished	Sep 11 09:21:18 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443701270 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.3443701270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3820990020
Short name	T261
Test name
Test status
Simulation time	380568479 ps
CPU time	5.75 seconds
Started	Sep 11 08:51:58 AM UTC 24
Finished	Sep 11 08:52:05 AM UTC 24
Peak memory	214128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820990020 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.3820990020
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1927102807
Short name	T258
Test name
Test status
Simulation time	214645532 ps
CPU time	17.27 seconds
Started	Sep 11 08:51:39 AM UTC 24
Finished	Sep 11 08:51:58 AM UTC 24
Peak memory	286476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 927102807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma x_throughput.1927102807
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.975656077
Short name	T264
Test name
Test status
Simulation time	586652703 ps
CPU time	7.27 seconds
Started	Sep 11 08:52:17 AM UTC 24
Finished	Sep 11 08:52:25 AM UTC 24
Peak memory	224080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975656077 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.975656077
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.1775701791
Short name	T263
Test name
Test status
Simulation time	226700851 ps
CPU time	7.03 seconds
Started	Sep 11 08:52:17 AM UTC 24
Finished	Sep 11 08:52:25 AM UTC 24
Peak memory	224132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775701791 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.1775701791
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2514817224
Short name	T382
Test name
Test status
Simulation time	13581265991 ps
CPU time	749.69 seconds
Started	Sep 11 08:51:08 AM UTC 24
Finished	Sep 11 09:03:46 AM UTC 24
Peak memory	380840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514817224 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.2514817224
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.304123030
Short name	T271
Test name
Test status
Simulation time	540754237 ps
CPU time	84.11 seconds
Started	Sep 11 08:51:32 AM UTC 24
Finished	Sep 11 08:52:58 AM UTC 24
Peak memory	352332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304123030 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.304123030
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1278986238
Short name	T344
Test name
Test status
Simulation time	81957558708 ps
CPU time	483.99 seconds
Started	Sep 11 08:51:32 AM UTC 24
Finished	Sep 11 08:59:42 AM UTC 24
Peak memory	213772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278986238 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acc ess_b2b.1278986238
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2740427427
Short name	T262
Test name
Test status
Simulation time	90024494 ps
CPU time	1.12 seconds
Started	Sep 11 08:52:14 AM UTC 24
Finished	Sep 11 08:52:16 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740427427 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2740427427
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.2518006191
Short name	T257
Test name
Test status
Simulation time	870071634 ps
CPU time	30.25 seconds
Started	Sep 11 08:51:06 AM UTC 24
Finished	Sep 11 08:51:38 AM UTC 24
Peak memory	319268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518006191 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2518006191
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1268105969
Short name	T521
Test name
Test status
Simulation time	79916313999 ps
CPU time	1443.92 seconds
Started	Sep 11 08:52:25 AM UTC 24
Finished	Sep 11 09:16:44 AM UTC 24
Peak memory	395100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126810596 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.1268105969
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.718493698
Short name	T138
Test name
Test status
Simulation time	737875229 ps
CPU time	310.47 seconds
Started	Sep 11 08:52:23 AM UTC 24
Finished	Sep 11 08:57:38 AM UTC 24
Peak memory	391004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718493698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.718493698
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3611834589
Short name	T286
Test name
Test status
Simulation time	7064856208 ps
CPU time	188.97 seconds
Started	Sep 11 08:51:14 AM UTC 24
Finished	Sep 11 08:54:26 AM UTC 24
Peak memory	213976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611834589 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.3611834589
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1484803302
Short name	T260
Test name
Test status
Simulation time	57475396 ps
CPU time	5.98 seconds
Started	Sep 11 08:51:52 AM UTC 24
Finished	Sep 11 08:51:59 AM UTC 24
Peak memory	237404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1484803302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_t hroughput_w_partial_write.1484803302
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2401689204
Short name	T432
Test name
Test status
Simulation time	33429858433 ps
CPU time	876.57 seconds
Started	Sep 11 08:53:08 AM UTC 24
Finished	Sep 11 09:07:54 AM UTC 24
Peak memory	383136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401689204 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during _key_req.2401689204
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.473154913
Short name	T282
Test name
Test status
Simulation time	18240156 ps
CPU time	0.99 seconds
Started	Sep 11 08:53:44 AM UTC 24
Finished	Sep 11 08:53:46 AM UTC 24
Peak memory	212632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473154913 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.473154913
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.551400788
Short name	T283
Test name
Test status
Simulation time	4517132236 ps
CPU time	80.25 seconds
Started	Sep 11 08:52:40 AM UTC 24
Finished	Sep 11 08:54:02 AM UTC 24
Peak memory	213936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551400788 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.551400788
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.3377474419
Short name	T378
Test name
Test status
Simulation time	6787695827 ps
CPU time	602.49 seconds
Started	Sep 11 08:53:15 AM UTC 24
Finished	Sep 11 09:03:25 AM UTC 24
Peak memory	348272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377474419 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.3377474419
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2634195493
Short name	T275
Test name
Test status
Simulation time	1106244602 ps
CPU time	10.56 seconds
Started	Sep 11 08:53:08 AM UTC 24
Finished	Sep 11 08:53:20 AM UTC 24
Peak memory	213868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634195493 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.2634195493
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.750487232
Short name	T272
Test name
Test status
Simulation time	57958797 ps
CPU time	8.31 seconds
Started	Sep 11 08:52:57 AM UTC 24
Finished	Sep 11 08:53:07 AM UTC 24
Peak memory	247912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 50487232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_max _throughput.750487232
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.758866980
Short name	T278
Test name
Test status
Simulation time	96678578 ps
CPU time	4.31 seconds
Started	Sep 11 08:53:35 AM UTC 24
Finished	Sep 11 08:53:41 AM UTC 24
Peak memory	224368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758866980 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.758866980
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2537120131
Short name	T279
Test name
Test status
Simulation time	370071981 ps
CPU time	8.39 seconds
Started	Sep 11 08:53:33 AM UTC 24
Finished	Sep 11 08:53:43 AM UTC 24
Peak memory	224100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537120131 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.2537120131
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1732780013
Short name	T312
Test name
Test status
Simulation time	4523904778 ps
CPU time	249.18 seconds
Started	Sep 11 08:52:29 AM UTC 24
Finished	Sep 11 08:56:42 AM UTC 24
Peak memory	383080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732780013 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.1732780013
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3341295858
Short name	T281
Test name
Test status
Simulation time	207008844 ps
CPU time	56.37 seconds
Started	Sep 11 08:52:45 AM UTC 24
Finished	Sep 11 08:53:43 AM UTC 24
Peak memory	360560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341295858 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.3341295858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2665254474
Short name	T319
Test name
Test status
Simulation time	3631351391 ps
CPU time	284.19 seconds
Started	Sep 11 08:52:46 AM UTC 24
Finished	Sep 11 08:57:35 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665254474 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acc ess_b2b.2665254474
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2937883268
Short name	T277
Test name
Test status
Simulation time	49688383 ps
CPU time	1.07 seconds
Started	Sep 11 08:53:32 AM UTC 24
Finished	Sep 11 08:53:34 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937883268 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2937883268
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.4010354040
Short name	T387
Test name
Test status
Simulation time	12096016060 ps
CPU time	655.25 seconds
Started	Sep 11 08:53:20 AM UTC 24
Finished	Sep 11 09:04:23 AM UTC 24
Peak memory	375024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010354040 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.4010354040
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.1114141000
Short name	T267
Test name
Test status
Simulation time	793370264 ps
CPU time	15.55 seconds
Started	Sep 11 08:52:26 AM UTC 24
Finished	Sep 11 08:52:42 AM UTC 24
Peak memory	214136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114141000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1114141000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3292101672
Short name	T339
Test name
Test status
Simulation time	3605100901 ps
CPU time	337.98 seconds
Started	Sep 11 08:53:44 AM UTC 24
Finished	Sep 11 08:59:26 AM UTC 24
Peak memory	358440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329210167 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.3292101672
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2415493860
Short name	T347
Test name
Test status
Simulation time	32472136436 ps
CPU time	418.73 seconds
Started	Sep 11 08:52:43 AM UTC 24
Finished	Sep 11 08:59:47 AM UTC 24
Peak memory	214200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415493860 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.2415493860
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3305756901
Short name	T284
Test name
Test status
Simulation time	640767383 ps
CPU time	67.68 seconds
Started	Sep 11 08:52:59 AM UTC 24
Finished	Sep 11 08:54:08 AM UTC 24
Peak memory	348004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3305756901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.3305756901
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2564280905
Short name	T541
Test name
Test status
Simulation time	13508884877 ps
CPU time	1347.83 seconds
Started	Sep 11 08:55:02 AM UTC 24
Finished	Sep 11 09:17:46 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564280905 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during _key_req.2564280905
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3262693751
Short name	T296
Test name
Test status
Simulation time	19821066 ps
CPU time	0.95 seconds
Started	Sep 11 08:55:23 AM UTC 24
Finished	Sep 11 08:55:25 AM UTC 24
Peak memory	212576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262693751 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3262693751
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1290052585
Short name	T295
Test name
Test status
Simulation time	21666981301 ps
CPU time	72.25 seconds
Started	Sep 11 08:54:09 AM UTC 24
Finished	Sep 11 08:55:23 AM UTC 24
Peak memory	213932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290052585 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1290052585
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.3083061106
Short name	T141
Test name
Test status
Simulation time	7969912737 ps
CPU time	416.41 seconds
Started	Sep 11 08:55:04 AM UTC 24
Finished	Sep 11 09:02:06 AM UTC 24
Peak memory	384864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083061106 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.3083061106
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1075841776
Short name	T289
Test name
Test status
Simulation time	190286957 ps
CPU time	1.48 seconds
Started	Sep 11 08:54:58 AM UTC 24
Finished	Sep 11 08:55:01 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075841776 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1075841776
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.999619167
Short name	T280
Test name
Test status
Simulation time	177925662 ps
CPU time	24.52 seconds
Started	Sep 11 08:54:38 AM UTC 24
Finished	Sep 11 08:55:03 AM UTC 24
Peak memory	304920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 99619167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_max _throughput.999619167
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2942701108
Short name	T297
Test name
Test status
Simulation time	2690009195 ps
CPU time	7.95 seconds
Started	Sep 11 08:55:17 AM UTC 24
Finished	Sep 11 08:55:26 AM UTC 24
Peak memory	224024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942701108 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.2942701108
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.874890484
Short name	T298
Test name
Test status
Simulation time	696159229 ps
CPU time	12.77 seconds
Started	Sep 11 08:55:15 AM UTC 24
Finished	Sep 11 08:55:29 AM UTC 24
Peak memory	224248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874890484 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.874890484
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3190605780
Short name	T439
Test name
Test status
Simulation time	32953382001 ps
CPU time	857.05 seconds
Started	Sep 11 08:54:03 AM UTC 24
Finished	Sep 11 09:08:30 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190605780 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3190605780
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3514310613
Short name	T287
Test name
Test status
Simulation time	152260641 ps
CPU time	5.23 seconds
Started	Sep 11 08:54:27 AM UTC 24
Finished	Sep 11 08:54:34 AM UTC 24
Peak memory	213724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514310613 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.3514310613
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2271655025
Short name	T371
Test name
Test status
Simulation time	201813208690 ps
CPU time	487.2 seconds
Started	Sep 11 08:54:34 AM UTC 24
Finished	Sep 11 09:02:48 AM UTC 24
Peak memory	213980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271655025 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acc ess_b2b.2271655025
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1607748500
Short name	T291
Test name
Test status
Simulation time	27854060 ps
CPU time	0.96 seconds
Started	Sep 11 08:55:13 AM UTC 24
Finished	Sep 11 08:55:16 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607748500 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1607748500
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3654964183
Short name	T140
Test name
Test status
Simulation time	423781456 ps
CPU time	91.32 seconds
Started	Sep 11 08:55:13 AM UTC 24
Finished	Sep 11 08:56:47 AM UTC 24
Peak memory	335656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654964183 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3654964183
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.342992768
Short name	T293
Test name
Test status
Simulation time	747205738 ps
CPU time	91.52 seconds
Started	Sep 11 08:53:47 AM UTC 24
Finished	Sep 11 08:55:20 AM UTC 24
Peak memory	378996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342992768 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.342992768
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1282709489
Short name	T764
Test name
Test status
Simulation time	10746061652 ps
CPU time	2665.37 seconds
Started	Sep 11 08:55:22 AM UTC 24
Finished	Sep 11 09:40:15 AM UTC 24
Peak memory	395436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128270948 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.1282709489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2498418563
Short name	T143
Test name
Test status
Simulation time	3928589008 ps
CPU time	122.71 seconds
Started	Sep 11 08:55:21 AM UTC 24
Finished	Sep 11 08:57:26 AM UTC 24
Peak memory	307132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498418563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2498418563
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2653409032
Short name	T350
Test name
Test status
Simulation time	6744297797 ps
CPU time	332.77 seconds
Started	Sep 11 08:54:22 AM UTC 24
Finished	Sep 11 09:00:00 AM UTC 24
Peak memory	213896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653409032 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.2653409032
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2265009983
Short name	T306
Test name
Test status
Simulation time	1628892723 ps
CPU time	95.41 seconds
Started	Sep 11 08:54:39 AM UTC 24
Finished	Sep 11 08:56:16 AM UTC 24
Peak memory	380764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2265009983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t hroughput_w_partial_write.2265009983
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.803819418
Short name	T534
Test name
Test status
Simulation time	24716077324 ps
CPU time	1275.64 seconds
Started	Sep 11 08:55:58 AM UTC 24
Finished	Sep 11 09:17:27 AM UTC 24
Peak memory	387176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803819418 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_ key_req.803819418
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.174094164
Short name	T313
Test name
Test status
Simulation time	27502575 ps
CPU time	0.87 seconds
Started	Sep 11 08:56:42 AM UTC 24
Finished	Sep 11 08:56:44 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174094164 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.174094164
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.623657111
Short name	T315
Test name
Test status
Simulation time	27533471151 ps
CPU time	94.58 seconds
Started	Sep 11 08:55:27 AM UTC 24
Finished	Sep 11 08:57:04 AM UTC 24
Peak memory	214304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623657111 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.623657111
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.3781163973
Short name	T318
Test name
Test status
Simulation time	4289869305 ps
CPU time	80.68 seconds
Started	Sep 11 08:56:11 AM UTC 24
Finished	Sep 11 08:57:34 AM UTC 24
Peak memory	214188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781163973 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.3781163973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.793076965
Short name	T304
Test name
Test status
Simulation time	1913105594 ps
CPU time	10.41 seconds
Started	Sep 11 08:55:46 AM UTC 24
Finished	Sep 11 08:55:58 AM UTC 24
Peak memory	213736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793076965 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.793076965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3810494308
Short name	T303
Test name
Test status
Simulation time	175553098 ps
CPU time	3.22 seconds
Started	Sep 11 08:55:41 AM UTC 24
Finished	Sep 11 08:55:45 AM UTC 24
Peak memory	224336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 810494308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma x_throughput.3810494308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1898218365
Short name	T310
Test name
Test status
Simulation time	64369469 ps
CPU time	6.69 seconds
Started	Sep 11 08:56:22 AM UTC 24
Finished	Sep 11 08:56:29 AM UTC 24
Peak memory	224288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898218365 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.1898218365
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2875609196
Short name	T311
Test name
Test status
Simulation time	461289780 ps
CPU time	12.86 seconds
Started	Sep 11 08:56:19 AM UTC 24
Finished	Sep 11 08:56:33 AM UTC 24
Peak memory	224112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875609196 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.2875609196
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1326027462
Short name	T331
Test name
Test status
Simulation time	24617223776 ps
CPU time	192.93 seconds
Started	Sep 11 08:55:26 AM UTC 24
Finished	Sep 11 08:58:42 AM UTC 24
Peak memory	329640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326027462 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.1326027462
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1686705188
Short name	T300
Test name
Test status
Simulation time	108933453 ps
CPU time	5.51 seconds
Started	Sep 11 08:55:33 AM UTC 24
Finished	Sep 11 08:55:39 AM UTC 24
Peak memory	214156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686705188 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1686705188
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2069807755
Short name	T332
Test name
Test status
Simulation time	1906938736 ps
CPU time	184.19 seconds
Started	Sep 11 08:55:41 AM UTC 24
Finished	Sep 11 08:58:48 AM UTC 24
Peak memory	213796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069807755 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acc ess_b2b.2069807755
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3420361478
Short name	T309
Test name
Test status
Simulation time	41629377 ps
CPU time	1.14 seconds
Started	Sep 11 08:56:19 AM UTC 24
Finished	Sep 11 08:56:21 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420361478 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3420361478
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.617223787
Short name	T520
Test name
Test status
Simulation time	85680413698 ps
CPU time	1204.77 seconds
Started	Sep 11 08:56:17 AM UTC 24
Finished	Sep 11 09:16:35 AM UTC 24
Peak memory	384944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617223787 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.617223787
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3454377868
Short name	T301
Test name
Test status
Simulation time	188006867 ps
CPU time	14.81 seconds
Started	Sep 11 08:55:24 AM UTC 24
Finished	Sep 11 08:55:40 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454377868 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3454377868
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1058606986
Short name	T918
Test name
Test status
Simulation time	13686846958 ps
CPU time	4501.38 seconds
Started	Sep 11 08:56:33 AM UTC 24
Finished	Sep 11 10:12:22 AM UTC 24
Peak memory	386988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105860698 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.1058606986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.82362795
Short name	T351
Test name
Test status
Simulation time	5722776843 ps
CPU time	269.54 seconds
Started	Sep 11 08:55:30 AM UTC 24
Finished	Sep 11 09:00:04 AM UTC 24
Peak memory	213980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82362795 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.82362795
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.3282879317
Short name	T321
Test name
Test status
Simulation time	974499665 ps
CPU time	121.32 seconds
Started	Sep 11 08:55:44 AM UTC 24
Finished	Sep 11 08:57:48 AM UTC 24
Peak memory	374624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3282879317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_t hroughput_w_partial_write.3282879317
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1429602813
Short name	T453
Test name
Test status
Simulation time	16000561831 ps
CPU time	746.89 seconds
Started	Sep 11 08:57:35 AM UTC 24
Finished	Sep 11 09:10:11 AM UTC 24
Peak memory	372544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429602813 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during _key_req.1429602813
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1743875476
Short name	T327
Test name
Test status
Simulation time	15114216 ps
CPU time	0.94 seconds
Started	Sep 11 08:57:58 AM UTC 24
Finished	Sep 11 08:58:00 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743875476 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.1743875476
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.3592701293
Short name	T323
Test name
Test status
Simulation time	4267899211 ps
CPU time	49.4 seconds
Started	Sep 11 08:57:00 AM UTC 24
Finished	Sep 11 08:57:51 AM UTC 24
Peak memory	214232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592701293 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.3592701293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.128938185
Short name	T393
Test name
Test status
Simulation time	6774727572 ps
CPU time	427.5 seconds
Started	Sep 11 08:57:38 AM UTC 24
Finished	Sep 11 09:04:51 AM UTC 24
Peak memory	384868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128938185 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.128938185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2469166627
Short name	T320
Test name
Test status
Simulation time	803361351 ps
CPU time	5.99 seconds
Started	Sep 11 08:57:35 AM UTC 24
Finished	Sep 11 08:57:42 AM UTC 24
Peak memory	224084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469166627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.2469166627
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1376599275
Short name	T335
Test name
Test status
Simulation time	167631989 ps
CPU time	80.75 seconds
Started	Sep 11 08:57:33 AM UTC 24
Finished	Sep 11 08:58:56 AM UTC 24
Peak memory	380776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 376599275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ma x_throughput.1376599275
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2651546553
Short name	T326
Test name
Test status
Simulation time	343845581 ps
CPU time	4.57 seconds
Started	Sep 11 08:57:52 AM UTC 24
Finished	Sep 11 08:57:57 AM UTC 24
Peak memory	224032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651546553 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.2651546553
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2917284066
Short name	T328
Test name
Test status
Simulation time	696344207 ps
CPU time	12.52 seconds
Started	Sep 11 08:57:50 AM UTC 24
Finished	Sep 11 08:58:03 AM UTC 24
Peak memory	224332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917284066 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.2917284066
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2356121686
Short name	T316
Test name
Test status
Simulation time	1884211160 ps
CPU time	41.46 seconds
Started	Sep 11 08:56:47 AM UTC 24
Finished	Sep 11 08:57:30 AM UTC 24
Peak memory	213868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356121686 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.2356121686
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2408695854
Short name	T317
Test name
Test status
Simulation time	274789438 ps
CPU time	4.41 seconds
Started	Sep 11 08:57:27 AM UTC 24
Finished	Sep 11 08:57:32 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408695854 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.2408695854
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1130201090
Short name	T368
Test name
Test status
Simulation time	14078308069 ps
CPU time	282.16 seconds
Started	Sep 11 08:57:31 AM UTC 24
Finished	Sep 11 09:02:17 AM UTC 24
Peak memory	213880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130201090 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc ess_b2b.1130201090
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1844627803
Short name	T324
Test name
Test status
Simulation time	102935745 ps
CPU time	1.13 seconds
Started	Sep 11 08:57:49 AM UTC 24
Finished	Sep 11 08:57:51 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844627803 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1844627803
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.3760828165
Short name	T543
Test name
Test status
Simulation time	14506062006 ps
CPU time	1197.04 seconds
Started	Sep 11 08:57:43 AM UTC 24
Finished	Sep 11 09:17:54 AM UTC 24
Peak memory	372596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760828165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3760828165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.2705744376
Short name	T314
Test name
Test status
Simulation time	190031373 ps
CPU time	12.41 seconds
Started	Sep 11 08:56:45 AM UTC 24
Finished	Sep 11 08:56:59 AM UTC 24
Peak memory	214076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705744376 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2705744376
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3639984800
Short name	T923
Test name
Test status
Simulation time	31818407505 ps
CPU time	4907.94 seconds
Started	Sep 11 08:57:57 AM UTC 24
Finished	Sep 11 10:20:36 AM UTC 24
Peak memory	397224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363998480 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.3639984800
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1452530059
Short name	T360
Test name
Test status
Simulation time	2340842611 ps
CPU time	224.75 seconds
Started	Sep 11 08:57:05 AM UTC 24
Finished	Sep 11 09:00:53 AM UTC 24
Peak memory	213896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452530059 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.1452530059
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3414350761
Short name	T322
Test name
Test status
Simulation time	79494044 ps
CPU time	14.06 seconds
Started	Sep 11 08:57:33 AM UTC 24
Finished	Sep 11 08:57:48 AM UTC 24
Peak memory	280340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3414350761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t hroughput_w_partial_write.3414350761
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2502144920
Short name	T522
Test name
Test status
Simulation time	3046752141 ps
CPU time	1060.25 seconds
Started	Sep 11 08:59:00 AM UTC 24
Finished	Sep 11 09:16:52 AM UTC 24
Peak memory	385184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502144920 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during _key_req.2502144920
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.595934956
Short name	T345
Test name
Test status
Simulation time	15627467 ps
CPU time	1.09 seconds
Started	Sep 11 08:59:43 AM UTC 24
Finished	Sep 11 08:59:45 AM UTC 24
Peak memory	212632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595934956 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.595934956
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1833621198
Short name	T340
Test name
Test status
Simulation time	4040075698 ps
CPU time	76.1 seconds
Started	Sep 11 08:58:09 AM UTC 24
Finished	Sep 11 08:59:27 AM UTC 24
Peak memory	213908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833621198 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1833621198
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1781215870
Short name	T389
Test name
Test status
Simulation time	7149068951 ps
CPU time	326.99 seconds
Started	Sep 11 08:59:06 AM UTC 24
Finished	Sep 11 09:04:38 AM UTC 24
Peak memory	358316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781215870 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.1781215870
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1576335616
Short name	T337
Test name
Test status
Simulation time	520428740 ps
CPU time	6.83 seconds
Started	Sep 11 08:58:56 AM UTC 24
Finished	Sep 11 08:59:04 AM UTC 24
Peak memory	213872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576335616 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.1576335616
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1828405852
Short name	T349
Test name
Test status
Simulation time	157500238 ps
CPU time	65.3 seconds
Started	Sep 11 08:58:51 AM UTC 24
Finished	Sep 11 08:59:58 AM UTC 24
Peak memory	358248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 828405852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma x_throughput.1828405852
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1553496744
Short name	T342
Test name
Test status
Simulation time	112611825 ps
CPU time	4.44 seconds
Started	Sep 11 08:59:30 AM UTC 24
Finished	Sep 11 08:59:36 AM UTC 24
Peak memory	223960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553496744 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1553496744
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.202053280
Short name	T343
Test name
Test status
Simulation time	469041233 ps
CPU time	11.55 seconds
Started	Sep 11 08:59:28 AM UTC 24
Finished	Sep 11 08:59:41 AM UTC 24
Peak memory	224436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202053280 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.202053280
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.636589996
Short name	T535
Test name
Test status
Simulation time	54279145575 ps
CPU time	1150.49 seconds
Started	Sep 11 08:58:04 AM UTC 24
Finished	Sep 11 09:17:27 AM UTC 24
Peak memory	381036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636589996 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.636589996
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2495747398
Short name	T334
Test name
Test status
Simulation time	124160914 ps
CPU time	6.68 seconds
Started	Sep 11 08:58:43 AM UTC 24
Finished	Sep 11 08:58:51 AM UTC 24
Peak memory	213872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495747398 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.2495747398
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3051531971
Short name	T411
Test name
Test status
Simulation time	16052972843 ps
CPU time	423.52 seconds
Started	Sep 11 08:58:49 AM UTC 24
Finished	Sep 11 09:05:58 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051531971 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc ess_b2b.3051531971
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3503656502
Short name	T341
Test name
Test status
Simulation time	89994251 ps
CPU time	1.13 seconds
Started	Sep 11 08:59:27 AM UTC 24
Finished	Sep 11 08:59:29 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503656502 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3503656502
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.3220177183
Short name	T526
Test name
Test status
Simulation time	12335795056 ps
CPU time	1068.14 seconds
Started	Sep 11 08:59:07 AM UTC 24
Finished	Sep 11 09:17:06 AM UTC 24
Peak memory	376676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220177183 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3220177183
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.3332157693
Short name	T330
Test name
Test status
Simulation time	975406850 ps
CPU time	22.96 seconds
Started	Sep 11 08:58:01 AM UTC 24
Finished	Sep 11 08:58:26 AM UTC 24
Peak memory	276332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332157693 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3332157693
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.688394917
Short name	T573
Test name
Test status
Simulation time	41608670139 ps
CPU time	1230.76 seconds
Started	Sep 11 08:59:41 AM UTC 24
Finished	Sep 11 09:20:25 AM UTC 24
Peak memory	382896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688394917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.688394917
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2664807016
Short name	T391
Test name
Test status
Simulation time	8268843023 ps
CPU time	303.79 seconds
Started	Sep 11 08:59:36 AM UTC 24
Finished	Sep 11 09:04:45 AM UTC 24
Peak memory	380912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664807016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2664807016
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.502069712
Short name	T376
Test name
Test status
Simulation time	26411879043 ps
CPU time	287.01 seconds
Started	Sep 11 08:58:27 AM UTC 24
Finished	Sep 11 09:03:18 AM UTC 24
Peak memory	213972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502069712 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.502069712
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.311236217
Short name	T336
Test name
Test status
Simulation time	206474330 ps
CPU time	7.57 seconds
Started	Sep 11 08:58:51 AM UTC 24
Finished	Sep 11 08:59:00 AM UTC 24
Peak memory	247908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 311236217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_th roughput_w_partial_write.311236217
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3073591689
Short name	T35
Test name
Test status
Simulation time	2196835090 ps
CPU time	525 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:49:34 AM UTC 24
Peak memory	381096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073591689 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_ key_req.3073591689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.4069419705
Short name	T11
Test name
Test status
Simulation time	25167787 ps
CPU time	0.58 seconds
Started	Sep 11 08:40:35 AM UTC 24
Finished	Sep 11 08:40:39 AM UTC 24
Peak memory	212628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069419705 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4069419705
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.409095690
Short name	T170
Test name
Test status
Simulation time	2323207873 ps
CPU time	59.4 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:41:43 AM UTC 24
Peak memory	213992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409095690 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.409095690
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.3730139087
Short name	T384
Test name
Test status
Simulation time	20606111344 ps
CPU time	1394.14 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 09:04:11 AM UTC 24
Peak memory	384912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730139087 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.3730139087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1761008524
Short name	T50
Test name
Test status
Simulation time	71156856 ps
CPU time	12.72 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:40:59 AM UTC 24
Peak memory	264036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 761008524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max _throughput.1761008524
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2321562118
Short name	T31
Test name
Test status
Simulation time	172340859 ps
CPU time	5.4 seconds
Started	Sep 11 08:40:29 AM UTC 24
Finished	Sep 11 08:40:49 AM UTC 24
Peak memory	224248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321562118 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.2321562118
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3348236227
Short name	T63
Test name
Test status
Simulation time	217247580 ps
CPU time	8.28 seconds
Started	Sep 11 08:40:27 AM UTC 24
Finished	Sep 11 08:40:54 AM UTC 24
Peak memory	224140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348236227 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.3348236227
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4294201540
Short name	T232
Test name
Test status
Simulation time	43678138048 ps
CPU time	562.01 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:50:03 AM UTC 24
Peak memory	384852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294201540 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.4294201540
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2047721653
Short name	T65
Test name
Test status
Simulation time	2150083196 ps
CPU time	10.82 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:40:54 AM UTC 24
Peak memory	213752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047721653 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.2047721653
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3827814679
Short name	T250
Test name
Test status
Simulation time	76357087910 ps
CPU time	606.28 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:50:59 AM UTC 24
Peak memory	213968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827814679 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce ss_b2b.3827814679
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2431910599
Short name	T13
Test name
Test status
Simulation time	38225478 ps
CPU time	0.77 seconds
Started	Sep 11 08:40:26 AM UTC 24
Finished	Sep 11 08:40:46 AM UTC 24
Peak memory	212684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431910599 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2431910599
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.4253496271
Short name	T27
Test name
Test status
Simulation time	1501317729 ps
CPU time	19.08 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:41:03 AM UTC 24
Peak memory	265992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253496271 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.4253496271
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.3266262864
Short name	T150
Test name
Test status
Simulation time	205829851 ps
CPU time	90.22 seconds
Started	Sep 11 08:40:24 AM UTC 24
Finished	Sep 11 08:42:09 AM UTC 24
Peak memory	380784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266262864 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3266262864
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1430676894
Short name	T848
Test name
Test status
Simulation time	54752914473 ps
CPU time	3974.51 seconds
Started	Sep 11 08:40:31 AM UTC 24
Finished	Sep 11 09:47:39 AM UTC 24
Peak memory	386980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143067689 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.1430676894
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.202445099
Short name	T18
Test name
Test status
Simulation time	2009381478 ps
CPU time	396.56 seconds
Started	Sep 11 08:40:30 AM UTC 24
Finished	Sep 11 08:47:19 AM UTC 24
Peak memory	368760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202445099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.202445099
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3877393270
Short name	T96
Test name
Test status
Simulation time	3669982410 ps
CPU time	168.2 seconds
Started	Sep 11 08:40:25 AM UTC 24
Finished	Sep 11 08:43:33 AM UTC 24
Peak memory	213908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877393270 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.3877393270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2531500233
Short name	T417
Test name
Test status
Simulation time	1503189023 ps
CPU time	372.53 seconds
Started	Sep 11 09:00:18 AM UTC 24
Finished	Sep 11 09:06:36 AM UTC 24
Peak memory	380768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531500233 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during _key_req.2531500233
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1268624246
Short name	T361
Test name
Test status
Simulation time	28197568 ps
CPU time	0.89 seconds
Started	Sep 11 09:00:56 AM UTC 24
Finished	Sep 11 09:00:58 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268624246 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1268624246
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.785186496
Short name	T363
Test name
Test status
Simulation time	7545541933 ps
CPU time	97 seconds
Started	Sep 11 08:59:49 AM UTC 24
Finished	Sep 11 09:01:28 AM UTC 24
Peak memory	213832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785186496 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.785186496
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3082946787
Short name	T431
Test name
Test status
Simulation time	7070521556 ps
CPU time	443.57 seconds
Started	Sep 11 09:00:20 AM UTC 24
Finished	Sep 11 09:07:49 AM UTC 24
Peak memory	382836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082946787 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.3082946787
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.47119691
Short name	T353
Test name
Test status
Simulation time	561359540 ps
CPU time	8.59 seconds
Started	Sep 11 09:00:08 AM UTC 24
Finished	Sep 11 09:00:18 AM UTC 24
Peak memory	214156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47119691 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.47119691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.935577731
Short name	T358
Test name
Test status
Simulation time	422407759 ps
CPU time	44.99 seconds
Started	Sep 11 09:00:00 AM UTC 24
Finished	Sep 11 09:00:47 AM UTC 24
Peak memory	333800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 35577731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max _throughput.935577731
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1005095768
Short name	T346
Test name
Test status
Simulation time	367823563 ps
CPU time	7.32 seconds
Started	Sep 11 09:00:47 AM UTC 24
Finished	Sep 11 09:00:55 AM UTC 24
Peak memory	224416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005095768 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.1005095768
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.1529036182
Short name	T359
Test name
Test status
Simulation time	540329661 ps
CPU time	9.83 seconds
Started	Sep 11 09:00:40 AM UTC 24
Finished	Sep 11 09:00:51 AM UTC 24
Peak memory	224132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529036182 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.1529036182
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2027383723
Short name	T366
Test name
Test status
Simulation time	1047590427 ps
CPU time	111.78 seconds
Started	Sep 11 08:59:48 AM UTC 24
Finished	Sep 11 09:01:42 AM UTC 24
Peak memory	308964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027383723 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.2027383723
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1467790206
Short name	T352
Test name
Test status
Simulation time	203017157 ps
CPU time	7.54 seconds
Started	Sep 11 08:59:59 AM UTC 24
Finished	Sep 11 09:00:08 AM UTC 24
Peak memory	235628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467790206 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.1467790206
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1719363096
Short name	T426
Test name
Test status
Simulation time	65738818016 ps
CPU time	439.4 seconds
Started	Sep 11 08:59:59 AM UTC 24
Finished	Sep 11 09:07:24 AM UTC 24
Peak memory	214192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719363096 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc ess_b2b.1719363096
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2398390886
Short name	T357
Test name
Test status
Simulation time	52802745 ps
CPU time	1.12 seconds
Started	Sep 11 09:00:37 AM UTC 24
Finished	Sep 11 09:00:39 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398390886 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2398390886
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.4089341989
Short name	T487
Test name
Test status
Simulation time	11867122005 ps
CPU time	768.91 seconds
Started	Sep 11 09:00:31 AM UTC 24
Finished	Sep 11 09:13:29 AM UTC 24
Peak memory	372588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089341989 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.4089341989
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.3412055540
Short name	T362
Test name
Test status
Simulation time	576716182 ps
CPU time	95.82 seconds
Started	Sep 11 08:59:47 AM UTC 24
Finished	Sep 11 09:01:24 AM UTC 24
Peak memory	360300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412055540 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3412055540
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1179436872
Short name	T514
Test name
Test status
Simulation time	47008559819 ps
CPU time	901.2 seconds
Started	Sep 11 09:00:53 AM UTC 24
Finished	Sep 11 09:16:04 AM UTC 24
Peak memory	385144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117943687 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.1179436872
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3020895675
Short name	T370
Test name
Test status
Simulation time	397674296 ps
CPU time	109.94 seconds
Started	Sep 11 09:00:52 AM UTC 24
Finished	Sep 11 09:02:44 AM UTC 24
Peak memory	345960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020895675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3020895675
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3048536893
Short name	T383
Test name
Test status
Simulation time	45856340439 ps
CPU time	237.77 seconds
Started	Sep 11 08:59:53 AM UTC 24
Finished	Sep 11 09:03:54 AM UTC 24
Peak memory	214152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048536893 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.3048536893
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1453725334
Short name	T356
Test name
Test status
Simulation time	92921291 ps
CPU time	27.72 seconds
Started	Sep 11 09:00:07 AM UTC 24
Finished	Sep 11 09:00:36 AM UTC 24
Peak memory	286560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1453725334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t hroughput_w_partial_write.1453725334
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.4050517812
Short name	T624
Test name
Test status
Simulation time	15849719048 ps
CPU time	1334.85 seconds
Started	Sep 11 09:02:18 AM UTC 24
Finished	Sep 11 09:24:45 AM UTC 24
Peak memory	384980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050517812 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during _key_req.4050517812
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.4122457052
Short name	T377
Test name
Test status
Simulation time	40428394 ps
CPU time	1.05 seconds
Started	Sep 11 09:03:19 AM UTC 24
Finished	Sep 11 09:03:21 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122457052 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.4122457052
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.257167688
Short name	T367
Test name
Test status
Simulation time	1277476958 ps
CPU time	21.85 seconds
Started	Sep 11 09:01:25 AM UTC 24
Finished	Sep 11 09:01:48 AM UTC 24
Peak memory	213840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257167688 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.257167688
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1539722966
Short name	T667
Test name
Test status
Simulation time	14801387135 ps
CPU time	1603.38 seconds
Started	Sep 11 09:02:24 AM UTC 24
Finished	Sep 11 09:29:25 AM UTC 24
Peak memory	380844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539722966 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.1539722966
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.2573023858
Short name	T369
Test name
Test status
Simulation time	5393976307 ps
CPU time	14.97 seconds
Started	Sep 11 09:02:07 AM UTC 24
Finished	Sep 11 09:02:23 AM UTC 24
Peak memory	213908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573023858 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.2573023858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3410333851
Short name	T374
Test name
Test status
Simulation time	135264344 ps
CPU time	85.61 seconds
Started	Sep 11 09:01:42 AM UTC 24
Finished	Sep 11 09:03:10 AM UTC 24
Peak memory	380708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 410333851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma x_throughput.3410333851
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1863098008
Short name	T375
Test name
Test status
Simulation time	435915374 ps
CPU time	8.52 seconds
Started	Sep 11 09:03:04 AM UTC 24
Finished	Sep 11 09:03:14 AM UTC 24
Peak memory	224240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863098008 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.1863098008
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1549119007
Short name	T373
Test name
Test status
Simulation time	281604066 ps
CPU time	10.3 seconds
Started	Sep 11 09:02:52 AM UTC 24
Finished	Sep 11 09:03:04 AM UTC 24
Peak memory	224084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549119007 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1549119007
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.4209078625
Short name	T456
Test name
Test status
Simulation time	2012337266 ps
CPU time	546.38 seconds
Started	Sep 11 09:01:05 AM UTC 24
Finished	Sep 11 09:10:18 AM UTC 24
Peak memory	382728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209078625 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.4209078625
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.646098863
Short name	T365
Test name
Test status
Simulation time	61679286 ps
CPU time	2.79 seconds
Started	Sep 11 09:01:37 AM UTC 24
Finished	Sep 11 09:01:41 AM UTC 24
Peak memory	213804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646098863 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.646098863
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1080691767
Short name	T407
Test name
Test status
Simulation time	30191237586 ps
CPU time	241.68 seconds
Started	Sep 11 09:01:42 AM UTC 24
Finished	Sep 11 09:05:48 AM UTC 24
Peak memory	213688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080691767 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc ess_b2b.1080691767
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.926473682
Short name	T372
Test name
Test status
Simulation time	52359282 ps
CPU time	1.02 seconds
Started	Sep 11 09:02:49 AM UTC 24
Finished	Sep 11 09:02:51 AM UTC 24
Peak memory	212408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926473682 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.926473682
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1235893164
Short name	T454
Test name
Test status
Simulation time	47907668037 ps
CPU time	443.99 seconds
Started	Sep 11 09:02:45 AM UTC 24
Finished	Sep 11 09:10:15 AM UTC 24
Peak memory	385140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235893164 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1235893164
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.3623159130
Short name	T364
Test name
Test status
Simulation time	3355381555 ps
CPU time	35.02 seconds
Started	Sep 11 09:01:00 AM UTC 24
Finished	Sep 11 09:01:36 AM UTC 24
Peak memory	317360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623159130 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3623159130
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.4290209647
Short name	T820
Test name
Test status
Simulation time	76962044807 ps
CPU time	2534.8 seconds
Started	Sep 11 09:03:15 AM UTC 24
Finished	Sep 11 09:45:56 AM UTC 24
Peak memory	385256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429020964 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.4290209647
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3021531265
Short name	T415
Test name
Test status
Simulation time	1399092739 ps
CPU time	189.78 seconds
Started	Sep 11 09:03:10 AM UTC 24
Finished	Sep 11 09:06:23 AM UTC 24
Peak memory	368556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021531265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3021531265
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3956547081
Short name	T380
Test name
Test status
Simulation time	1029523902 ps
CPU time	117.52 seconds
Started	Sep 11 09:01:29 AM UTC 24
Finished	Sep 11 09:03:29 AM UTC 24
Peak memory	213808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956547081 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.3956547081
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.4042907508
Short name	T379
Test name
Test status
Simulation time	165359934 ps
CPU time	95.06 seconds
Started	Sep 11 09:01:48 AM UTC 24
Finished	Sep 11 09:03:25 AM UTC 24
Peak memory	380776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4042907508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_t hroughput_w_partial_write.4042907508
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1124796310
Short name	T637
Test name
Test status
Simulation time	3501360286 ps
CPU time	1271 seconds
Started	Sep 11 09:04:21 AM UTC 24
Finished	Sep 11 09:25:46 AM UTC 24
Peak memory	380760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124796310 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during _key_req.1124796310
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.172936254
Short name	T396
Test name
Test status
Simulation time	38709033 ps
CPU time	1.03 seconds
Started	Sep 11 09:04:52 AM UTC 24
Finished	Sep 11 09:04:54 AM UTC 24
Peak memory	212632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172936254 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.172936254
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3897464263
Short name	T399
Test name
Test status
Simulation time	3763399598 ps
CPU time	92.82 seconds
Started	Sep 11 09:03:26 AM UTC 24
Finished	Sep 11 09:05:01 AM UTC 24
Peak memory	214228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897464263 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.3897464263
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.1555237272
Short name	T542
Test name
Test status
Simulation time	25104637605 ps
CPU time	799.44 seconds
Started	Sep 11 09:04:24 AM UTC 24
Finished	Sep 11 09:17:53 AM UTC 24
Peak memory	384880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555237272 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.1555237272
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3903408627
Short name	T388
Test name
Test status
Simulation time	1668101981 ps
CPU time	7.79 seconds
Started	Sep 11 09:04:15 AM UTC 24
Finished	Sep 11 09:04:24 AM UTC 24
Peak memory	224412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903408627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.3903408627
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.893972058
Short name	T385
Test name
Test status
Simulation time	269949644 ps
CPU time	18.54 seconds
Started	Sep 11 09:03:54 AM UTC 24
Finished	Sep 11 09:04:14 AM UTC 24
Peak memory	272228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 93972058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max _throughput.893972058
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.384961088
Short name	T392
Test name
Test status
Simulation time	338981775 ps
CPU time	7.69 seconds
Started	Sep 11 09:04:40 AM UTC 24
Finished	Sep 11 09:04:49 AM UTC 24
Peak memory	224040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384961088 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.384961088
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2333012445
Short name	T395
Test name
Test status
Simulation time	443806662 ps
CPU time	13.09 seconds
Started	Sep 11 09:04:39 AM UTC 24
Finished	Sep 11 09:04:53 AM UTC 24
Peak memory	224056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333012445 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.2333012445
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3777148638
Short name	T471
Test name
Test status
Simulation time	12522631534 ps
CPU time	486.71 seconds
Started	Sep 11 09:03:26 AM UTC 24
Finished	Sep 11 09:11:38 AM UTC 24
Peak memory	378720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777148638 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.3777148638
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4093577823
Short name	T401
Test name
Test status
Simulation time	578249726 ps
CPU time	96.92 seconds
Started	Sep 11 09:03:36 AM UTC 24
Finished	Sep 11 09:05:15 AM UTC 24
Peak memory	380784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093577823 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.4093577823
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1841466878
Short name	T483
Test name
Test status
Simulation time	62991218192 ps
CPU time	532.47 seconds
Started	Sep 11 09:03:47 AM UTC 24
Finished	Sep 11 09:12:47 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841466878 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc ess_b2b.1841466878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.641798362
Short name	T390
Test name
Test status
Simulation time	82677145 ps
CPU time	1.09 seconds
Started	Sep 11 09:04:37 AM UTC 24
Finished	Sep 11 09:04:39 AM UTC 24
Peak memory	212528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641798362 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.641798362
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.3541382423
Short name	T494
Test name
Test status
Simulation time	25341292914 ps
CPU time	582.34 seconds
Started	Sep 11 09:04:24 AM UTC 24
Finished	Sep 11 09:14:14 AM UTC 24
Peak memory	368484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541382423 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3541382423
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.988930490
Short name	T381
Test name
Test status
Simulation time	810336304 ps
CPU time	12.62 seconds
Started	Sep 11 09:03:22 AM UTC 24
Finished	Sep 11 09:03:36 AM UTC 24
Peak memory	253672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988930490 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.988930490
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2193791090
Short name	T915
Test name
Test status
Simulation time	40621537636 ps
CPU time	3650.93 seconds
Started	Sep 11 09:04:49 AM UTC 24
Finished	Sep 11 10:06:20 AM UTC 24
Peak memory	387240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219379109 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.2193791090
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3232956256
Short name	T416
Test name
Test status
Simulation time	550658084 ps
CPU time	102.58 seconds
Started	Sep 11 09:04:46 AM UTC 24
Finished	Sep 11 09:06:31 AM UTC 24
Peak memory	317240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232956256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3232956256
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.64031141
Short name	T446
Test name
Test status
Simulation time	12857221186 ps
CPU time	355.65 seconds
Started	Sep 11 09:03:30 AM UTC 24
Finished	Sep 11 09:09:31 AM UTC 24
Peak memory	214184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64031141 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.64031141
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2469007599
Short name	T414
Test name
Test status
Simulation time	303706294 ps
CPU time	113.46 seconds
Started	Sep 11 09:04:13 AM UTC 24
Finished	Sep 11 09:06:08 AM UTC 24
Peak memory	380896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2469007599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t hroughput_w_partial_write.2469007599
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2943836711
Short name	T588
Test name
Test status
Simulation time	16685096873 ps
CPU time	969.47 seconds
Started	Sep 11 09:05:28 AM UTC 24
Finished	Sep 11 09:21:48 AM UTC 24
Peak memory	382820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943836711 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during _key_req.2943836711
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3842923803
Short name	T412
Test name
Test status
Simulation time	68961771 ps
CPU time	0.94 seconds
Started	Sep 11 09:05:57 AM UTC 24
Finished	Sep 11 09:05:59 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842923803 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3842923803
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2438501193
Short name	T405
Test name
Test status
Simulation time	2392034565 ps
CPU time	42.49 seconds
Started	Sep 11 09:04:56 AM UTC 24
Finished	Sep 11 09:05:40 AM UTC 24
Peak memory	213976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438501193 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.2438501193
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.173749325
Short name	T517
Test name
Test status
Simulation time	2898313472 ps
CPU time	640.74 seconds
Started	Sep 11 09:05:31 AM UTC 24
Finished	Sep 11 09:16:19 AM UTC 24
Peak memory	379120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173749325 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.173749325
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.408472979
Short name	T403
Test name
Test status
Simulation time	319181254 ps
CPU time	2.79 seconds
Started	Sep 11 09:05:27 AM UTC 24
Finished	Sep 11 09:05:31 AM UTC 24
Peak memory	213832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408472979 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.408472979
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.4007766810
Short name	T413
Test name
Test status
Simulation time	225947074 ps
CPU time	48.92 seconds
Started	Sep 11 09:05:10 AM UTC 24
Finished	Sep 11 09:06:00 AM UTC 24
Peak memory	338084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 007766810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma x_throughput.4007766810
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3420167818
Short name	T409
Test name
Test status
Simulation time	92946633 ps
CPU time	4.44 seconds
Started	Sep 11 09:05:49 AM UTC 24
Finished	Sep 11 09:05:54 AM UTC 24
Peak memory	224008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420167818 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3420167818
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2422193286
Short name	T408
Test name
Test status
Simulation time	905100626 ps
CPU time	7.63 seconds
Started	Sep 11 09:05:43 AM UTC 24
Finished	Sep 11 09:05:52 AM UTC 24
Peak memory	224128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422193286 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2422193286
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.978658535
Short name	T507
Test name
Test status
Simulation time	35534233532 ps
CPU time	643.06 seconds
Started	Sep 11 09:04:54 AM UTC 24
Finished	Sep 11 09:15:45 AM UTC 24
Peak memory	387044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978658535 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.978658535
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1378169926
Short name	T400
Test name
Test status
Simulation time	95910885 ps
CPU time	6.89 seconds
Started	Sep 11 09:05:01 AM UTC 24
Finished	Sep 11 09:05:09 AM UTC 24
Peak memory	213768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378169926 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.1378169926
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1244763962
Short name	T459
Test name
Test status
Simulation time	22212733924 ps
CPU time	327.04 seconds
Started	Sep 11 09:05:02 AM UTC 24
Finished	Sep 11 09:10:34 AM UTC 24
Peak memory	213876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244763962 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acc ess_b2b.1244763962
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.10411299
Short name	T406
Test name
Test status
Simulation time	125517544 ps
CPU time	1.04 seconds
Started	Sep 11 09:05:40 AM UTC 24
Finished	Sep 11 09:05:42 AM UTC 24
Peak memory	212532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10411299 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.10411299
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.4280467820
Short name	T473
Test name
Test status
Simulation time	7241505052 ps
CPU time	375.27 seconds
Started	Sep 11 09:05:36 AM UTC 24
Finished	Sep 11 09:11:56 AM UTC 24
Peak memory	370536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280467820 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.4280467820
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.4108715769
Short name	T398
Test name
Test status
Simulation time	353595654 ps
CPU time	5.79 seconds
Started	Sep 11 09:04:53 AM UTC 24
Finished	Sep 11 09:05:00 AM UTC 24
Peak memory	214220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108715769 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.4108715769
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3373368682
Short name	T890
Test name
Test status
Simulation time	38869668539 ps
CPU time	2878.95 seconds
Started	Sep 11 09:05:55 AM UTC 24
Finished	Sep 11 09:54:23 AM UTC 24
Peak memory	384932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337336868 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.3373368682
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2522119433
Short name	T491
Test name
Test status
Simulation time	4327624804 ps
CPU time	489.62 seconds
Started	Sep 11 09:05:53 AM UTC 24
Finished	Sep 11 09:14:08 AM UTC 24
Peak memory	391080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522119433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2522119433
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1651895996
Short name	T420
Test name
Test status
Simulation time	1044912549 ps
CPU time	120.83 seconds
Started	Sep 11 09:05:01 AM UTC 24
Finished	Sep 11 09:07:04 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651895996 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1651895996
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.4227555591
Short name	T402
Test name
Test status
Simulation time	235181153 ps
CPU time	8.86 seconds
Started	Sep 11 09:05:16 AM UTC 24
Finished	Sep 11 09:05:26 AM UTC 24
Peak memory	249960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4227555591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_t hroughput_w_partial_write.4227555591
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2365382804
Short name	T527
Test name
Test status
Simulation time	3738428307 ps
CPU time	597.47 seconds
Started	Sep 11 09:07:05 AM UTC 24
Finished	Sep 11 09:17:10 AM UTC 24
Peak memory	360608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365382804 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during _key_req.2365382804
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.285093898
Short name	T430
Test name
Test status
Simulation time	55284772 ps
CPU time	0.91 seconds
Started	Sep 11 09:07:34 AM UTC 24
Finished	Sep 11 09:07:37 AM UTC 24
Peak memory	212804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285093898 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.285093898
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1591695419
Short name	T429
Test name
Test status
Simulation time	9498759450 ps
CPU time	93.26 seconds
Started	Sep 11 09:06:01 AM UTC 24
Finished	Sep 11 09:07:36 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591695419 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.1591695419
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2611327065
Short name	T468
Test name
Test status
Simulation time	8587336099 ps
CPU time	238.19 seconds
Started	Sep 11 09:07:06 AM UTC 24
Finished	Sep 11 09:11:08 AM UTC 24
Peak memory	335716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611327065 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.2611327065
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.577509366
Short name	T421
Test name
Test status
Simulation time	282918635 ps
CPU time	4.57 seconds
Started	Sep 11 09:07:00 AM UTC 24
Finished	Sep 11 09:07:06 AM UTC 24
Peak memory	224364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577509366 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.577509366
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2729649195
Short name	T418
Test name
Test status
Simulation time	166580645 ps
CPU time	2.73 seconds
Started	Sep 11 09:06:37 AM UTC 24
Finished	Sep 11 09:06:41 AM UTC 24
Peak memory	231220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 729649195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ma x_throughput.2729649195
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2106585385
Short name	T427
Test name
Test status
Simulation time	112625808 ps
CPU time	5.23 seconds
Started	Sep 11 09:07:24 AM UTC 24
Finished	Sep 11 09:07:30 AM UTC 24
Peak memory	224056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106585385 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.2106585385
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1047149943
Short name	T425
Test name
Test status
Simulation time	95183725 ps
CPU time	6.83 seconds
Started	Sep 11 09:07:14 AM UTC 24
Finished	Sep 11 09:07:22 AM UTC 24
Peak memory	224000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047149943 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.1047149943
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.408442858
Short name	T558
Test name
Test status
Simulation time	2685490181 ps
CPU time	752.26 seconds
Started	Sep 11 09:06:00 AM UTC 24
Finished	Sep 11 09:18:40 AM UTC 24
Peak memory	384860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408442858 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.408442858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1694171837
Short name	T428
Test name
Test status
Simulation time	1179003673 ps
CPU time	66.53 seconds
Started	Sep 11 09:06:24 AM UTC 24
Finished	Sep 11 09:07:33 AM UTC 24
Peak memory	356460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694171837 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.1694171837
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2279687312
Short name	T464
Test name
Test status
Simulation time	11282229012 ps
CPU time	248.88 seconds
Started	Sep 11 09:06:32 AM UTC 24
Finished	Sep 11 09:10:44 AM UTC 24
Peak memory	214212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279687312 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc ess_b2b.2279687312
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3622802512
Short name	T424
Test name
Test status
Simulation time	73545582 ps
CPU time	1.04 seconds
Started	Sep 11 09:07:11 AM UTC 24
Finished	Sep 11 09:07:13 AM UTC 24
Peak memory	212408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622802512 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3622802512
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.817051212
Short name	T450
Test name
Test status
Simulation time	12030828970 ps
CPU time	156.81 seconds
Started	Sep 11 09:07:10 AM UTC 24
Finished	Sep 11 09:09:50 AM UTC 24
Peak memory	341888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817051212 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.817051212
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3194166956
Short name	T419
Test name
Test status
Simulation time	551013529 ps
CPU time	58.73 seconds
Started	Sep 11 09:05:59 AM UTC 24
Finished	Sep 11 09:06:59 AM UTC 24
Peak memory	352108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194166956 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3194166956
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3565309830
Short name	T744
Test name
Test status
Simulation time	102275209010 ps
CPU time	1828.87 seconds
Started	Sep 11 09:07:31 AM UTC 24
Finished	Sep 11 09:38:20 AM UTC 24
Peak memory	391256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356530983 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.3565309830
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4105893006
Short name	T451
Test name
Test status
Simulation time	4587391845 ps
CPU time	151.81 seconds
Started	Sep 11 09:07:25 AM UTC 24
Finished	Sep 11 09:09:59 AM UTC 24
Peak memory	315296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105893006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.4105893006
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1852526630
Short name	T466
Test name
Test status
Simulation time	11583504458 ps
CPU time	282.35 seconds
Started	Sep 11 09:06:09 AM UTC 24
Finished	Sep 11 09:10:56 AM UTC 24
Peak memory	213968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852526630 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.1852526630
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2962797433
Short name	T423
Test name
Test status
Simulation time	358210729 ps
CPU time	26.64 seconds
Started	Sep 11 09:06:42 AM UTC 24
Finished	Sep 11 09:07:10 AM UTC 24
Peak memory	296800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2962797433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t hroughput_w_partial_write.2962797433
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1508696366
Short name	T480
Test name
Test status
Simulation time	4070716947 ps
CPU time	246.96 seconds
Started	Sep 11 09:08:27 AM UTC 24
Finished	Sep 11 09:12:38 AM UTC 24
Peak memory	378984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508696366 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during _key_req.1508696366
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2887112932
Short name	T447
Test name
Test status
Simulation time	12310925 ps
CPU time	0.9 seconds
Started	Sep 11 09:09:32 AM UTC 24
Finished	Sep 11 09:09:34 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887112932 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2887112932
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2947473175
Short name	T437
Test name
Test status
Simulation time	810180430 ps
CPU time	34.71 seconds
Started	Sep 11 09:07:49 AM UTC 24
Finished	Sep 11 09:08:25 AM UTC 24
Peak memory	213912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947473175 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.2947473175
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.4146367183
Short name	T579
Test name
Test status
Simulation time	12644416607 ps
CPU time	763.46 seconds
Started	Sep 11 09:08:31 AM UTC 24
Finished	Sep 11 09:21:23 AM UTC 24
Peak memory	387260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146367183 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.4146367183
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3428294029
Short name	T440
Test name
Test status
Simulation time	985957338 ps
CPU time	12.28 seconds
Started	Sep 11 09:08:26 AM UTC 24
Finished	Sep 11 09:08:40 AM UTC 24
Peak memory	213868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428294029 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.3428294029
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2085776959
Short name	T444
Test name
Test status
Simulation time	123196724 ps
CPU time	56.46 seconds
Started	Sep 11 09:08:20 AM UTC 24
Finished	Sep 11 09:09:18 AM UTC 24
Peak memory	349988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 085776959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma x_throughput.2085776959
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4078048939
Short name	T445
Test name
Test status
Simulation time	346286007 ps
CPU time	7.43 seconds
Started	Sep 11 09:09:13 AM UTC 24
Finished	Sep 11 09:09:21 AM UTC 24
Peak memory	224024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078048939 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.4078048939
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.953757001
Short name	T443
Test name
Test status
Simulation time	2543769368 ps
CPU time	10.31 seconds
Started	Sep 11 09:09:01 AM UTC 24
Finished	Sep 11 09:09:12 AM UTC 24
Peak memory	224444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953757001 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.953757001
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1790391159
Short name	T665
Test name
Test status
Simulation time	20310765676 ps
CPU time	1282.76 seconds
Started	Sep 11 09:07:37 AM UTC 24
Finished	Sep 11 09:29:15 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790391159 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.1790391159
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3952553216
Short name	T435
Test name
Test status
Simulation time	151499581 ps
CPU time	9.83 seconds
Started	Sep 11 09:08:07 AM UTC 24
Finished	Sep 11 09:08:18 AM UTC 24
Peak memory	214080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952553216 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3952553216
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3418877581
Short name	T497
Test name
Test status
Simulation time	44406016394 ps
CPU time	369.45 seconds
Started	Sep 11 09:08:10 AM UTC 24
Finished	Sep 11 09:14:25 AM UTC 24
Peak memory	213856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418877581 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc ess_b2b.3418877581
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2266837687
Short name	T442
Test name
Test status
Simulation time	66745326 ps
CPU time	1.2 seconds
Started	Sep 11 09:08:57 AM UTC 24
Finished	Sep 11 09:09:00 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266837687 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2266837687
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.3109500455
Short name	T448
Test name
Test status
Simulation time	145872191 ps
CPU time	56.78 seconds
Started	Sep 11 09:08:40 AM UTC 24
Finished	Sep 11 09:09:39 AM UTC 24
Peak memory	296736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109500455 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3109500455
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2218731437
Short name	T434
Test name
Test status
Simulation time	1236297248 ps
CPU time	29.24 seconds
Started	Sep 11 09:07:37 AM UTC 24
Finished	Sep 11 09:08:08 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218731437 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2218731437
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.877844250
Short name	T790
Test name
Test status
Simulation time	8145688426 ps
CPU time	1950.21 seconds
Started	Sep 11 09:09:22 AM UTC 24
Finished	Sep 11 09:42:12 AM UTC 24
Peak memory	395180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877844250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.877844250
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3984058400
Short name	T38
Test name
Test status
Simulation time	7945314969 ps
CPU time	70.3 seconds
Started	Sep 11 09:09:19 AM UTC 24
Finished	Sep 11 09:10:31 AM UTC 24
Peak memory	226240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984058400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3984058400
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2471214568
Short name	T478
Test name
Test status
Simulation time	5424943674 ps
CPU time	267.99 seconds
Started	Sep 11 09:07:55 AM UTC 24
Finished	Sep 11 09:12:27 AM UTC 24
Peak memory	214184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471214568 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.2471214568
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3908076881
Short name	T452
Test name
Test status
Simulation time	294464695 ps
CPU time	98.29 seconds
Started	Sep 11 09:08:25 AM UTC 24
Finished	Sep 11 09:10:05 AM UTC 24
Peak memory	368408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3908076881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t hroughput_w_partial_write.3908076881
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3349048204
Short name	T502
Test name
Test status
Simulation time	2042501862 ps
CPU time	284.43 seconds
Started	Sep 11 09:10:19 AM UTC 24
Finished	Sep 11 09:15:08 AM UTC 24
Peak memory	382824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349048204 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during _key_req.3349048204
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2918449877
Short name	T465
Test name
Test status
Simulation time	57324953 ps
CPU time	0.9 seconds
Started	Sep 11 09:10:43 AM UTC 24
Finished	Sep 11 09:10:45 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918449877 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2918449877
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1464463530
Short name	T455
Test name
Test status
Simulation time	7122854787 ps
CPU time	33.77 seconds
Started	Sep 11 09:09:41 AM UTC 24
Finished	Sep 11 09:10:17 AM UTC 24
Peak memory	213980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464463530 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.1464463530
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.28735429
Short name	T632
Test name
Test status
Simulation time	2487441734 ps
CPU time	902.31 seconds
Started	Sep 11 09:10:22 AM UTC 24
Finished	Sep 11 09:25:34 AM UTC 24
Peak memory	384892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28735429 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.28735429
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3443538543
Short name	T457
Test name
Test status
Simulation time	382404246 ps
CPU time	2.37 seconds
Started	Sep 11 09:10:17 AM UTC 24
Finished	Sep 11 09:10:21 AM UTC 24
Peak memory	224132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443538543 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.3443538543
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3392014136
Short name	T461
Test name
Test status
Simulation time	297937764 ps
CPU time	25.03 seconds
Started	Sep 11 09:10:12 AM UTC 24
Finished	Sep 11 09:10:39 AM UTC 24
Peak memory	286572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 392014136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ma x_throughput.3392014136
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3315088894
Short name	T462
Test name
Test status
Simulation time	128555740 ps
CPU time	4.25 seconds
Started	Sep 11 09:10:35 AM UTC 24
Finished	Sep 11 09:10:40 AM UTC 24
Peak memory	224416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315088894 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.3315088894
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1541491656
Short name	T463
Test name
Test status
Simulation time	394853481 ps
CPU time	6.59 seconds
Started	Sep 11 09:10:35 AM UTC 24
Finished	Sep 11 09:10:43 AM UTC 24
Peak memory	222616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541491656 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.1541491656
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3379032112
Short name	T554
Test name
Test status
Simulation time	2000704969 ps
CPU time	511.99 seconds
Started	Sep 11 09:09:39 AM UTC 24
Finished	Sep 11 09:18:17 AM UTC 24
Peak memory	382828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379032112 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3379032112
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2206309965
Short name	T458
Test name
Test status
Simulation time	626093158 ps
CPU time	18.82 seconds
Started	Sep 11 09:10:00 AM UTC 24
Finished	Sep 11 09:10:22 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206309965 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.2206309965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1250368992
Short name	T505
Test name
Test status
Simulation time	16368612048 ps
CPU time	317.69 seconds
Started	Sep 11 09:10:06 AM UTC 24
Finished	Sep 11 09:15:28 AM UTC 24
Peak memory	214128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250368992 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc ess_b2b.1250368992
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1318667720
Short name	T460
Test name
Test status
Simulation time	44352456 ps
CPU time	1.19 seconds
Started	Sep 11 09:10:32 AM UTC 24
Finished	Sep 11 09:10:34 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318667720 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1318667720
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.794502990
Short name	T583
Test name
Test status
Simulation time	28506529436 ps
CPU time	666.97 seconds
Started	Sep 11 09:10:23 AM UTC 24
Finished	Sep 11 09:21:37 AM UTC 24
Peak memory	384876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794502990 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.794502990
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.1099727537
Short name	T449
Test name
Test status
Simulation time	164802640 ps
CPU time	4.68 seconds
Started	Sep 11 09:09:35 AM UTC 24
Finished	Sep 11 09:09:41 AM UTC 24
Peak memory	227172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099727537 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1099727537
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3208358301
Short name	T835
Test name
Test status
Simulation time	7609545911 ps
CPU time	2150.37 seconds
Started	Sep 11 09:10:41 AM UTC 24
Finished	Sep 11 09:46:52 AM UTC 24
Peak memory	385168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320835830 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.3208358301
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3354781285
Short name	T490
Test name
Test status
Simulation time	2243824259 ps
CPU time	200.44 seconds
Started	Sep 11 09:10:40 AM UTC 24
Finished	Sep 11 09:14:03 AM UTC 24
Peak memory	339948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354781285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3354781285
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1400272835
Short name	T500
Test name
Test status
Simulation time	38489972269 ps
CPU time	278.1 seconds
Started	Sep 11 09:09:51 AM UTC 24
Finished	Sep 11 09:14:33 AM UTC 24
Peak memory	214200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400272835 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.1400272835
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1033184216
Short name	T467
Test name
Test status
Simulation time	560378969 ps
CPU time	49.92 seconds
Started	Sep 11 09:10:16 AM UTC 24
Finished	Sep 11 09:11:08 AM UTC 24
Peak memory	319332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1033184216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t hroughput_w_partial_write.1033184216
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3264908370
Short name	T590
Test name
Test status
Simulation time	30914940840 ps
CPU time	593.4 seconds
Started	Sep 11 09:11:57 AM UTC 24
Finished	Sep 11 09:21:58 AM UTC 24
Peak memory	380832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264908370 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during _key_req.3264908370
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3956869238
Short name	T482
Test name
Test status
Simulation time	24130611 ps
CPU time	0.86 seconds
Started	Sep 11 09:12:39 AM UTC 24
Finished	Sep 11 09:12:41 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956869238 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3956869238
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.1292485252
Short name	T472
Test name
Test status
Simulation time	2081944903 ps
CPU time	48.38 seconds
Started	Sep 11 09:10:56 AM UTC 24
Finished	Sep 11 09:11:47 AM UTC 24
Peak memory	214064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292485252 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.1292485252
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3961916502
Short name	T591
Test name
Test status
Simulation time	9947297167 ps
CPU time	593.04 seconds
Started	Sep 11 09:12:02 AM UTC 24
Finished	Sep 11 09:22:01 AM UTC 24
Peak memory	382892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961916502 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.3961916502
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1758239388
Short name	T474
Test name
Test status
Simulation time	1277173787 ps
CPU time	12.54 seconds
Started	Sep 11 09:11:47 AM UTC 24
Finished	Sep 11 09:12:01 AM UTC 24
Peak memory	214076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758239388 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.1758239388
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2688475576
Short name	T485
Test name
Test status
Simulation time	194360144 ps
CPU time	112.46 seconds
Started	Sep 11 09:11:21 AM UTC 24
Finished	Sep 11 09:13:16 AM UTC 24
Peak memory	382752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 688475576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ma x_throughput.2688475576
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.575553041
Short name	T479
Test name
Test status
Simulation time	167331291 ps
CPU time	3.27 seconds
Started	Sep 11 09:12:28 AM UTC 24
Finished	Sep 11 09:12:32 AM UTC 24
Peak memory	224008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575553041 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.575553041
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3574025344
Short name	T481
Test name
Test status
Simulation time	138174740 ps
CPU time	10.41 seconds
Started	Sep 11 09:12:26 AM UTC 24
Finished	Sep 11 09:12:38 AM UTC 24
Peak memory	224156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574025344 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.3574025344
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2644011542
Short name	T772
Test name
Test status
Simulation time	36626418325 ps
CPU time	1805.08 seconds
Started	Sep 11 09:10:46 AM UTC 24
Finished	Sep 11 09:41:11 AM UTC 24
Peak memory	377000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644011542 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2644011542
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2183239895
Short name	T470
Test name
Test status
Simulation time	367199399 ps
CPU time	10.54 seconds
Started	Sep 11 09:11:09 AM UTC 24
Finished	Sep 11 09:11:21 AM UTC 24
Peak memory	214136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183239895 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.2183239895
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1940121697
Short name	T536
Test name
Test status
Simulation time	37054744238 ps
CPU time	368.86 seconds
Started	Sep 11 09:11:15 AM UTC 24
Finished	Sep 11 09:17:29 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940121697 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acc ess_b2b.1940121697
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3945774750
Short name	T477
Test name
Test status
Simulation time	31140904 ps
CPU time	1.1 seconds
Started	Sep 11 09:12:23 AM UTC 24
Finished	Sep 11 09:12:25 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945774750 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3945774750
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.2099941516
Short name	T476
Test name
Test status
Simulation time	55894852 ps
CPU time	6.91 seconds
Started	Sep 11 09:12:14 AM UTC 24
Finished	Sep 11 09:12:22 AM UTC 24
Peak memory	239416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099941516 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2099941516
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.920114550
Short name	T469
Test name
Test status
Simulation time	568015994 ps
CPU time	26.79 seconds
Started	Sep 11 09:10:45 AM UTC 24
Finished	Sep 11 09:11:13 AM UTC 24
Peak memory	288948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920114550 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.920114550
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1426820815
Short name	T710
Test name
Test status
Simulation time	27558949151 ps
CPU time	1321.52 seconds
Started	Sep 11 09:12:38 AM UTC 24
Finished	Sep 11 09:34:53 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142682081 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.1426820815
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2217512668
Short name	T519
Test name
Test status
Simulation time	9657675766 ps
CPU time	319.98 seconds
Started	Sep 11 09:11:09 AM UTC 24
Finished	Sep 11 09:16:33 AM UTC 24
Peak memory	213872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217512668 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2217512668
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1437388691
Short name	T475
Test name
Test status
Simulation time	201776170 ps
CPU time	31.95 seconds
Started	Sep 11 09:11:39 AM UTC 24
Finished	Sep 11 09:12:13 AM UTC 24
Peak memory	301152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1437388691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t hroughput_w_partial_write.1437388691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1198427557
Short name	T643
Test name
Test status
Simulation time	6537840467 ps
CPU time	756.67 seconds
Started	Sep 11 09:13:52 AM UTC 24
Finished	Sep 11 09:26:37 AM UTC 24
Peak memory	384928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198427557 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during _key_req.1198427557
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.2622611720
Short name	T498
Test name
Test status
Simulation time	75331404 ps
CPU time	0.8 seconds
Started	Sep 11 09:14:26 AM UTC 24
Finished	Sep 11 09:14:28 AM UTC 24
Peak memory	212808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622611720 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2622611720
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1807456113
Short name	T499
Test name
Test status
Simulation time	5431027276 ps
CPU time	98.17 seconds
Started	Sep 11 09:12:50 AM UTC 24
Finished	Sep 11 09:14:30 AM UTC 24
Peak memory	213800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807456113 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.1807456113
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.4179303000
Short name	T662
Test name
Test status
Simulation time	11466755362 ps
CPU time	894.91 seconds
Started	Sep 11 09:14:04 AM UTC 24
Finished	Sep 11 09:29:09 AM UTC 24
Peak memory	386924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179303000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.4179303000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.920522578
Short name	T492
Test name
Test status
Simulation time	2595855918 ps
CPU time	16.47 seconds
Started	Sep 11 09:13:51 AM UTC 24
Finished	Sep 11 09:14:09 AM UTC 24
Peak memory	213920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920522578 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.920522578
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.395537133
Short name	T504
Test name
Test status
Simulation time	690610558 ps
CPU time	99 seconds
Started	Sep 11 09:13:29 AM UTC 24
Finished	Sep 11 09:15:10 AM UTC 24
Peak memory	376596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 95537133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max _throughput.395537133
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2956167725
Short name	T496
Test name
Test status
Simulation time	91270026 ps
CPU time	6.38 seconds
Started	Sep 11 09:14:15 AM UTC 24
Finished	Sep 11 09:14:22 AM UTC 24
Peak memory	224160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956167725 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.2956167725
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2794099901
Short name	T495
Test name
Test status
Simulation time	284652036 ps
CPU time	6.43 seconds
Started	Sep 11 09:14:12 AM UTC 24
Finished	Sep 11 09:14:20 AM UTC 24
Peak memory	224000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794099901 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.2794099901
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2269083930
Short name	T630
Test name
Test status
Simulation time	65678459838 ps
CPU time	755.72 seconds
Started	Sep 11 09:12:48 AM UTC 24
Finished	Sep 11 09:25:32 AM UTC 24
Peak memory	374564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269083930 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.2269083930
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1513014400
Short name	T488
Test name
Test status
Simulation time	6118246741 ps
CPU time	24.41 seconds
Started	Sep 11 09:13:24 AM UTC 24
Finished	Sep 11 09:13:50 AM UTC 24
Peak memory	213912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513014400 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.1513014400
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2868442078
Short name	T545
Test name
Test status
Simulation time	3502898693 ps
CPU time	268.61 seconds
Started	Sep 11 09:13:25 AM UTC 24
Finished	Sep 11 09:17:58 AM UTC 24
Peak memory	213920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868442078 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acc ess_b2b.2868442078
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3761684880
Short name	T493
Test name
Test status
Simulation time	30307710 ps
CPU time	1.13 seconds
Started	Sep 11 09:14:09 AM UTC 24
Finished	Sep 11 09:14:12 AM UTC 24
Peak memory	212528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761684880 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3761684880
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.3358612899
Short name	T661
Test name
Test status
Simulation time	7716065729 ps
CPU time	866.02 seconds
Started	Sep 11 09:14:09 AM UTC 24
Finished	Sep 11 09:28:45 AM UTC 24
Peak memory	381100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358612899 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3358612899
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.323126132
Short name	T484
Test name
Test status
Simulation time	278832294 ps
CPU time	5.64 seconds
Started	Sep 11 09:12:42 AM UTC 24
Finished	Sep 11 09:12:49 AM UTC 24
Peak memory	233324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323126132 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.323126132
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2698183498
Short name	T913
Test name
Test status
Simulation time	64148834252 ps
CPU time	2890.87 seconds
Started	Sep 11 09:14:23 AM UTC 24
Finished	Sep 11 10:03:03 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269818349 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.2698183498
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.60400312
Short name	T103
Test name
Test status
Simulation time	2759241442 ps
CPU time	42.43 seconds
Started	Sep 11 09:14:21 AM UTC 24
Finished	Sep 11 09:15:05 AM UTC 24
Peak memory	319468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60400312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.60400312
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.432721816
Short name	T518
Test name
Test status
Simulation time	2147504792 ps
CPU time	181.13 seconds
Started	Sep 11 09:13:17 AM UTC 24
Finished	Sep 11 09:16:21 AM UTC 24
Peak memory	213844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432721816 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.432721816
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.239105615
Short name	T489
Test name
Test status
Simulation time	38482265 ps
CPU time	1.25 seconds
Started	Sep 11 09:13:49 AM UTC 24
Finished	Sep 11 09:13:51 AM UTC 24
Peak memory	212516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 239105615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_th roughput_w_partial_write.239105615
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4188627264
Short name	T539
Test name
Test status
Simulation time	1226733341 ps
CPU time	122.27 seconds
Started	Sep 11 09:15:36 AM UTC 24
Finished	Sep 11 09:17:41 AM UTC 24
Peak memory	331616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188627264 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.4188627264
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.4253723012
Short name	T515
Test name
Test status
Simulation time	15395169 ps
CPU time	0.97 seconds
Started	Sep 11 09:16:05 AM UTC 24
Finished	Sep 11 09:16:07 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253723012 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.4253723012
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.4284030128
Short name	T509
Test name
Test status
Simulation time	3556804236 ps
CPU time	72.38 seconds
Started	Sep 11 09:14:33 AM UTC 24
Finished	Sep 11 09:15:47 AM UTC 24
Peak memory	213776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284030128 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.4284030128
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3869953865
Short name	T615
Test name
Test status
Simulation time	1915934680 ps
CPU time	480.73 seconds
Started	Sep 11 09:15:46 AM UTC 24
Finished	Sep 11 09:23:53 AM UTC 24
Peak memory	378656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869953865 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3869953865
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1393374698
Short name	T506
Test name
Test status
Simulation time	301296110 ps
CPU time	4.79 seconds
Started	Sep 11 09:15:29 AM UTC 24
Finished	Sep 11 09:15:35 AM UTC 24
Peak memory	213784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393374698 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.1393374698
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3429807450
Short name	T508
Test name
Test status
Simulation time	96261607 ps
CPU time	34.83 seconds
Started	Sep 11 09:15:11 AM UTC 24
Finished	Sep 11 09:15:47 AM UTC 24
Peak memory	313120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 429807450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma x_throughput.3429807450
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2531221016
Short name	T516
Test name
Test status
Simulation time	224719719 ps
CPU time	4.58 seconds
Started	Sep 11 09:16:02 AM UTC 24
Finished	Sep 11 09:16:08 AM UTC 24
Peak memory	224080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531221016 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.2531221016
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.750931157
Short name	T511
Test name
Test status
Simulation time	192169266 ps
CPU time	7.4 seconds
Started	Sep 11 09:15:52 AM UTC 24
Finished	Sep 11 09:16:00 AM UTC 24
Peak memory	224320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750931157 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.750931157
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1008373143
Short name	T602
Test name
Test status
Simulation time	9211114223 ps
CPU time	496.28 seconds
Started	Sep 11 09:14:31 AM UTC 24
Finished	Sep 11 09:22:54 AM UTC 24
Peak memory	352048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008373143 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.1008373143
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3977004000
Short name	T503
Test name
Test status
Simulation time	210953484 ps
CPU time	3.61 seconds
Started	Sep 11 09:15:06 AM UTC 24
Finished	Sep 11 09:15:10 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977004000 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.3977004000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.464947609
Short name	T565
Test name
Test status
Simulation time	8676149553 ps
CPU time	230.29 seconds
Started	Sep 11 09:15:09 AM UTC 24
Finished	Sep 11 09:19:02 AM UTC 24
Peak memory	213992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464947609 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acce ss_b2b.464947609
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.2954381145
Short name	T510
Test name
Test status
Simulation time	54045279 ps
CPU time	1.18 seconds
Started	Sep 11 09:15:49 AM UTC 24
Finished	Sep 11 09:15:51 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954381145 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2954381145
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.800577783
Short name	T711
Test name
Test status
Simulation time	50510837273 ps
CPU time	1153.41 seconds
Started	Sep 11 09:15:47 AM UTC 24
Finished	Sep 11 09:35:14 AM UTC 24
Peak memory	384872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800577783 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.800577783
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.837428687
Short name	T501
Test name
Test status
Simulation time	121101495 ps
CPU time	5.97 seconds
Started	Sep 11 09:14:29 AM UTC 24
Finished	Sep 11 09:14:36 AM UTC 24
Peak memory	214188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837428687 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.837428687
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3044471514
Short name	T884
Test name
Test status
Simulation time	57737057011 ps
CPU time	2220.95 seconds
Started	Sep 11 09:16:04 AM UTC 24
Finished	Sep 11 09:53:27 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304447151 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.3044471514
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.245362356
Short name	T39
Test name
Test status
Simulation time	1833239030 ps
CPU time	101.41 seconds
Started	Sep 11 09:16:02 AM UTC 24
Finished	Sep 11 09:17:46 AM UTC 24
Peak memory	329644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245362356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.245362356
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2882956546
Short name	T557
Test name
Test status
Simulation time	9455387804 ps
CPU time	236.68 seconds
Started	Sep 11 09:14:37 AM UTC 24
Finished	Sep 11 09:18:38 AM UTC 24
Peak memory	213840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882956546 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.2882956546
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2501229251
Short name	T512
Test name
Test status
Simulation time	878848371 ps
CPU time	47.37 seconds
Started	Sep 11 09:15:12 AM UTC 24
Finished	Sep 11 09:16:01 AM UTC 24
Peak memory	319268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2501229251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t hroughput_w_partial_write.2501229251
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2197826404
Short name	T276
Test name
Test status
Simulation time	10377900625 ps
CPU time	758.86 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:53:33 AM UTC 24
Peak memory	372628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197826404 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_ key_req.2197826404
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2031983573
Short name	T15
Test name
Test status
Simulation time	141006191 ps
CPU time	0.97 seconds
Started	Sep 11 08:40:47 AM UTC 24
Finished	Sep 11 08:40:49 AM UTC 24
Peak memory	212628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031983573 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2031983573
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3459723818
Short name	T172
Test name
Test status
Simulation time	6275816417 ps
CPU time	59.23 seconds
Started	Sep 11 08:40:38 AM UTC 24
Finished	Sep 11 08:41:46 AM UTC 24
Peak memory	213984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459723818 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3459723818
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1518695610
Short name	T26
Test name
Test status
Simulation time	28238229344 ps
CPU time	40.65 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:41:27 AM UTC 24
Peak memory	213840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518695610 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.1518695610
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3059426290
Short name	T10
Test name
Test status
Simulation time	7940410094 ps
CPU time	9.51 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:40:56 AM UTC 24
Peak memory	213920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059426290 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.3059426290
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.136240360
Short name	T28
Test name
Test status
Simulation time	56832071 ps
CPU time	4.94 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:40:51 AM UTC 24
Peak memory	247980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 36240360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_ throughput.136240360
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.690312191
Short name	T40
Test name
Test status
Simulation time	873966876 ps
CPU time	4.33 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:40:54 AM UTC 24
Peak memory	224024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690312191 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.690312191
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3630943165
Short name	T37
Test name
Test status
Simulation time	645794329 ps
CPU time	5.91 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:40:55 AM UTC 24
Peak memory	224112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630943165 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.3630943165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.956320700
Short name	T233
Test name
Test status
Simulation time	12669941890 ps
CPU time	554.52 seconds
Started	Sep 11 08:40:36 AM UTC 24
Finished	Sep 11 08:50:04 AM UTC 24
Peak memory	378792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956320700 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.956320700
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.8802026
Short name	T145
Test name
Test status
Simulation time	975419892 ps
CPU time	18.5 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:41:05 AM UTC 24
Peak memory	263896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8802026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.8802026
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.808423462
Short name	T209
Test name
Test status
Simulation time	4571767699 ps
CPU time	370.69 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:47:01 AM UTC 24
Peak memory	213984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808423462 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acces s_b2b.808423462
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3816757256
Short name	T14
Test name
Test status
Simulation time	27810879 ps
CPU time	1.07 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:40:47 AM UTC 24
Peak memory	212396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816757256 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3816757256
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2672135320
Short name	T29
Test name
Test status
Simulation time	407569513 ps
CPU time	2.21 seconds
Started	Sep 11 08:40:46 AM UTC 24
Finished	Sep 11 08:40:51 AM UTC 24
Peak memory	250064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672135320 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.2672135320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2785118671
Short name	T540
Test name
Test status
Simulation time	19706182153 ps
CPU time	2191.77 seconds
Started	Sep 11 08:40:46 AM UTC 24
Finished	Sep 11 09:17:43 AM UTC 24
Peak memory	386908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278511867 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.2785118671
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.844010772
Short name	T97
Test name
Test status
Simulation time	7117996623 ps
CPU time	173.89 seconds
Started	Sep 11 08:40:40 AM UTC 24
Finished	Sep 11 08:43:40 AM UTC 24
Peak memory	213912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844010772 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.844010772
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1492350375
Short name	T7
Test name
Test status
Simulation time	271880634 ps
CPU time	1.29 seconds
Started	Sep 11 08:40:45 AM UTC 24
Finished	Sep 11 08:40:47 AM UTC 24
Peak memory	222756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1492350375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th roughput_w_partial_write.1492350375
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.980206398
Short name	T622
Test name
Test status
Simulation time	25385451798 ps
CPU time	448.16 seconds
Started	Sep 11 09:16:59 AM UTC 24
Finished	Sep 11 09:24:33 AM UTC 24
Peak memory	383140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980206398 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_ key_req.980206398
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3695730142
Short name	T533
Test name
Test status
Simulation time	13859648 ps
CPU time	0.91 seconds
Started	Sep 11 09:17:24 AM UTC 24
Finished	Sep 11 09:17:26 AM UTC 24
Peak memory	212808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695730142 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3695730142
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2000096156
Short name	T524
Test name
Test status
Simulation time	9067501990 ps
CPU time	37.72 seconds
Started	Sep 11 09:16:19 AM UTC 24
Finished	Sep 11 09:16:59 AM UTC 24
Peak memory	214224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000096156 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2000096156
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.1052529165
Short name	T631
Test name
Test status
Simulation time	1821142582 ps
CPU time	506.17 seconds
Started	Sep 11 09:17:00 AM UTC 24
Finished	Sep 11 09:25:33 AM UTC 24
Peak memory	378728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052529165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.1052529165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1064509036
Short name	T528
Test name
Test status
Simulation time	1967919142 ps
CPU time	10.74 seconds
Started	Sep 11 09:16:58 AM UTC 24
Finished	Sep 11 09:17:10 AM UTC 24
Peak memory	213840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064509036 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.1064509036
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.507160416
Short name	T532
Test name
Test status
Simulation time	362526204 ps
CPU time	36.93 seconds
Started	Sep 11 09:16:45 AM UTC 24
Finished	Sep 11 09:17:23 AM UTC 24
Peak memory	317280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 07160416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_max _throughput.507160416
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3547707778
Short name	T531
Test name
Test status
Simulation time	175589307 ps
CPU time	7.85 seconds
Started	Sep 11 09:17:13 AM UTC 24
Finished	Sep 11 09:17:22 AM UTC 24
Peak memory	224152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547707778 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.3547707778
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.785459106
Short name	T537
Test name
Test status
Simulation time	5939893735 ps
CPU time	21.76 seconds
Started	Sep 11 09:17:11 AM UTC 24
Finished	Sep 11 09:17:34 AM UTC 24
Peak memory	224384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785459106 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.785459106
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.685568768
Short name	T525
Test name
Test status
Simulation time	492722913 ps
CPU time	49.23 seconds
Started	Sep 11 09:16:08 AM UTC 24
Finished	Sep 11 09:16:59 AM UTC 24
Peak memory	280612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685568768 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.685568768
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1356115195
Short name	T529
Test name
Test status
Simulation time	453054673 ps
CPU time	35.42 seconds
Started	Sep 11 09:16:35 AM UTC 24
Finished	Sep 11 09:17:11 AM UTC 24
Peak memory	301164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356115195 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.1356115195
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1947300254
Short name	T613
Test name
Test status
Simulation time	5887026581 ps
CPU time	422.33 seconds
Started	Sep 11 09:16:36 AM UTC 24
Finished	Sep 11 09:23:43 AM UTC 24
Peak memory	213912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947300254 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acc ess_b2b.1947300254
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.900532559
Short name	T530
Test name
Test status
Simulation time	56023536 ps
CPU time	1.15 seconds
Started	Sep 11 09:17:11 AM UTC 24
Finished	Sep 11 09:17:13 AM UTC 24
Peak memory	212624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900532559 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.900532559
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.668273841
Short name	T563
Test name
Test status
Simulation time	2984157551 ps
CPU time	107.01 seconds
Started	Sep 11 09:17:07 AM UTC 24
Finished	Sep 11 09:18:57 AM UTC 24
Peak memory	341856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668273841 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.668273841
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.4222306891
Short name	T553
Test name
Test status
Simulation time	1332437224 ps
CPU time	120.17 seconds
Started	Sep 11 09:16:08 AM UTC 24
Finished	Sep 11 09:18:11 AM UTC 24
Peak memory	380736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222306891 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.4222306891
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2605800240
Short name	T832
Test name
Test status
Simulation time	67939518376 ps
CPU time	1735.56 seconds
Started	Sep 11 09:17:23 AM UTC 24
Finished	Sep 11 09:46:37 AM UTC 24
Peak memory	395100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260580024 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.2605800240
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3103658727
Short name	T592
Test name
Test status
Simulation time	1711524299 ps
CPU time	286.6 seconds
Started	Sep 11 09:17:14 AM UTC 24
Finished	Sep 11 09:22:04 AM UTC 24
Peak memory	388980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103658727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3103658727
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2899483090
Short name	T604
Test name
Test status
Simulation time	3391543031 ps
CPU time	394.75 seconds
Started	Sep 11 09:16:21 AM UTC 24
Finished	Sep 11 09:23:02 AM UTC 24
Peak memory	214264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899483090 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.2899483090
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.921973877
Short name	T523
Test name
Test status
Simulation time	421855246 ps
CPU time	2.96 seconds
Started	Sep 11 09:16:53 AM UTC 24
Finished	Sep 11 09:16:57 AM UTC 24
Peak memory	230428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 921973877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_th roughput_w_partial_write.921973877
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3076622024
Short name	T649
Test name
Test status
Simulation time	30141693723 ps
CPU time	541.39 seconds
Started	Sep 11 09:17:47 AM UTC 24
Finished	Sep 11 09:26:55 AM UTC 24
Peak memory	384928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076622024 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during _key_req.3076622024
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2641931024
Short name	T550
Test name
Test status
Simulation time	14526175 ps
CPU time	0.82 seconds
Started	Sep 11 09:18:04 AM UTC 24
Finished	Sep 11 09:18:06 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641931024 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2641931024
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1442930548
Short name	T552
Test name
Test status
Simulation time	8772641402 ps
CPU time	40.12 seconds
Started	Sep 11 09:17:28 AM UTC 24
Finished	Sep 11 09:18:10 AM UTC 24
Peak memory	213856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442930548 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.1442930548
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.4172408118
Short name	T728
Test name
Test status
Simulation time	36659962904 ps
CPU time	1123.06 seconds
Started	Sep 11 09:17:53 AM UTC 24
Finished	Sep 11 09:36:48 AM UTC 24
Peak memory	384952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172408118 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.4172408118
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2632405437
Short name	T547
Test name
Test status
Simulation time	2742949398 ps
CPU time	12.91 seconds
Started	Sep 11 09:17:46 AM UTC 24
Finished	Sep 11 09:18:00 AM UTC 24
Peak memory	214240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632405437 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.2632405437
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2836639849
Short name	T559
Test name
Test status
Simulation time	249817648 ps
CPU time	62.79 seconds
Started	Sep 11 09:17:42 AM UTC 24
Finished	Sep 11 09:18:46 AM UTC 24
Peak memory	368488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 836639849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma x_throughput.2836639849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.2442433500
Short name	T549
Test name
Test status
Simulation time	186137260 ps
CPU time	3.25 seconds
Started	Sep 11 09:17:59 AM UTC 24
Finished	Sep 11 09:18:03 AM UTC 24
Peak memory	224088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442433500 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.2442433500
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1932207757
Short name	T551
Test name
Test status
Simulation time	237091249 ps
CPU time	7.99 seconds
Started	Sep 11 09:17:59 AM UTC 24
Finished	Sep 11 09:18:08 AM UTC 24
Peak memory	224344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932207757 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.1932207757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.335829449
Short name	T645
Test name
Test status
Simulation time	2632042182 ps
CPU time	549.49 seconds
Started	Sep 11 09:17:28 AM UTC 24
Finished	Sep 11 09:26:45 AM UTC 24
Peak memory	381092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335829449 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.335829449
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1676208293
Short name	T548
Test name
Test status
Simulation time	6642218103 ps
CPU time	26.16 seconds
Started	Sep 11 09:17:35 AM UTC 24
Finished	Sep 11 09:18:02 AM UTC 24
Peak memory	213968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676208293 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1676208293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3163387797
Short name	T576
Test name
Test status
Simulation time	2066043661 ps
CPU time	193.23 seconds
Started	Sep 11 09:17:39 AM UTC 24
Finished	Sep 11 09:20:55 AM UTC 24
Peak memory	213896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163387797 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc ess_b2b.3163387797
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1861704938
Short name	T546
Test name
Test status
Simulation time	50083636 ps
CPU time	1.17 seconds
Started	Sep 11 09:17:56 AM UTC 24
Finished	Sep 11 09:17:58 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861704938 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1861704938
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3811697722
Short name	T681
Test name
Test status
Simulation time	3833075292 ps
CPU time	745.15 seconds
Started	Sep 11 09:17:55 AM UTC 24
Finished	Sep 11 09:30:28 AM UTC 24
Peak memory	387244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811697722 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3811697722
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2709050981
Short name	T538
Test name
Test status
Simulation time	324245867 ps
CPU time	9.86 seconds
Started	Sep 11 09:17:27 AM UTC 24
Finished	Sep 11 09:17:38 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709050981 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2709050981
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1929900318
Short name	T658
Test name
Test status
Simulation time	21358556232 ps
CPU time	606.25 seconds
Started	Sep 11 09:18:03 AM UTC 24
Finished	Sep 11 09:28:17 AM UTC 24
Peak memory	381096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192990031 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.1929900318
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4224346115
Short name	T593
Test name
Test status
Simulation time	559355196 ps
CPU time	239.78 seconds
Started	Sep 11 09:18:01 AM UTC 24
Finished	Sep 11 09:22:05 AM UTC 24
Peak memory	397160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224346115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.4224346115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3359517970
Short name	T575
Test name
Test status
Simulation time	10168675650 ps
CPU time	192.86 seconds
Started	Sep 11 09:17:30 AM UTC 24
Finished	Sep 11 09:20:45 AM UTC 24
Peak memory	213952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359517970 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.3359517970
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2003130663
Short name	T544
Test name
Test status
Simulation time	252260094 ps
CPU time	10.79 seconds
Started	Sep 11 09:17:43 AM UTC 24
Finished	Sep 11 09:17:55 AM UTC 24
Peak memory	264096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2003130663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t hroughput_w_partial_write.2003130663
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2129661256
Short name	T628
Test name
Test status
Simulation time	2016435613 ps
CPU time	382.87 seconds
Started	Sep 11 09:18:48 AM UTC 24
Finished	Sep 11 09:25:15 AM UTC 24
Peak memory	380672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129661256 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.2129661256
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1395407635
Short name	T568
Test name
Test status
Simulation time	17213465 ps
CPU time	0.93 seconds
Started	Sep 11 09:19:07 AM UTC 24
Finished	Sep 11 09:19:09 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395407635 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1395407635
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.2894334464
Short name	T562
Test name
Test status
Simulation time	9078698608 ps
CPU time	43.01 seconds
Started	Sep 11 09:18:11 AM UTC 24
Finished	Sep 11 09:18:55 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894334464 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.2894334464
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.222847742
Short name	T674
Test name
Test status
Simulation time	16007162137 ps
CPU time	661.17 seconds
Started	Sep 11 09:18:48 AM UTC 24
Finished	Sep 11 09:29:56 AM UTC 24
Peak memory	384868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222847742 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.222847742
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.842880345
Short name	T561
Test name
Test status
Simulation time	3244682870 ps
CPU time	11.9 seconds
Started	Sep 11 09:18:42 AM UTC 24
Finished	Sep 11 09:18:55 AM UTC 24
Peak memory	213876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842880345 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.842880345
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2373338570
Short name	T571
Test name
Test status
Simulation time	516193625 ps
CPU time	97.91 seconds
Started	Sep 11 09:18:25 AM UTC 24
Finished	Sep 11 09:20:05 AM UTC 24
Peak memory	381096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 373338570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma x_throughput.2373338570
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2301616331
Short name	T567
Test name
Test status
Simulation time	80784517 ps
CPU time	6.33 seconds
Started	Sep 11 09:18:59 AM UTC 24
Finished	Sep 11 09:19:07 AM UTC 24
Peak memory	223976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301616331 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2301616331
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3417069983
Short name	T569
Test name
Test status
Simulation time	1698660892 ps
CPU time	13.01 seconds
Started	Sep 11 09:18:58 AM UTC 24
Finished	Sep 11 09:19:12 AM UTC 24
Peak memory	224072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417069983 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.3417069983
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3009844057
Short name	T685
Test name
Test status
Simulation time	2117130021 ps
CPU time	747.82 seconds
Started	Sep 11 09:18:09 AM UTC 24
Finished	Sep 11 09:30:45 AM UTC 24
Peak memory	384800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009844057 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.3009844057
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1298219826
Short name	T560
Test name
Test status
Simulation time	3714810958 ps
CPU time	27.09 seconds
Started	Sep 11 09:18:18 AM UTC 24
Finished	Sep 11 09:18:46 AM UTC 24
Peak memory	282480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298219826 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1298219826
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.115211921
Short name	T623
Test name
Test status
Simulation time	154096074246 ps
CPU time	376.88 seconds
Started	Sep 11 09:18:20 AM UTC 24
Finished	Sep 11 09:24:42 AM UTC 24
Peak memory	213864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115211921 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acce ss_b2b.115211921
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2749943805
Short name	T564
Test name
Test status
Simulation time	86595134 ps
CPU time	1.15 seconds
Started	Sep 11 09:18:56 AM UTC 24
Finished	Sep 11 09:18:58 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749943805 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2749943805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.1924150486
Short name	T695
Test name
Test status
Simulation time	5294017021 ps
CPU time	791.52 seconds
Started	Sep 11 09:18:56 AM UTC 24
Finished	Sep 11 09:32:16 AM UTC 24
Peak memory	386920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924150486 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1924150486
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.413488945
Short name	T555
Test name
Test status
Simulation time	367588214 ps
CPU time	10.6 seconds
Started	Sep 11 09:18:08 AM UTC 24
Finished	Sep 11 09:18:19 AM UTC 24
Peak memory	213780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413488945 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.413488945
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.239091354
Short name	T916
Test name
Test status
Simulation time	134885954893 ps
CPU time	2984.14 seconds
Started	Sep 11 09:19:06 AM UTC 24
Finished	Sep 11 10:09:24 AM UTC 24
Peak memory	389288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239091354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.239091354
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3939538753
Short name	T582
Test name
Test status
Simulation time	3859084919 ps
CPU time	200.82 seconds
Started	Sep 11 09:18:12 AM UTC 24
Finished	Sep 11 09:21:36 AM UTC 24
Peak memory	213792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939538753 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.3939538753
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3741154255
Short name	T566
Test name
Test status
Simulation time	166493327 ps
CPU time	25.19 seconds
Started	Sep 11 09:18:38 AM UTC 24
Finished	Sep 11 09:19:05 AM UTC 24
Peak memory	286816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3741154255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t hroughput_w_partial_write.3741154255
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1348020991
Short name	T730
Test name
Test status
Simulation time	18221004047 ps
CPU time	953.04 seconds
Started	Sep 11 09:21:04 AM UTC 24
Finished	Sep 11 09:37:07 AM UTC 24
Peak memory	372636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348020991 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during _key_req.1348020991
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.568746729
Short name	T586
Test name
Test status
Simulation time	41713919 ps
CPU time	1.02 seconds
Started	Sep 11 09:21:41 AM UTC 24
Finished	Sep 11 09:21:43 AM UTC 24
Peak memory	212632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568746729 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.568746729
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.477182068
Short name	T572
Test name
Test status
Simulation time	9184575742 ps
CPU time	49.59 seconds
Started	Sep 11 09:19:26 AM UTC 24
Finished	Sep 11 09:20:17 AM UTC 24
Peak memory	213984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477182068 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.477182068
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.952708905
Short name	T585
Test name
Test status
Simulation time	321500763 ps
CPU time	20.83 seconds
Started	Sep 11 09:21:19 AM UTC 24
Finished	Sep 11 09:21:41 AM UTC 24
Peak memory	213992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952708905 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.952708905
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1888923592
Short name	T577
Test name
Test status
Simulation time	566317895 ps
CPU time	5.86 seconds
Started	Sep 11 09:20:56 AM UTC 24
Finished	Sep 11 09:21:03 AM UTC 24
Peak memory	228260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888923592 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.1888923592
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1589344305
Short name	T580
Test name
Test status
Simulation time	110134981 ps
CPU time	52.78 seconds
Started	Sep 11 09:20:33 AM UTC 24
Finished	Sep 11 09:21:27 AM UTC 24
Peak memory	337964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 589344305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma x_throughput.1589344305
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.4143625706
Short name	T584
Test name
Test status
Simulation time	197228572 ps
CPU time	3.49 seconds
Started	Sep 11 09:21:35 AM UTC 24
Finished	Sep 11 09:21:40 AM UTC 24
Peak memory	224008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143625706 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.4143625706
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1658725586
Short name	T587
Test name
Test status
Simulation time	3594279406 ps
CPU time	14.99 seconds
Started	Sep 11 09:21:31 AM UTC 24
Finished	Sep 11 09:21:47 AM UTC 24
Peak memory	213924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658725586 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.1658725586
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1063063802
Short name	T713
Test name
Test status
Simulation time	16475421239 ps
CPU time	976.93 seconds
Started	Sep 11 09:19:13 AM UTC 24
Finished	Sep 11 09:35:40 AM UTC 24
Peak memory	386888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063063802 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.1063063802
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2877733868
Short name	T574
Test name
Test status
Simulation time	1126997295 ps
CPU time	12.16 seconds
Started	Sep 11 09:20:18 AM UTC 24
Finished	Sep 11 09:20:32 AM UTC 24
Peak memory	213824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877733868 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.2877733868
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2655240090
Short name	T654
Test name
Test status
Simulation time	5751268135 ps
CPU time	439.9 seconds
Started	Sep 11 09:20:26 AM UTC 24
Finished	Sep 11 09:27:52 AM UTC 24
Peak memory	213824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655240090 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc ess_b2b.2655240090
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.435573818
Short name	T581
Test name
Test status
Simulation time	49286542 ps
CPU time	1.06 seconds
Started	Sep 11 09:21:27 AM UTC 24
Finished	Sep 11 09:21:30 AM UTC 24
Peak memory	212408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435573818 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.435573818
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.3102710157
Short name	T745
Test name
Test status
Simulation time	15973604482 ps
CPU time	1007.05 seconds
Started	Sep 11 09:21:23 AM UTC 24
Finished	Sep 11 09:38:22 AM UTC 24
Peak memory	374704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102710157 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3102710157
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.885980782
Short name	T570
Test name
Test status
Simulation time	529938642 ps
CPU time	13.22 seconds
Started	Sep 11 09:19:11 AM UTC 24
Finished	Sep 11 09:19:25 AM UTC 24
Peak memory	213748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885980782 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.885980782
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.411628644
Short name	T856
Test name
Test status
Simulation time	66994689267 ps
CPU time	1592.92 seconds
Started	Sep 11 09:21:38 AM UTC 24
Finished	Sep 11 09:48:29 AM UTC 24
Peak memory	384808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411628644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.411628644
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2260839875
Short name	T104
Test name
Test status
Simulation time	4515308481 ps
CPU time	82.6 seconds
Started	Sep 11 09:21:37 AM UTC 24
Finished	Sep 11 09:23:02 AM UTC 24
Peak memory	255936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260839875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2260839875
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.379030637
Short name	T639
Test name
Test status
Simulation time	12662222854 ps
CPU time	340.27 seconds
Started	Sep 11 09:20:06 AM UTC 24
Finished	Sep 11 09:25:51 AM UTC 24
Peak memory	213948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379030637 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.379030637
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2831391510
Short name	T597
Test name
Test status
Simulation time	151447007 ps
CPU time	102.74 seconds
Started	Sep 11 09:20:47 AM UTC 24
Finished	Sep 11 09:22:32 AM UTC 24
Peak memory	380768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2831391510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_t hroughput_w_partial_write.2831391510
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1977639759
Short name	T785
Test name
Test status
Simulation time	6840583467 ps
CPU time	1177.19 seconds
Started	Sep 11 09:22:08 AM UTC 24
Finished	Sep 11 09:41:59 AM UTC 24
Peak memory	383136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977639759 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during _key_req.1977639759
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.2119526163
Short name	T603
Test name
Test status
Simulation time	27424453 ps
CPU time	0.87 seconds
Started	Sep 11 09:22:55 AM UTC 24
Finished	Sep 11 09:22:57 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119526163 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2119526163
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1285394578
Short name	T606
Test name
Test status
Simulation time	12458864157 ps
CPU time	77.29 seconds
Started	Sep 11 09:21:47 AM UTC 24
Finished	Sep 11 09:23:07 AM UTC 24
Peak memory	213872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285394578 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1285394578
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3847505392
Short name	T904
Test name
Test status
Simulation time	220328045720 ps
CPU time	2142.84 seconds
Started	Sep 11 09:22:10 AM UTC 24
Finished	Sep 11 09:58:17 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847505392 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.3847505392
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2077140118
Short name	T595
Test name
Test status
Simulation time	379564647 ps
CPU time	2.73 seconds
Started	Sep 11 09:22:06 AM UTC 24
Finished	Sep 11 09:22:10 AM UTC 24
Peak memory	213852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077140118 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.2077140118
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1644743169
Short name	T607
Test name
Test status
Simulation time	136307196 ps
CPU time	70.83 seconds
Started	Sep 11 09:22:02 AM UTC 24
Finished	Sep 11 09:23:14 AM UTC 24
Peak memory	378656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 644743169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ma x_throughput.1644743169
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2195483702
Short name	T600
Test name
Test status
Simulation time	102349553 ps
CPU time	3.45 seconds
Started	Sep 11 09:22:38 AM UTC 24
Finished	Sep 11 09:22:42 AM UTC 24
Peak memory	223960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195483702 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.2195483702
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3442861489
Short name	T601
Test name
Test status
Simulation time	118123122 ps
CPU time	6.7 seconds
Started	Sep 11 09:22:36 AM UTC 24
Finished	Sep 11 09:22:44 AM UTC 24
Peak memory	224000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442861489 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.3442861489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3879076580
Short name	T726
Test name
Test status
Simulation time	53234211678 ps
CPU time	873.09 seconds
Started	Sep 11 09:21:44 AM UTC 24
Finished	Sep 11 09:36:27 AM UTC 24
Peak memory	387240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879076580 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.3879076580
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3144683566
Short name	T594
Test name
Test status
Simulation time	606811873 ps
CPU time	14.64 seconds
Started	Sep 11 09:21:52 AM UTC 24
Finished	Sep 11 09:22:07 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144683566 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.3144683566
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3637548778
Short name	T664
Test name
Test status
Simulation time	23468901086 ps
CPU time	429.37 seconds
Started	Sep 11 09:21:59 AM UTC 24
Finished	Sep 11 09:29:14 AM UTC 24
Peak memory	213952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637548778 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc ess_b2b.3637548778
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2783986869
Short name	T598
Test name
Test status
Simulation time	78784910 ps
CPU time	0.97 seconds
Started	Sep 11 09:22:33 AM UTC 24
Finished	Sep 11 09:22:35 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783986869 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2783986869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.427337403
Short name	T660
Test name
Test status
Simulation time	5450638695 ps
CPU time	380.81 seconds
Started	Sep 11 09:22:11 AM UTC 24
Finished	Sep 11 09:28:37 AM UTC 24
Peak memory	374896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427337403 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.427337403
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.188783783
Short name	T589
Test name
Test status
Simulation time	1369258450 ps
CPU time	6.87 seconds
Started	Sep 11 09:21:42 AM UTC 24
Finished	Sep 11 09:21:51 AM UTC 24
Peak memory	213932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188783783 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.188783783
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.4197878989
Short name	T907
Test name
Test status
Simulation time	33235059916 ps
CPU time	2121.51 seconds
Started	Sep 11 09:22:44 AM UTC 24
Finished	Sep 11 09:58:27 AM UTC 24
Peak memory	381096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419787898 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.4197878989
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2022421523
Short name	T105
Test name
Test status
Simulation time	563359724 ps
CPU time	22.83 seconds
Started	Sep 11 09:22:43 AM UTC 24
Finished	Sep 11 09:23:07 AM UTC 24
Peak memory	224176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022421523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2022421523
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3958379661
Short name	T641
Test name
Test status
Simulation time	11342957684 ps
CPU time	274.22 seconds
Started	Sep 11 09:21:49 AM UTC 24
Finished	Sep 11 09:26:27 AM UTC 24
Peak memory	213976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958379661 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.3958379661
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.4120564105
Short name	T596
Test name
Test status
Simulation time	95724235 ps
CPU time	4.5 seconds
Started	Sep 11 09:22:05 AM UTC 24
Finished	Sep 11 09:22:11 AM UTC 24
Peak memory	231200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4120564105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t hroughput_w_partial_write.4120564105
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1870415057
Short name	T679
Test name
Test status
Simulation time	1651211525 ps
CPU time	400.56 seconds
Started	Sep 11 09:23:33 AM UTC 24
Finished	Sep 11 09:30:19 AM UTC 24
Peak memory	378972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870415057 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during _key_req.1870415057
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2572947980
Short name	T619
Test name
Test status
Simulation time	43704854 ps
CPU time	0.86 seconds
Started	Sep 11 09:24:00 AM UTC 24
Finished	Sep 11 09:24:02 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572947980 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2572947980
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.108807903
Short name	T611
Test name
Test status
Simulation time	3919719762 ps
CPU time	28.77 seconds
Started	Sep 11 09:23:03 AM UTC 24
Finished	Sep 11 09:23:33 AM UTC 24
Peak memory	214304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108807903 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.108807903
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2543613003
Short name	T768
Test name
Test status
Simulation time	11011319441 ps
CPU time	1032.26 seconds
Started	Sep 11 09:23:33 AM UTC 24
Finished	Sep 11 09:40:57 AM UTC 24
Peak memory	382888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543613003 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.2543613003
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1017799454
Short name	T612
Test name
Test status
Simulation time	414748417 ps
CPU time	2.58 seconds
Started	Sep 11 09:23:32 AM UTC 24
Finished	Sep 11 09:23:36 AM UTC 24
Peak memory	213752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017799454 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.1017799454
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2322573528
Short name	T608
Test name
Test status
Simulation time	236258089 ps
CPU time	9.94 seconds
Started	Sep 11 09:23:15 AM UTC 24
Finished	Sep 11 09:23:26 AM UTC 24
Peak memory	247584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 322573528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma x_throughput.2322573528
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.1642848475
Short name	T618
Test name
Test status
Simulation time	114613474 ps
CPU time	4.28 seconds
Started	Sep 11 09:23:54 AM UTC 24
Finished	Sep 11 09:23:59 AM UTC 24
Peak memory	223976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642848475 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.1642848475
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2660344233
Short name	T616
Test name
Test status
Simulation time	77014204 ps
CPU time	5.76 seconds
Started	Sep 11 09:23:48 AM UTC 24
Finished	Sep 11 09:23:55 AM UTC 24
Peak memory	213872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660344233 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.2660344233
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1854926353
Short name	T761
Test name
Test status
Simulation time	4360702169 ps
CPU time	1008.06 seconds
Started	Sep 11 09:23:02 AM UTC 24
Finished	Sep 11 09:40:02 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854926353 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.1854926353
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.673955197
Short name	T609
Test name
Test status
Simulation time	5001286978 ps
CPU time	21.97 seconds
Started	Sep 11 09:23:08 AM UTC 24
Finished	Sep 11 09:23:31 AM UTC 24
Peak memory	214036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673955197 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.673955197
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1991058251
Short name	T673
Test name
Test status
Simulation time	28502887501 ps
CPU time	401.78 seconds
Started	Sep 11 09:23:08 AM UTC 24
Finished	Sep 11 09:29:55 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991058251 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acc ess_b2b.1991058251
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.770761419
Short name	T614
Test name
Test status
Simulation time	30570451 ps
CPU time	1.04 seconds
Started	Sep 11 09:23:45 AM UTC 24
Finished	Sep 11 09:23:47 AM UTC 24
Peak memory	212408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770761419 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.770761419
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.2084147533
Short name	T617
Test name
Test status
Simulation time	1606027043 ps
CPU time	19.87 seconds
Started	Sep 11 09:23:37 AM UTC 24
Finished	Sep 11 09:23:58 AM UTC 24
Peak memory	222980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084147533 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2084147533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.4256871857
Short name	T605
Test name
Test status
Simulation time	301161461 ps
CPU time	4.22 seconds
Started	Sep 11 09:22:58 AM UTC 24
Finished	Sep 11 09:23:03 AM UTC 24
Peak memory	220016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256871857 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.4256871857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3145385119
Short name	T919
Test name
Test status
Simulation time	11989636382 ps
CPU time	2934.56 seconds
Started	Sep 11 09:23:58 AM UTC 24
Finished	Sep 11 10:13:24 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314538511 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.3145385119
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2173110318
Short name	T621
Test name
Test status
Simulation time	1485052686 ps
CPU time	27.03 seconds
Started	Sep 11 09:23:55 AM UTC 24
Finished	Sep 11 09:24:23 AM UTC 24
Peak memory	270124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173110318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2173110318
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1735203531
Short name	T677
Test name
Test status
Simulation time	71855618444 ps
CPU time	410.05 seconds
Started	Sep 11 09:23:05 AM UTC 24
Finished	Sep 11 09:30:00 AM UTC 24
Peak memory	214100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735203531 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.1735203531
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1506604747
Short name	T610
Test name
Test status
Simulation time	52965553 ps
CPU time	4.09 seconds
Started	Sep 11 09:23:27 AM UTC 24
Finished	Sep 11 09:23:32 AM UTC 24
Peak memory	230984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1506604747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t hroughput_w_partial_write.1506604747
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3430650751
Short name	T763
Test name
Test status
Simulation time	2506246551 ps
CPU time	881.43 seconds
Started	Sep 11 09:25:16 AM UTC 24
Finished	Sep 11 09:40:07 AM UTC 24
Peak memory	384932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430650751 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during _key_req.3430650751
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.772201413
Short name	T638
Test name
Test status
Simulation time	12408614 ps
CPU time	0.92 seconds
Started	Sep 11 09:25:45 AM UTC 24
Finished	Sep 11 09:25:46 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772201413 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.772201413
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2270939944
Short name	T627
Test name
Test status
Simulation time	959017176 ps
CPU time	36.23 seconds
Started	Sep 11 09:24:25 AM UTC 24
Finished	Sep 11 09:25:03 AM UTC 24
Peak memory	213916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270939944 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.2270939944
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3757724041
Short name	T779
Test name
Test status
Simulation time	76302700658 ps
CPU time	974.63 seconds
Started	Sep 11 09:25:18 AM UTC 24
Finished	Sep 11 09:41:44 AM UTC 24
Peak memory	382904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757724041 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.3757724041
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3999332428
Short name	T629
Test name
Test status
Simulation time	2654823438 ps
CPU time	11.87 seconds
Started	Sep 11 09:25:04 AM UTC 24
Finished	Sep 11 09:25:16 AM UTC 24
Peak memory	213840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999332428 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.3999332428
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1421466608
Short name	T636
Test name
Test status
Simulation time	129425888 ps
CPU time	51.02 seconds
Started	Sep 11 09:24:51 AM UTC 24
Finished	Sep 11 09:25:44 AM UTC 24
Peak memory	325408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 421466608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ma x_throughput.1421466608
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.4011720053
Short name	T634
Test name
Test status
Simulation time	79049355 ps
CPU time	3.06 seconds
Started	Sep 11 09:25:36 AM UTC 24
Finished	Sep 11 09:25:40 AM UTC 24
Peak memory	224008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011720053 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.4011720053
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.901277211
Short name	T635
Test name
Test status
Simulation time	154821035 ps
CPU time	6.08 seconds
Started	Sep 11 09:25:34 AM UTC 24
Finished	Sep 11 09:25:41 AM UTC 24
Peak memory	224164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901277211 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.901277211
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3463085970
Short name	T770
Test name
Test status
Simulation time	132196335205 ps
CPU time	996.56 seconds
Started	Sep 11 09:24:20 AM UTC 24
Finished	Sep 11 09:41:07 AM UTC 24
Peak memory	386908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463085970 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.3463085970
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1574637382
Short name	T625
Test name
Test status
Simulation time	400101235 ps
CPU time	6.02 seconds
Started	Sep 11 09:24:43 AM UTC 24
Finished	Sep 11 09:24:51 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574637382 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.1574637382
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1444823097
Short name	T696
Test name
Test status
Simulation time	5041883562 ps
CPU time	444.31 seconds
Started	Sep 11 09:24:46 AM UTC 24
Finished	Sep 11 09:32:17 AM UTC 24
Peak memory	214104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444823097 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acc ess_b2b.1444823097
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.882102224
Short name	T633
Test name
Test status
Simulation time	84385179 ps
CPU time	1.15 seconds
Started	Sep 11 09:25:33 AM UTC 24
Finished	Sep 11 09:25:35 AM UTC 24
Peak memory	212624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882102224 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.882102224
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.358288859
Short name	T747
Test name
Test status
Simulation time	6728017996 ps
CPU time	772.4 seconds
Started	Sep 11 09:25:33 AM UTC 24
Finished	Sep 11 09:38:34 AM UTC 24
Peak memory	385196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358288859 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.358288859
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2603087777
Short name	T620
Test name
Test status
Simulation time	1278693021 ps
CPU time	14.38 seconds
Started	Sep 11 09:24:03 AM UTC 24
Finished	Sep 11 09:24:19 AM UTC 24
Peak memory	213816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603087777 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2603087777
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.23323804
Short name	T902
Test name
Test status
Simulation time	29402295646 ps
CPU time	1879.69 seconds
Started	Sep 11 09:25:42 AM UTC 24
Finished	Sep 11 09:57:22 AM UTC 24
Peak memory	387244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23323804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.23323804
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1379852417
Short name	T663
Test name
Test status
Simulation time	568062370 ps
CPU time	205.35 seconds
Started	Sep 11 09:25:41 AM UTC 24
Finished	Sep 11 09:29:10 AM UTC 24
Peak memory	391088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379852417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1379852417
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1523490028
Short name	T659
Test name
Test status
Simulation time	2482431499 ps
CPU time	231.45 seconds
Started	Sep 11 09:24:34 AM UTC 24
Finished	Sep 11 09:28:29 AM UTC 24
Peak memory	214180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523490028 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.1523490028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.631570933
Short name	T644
Test name
Test status
Simulation time	938440863 ps
CPU time	103.08 seconds
Started	Sep 11 09:24:57 AM UTC 24
Finished	Sep 11 09:26:42 AM UTC 24
Peak memory	374700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 631570933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_th roughput_w_partial_write.631570933
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.622204551
Short name	T840
Test name
Test status
Simulation time	38641099299 ps
CPU time	1208.58 seconds
Started	Sep 11 09:26:48 AM UTC 24
Finished	Sep 11 09:47:10 AM UTC 24
Peak memory	384932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622204551 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_ key_req.622204551
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.988939336
Short name	T655
Test name
Test status
Simulation time	18881562 ps
CPU time	0.9 seconds
Started	Sep 11 09:27:53 AM UTC 24
Finished	Sep 11 09:27:55 AM UTC 24
Peak memory	212572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988939336 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.988939336
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.3424285020
Short name	T646
Test name
Test status
Simulation time	750812876 ps
CPU time	52.95 seconds
Started	Sep 11 09:25:52 AM UTC 24
Finished	Sep 11 09:26:46 AM UTC 24
Peak memory	214044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424285020 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.3424285020
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.770108825
Short name	T859
Test name
Test status
Simulation time	8965518969 ps
CPU time	1296.19 seconds
Started	Sep 11 09:26:49 AM UTC 24
Finished	Sep 11 09:48:39 AM UTC 24
Peak memory	378800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770108825 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.770108825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3047444012
Short name	T648
Test name
Test status
Simulation time	1006384006 ps
CPU time	6.29 seconds
Started	Sep 11 09:26:46 AM UTC 24
Finished	Sep 11 09:26:53 AM UTC 24
Peak memory	213820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047444012 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.3047444012
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.883771035
Short name	T647
Test name
Test status
Simulation time	76021011 ps
CPU time	9.19 seconds
Started	Sep 11 09:26:37 AM UTC 24
Finished	Sep 11 09:26:48 AM UTC 24
Peak memory	264008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 83771035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max _throughput.883771035
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1383121393
Short name	T652
Test name
Test status
Simulation time	758751140 ps
CPU time	7.86 seconds
Started	Sep 11 09:27:09 AM UTC 24
Finished	Sep 11 09:27:18 AM UTC 24
Peak memory	223976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383121393 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1383121393
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2580343597
Short name	T651
Test name
Test status
Simulation time	1330575548 ps
CPU time	8.18 seconds
Started	Sep 11 09:26:59 AM UTC 24
Finished	Sep 11 09:27:08 AM UTC 24
Peak memory	224396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580343597 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.2580343597
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.216807945
Short name	T706
Test name
Test status
Simulation time	89175627812 ps
CPU time	509.5 seconds
Started	Sep 11 09:25:48 AM UTC 24
Finished	Sep 11 09:34:23 AM UTC 24
Peak memory	354152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216807945 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.216807945
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.4170769884
Short name	T642
Test name
Test status
Simulation time	888507160 ps
CPU time	6.01 seconds
Started	Sep 11 09:26:28 AM UTC 24
Finished	Sep 11 09:26:35 AM UTC 24
Peak memory	213876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170769884 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.4170769884
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1758998078
Short name	T697
Test name
Test status
Simulation time	19125488768 ps
CPU time	355.29 seconds
Started	Sep 11 09:26:36 AM UTC 24
Finished	Sep 11 09:32:36 AM UTC 24
Peak memory	214128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758998078 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc ess_b2b.1758998078
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1821725001
Short name	T650
Test name
Test status
Simulation time	57231560 ps
CPU time	1.23 seconds
Started	Sep 11 09:26:56 AM UTC 24
Finished	Sep 11 09:26:58 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821725001 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1821725001
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2666450995
Short name	T769
Test name
Test status
Simulation time	118855281750 ps
CPU time	837.27 seconds
Started	Sep 11 09:26:54 AM UTC 24
Finished	Sep 11 09:41:01 AM UTC 24
Peak memory	385200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666450995 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2666450995
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2686396902
Short name	T640
Test name
Test status
Simulation time	273665649 ps
CPU time	8.33 seconds
Started	Sep 11 09:25:47 AM UTC 24
Finished	Sep 11 09:25:56 AM UTC 24
Peak memory	213840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686396902 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2686396902
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.546349770
Short name	T805
Test name
Test status
Simulation time	19939781602 ps
CPU time	1480.72 seconds
Started	Sep 11 09:27:22 AM UTC 24
Finished	Sep 11 09:52:19 AM UTC 24
Peak memory	387176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546349770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.546349770
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4236033765
Short name	T690
Test name
Test status
Simulation time	2378906015 ps
CPU time	253.63 seconds
Started	Sep 11 09:27:19 AM UTC 24
Finished	Sep 11 09:31:36 AM UTC 24
Peak memory	385008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236033765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.4236033765
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2969927174
Short name	T656
Test name
Test status
Simulation time	2146845066 ps
CPU time	121.85 seconds
Started	Sep 11 09:25:57 AM UTC 24
Finished	Sep 11 09:28:01 AM UTC 24
Peak memory	213784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969927174 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2969927174
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1448812080
Short name	T653
Test name
Test status
Simulation time	113679664 ps
CPU time	37.23 seconds
Started	Sep 11 09:26:43 AM UTC 24
Finished	Sep 11 09:27:22 AM UTC 24
Peak memory	313368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1448812080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t hroughput_w_partial_write.1448812080
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3097376180
Short name	T716
Test name
Test status
Simulation time	41494996174 ps
CPU time	389.69 seconds
Started	Sep 11 09:29:15 AM UTC 24
Finished	Sep 11 09:35:50 AM UTC 24
Peak memory	380832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097376180 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during _key_req.3097376180
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.223055759
Short name	T676
Test name
Test status
Simulation time	18465751 ps
CPU time	0.97 seconds
Started	Sep 11 09:29:55 AM UTC 24
Finished	Sep 11 09:29:57 AM UTC 24
Peak memory	212632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223055759 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.223055759
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.750957219
Short name	T675
Test name
Test status
Simulation time	38567623743 ps
CPU time	108.27 seconds
Started	Sep 11 09:28:06 AM UTC 24
Finished	Sep 11 09:29:57 AM UTC 24
Peak memory	213816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750957219 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.750957219
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.570171825
Short name	T852
Test name
Test status
Simulation time	19177321115 ps
CPU time	1121.11 seconds
Started	Sep 11 09:29:16 AM UTC 24
Finished	Sep 11 09:48:10 AM UTC 24
Peak memory	364460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570171825 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.570171825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1687852346
Short name	T666
Test name
Test status
Simulation time	1111386352 ps
CPU time	9.01 seconds
Started	Sep 11 09:29:11 AM UTC 24
Finished	Sep 11 09:29:21 AM UTC 24
Peak memory	214132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687852346 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.1687852346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1004297628
Short name	T669
Test name
Test status
Simulation time	421306494 ps
CPU time	43.53 seconds
Started	Sep 11 09:28:45 AM UTC 24
Finished	Sep 11 09:29:30 AM UTC 24
Peak memory	333544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 004297628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ma x_throughput.1004297628
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3817442180
Short name	T671
Test name
Test status
Simulation time	66203348 ps
CPU time	4.65 seconds
Started	Sep 11 09:29:32 AM UTC 24
Finished	Sep 11 09:29:38 AM UTC 24
Peak memory	224160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817442180 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.3817442180
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2167962511
Short name	T670
Test name
Test status
Simulation time	271685318 ps
CPU time	4.77 seconds
Started	Sep 11 09:29:28 AM UTC 24
Finished	Sep 11 09:29:34 AM UTC 24
Peak memory	224328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167962511 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.2167962511
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1448684064
Short name	T851
Test name
Test status
Simulation time	40076581153 ps
CPU time	1190.28 seconds
Started	Sep 11 09:28:02 AM UTC 24
Finished	Sep 11 09:48:06 AM UTC 24
Peak memory	386988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448684064 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1448684064
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2173557337
Short name	T672
Test name
Test status
Simulation time	738269584 ps
CPU time	82.08 seconds
Started	Sep 11 09:28:30 AM UTC 24
Finished	Sep 11 09:29:54 AM UTC 24
Peak memory	358188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173557337 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.2173557337
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.78128529
Short name	T732
Test name
Test status
Simulation time	23941687394 ps
CPU time	518.6 seconds
Started	Sep 11 09:28:38 AM UTC 24
Finished	Sep 11 09:37:24 AM UTC 24
Peak memory	214156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78128529 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acces s_b2b.78128529
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4161815809
Short name	T668
Test name
Test status
Simulation time	88456969 ps
CPU time	1.08 seconds
Started	Sep 11 09:29:25 AM UTC 24
Finished	Sep 11 09:29:28 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161815809 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.4161815809
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.3858047122
Short name	T801
Test name
Test status
Simulation time	39923111191 ps
CPU time	842.4 seconds
Started	Sep 11 09:29:22 AM UTC 24
Finished	Sep 11 09:43:34 AM UTC 24
Peak memory	386920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858047122 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3858047122
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.1607957421
Short name	T657
Test name
Test status
Simulation time	1605132596 ps
CPU time	8.16 seconds
Started	Sep 11 09:27:56 AM UTC 24
Finished	Sep 11 09:28:05 AM UTC 24
Peak memory	213748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607957421 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1607957421
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.602693633
Short name	T917
Test name
Test status
Simulation time	41304915770 ps
CPU time	2377.12 seconds
Started	Sep 11 09:29:39 AM UTC 24
Finished	Sep 11 10:09:41 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602693633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.602693633
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3057655468
Short name	T700
Test name
Test status
Simulation time	2154053197 ps
CPU time	194.36 seconds
Started	Sep 11 09:29:35 AM UTC 24
Finished	Sep 11 09:32:52 AM UTC 24
Peak memory	368564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057655468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3057655468
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2466625543
Short name	T693
Test name
Test status
Simulation time	7872418768 ps
CPU time	231.12 seconds
Started	Sep 11 09:28:18 AM UTC 24
Finished	Sep 11 09:32:13 AM UTC 24
Peak memory	213816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466625543 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.2466625543
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2937277823
Short name	T680
Test name
Test status
Simulation time	732134064 ps
CPU time	73.78 seconds
Started	Sep 11 09:29:10 AM UTC 24
Finished	Sep 11 09:30:25 AM UTC 24
Peak memory	378976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2937277823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t hroughput_w_partial_write.2937277823
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.892831229
Short name	T707
Test name
Test status
Simulation time	2781102278 ps
CPU time	225.09 seconds
Started	Sep 11 09:30:36 AM UTC 24
Finished	Sep 11 09:34:24 AM UTC 24
Peak memory	360584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892831229 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during_ key_req.892831229
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2503200939
Short name	T691
Test name
Test status
Simulation time	53617870 ps
CPU time	0.91 seconds
Started	Sep 11 09:31:37 AM UTC 24
Finished	Sep 11 09:31:39 AM UTC 24
Peak memory	212576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503200939 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2503200939
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.1807548972
Short name	T684
Test name
Test status
Simulation time	1806120331 ps
CPU time	42.34 seconds
Started	Sep 11 09:29:58 AM UTC 24
Finished	Sep 11 09:30:42 AM UTC 24
Peak memory	214168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807548972 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.1807548972
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.6028709
Short name	T750
Test name
Test status
Simulation time	6703425122 ps
CPU time	492.33 seconds
Started	Sep 11 09:30:41 AM UTC 24
Finished	Sep 11 09:38:59 AM UTC 24
Peak memory	379000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6028709 -assert nopostproc +UVM_TESTNA ME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.6028709
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3604360855
Short name	T683
Test name
Test status
Simulation time	2852877889 ps
CPU time	10.63 seconds
Started	Sep 11 09:30:29 AM UTC 24
Finished	Sep 11 09:30:41 AM UTC 24
Peak memory	214200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604360855 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.3604360855
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3830683032
Short name	T682
Test name
Test status
Simulation time	100615606 ps
CPU time	14.3 seconds
Started	Sep 11 09:30:20 AM UTC 24
Finished	Sep 11 09:30:35 AM UTC 24
Peak memory	270184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 830683032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ma x_throughput.3830683032
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3937752021
Short name	T688
Test name
Test status
Simulation time	336153756 ps
CPU time	7.49 seconds
Started	Sep 11 09:30:56 AM UTC 24
Finished	Sep 11 09:31:04 AM UTC 24
Peak memory	224328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937752021 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.3937752021
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.749927774
Short name	T687
Test name
Test status
Simulation time	983337397 ps
CPU time	4.47 seconds
Started	Sep 11 09:30:49 AM UTC 24
Finished	Sep 11 09:30:55 AM UTC 24
Peak memory	223992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749927774 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.749927774
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.559668909
Short name	T802
Test name
Test status
Simulation time	18078784767 ps
CPU time	815.56 seconds
Started	Sep 11 09:29:57 AM UTC 24
Finished	Sep 11 09:43:42 AM UTC 24
Peak memory	364708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559668909 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.559668909
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.4082234244
Short name	T678
Test name
Test status
Simulation time	465958255 ps
CPU time	15.38 seconds
Started	Sep 11 09:30:00 AM UTC 24
Finished	Sep 11 09:30:17 AM UTC 24
Peak memory	256112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082234244 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.4082234244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2296214931
Short name	T731
Test name
Test status
Simulation time	51742344487 ps
CPU time	412.39 seconds
Started	Sep 11 09:30:18 AM UTC 24
Finished	Sep 11 09:37:15 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296214931 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acc ess_b2b.2296214931
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.962732773
Short name	T686
Test name
Test status
Simulation time	81737433 ps
CPU time	1.1 seconds
Started	Sep 11 09:30:46 AM UTC 24
Finished	Sep 11 09:30:48 AM UTC 24
Peak memory	212408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962732773 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.962732773
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2870648456
Short name	T876
Test name
Test status
Simulation time	9865650836 ps
CPU time	1232.72 seconds
Started	Sep 11 09:30:43 AM UTC 24
Finished	Sep 11 09:51:29 AM UTC 24
Peak memory	387116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870648456 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2870648456
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2259342063
Short name	T689
Test name
Test status
Simulation time	967479719 ps
CPU time	67.05 seconds
Started	Sep 11 09:29:56 AM UTC 24
Finished	Sep 11 09:31:05 AM UTC 24
Peak memory	339740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259342063 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2259342063
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3129860409
Short name	T895
Test name
Test status
Simulation time	60833174439 ps
CPU time	1488.68 seconds
Started	Sep 11 09:31:06 AM UTC 24
Finished	Sep 11 09:56:12 AM UTC 24
Peak memory	386980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312986040 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.3129860409
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3966883711
Short name	T717
Test name
Test status
Simulation time	3170561217 ps
CPU time	349.88 seconds
Started	Sep 11 09:29:58 AM UTC 24
Finished	Sep 11 09:35:53 AM UTC 24
Peak memory	214200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966883711 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3966883711
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.210722964
Short name	T694
Test name
Test status
Simulation time	302240184 ps
CPU time	105.65 seconds
Started	Sep 11 09:30:26 AM UTC 24
Finished	Sep 11 09:32:14 AM UTC 24
Peak memory	380704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 210722964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_th roughput_w_partial_write.210722964
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2716807303
Short name	T274
Test name
Test status
Simulation time	5786413584 ps
CPU time	734.31 seconds
Started	Sep 11 08:40:51 AM UTC 24
Finished	Sep 11 08:53:14 AM UTC 24
Peak memory	376744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716807303 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_ key_req.2716807303
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2339398506
Short name	T112
Test name
Test status
Simulation time	43638126 ps
CPU time	0.97 seconds
Started	Sep 11 08:40:55 AM UTC 24
Finished	Sep 11 08:41:17 AM UTC 24
Peak memory	212540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339398506 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2339398506
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.82921643
Short name	T64
Test name
Test status
Simulation time	1030078676 ps
CPU time	69.4 seconds
Started	Sep 11 08:40:48 AM UTC 24
Finished	Sep 11 08:41:59 AM UTC 24
Peak memory	213240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82921643 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.82921643
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.278398198
Short name	T25
Test name
Test status
Simulation time	2100105800 ps
CPU time	127.67 seconds
Started	Sep 11 08:40:51 AM UTC 24
Finished	Sep 11 08:43:01 AM UTC 24
Peak memory	358372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278398198 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.278398198
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1922359533
Short name	T56
Test name
Test status
Simulation time	592528462 ps
CPU time	9.81 seconds
Started	Sep 11 08:40:50 AM UTC 24
Finished	Sep 11 08:41:01 AM UTC 24
Peak memory	214168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922359533 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.1922359533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2138510811
Short name	T51
Test name
Test status
Simulation time	108955089 ps
CPU time	22.84 seconds
Started	Sep 11 08:40:49 AM UTC 24
Finished	Sep 11 08:41:13 AM UTC 24
Peak memory	300896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 138510811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max _throughput.2138510811
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2810738458
Short name	T41
Test name
Test status
Simulation time	86608494 ps
CPU time	4.77 seconds
Started	Sep 11 08:40:53 AM UTC 24
Finished	Sep 11 08:40:58 AM UTC 24
Peak memory	224312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810738458 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.2810738458
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1762239783
Short name	T42
Test name
Test status
Simulation time	1833851759 ps
CPU time	10.59 seconds
Started	Sep 11 08:40:52 AM UTC 24
Finished	Sep 11 08:41:04 AM UTC 24
Peak memory	224084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762239783 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.1762239783
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3571616657
Short name	T355
Test name
Test status
Simulation time	2614872740 ps
CPU time	1169.02 seconds
Started	Sep 11 08:40:47 AM UTC 24
Finished	Sep 11 09:00:30 AM UTC 24
Peak memory	382824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571616657 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.3571616657
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3209698590
Short name	T108
Test name
Test status
Simulation time	382228292 ps
CPU time	17.17 seconds
Started	Sep 11 08:40:48 AM UTC 24
Finished	Sep 11 08:41:06 AM UTC 24
Peak memory	214056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209698590 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.3209698590
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3972774124
Short name	T198
Test name
Test status
Simulation time	4149338942 ps
CPU time	300.15 seconds
Started	Sep 11 08:40:49 AM UTC 24
Finished	Sep 11 08:45:53 AM UTC 24
Peak memory	213964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972774124 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce ss_b2b.3972774124
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3558654881
Short name	T66
Test name
Test status
Simulation time	30132938 ps
CPU time	1.26 seconds
Started	Sep 11 08:40:52 AM UTC 24
Finished	Sep 11 08:40:55 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558654881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3558654881
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3096127697
Short name	T132
Test name
Test status
Simulation time	14728035945 ps
CPU time	500.96 seconds
Started	Sep 11 08:40:52 AM UTC 24
Finished	Sep 11 08:49:19 AM UTC 24
Peak memory	368512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096127697 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3096127697
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1293595038
Short name	T30
Test name
Test status
Simulation time	679518188 ps
CPU time	3.18 seconds
Started	Sep 11 08:40:55 AM UTC 24
Finished	Sep 11 08:41:20 AM UTC 24
Peak memory	250192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293595038 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1293595038
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2622690921
Short name	T109
Test name
Test status
Simulation time	1942507905 ps
CPU time	18.13 seconds
Started	Sep 11 08:40:47 AM UTC 24
Finished	Sep 11 08:41:07 AM UTC 24
Peak memory	213616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622690921 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2622690921
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2782060888
Short name	T20
Test name
Test status
Simulation time	2431689356 ps
CPU time	100.74 seconds
Started	Sep 11 08:40:55 AM UTC 24
Finished	Sep 11 08:42:58 AM UTC 24
Peak memory	224420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278206088 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.2782060888
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.102423564
Short name	T98
Test name
Test status
Simulation time	3864160882 ps
CPU time	237.07 seconds
Started	Sep 11 08:40:48 AM UTC 24
Finished	Sep 11 08:44:49 AM UTC 24
Peak memory	214308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102423564 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.102423564
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3286935621
Short name	T151
Test name
Test status
Simulation time	455533272 ps
CPU time	39.35 seconds
Started	Sep 11 08:40:50 AM UTC 24
Finished	Sep 11 08:41:31 AM UTC 24
Peak memory	323744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3286935621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th roughput_w_partial_write.3286935621
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.387310686
Short name	T881
Test name
Test status
Simulation time	6643744597 ps
CPU time	1161.44 seconds
Started	Sep 11 09:32:53 AM UTC 24
Finished	Sep 11 09:52:28 AM UTC 24
Peak memory	386980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387310686 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during_ key_req.387310686
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1118986857
Short name	T709
Test name
Test status
Simulation time	26242269 ps
CPU time	0.83 seconds
Started	Sep 11 09:34:29 AM UTC 24
Finished	Sep 11 09:34:31 AM UTC 24
Peak memory	212576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118986857 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1118986857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1738149280
Short name	T698
Test name
Test status
Simulation time	3490502994 ps
CPU time	23.95 seconds
Started	Sep 11 09:32:13 AM UTC 24
Finished	Sep 11 09:32:39 AM UTC 24
Peak memory	213908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738149280 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.1738149280
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.2365008432
Short name	T798
Test name
Test status
Simulation time	2030820779 ps
CPU time	590.29 seconds
Started	Sep 11 09:32:58 AM UTC 24
Finished	Sep 11 09:42:55 AM UTC 24
Peak memory	384828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365008432 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.2365008432
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3307049567
Short name	T701
Test name
Test status
Simulation time	674819605 ps
CPU time	12 seconds
Started	Sep 11 09:32:44 AM UTC 24
Finished	Sep 11 09:32:58 AM UTC 24
Peak memory	214128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307049567 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.3307049567
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2994254600
Short name	T702
Test name
Test status
Simulation time	103451169 ps
CPU time	48.45 seconds
Started	Sep 11 09:32:37 AM UTC 24
Finished	Sep 11 09:33:27 AM UTC 24
Peak memory	317216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 994254600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ma x_throughput.2994254600
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.721471229
Short name	T708
Test name
Test status
Simulation time	91405139 ps
CPU time	4.09 seconds
Started	Sep 11 09:34:23 AM UTC 24
Finished	Sep 11 09:34:28 AM UTC 24
Peak memory	224168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721471229 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.721471229
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.4103360185
Short name	T705
Test name
Test status
Simulation time	1368183676 ps
CPU time	13.19 seconds
Started	Sep 11 09:34:08 AM UTC 24
Finished	Sep 11 09:34:22 AM UTC 24
Peak memory	213816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103360185 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.4103360185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3363490509
Short name	T808
Test name
Test status
Simulation time	5639254207 ps
CPU time	743.27 seconds
Started	Sep 11 09:31:56 AM UTC 24
Finished	Sep 11 09:44:28 AM UTC 24
Peak memory	380840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363490509 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.3363490509
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2096026534
Short name	T699
Test name
Test status
Simulation time	1201474933 ps
CPU time	25.08 seconds
Started	Sep 11 09:32:17 AM UTC 24
Finished	Sep 11 09:32:43 AM UTC 24
Peak memory	213880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096026534 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.2096026534
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3041213894
Short name	T737
Test name
Test status
Simulation time	31991466051 ps
CPU time	332.54 seconds
Started	Sep 11 09:32:18 AM UTC 24
Finished	Sep 11 09:37:55 AM UTC 24
Peak memory	213952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041213894 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc ess_b2b.3041213894
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.1738222434
Short name	T704
Test name
Test status
Simulation time	119738777 ps
CPU time	1.19 seconds
Started	Sep 11 09:34:05 AM UTC 24
Finished	Sep 11 09:34:07 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738222434 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1738222434
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2434390775
Short name	T855
Test name
Test status
Simulation time	4493011707 ps
CPU time	886.56 seconds
Started	Sep 11 09:33:29 AM UTC 24
Finished	Sep 11 09:48:25 AM UTC 24
Peak memory	384948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434390775 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2434390775
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.2629501343
Short name	T692
Test name
Test status
Simulation time	189287869 ps
CPU time	14.03 seconds
Started	Sep 11 09:31:40 AM UTC 24
Finished	Sep 11 09:31:55 AM UTC 24
Peak memory	213900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629501343 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2629501343
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2157288085
Short name	T910
Test name
Test status
Simulation time	40940661902 ps
CPU time	1491.24 seconds
Started	Sep 11 09:34:25 AM UTC 24
Finished	Sep 11 09:59:33 AM UTC 24
Peak memory	386916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215728808 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.2157288085
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2343873148
Short name	T106
Test name
Test status
Simulation time	1116264251 ps
CPU time	28.49 seconds
Started	Sep 11 09:34:24 AM UTC 24
Finished	Sep 11 09:34:54 AM UTC 24
Peak memory	224056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343873148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2343873148
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2514452959
Short name	T729
Test name
Test status
Simulation time	2911084079 ps
CPU time	285.81 seconds
Started	Sep 11 09:32:15 AM UTC 24
Finished	Sep 11 09:37:04 AM UTC 24
Peak memory	213884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514452959 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.2514452959
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.2541361881
Short name	T703
Test name
Test status
Simulation time	138337273 ps
CPU time	82.21 seconds
Started	Sep 11 09:32:40 AM UTC 24
Finished	Sep 11 09:34:04 AM UTC 24
Peak memory	356444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2541361881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_t hroughput_w_partial_write.2541361881
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2670087537
Short name	T841
Test name
Test status
Simulation time	2744172287 ps
CPU time	674.09 seconds
Started	Sep 11 09:35:51 AM UTC 24
Finished	Sep 11 09:47:13 AM UTC 24
Peak memory	372640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670087537 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during _key_req.2670087537
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3382044483
Short name	T725
Test name
Test status
Simulation time	16701662 ps
CPU time	0.99 seconds
Started	Sep 11 09:36:06 AM UTC 24
Finished	Sep 11 09:36:08 AM UTC 24
Peak memory	212808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382044483 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3382044483
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3180660475
Short name	T718
Test name
Test status
Simulation time	1026250179 ps
CPU time	57.44 seconds
Started	Sep 11 09:34:55 AM UTC 24
Finished	Sep 11 09:35:54 AM UTC 24
Peak memory	213844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180660475 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.3180660475
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2320261386
Short name	T858
Test name
Test status
Simulation time	33926967955 ps
CPU time	753.94 seconds
Started	Sep 11 09:35:54 AM UTC 24
Finished	Sep 11 09:48:36 AM UTC 24
Peak memory	376956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320261386 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.2320261386
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1032359029
Short name	T719
Test name
Test status
Simulation time	871081291 ps
CPU time	6.63 seconds
Started	Sep 11 09:35:48 AM UTC 24
Finished	Sep 11 09:35:56 AM UTC 24
Peak memory	224108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032359029 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.1032359029
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.3014887775
Short name	T715
Test name
Test status
Simulation time	55288802 ps
CPU time	5.74 seconds
Started	Sep 11 09:35:41 AM UTC 24
Finished	Sep 11 09:35:48 AM UTC 24
Peak memory	237416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 014887775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma x_throughput.3014887775
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2766192745
Short name	T724
Test name
Test status
Simulation time	613849943 ps
CPU time	6.54 seconds
Started	Sep 11 09:35:58 AM UTC 24
Finished	Sep 11 09:36:06 AM UTC 24
Peak memory	224080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766192745 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.2766192745
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.3972968227
Short name	T723
Test name
Test status
Simulation time	682175199 ps
CPU time	6.88 seconds
Started	Sep 11 09:35:57 AM UTC 24
Finished	Sep 11 09:36:05 AM UTC 24
Peak memory	213812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972968227 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.3972968227
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.381550168
Short name	T870
Test name
Test status
Simulation time	3433557817 ps
CPU time	887.14 seconds
Started	Sep 11 09:34:55 AM UTC 24
Finished	Sep 11 09:49:52 AM UTC 24
Peak memory	384876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381550168 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.381550168
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2818081865
Short name	T712
Test name
Test status
Simulation time	108660243 ps
CPU time	2.37 seconds
Started	Sep 11 09:35:35 AM UTC 24
Finished	Sep 11 09:35:38 AM UTC 24
Peak memory	213824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818081865 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.2818081865
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1627861132
Short name	T781
Test name
Test status
Simulation time	61262864739 ps
CPU time	365.79 seconds
Started	Sep 11 09:35:39 AM UTC 24
Finished	Sep 11 09:41:50 AM UTC 24
Peak memory	214232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627861132 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc ess_b2b.1627861132
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2740735358
Short name	T722
Test name
Test status
Simulation time	279077212 ps
CPU time	1.06 seconds
Started	Sep 11 09:35:57 AM UTC 24
Finished	Sep 11 09:35:59 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740735358 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2740735358
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.2203852132
Short name	T742
Test name
Test status
Simulation time	12607703583 ps
CPU time	132.52 seconds
Started	Sep 11 09:35:55 AM UTC 24
Finished	Sep 11 09:38:10 AM UTC 24
Peak memory	384944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203852132 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2203852132
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.4283263111
Short name	T714
Test name
Test status
Simulation time	248765628 ps
CPU time	70.61 seconds
Started	Sep 11 09:34:32 AM UTC 24
Finished	Sep 11 09:35:45 AM UTC 24
Peak memory	356208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283263111 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4283263111
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1751697953
Short name	T924
Test name
Test status
Simulation time	52951006403 ps
CPU time	2643.72 seconds
Started	Sep 11 09:36:05 AM UTC 24
Finished	Sep 11 10:20:38 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175169795 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.1751697953
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3613241031
Short name	T754
Test name
Test status
Simulation time	368837902 ps
CPU time	209.61 seconds
Started	Sep 11 09:36:00 AM UTC 24
Finished	Sep 11 09:39:33 AM UTC 24
Peak memory	382892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613241031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3613241031
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3148693600
Short name	T746
Test name
Test status
Simulation time	3205410118 ps
CPU time	188.81 seconds
Started	Sep 11 09:35:15 AM UTC 24
Finished	Sep 11 09:38:27 AM UTC 24
Peak memory	213868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148693600 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.3148693600
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3366646024
Short name	T720
Test name
Test status
Simulation time	442381871 ps
CPU time	9.56 seconds
Started	Sep 11 09:35:45 AM UTC 24
Finished	Sep 11 09:35:56 AM UTC 24
Peak memory	253792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3366646024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t hroughput_w_partial_write.3366646024
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.58481925
Short name	T739
Test name
Test status
Simulation time	371617211 ps
CPU time	17.15 seconds
Started	Sep 11 09:37:43 AM UTC 24
Finished	Sep 11 09:38:01 AM UTC 24
Peak memory	237364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58481925 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during_k ey_req.58481925
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1181629044
Short name	T743
Test name
Test status
Simulation time	53105279 ps
CPU time	1.01 seconds
Started	Sep 11 09:38:10 AM UTC 24
Finished	Sep 11 09:38:12 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181629044 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1181629044
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.154299191
Short name	T734
Test name
Test status
Simulation time	4756953592 ps
CPU time	72.28 seconds
Started	Sep 11 09:36:28 AM UTC 24
Finished	Sep 11 09:37:42 AM UTC 24
Peak memory	213908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154299191 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.154299191
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.4256982575
Short name	T880
Test name
Test status
Simulation time	133521656948 ps
CPU time	852.12 seconds
Started	Sep 11 09:37:45 AM UTC 24
Finished	Sep 11 09:52:06 AM UTC 24
Peak memory	384948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256982575 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.4256982575
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3517786441
Short name	T736
Test name
Test status
Simulation time	4836680462 ps
CPU time	7.56 seconds
Started	Sep 11 09:37:41 AM UTC 24
Finished	Sep 11 09:37:50 AM UTC 24
Peak memory	213984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517786441 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.3517786441
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2761323832
Short name	T733
Test name
Test status
Simulation time	286421547 ps
CPU time	22.58 seconds
Started	Sep 11 09:37:16 AM UTC 24
Finished	Sep 11 09:37:40 AM UTC 24
Peak memory	280352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 761323832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma x_throughput.2761323832
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1735059298
Short name	T741
Test name
Test status
Simulation time	176545268 ps
CPU time	5.48 seconds
Started	Sep 11 09:38:02 AM UTC 24
Finished	Sep 11 09:38:09 AM UTC 24
Peak memory	224408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735059298 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.1735059298
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2541180039
Short name	T740
Test name
Test status
Simulation time	1603163280 ps
CPU time	7.94 seconds
Started	Sep 11 09:37:59 AM UTC 24
Finished	Sep 11 09:38:08 AM UTC 24
Peak memory	224100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541180039 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.2541180039
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3649220165
Short name	T766
Test name
Test status
Simulation time	2820578993 ps
CPU time	248.82 seconds
Started	Sep 11 09:36:28 AM UTC 24
Finished	Sep 11 09:40:40 AM UTC 24
Peak memory	376684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649220165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.3649220165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3843944460
Short name	T749
Test name
Test status
Simulation time	1290650978 ps
CPU time	103.66 seconds
Started	Sep 11 09:37:05 AM UTC 24
Finished	Sep 11 09:38:51 AM UTC 24
Peak memory	366704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843944460 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.3843944460
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.461074815
Short name	T800
Test name
Test status
Simulation time	11773348323 ps
CPU time	379.41 seconds
Started	Sep 11 09:37:08 AM UTC 24
Finished	Sep 11 09:43:33 AM UTC 24
Peak memory	213968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461074815 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acce ss_b2b.461074815
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3426831947
Short name	T738
Test name
Test status
Simulation time	43412859 ps
CPU time	1.05 seconds
Started	Sep 11 09:37:56 AM UTC 24
Finished	Sep 11 09:37:58 AM UTC 24
Peak memory	212524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426831947 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3426831947
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.2644918383
Short name	T776
Test name
Test status
Simulation time	1505278237 ps
CPU time	219.49 seconds
Started	Sep 11 09:37:51 AM UTC 24
Finished	Sep 11 09:41:33 AM UTC 24
Peak memory	384808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644918383 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2644918383
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2228631430
Short name	T727
Test name
Test status
Simulation time	3053918565 ps
CPU time	16.38 seconds
Started	Sep 11 09:36:09 AM UTC 24
Finished	Sep 11 09:36:27 AM UTC 24
Peak memory	213964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228631430 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2228631430
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1631234223
Short name	T920
Test name
Test status
Simulation time	42622360367 ps
CPU time	2150.52 seconds
Started	Sep 11 09:38:09 AM UTC 24
Finished	Sep 11 10:14:24 AM UTC 24
Peak memory	387240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163123422 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.1631234223
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3089413461
Short name	T777
Test name
Test status
Simulation time	1323880209 ps
CPU time	207.43 seconds
Started	Sep 11 09:38:09 AM UTC 24
Finished	Sep 11 09:41:40 AM UTC 24
Peak memory	384940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089413461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3089413461
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2504178824
Short name	T782
Test name
Test status
Simulation time	17387338080 ps
CPU time	298 seconds
Started	Sep 11 09:36:49 AM UTC 24
Finished	Sep 11 09:41:51 AM UTC 24
Peak memory	213968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504178824 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.2504178824
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.2390623715
Short name	T735
Test name
Test status
Simulation time	79294854 ps
CPU time	18.53 seconds
Started	Sep 11 09:37:24 AM UTC 24
Finished	Sep 11 09:37:44 AM UTC 24
Peak memory	272476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2390623715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.2390623715
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1570975633
Short name	T906
Test name
Test status
Simulation time	14389979452 ps
CPU time	1135.12 seconds
Started	Sep 11 09:39:12 AM UTC 24
Finished	Sep 11 09:58:19 AM UTC 24
Peak memory	384864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570975633 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during _key_req.1570975633
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3508676921
Short name	T760
Test name
Test status
Simulation time	46507462 ps
CPU time	1.03 seconds
Started	Sep 11 09:39:59 AM UTC 24
Finished	Sep 11 09:40:01 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508676921 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3508676921
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.961001739
Short name	T751
Test name
Test status
Simulation time	485754550 ps
CPU time	36.05 seconds
Started	Sep 11 09:38:23 AM UTC 24
Finished	Sep 11 09:39:00 AM UTC 24
Peak memory	213720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961001739 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.961001739
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2829786745
Short name	T834
Test name
Test status
Simulation time	10688689272 ps
CPU time	444.86 seconds
Started	Sep 11 09:39:15 AM UTC 24
Finished	Sep 11 09:46:45 AM UTC 24
Peak memory	384868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829786745 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.2829786745
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.817011383
Short name	T753
Test name
Test status
Simulation time	559015219 ps
CPU time	11.4 seconds
Started	Sep 11 09:39:02 AM UTC 24
Finished	Sep 11 09:39:14 AM UTC 24
Peak memory	224104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817011383 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.817011383
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.2686503828
Short name	T755
Test name
Test status
Simulation time	368060803 ps
CPU time	50.52 seconds
Started	Sep 11 09:38:51 AM UTC 24
Finished	Sep 11 09:39:43 AM UTC 24
Peak memory	321644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 686503828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma x_throughput.2686503828
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2262553272
Short name	T757
Test name
Test status
Simulation time	163958068 ps
CPU time	3.74 seconds
Started	Sep 11 09:39:45 AM UTC 24
Finished	Sep 11 09:39:49 AM UTC 24
Peak memory	224280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262553272 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.2262553272
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3182098497
Short name	T759
Test name
Test status
Simulation time	423288970 ps
CPU time	12.2 seconds
Started	Sep 11 09:39:44 AM UTC 24
Finished	Sep 11 09:39:58 AM UTC 24
Peak memory	224072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182098497 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3182098497
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3595798113
Short name	T883
Test name
Test status
Simulation time	4288876502 ps
CPU time	870.75 seconds
Started	Sep 11 09:38:21 AM UTC 24
Finished	Sep 11 09:53:01 AM UTC 24
Peak memory	386892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595798113 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.3595798113
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2307426107
Short name	T748
Test name
Test status
Simulation time	496293945 ps
CPU time	8.02 seconds
Started	Sep 11 09:38:35 AM UTC 24
Finished	Sep 11 09:38:44 AM UTC 24
Peak memory	213856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307426107 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.2307426107
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1018578458
Short name	T787
Test name
Test status
Simulation time	14494871723 ps
CPU time	193.19 seconds
Started	Sep 11 09:38:45 AM UTC 24
Finished	Sep 11 09:42:02 AM UTC 24
Peak memory	213784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018578458 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc ess_b2b.1018578458
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1324631901
Short name	T756
Test name
Test status
Simulation time	27959219 ps
CPU time	1.1 seconds
Started	Sep 11 09:39:41 AM UTC 24
Finished	Sep 11 09:39:44 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324631901 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1324631901
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.2976749403
Short name	T873
Test name
Test status
Simulation time	34435475599 ps
CPU time	643.76 seconds
Started	Sep 11 09:39:34 AM UTC 24
Finished	Sep 11 09:50:25 AM UTC 24
Peak memory	377004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976749403 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2976749403
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.2567005181
Short name	T758
Test name
Test status
Simulation time	2353268614 ps
CPU time	102.08 seconds
Started	Sep 11 09:38:14 AM UTC 24
Finished	Sep 11 09:39:58 AM UTC 24
Peak memory	372908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567005181 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2567005181
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2738118721
Short name	T922
Test name
Test status
Simulation time	166017857591 ps
CPU time	2313.3 seconds
Started	Sep 11 09:39:59 AM UTC 24
Finished	Sep 11 10:18:59 AM UTC 24
Peak memory	395184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273811872 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.2738118721
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3520297546
Short name	T817
Test name
Test status
Simulation time	1004327603 ps
CPU time	333.98 seconds
Started	Sep 11 09:39:50 AM UTC 24
Finished	Sep 11 09:45:28 AM UTC 24
Peak memory	387296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520297546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3520297546
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.4244833544
Short name	T780
Test name
Test status
Simulation time	3746833191 ps
CPU time	195.55 seconds
Started	Sep 11 09:38:28 AM UTC 24
Finished	Sep 11 09:41:47 AM UTC 24
Peak memory	213952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244833544 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.4244833544
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.340102252
Short name	T752
Test name
Test status
Simulation time	71486365 ps
CPU time	9.53 seconds
Started	Sep 11 09:39:00 AM UTC 24
Finished	Sep 11 09:39:11 AM UTC 24
Peak memory	247652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 340102252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_th roughput_w_partial_write.340102252
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2308080162
Short name	T816
Test name
Test status
Simulation time	1543753707 ps
CPU time	256.22 seconds
Started	Sep 11 09:41:02 AM UTC 24
Finished	Sep 11 09:45:22 AM UTC 24
Peak memory	376672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308080162 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during _key_req.2308080162
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.533802405
Short name	T778
Test name
Test status
Simulation time	14107087 ps
CPU time	0.84 seconds
Started	Sep 11 09:41:41 AM UTC 24
Finished	Sep 11 09:41:43 AM UTC 24
Peak memory	212632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533802405 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.533802405
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1453016500
Short name	T767
Test name
Test status
Simulation time	21825461872 ps
CPU time	45.48 seconds
Started	Sep 11 09:40:06 AM UTC 24
Finished	Sep 11 09:40:53 AM UTC 24
Peak memory	213896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453016500 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.1453016500
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.486565761
Short name	T842
Test name
Test status
Simulation time	30499888996 ps
CPU time	366.16 seconds
Started	Sep 11 09:41:07 AM UTC 24
Finished	Sep 11 09:47:18 AM UTC 24
Peak memory	325464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486565761 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.486565761
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.599905461
Short name	T771
Test name
Test status
Simulation time	794935444 ps
CPU time	11.48 seconds
Started	Sep 11 09:40:58 AM UTC 24
Finished	Sep 11 09:41:11 AM UTC 24
Peak memory	213792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599905461 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.599905461
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3915374880
Short name	T788
Test name
Test status
Simulation time	143837375 ps
CPU time	81.38 seconds
Started	Sep 11 09:40:41 AM UTC 24
Finished	Sep 11 09:42:04 AM UTC 24
Peak memory	380780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 915374880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ma x_throughput.3915374880
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.4280419646
Short name	T775
Test name
Test status
Simulation time	159448728 ps
CPU time	3.49 seconds
Started	Sep 11 09:41:26 AM UTC 24
Finished	Sep 11 09:41:30 AM UTC 24
Peak memory	224024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280419646 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.4280419646
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1558905603
Short name	T774
Test name
Test status
Simulation time	665774123 ps
CPU time	7.7 seconds
Started	Sep 11 09:41:16 AM UTC 24
Finished	Sep 11 09:41:24 AM UTC 24
Peak memory	224132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558905603 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.1558905603
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.935850405
Short name	T888
Test name
Test status
Simulation time	24635902816 ps
CPU time	819.31 seconds
Started	Sep 11 09:40:03 AM UTC 24
Finished	Sep 11 09:53:52 AM UTC 24
Peak memory	376876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935850405 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.935850405
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3943610760
Short name	T765
Test name
Test status
Simulation time	527038158 ps
CPU time	13 seconds
Started	Sep 11 09:40:15 AM UTC 24
Finished	Sep 11 09:40:30 AM UTC 24
Peak memory	213820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943610760 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.3943610760
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.474206489
Short name	T819
Test name
Test status
Simulation time	47266105909 ps
CPU time	307.31 seconds
Started	Sep 11 09:40:31 AM UTC 24
Finished	Sep 11 09:45:42 AM UTC 24
Peak memory	213960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474206489 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acce ss_b2b.474206489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.2374957951
Short name	T773
Test name
Test status
Simulation time	80592652 ps
CPU time	1.17 seconds
Started	Sep 11 09:41:12 AM UTC 24
Finished	Sep 11 09:41:15 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374957951 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2374957951
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.3963286152
Short name	T823
Test name
Test status
Simulation time	5175755371 ps
CPU time	293.26 seconds
Started	Sep 11 09:41:11 AM UTC 24
Finished	Sep 11 09:46:09 AM UTC 24
Peak memory	370604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963286152 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3963286152
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.3851138661
Short name	T762
Test name
Test status
Simulation time	63924970 ps
CPU time	2.56 seconds
Started	Sep 11 09:40:02 AM UTC 24
Finished	Sep 11 09:40:06 AM UTC 24
Peak memory	220588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851138661 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3851138661
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1747263982
Short name	T911
Test name
Test status
Simulation time	10248553819 ps
CPU time	1166.1 seconds
Started	Sep 11 09:41:34 AM UTC 24
Finished	Sep 11 10:01:14 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174726398 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.1747263982
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.3310583689
Short name	T812
Test name
Test status
Simulation time	3047644004 ps
CPU time	277.01 seconds
Started	Sep 11 09:40:08 AM UTC 24
Finished	Sep 11 09:44:49 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310583689 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.3310583689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.899217219
Short name	T784
Test name
Test status
Simulation time	285271774 ps
CPU time	62.77 seconds
Started	Sep 11 09:40:54 AM UTC 24
Finished	Sep 11 09:41:58 AM UTC 24
Peak memory	356196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 899217219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_th roughput_w_partial_write.899217219
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3373694750
Short name	T903
Test name
Test status
Simulation time	11053455727 ps
CPU time	946.87 seconds
Started	Sep 11 09:42:03 AM UTC 24
Finished	Sep 11 09:58:00 AM UTC 24
Peak memory	382876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373694750 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during _key_req.3373694750
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1386514550
Short name	T796
Test name
Test status
Simulation time	15241928 ps
CPU time	0.96 seconds
Started	Sep 11 09:42:30 AM UTC 24
Finished	Sep 11 09:42:32 AM UTC 24
Peak memory	212612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386514550 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1386514550
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3344998234
Short name	T789
Test name
Test status
Simulation time	256358985 ps
CPU time	14.94 seconds
Started	Sep 11 09:41:48 AM UTC 24
Finished	Sep 11 09:42:04 AM UTC 24
Peak memory	213916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344998234 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.3344998234
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3153328346
Short name	T882
Test name
Test status
Simulation time	63195913938 ps
CPU time	616.11 seconds
Started	Sep 11 09:42:05 AM UTC 24
Finished	Sep 11 09:52:29 AM UTC 24
Peak memory	376744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153328346 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3153328346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2874423004
Short name	T791
Test name
Test status
Simulation time	555375928 ps
CPU time	10.15 seconds
Started	Sep 11 09:42:02 AM UTC 24
Finished	Sep 11 09:42:13 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874423004 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.2874423004
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2062431792
Short name	T794
Test name
Test status
Simulation time	167432418 ps
CPU time	25.38 seconds
Started	Sep 11 09:42:00 AM UTC 24
Finished	Sep 11 09:42:26 AM UTC 24
Peak memory	300652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 062431792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ma x_throughput.2062431792
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.185336840
Short name	T793
Test name
Test status
Simulation time	220780689 ps
CPU time	2.99 seconds
Started	Sep 11 09:42:17 AM UTC 24
Finished	Sep 11 09:42:22 AM UTC 24
Peak memory	224352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185336840 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.185336840
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.3939102174
Short name	T795
Test name
Test status
Simulation time	307174770 ps
CPU time	12.67 seconds
Started	Sep 11 09:42:14 AM UTC 24
Finished	Sep 11 09:42:29 AM UTC 24
Peak memory	223996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939102174 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.3939102174
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1424530496
Short name	T850
Test name
Test status
Simulation time	12638420036 ps
CPU time	367.03 seconds
Started	Sep 11 09:41:44 AM UTC 24
Finished	Sep 11 09:47:56 AM UTC 24
Peak memory	385192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424530496 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.1424530496
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1471956784
Short name	T786
Test name
Test status
Simulation time	193765577 ps
CPU time	6.94 seconds
Started	Sep 11 09:41:52 AM UTC 24
Finished	Sep 11 09:42:01 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471956784 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.1471956784
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2695370275
Short name	T879
Test name
Test status
Simulation time	83436517470 ps
CPU time	605.82 seconds
Started	Sep 11 09:41:53 AM UTC 24
Finished	Sep 11 09:52:06 AM UTC 24
Peak memory	214112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695370275 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acc ess_b2b.2695370275
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2553068788
Short name	T792
Test name
Test status
Simulation time	86971810 ps
CPU time	1.07 seconds
Started	Sep 11 09:42:13 AM UTC 24
Finished	Sep 11 09:42:16 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553068788 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2553068788
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.947297328
Short name	T837
Test name
Test status
Simulation time	3183314478 ps
CPU time	296.54 seconds
Started	Sep 11 09:42:05 AM UTC 24
Finished	Sep 11 09:47:06 AM UTC 24
Peak memory	358576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947297328 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.947297328
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3040637175
Short name	T783
Test name
Test status
Simulation time	136811948 ps
CPU time	6.1 seconds
Started	Sep 11 09:41:44 AM UTC 24
Finished	Sep 11 09:41:51 AM UTC 24
Peak memory	213920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040637175 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3040637175
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.90039089
Short name	T926
Test name
Test status
Simulation time	52005871376 ps
CPU time	4045.09 seconds
Started	Sep 11 09:42:27 AM UTC 24
Finished	Sep 11 10:50:37 AM UTC 24
Peak memory	389028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90039089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.90039089
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3352351520
Short name	T107
Test name
Test status
Simulation time	2553256258 ps
CPU time	100.93 seconds
Started	Sep 11 09:42:23 AM UTC 24
Finished	Sep 11 09:44:06 AM UTC 24
Peak memory	339876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352351520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3352351520
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1463922270
Short name	T824
Test name
Test status
Simulation time	2419001191 ps
CPU time	254.99 seconds
Started	Sep 11 09:41:50 AM UTC 24
Finished	Sep 11 09:46:09 AM UTC 24
Peak memory	213888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463922270 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1463922270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3005624528
Short name	T797
Test name
Test status
Simulation time	202513427 ps
CPU time	31.38 seconds
Started	Sep 11 09:42:00 AM UTC 24
Finished	Sep 11 09:42:32 AM UTC 24
Peak memory	313308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3005624528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t hroughput_w_partial_write.3005624528
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.2880489870
Short name	T818
Test name
Test status
Simulation time	1757023375 ps
CPU time	91.34 seconds
Started	Sep 11 09:44:00 AM UTC 24
Finished	Sep 11 09:45:33 AM UTC 24
Peak memory	342176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880489870 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during _key_req.2880489870
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2276090734
Short name	T814
Test name
Test status
Simulation time	46735931 ps
CPU time	1.04 seconds
Started	Sep 11 09:44:50 AM UTC 24
Finished	Sep 11 09:44:52 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276090734 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2276090734
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.2999279181
Short name	T807
Test name
Test status
Simulation time	4414052526 ps
CPU time	89.98 seconds
Started	Sep 11 09:42:56 AM UTC 24
Finished	Sep 11 09:44:28 AM UTC 24
Peak memory	213872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999279181 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.2999279181
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1872126817
Short name	T878
Test name
Test status
Simulation time	21148335588 ps
CPU time	468.66 seconds
Started	Sep 11 09:44:06 AM UTC 24
Finished	Sep 11 09:52:01 AM UTC 24
Peak memory	384880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872126817 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.1872126817
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.346700109
Short name	T804
Test name
Test status
Simulation time	87696391 ps
CPU time	1.77 seconds
Started	Sep 11 09:43:56 AM UTC 24
Finished	Sep 11 09:43:59 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346700109 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.346700109
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3414917911
Short name	T806
Test name
Test status
Simulation time	381166168 ps
CPU time	30.8 seconds
Started	Sep 11 09:43:36 AM UTC 24
Finished	Sep 11 09:44:08 AM UTC 24
Peak memory	319336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 414917911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ma x_throughput.3414917911
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1724475309
Short name	T810
Test name
Test status
Simulation time	65143991 ps
CPU time	7.59 seconds
Started	Sep 11 09:44:33 AM UTC 24
Finished	Sep 11 09:44:41 AM UTC 24
Peak memory	224032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724475309 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.1724475309
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3699348178
Short name	T811
Test name
Test status
Simulation time	475112630 ps
CPU time	15.71 seconds
Started	Sep 11 09:44:30 AM UTC 24
Finished	Sep 11 09:44:47 AM UTC 24
Peak memory	224180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699348178 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.3699348178
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1552334462
Short name	T894
Test name
Test status
Simulation time	14869471252 ps
CPU time	788.43 seconds
Started	Sep 11 09:42:33 AM UTC 24
Finished	Sep 11 09:55:51 AM UTC 24
Peak memory	380764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552334462 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.1552334462
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3279689375
Short name	T813
Test name
Test status
Simulation time	1888796117 ps
CPU time	74.5 seconds
Started	Sep 11 09:43:34 AM UTC 24
Finished	Sep 11 09:44:50 AM UTC 24
Peak memory	358184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279689375 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.3279689375
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2659215463
Short name	T885
Test name
Test status
Simulation time	22302298262 ps
CPU time	591.99 seconds
Started	Sep 11 09:43:36 AM UTC 24
Finished	Sep 11 09:53:35 AM UTC 24
Peak memory	213864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659215463 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc ess_b2b.2659215463
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.125799454
Short name	T809
Test name
Test status
Simulation time	81231450 ps
CPU time	1.11 seconds
Started	Sep 11 09:44:29 AM UTC 24
Finished	Sep 11 09:44:32 AM UTC 24
Peak memory	212408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125799454 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.125799454
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2784278466
Short name	T900
Test name
Test status
Simulation time	47532664029 ps
CPU time	780.23 seconds
Started	Sep 11 09:44:08 AM UTC 24
Finished	Sep 11 09:57:19 AM UTC 24
Peak memory	362416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784278466 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2784278466
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.1582594513
Short name	T799
Test name
Test status
Simulation time	139410100 ps
CPU time	28.93 seconds
Started	Sep 11 09:42:33 AM UTC 24
Finished	Sep 11 09:43:04 AM UTC 24
Peak memory	292716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582594513 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1582594513
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2669561062
Short name	T897
Test name
Test status
Simulation time	14839136563 ps
CPU time	712.06 seconds
Started	Sep 11 09:44:48 AM UTC 24
Finished	Sep 11 09:56:48 AM UTC 24
Peak memory	383212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266956106 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.2669561062
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3327313335
Short name	T822
Test name
Test status
Simulation time	1669726428 ps
CPU time	84.32 seconds
Started	Sep 11 09:44:42 AM UTC 24
Finished	Sep 11 09:46:08 AM UTC 24
Peak memory	288900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327313335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3327313335
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2831044319
Short name	T853
Test name
Test status
Simulation time	9416888523 ps
CPU time	311.04 seconds
Started	Sep 11 09:43:04 AM UTC 24
Finished	Sep 11 09:48:20 AM UTC 24
Peak memory	213892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831044319 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.2831044319
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1818376920
Short name	T803
Test name
Test status
Simulation time	132080442 ps
CPU time	11.3 seconds
Started	Sep 11 09:43:43 AM UTC 24
Finished	Sep 11 09:43:55 AM UTC 24
Peak memory	253792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1818376920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t hroughput_w_partial_write.1818376920
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3389387633
Short name	T899
Test name
Test status
Simulation time	5703212200 ps
CPU time	635.81 seconds
Started	Sep 11 09:46:09 AM UTC 24
Finished	Sep 11 09:56:53 AM UTC 24
Peak memory	384856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389387633 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during _key_req.3389387633
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2030687818
Short name	T831
Test name
Test status
Simulation time	30836583 ps
CPU time	1 seconds
Started	Sep 11 09:46:33 AM UTC 24
Finished	Sep 11 09:46:35 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030687818 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2030687818
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.4085187490
Short name	T829
Test name
Test status
Simulation time	1532804382 ps
CPU time	70.13 seconds
Started	Sep 11 09:45:20 AM UTC 24
Finished	Sep 11 09:46:32 AM UTC 24
Peak memory	213716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085187490 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.4085187490
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.879297732
Short name	T872
Test name
Test status
Simulation time	16650662930 ps
CPU time	232.37 seconds
Started	Sep 11 09:46:09 AM UTC 24
Finished	Sep 11 09:50:05 AM UTC 24
Peak memory	337832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879297732 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.879297732
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.915813490
Short name	T825
Test name
Test status
Simulation time	998191507 ps
CPU time	5.48 seconds
Started	Sep 11 09:46:03 AM UTC 24
Finished	Sep 11 09:46:10 AM UTC 24
Peak memory	226156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915813490 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.915813490
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1078788965
Short name	T828
Test name
Test status
Simulation time	198285637 ps
CPU time	47.83 seconds
Started	Sep 11 09:45:43 AM UTC 24
Finished	Sep 11 09:46:32 AM UTC 24
Peak memory	323432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 078788965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ma x_throughput.1078788965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2130271672
Short name	T83
Test name
Test status
Simulation time	219795068 ps
CPU time	7.57 seconds
Started	Sep 11 09:46:23 AM UTC 24
Finished	Sep 11 09:46:32 AM UTC 24
Peak memory	224080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130271672 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.2130271672
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2090526353
Short name	T827
Test name
Test status
Simulation time	189331376 ps
CPU time	7.15 seconds
Started	Sep 11 09:46:14 AM UTC 24
Finished	Sep 11 09:46:22 AM UTC 24
Peak memory	224396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090526353 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.2090526353
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.4202034858
Short name	T905
Test name
Test status
Simulation time	14864853163 ps
CPU time	795.58 seconds
Started	Sep 11 09:44:53 AM UTC 24
Finished	Sep 11 09:58:18 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202034858 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.4202034858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3873041526
Short name	T821
Test name
Test status
Simulation time	610709627 ps
CPU time	31.1 seconds
Started	Sep 11 09:45:30 AM UTC 24
Finished	Sep 11 09:46:02 AM UTC 24
Peak memory	313200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873041526 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.3873041526
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1702585054
Short name	T889
Test name
Test status
Simulation time	89163312729 ps
CPU time	519.07 seconds
Started	Sep 11 09:45:34 AM UTC 24
Finished	Sep 11 09:54:19 AM UTC 24
Peak memory	213928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702585054 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc ess_b2b.1702585054
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.155951205
Short name	T826
Test name
Test status
Simulation time	89187671 ps
CPU time	1.18 seconds
Started	Sep 11 09:46:11 AM UTC 24
Finished	Sep 11 09:46:13 AM UTC 24
Peak memory	212624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155951205 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.155951205
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2922646027
Short name	T909
Test name
Test status
Simulation time	2104111402 ps
CPU time	757.68 seconds
Started	Sep 11 09:46:10 AM UTC 24
Finished	Sep 11 09:58:58 AM UTC 24
Peak memory	364400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922646027 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2922646027
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.1055283186
Short name	T815
Test name
Test status
Simulation time	1887736787 ps
CPU time	26.69 seconds
Started	Sep 11 09:44:51 AM UTC 24
Finished	Sep 11 09:45:19 AM UTC 24
Peak memory	290588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055283186 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1055283186
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2112732077
Short name	T898
Test name
Test status
Simulation time	16472958426 ps
CPU time	608.23 seconds
Started	Sep 11 09:46:33 AM UTC 24
Finished	Sep 11 09:56:48 AM UTC 24
Peak memory	378792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211273207 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.2112732077
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3220659091
Short name	T839
Test name
Test status
Simulation time	985934437 ps
CPU time	33.61 seconds
Started	Sep 11 09:46:33 AM UTC 24
Finished	Sep 11 09:47:08 AM UTC 24
Peak memory	224128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220659091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3220659091
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1932951877
Short name	T874
Test name
Test status
Simulation time	27907118192 ps
CPU time	307.27 seconds
Started	Sep 11 09:45:23 AM UTC 24
Finished	Sep 11 09:50:34 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932951877 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.1932951877
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2158885216
Short name	T830
Test name
Test status
Simulation time	237441708 ps
CPU time	34.55 seconds
Started	Sep 11 09:45:57 AM UTC 24
Finished	Sep 11 09:46:33 AM UTC 24
Peak memory	333920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2158885216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t hroughput_w_partial_write.2158885216
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1987712024
Short name	T896
Test name
Test status
Simulation time	2091395698 ps
CPU time	537.29 seconds
Started	Sep 11 09:47:09 AM UTC 24
Finished	Sep 11 09:56:13 AM UTC 24
Peak memory	384872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987712024 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during _key_req.1987712024
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3476397079
Short name	T849
Test name
Test status
Simulation time	17131075 ps
CPU time	0.97 seconds
Started	Sep 11 09:47:40 AM UTC 24
Finished	Sep 11 09:47:42 AM UTC 24
Peak memory	212552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476397079 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3476397079
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1242038692
Short name	T836
Test name
Test status
Simulation time	329325500 ps
CPU time	18.87 seconds
Started	Sep 11 09:46:37 AM UTC 24
Finished	Sep 11 09:46:58 AM UTC 24
Peak memory	213836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242038692 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1242038692
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.3161289320
Short name	T908
Test name
Test status
Simulation time	34119806064 ps
CPU time	693.88 seconds
Started	Sep 11 09:47:10 AM UTC 24
Finished	Sep 11 09:58:53 AM UTC 24
Peak memory	380768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161289320 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.3161289320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.884741834
Short name	T843
Test name
Test status
Simulation time	378573898 ps
CPU time	9.17 seconds
Started	Sep 11 09:47:09 AM UTC 24
Finished	Sep 11 09:47:19 AM UTC 24
Peak memory	213768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884741834 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.884741834
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2492269365
Short name	T838
Test name
Test status
Simulation time	63038869 ps
CPU time	7.95 seconds
Started	Sep 11 09:46:59 AM UTC 24
Finished	Sep 11 09:47:08 AM UTC 24
Peak memory	247660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 492269365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ma x_throughput.2492269365
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2525102157
Short name	T846
Test name
Test status
Simulation time	848033948 ps
CPU time	6.47 seconds
Started	Sep 11 09:47:23 AM UTC 24
Finished	Sep 11 09:47:30 AM UTC 24
Peak memory	223952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525102157 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2525102157
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3549746973
Short name	T845
Test name
Test status
Simulation time	234923877 ps
CPU time	7.37 seconds
Started	Sep 11 09:47:21 AM UTC 24
Finished	Sep 11 09:47:29 AM UTC 24
Peak memory	223996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549746973 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.3549746973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.4050520177
Short name	T914
Test name
Test status
Simulation time	24110474262 ps
CPU time	1108 seconds
Started	Sep 11 09:46:36 AM UTC 24
Finished	Sep 11 10:05:17 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050520177 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.4050520177
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1409194355
Short name	T847
Test name
Test status
Simulation time	423282457 ps
CPU time	51.43 seconds
Started	Sep 11 09:46:46 AM UTC 24
Finished	Sep 11 09:47:39 AM UTC 24
Peak memory	311076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409194355 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.1409194355
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2489509482
Short name	T875
Test name
Test status
Simulation time	35371230584 ps
CPU time	258.69 seconds
Started	Sep 11 09:46:53 AM UTC 24
Finished	Sep 11 09:51:15 AM UTC 24
Peak memory	214216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489509482 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc ess_b2b.2489509482
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.372289167
Short name	T844
Test name
Test status
Simulation time	136512356 ps
CPU time	1.15 seconds
Started	Sep 11 09:47:19 AM UTC 24
Finished	Sep 11 09:47:22 AM UTC 24
Peak memory	212564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372289167 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.372289167
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.1814855123
Short name	T912
Test name
Test status
Simulation time	5882687685 ps
CPU time	868.55 seconds
Started	Sep 11 09:47:13 AM UTC 24
Finished	Sep 11 10:01:52 AM UTC 24
Peak memory	386872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814855123 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1814855123
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.325008277
Short name	T833
Test name
Test status
Simulation time	190539432 ps
CPU time	5.7 seconds
Started	Sep 11 09:46:34 AM UTC 24
Finished	Sep 11 09:46:41 AM UTC 24
Peak memory	233484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325008277 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.325008277
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.947068204
Short name	T925
Test name
Test status
Simulation time	110514338639 ps
CPU time	2132.84 seconds
Started	Sep 11 09:47:31 AM UTC 24
Finished	Sep 11 10:23:28 AM UTC 24
Peak memory	386888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947068204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.947068204
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1575416687
Short name	T869
Test name
Test status
Simulation time	11556818008 ps
CPU time	175.51 seconds
Started	Sep 11 09:46:43 AM UTC 24
Finished	Sep 11 09:49:41 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575416687 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.1575416687
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.304963755
Short name	T861
Test name
Test status
Simulation time	154015911 ps
CPU time	94.92 seconds
Started	Sep 11 09:47:07 AM UTC 24
Finished	Sep 11 09:48:44 AM UTC 24
Peak memory	380772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 304963755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_th roughput_w_partial_write.304963755
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3960704988
Short name	T892
Test name
Test status
Simulation time	5322676431 ps
CPU time	408.47 seconds
Started	Sep 11 09:48:32 AM UTC 24
Finished	Sep 11 09:55:26 AM UTC 24
Peak memory	378992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960704988 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during _key_req.3960704988
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2638420003
Short name	T866
Test name
Test status
Simulation time	23431138 ps
CPU time	1.01 seconds
Started	Sep 11 09:48:53 AM UTC 24
Finished	Sep 11 09:48:55 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638420003 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2638420003
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2946868
Short name	T864
Test name
Test status
Simulation time	815281096 ps
CPU time	49.62 seconds
Started	Sep 11 09:47:56 AM UTC 24
Finished	Sep 11 09:48:48 AM UTC 24
Peak memory	213916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946868 -assert nopostproc +UVM_TESTNA ME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2946868
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.3767628002
Short name	T887
Test name
Test status
Simulation time	3118613103 ps
CPU time	309.96 seconds
Started	Sep 11 09:48:37 AM UTC 24
Finished	Sep 11 09:53:51 AM UTC 24
Peak memory	374636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767628002 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.3767628002
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1500405319
Short name	T860
Test name
Test status
Simulation time	2604269892 ps
CPU time	10.1 seconds
Started	Sep 11 09:48:30 AM UTC 24
Finished	Sep 11 09:48:41 AM UTC 24
Peak memory	224052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500405319 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.1500405319
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2449519141
Short name	T871
Test name
Test status
Simulation time	521220759 ps
CPU time	91.7 seconds
Started	Sep 11 09:48:26 AM UTC 24
Finished	Sep 11 09:49:59 AM UTC 24
Peak memory	381096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 449519141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma x_throughput.2449519141
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3598004926
Short name	T865
Test name
Test status
Simulation time	345599964 ps
CPU time	5.32 seconds
Started	Sep 11 09:48:46 AM UTC 24
Finished	Sep 11 09:48:52 AM UTC 24
Peak memory	224000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598004926 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.3598004926
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3346264338
Short name	T867
Test name
Test status
Simulation time	3154872093 ps
CPU time	14.3 seconds
Started	Sep 11 09:48:44 AM UTC 24
Finished	Sep 11 09:49:00 AM UTC 24
Peak memory	224196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346264338 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.3346264338
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.426420060
Short name	T901
Test name
Test status
Simulation time	67354386025 ps
CPU time	571.2 seconds
Started	Sep 11 09:47:43 AM UTC 24
Finished	Sep 11 09:57:22 AM UTC 24
Peak memory	385208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426420060 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.426420060
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.778592571
Short name	T854
Test name
Test status
Simulation time	91714666 ps
CPU time	13.66 seconds
Started	Sep 11 09:48:11 AM UTC 24
Finished	Sep 11 09:48:25 AM UTC 24
Peak memory	257820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778592571 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.778592571
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.4235094488
Short name	T891
Test name
Test status
Simulation time	9335663785 ps
CPU time	405.48 seconds
Started	Sep 11 09:48:21 AM UTC 24
Finished	Sep 11 09:55:12 AM UTC 24
Peak memory	214168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235094488 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc ess_b2b.4235094488
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1669364312
Short name	T862
Test name
Test status
Simulation time	126007015 ps
CPU time	1.27 seconds
Started	Sep 11 09:48:42 AM UTC 24
Finished	Sep 11 09:48:45 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669364312 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1669364312
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.2906438165
Short name	T877
Test name
Test status
Simulation time	6636196690 ps
CPU time	187.79 seconds
Started	Sep 11 09:48:40 AM UTC 24
Finished	Sep 11 09:51:51 AM UTC 24
Peak memory	343856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906438165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2906438165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.3764385954
Short name	T863
Test name
Test status
Simulation time	631266335 ps
CPU time	64.13 seconds
Started	Sep 11 09:47:40 AM UTC 24
Finished	Sep 11 09:48:46 AM UTC 24
Peak memory	356128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764385954 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3764385954
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3746567866
Short name	T921
Test name
Test status
Simulation time	24518375875 ps
CPU time	1752.25 seconds
Started	Sep 11 09:48:49 AM UTC 24
Finished	Sep 11 10:18:22 AM UTC 24
Peak memory	389288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374656786 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.3746567866
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1496046561
Short name	T868
Test name
Test status
Simulation time	161186674 ps
CPU time	13.77 seconds
Started	Sep 11 09:48:47 AM UTC 24
Finished	Sep 11 09:49:02 AM UTC 24
Peak memory	224112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496046561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1496046561
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3354127300
Short name	T893
Test name
Test status
Simulation time	3691902429 ps
CPU time	452.43 seconds
Started	Sep 11 09:48:06 AM UTC 24
Finished	Sep 11 09:55:45 AM UTC 24
Peak memory	214120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354127300 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.3354127300
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1195974322
Short name	T857
Test name
Test status
Simulation time	177887019 ps
CPU time	4.8 seconds
Started	Sep 11 09:48:26 AM UTC 24
Finished	Sep 11 09:48:32 AM UTC 24
Peak memory	231180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1195974322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t hroughput_w_partial_write.1195974322
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1935680728
Short name	T36
Test name
Test status
Simulation time	5462239987 ps
CPU time	541.46 seconds
Started	Sep 11 08:41:04 AM UTC 24
Finished	Sep 11 08:50:16 AM UTC 24
Peak memory	370912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935680728 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_ key_req.1935680728
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3534323500
Short name	T161
Test name
Test status
Simulation time	19574937 ps
CPU time	0.99 seconds
Started	Sep 11 08:41:18 AM UTC 24
Finished	Sep 11 08:41:20 AM UTC 24
Peak memory	212544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534323500 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3534323500
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2263806393
Short name	T162
Test name
Test status
Simulation time	3523100549 ps
CPU time	62.54 seconds
Started	Sep 11 08:40:56 AM UTC 24
Finished	Sep 11 08:42:07 AM UTC 24
Peak memory	213900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263806393 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2263806393
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3509836834
Short name	T159
Test name
Test status
Simulation time	279304157 ps
CPU time	5.06 seconds
Started	Sep 11 08:41:03 AM UTC 24
Finished	Sep 11 08:41:20 AM UTC 24
Peak memory	213872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509836834 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.3509836834
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.4242574742
Short name	T173
Test name
Test status
Simulation time	360065726 ps
CPU time	31.62 seconds
Started	Sep 11 08:41:00 AM UTC 24
Finished	Sep 11 08:41:47 AM UTC 24
Peak memory	304940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 242574742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max _throughput.4242574742
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.3304858950
Short name	T43
Test name
Test status
Simulation time	94808839 ps
CPU time	7.53 seconds
Started	Sep 11 08:41:11 AM UTC 24
Finished	Sep 11 08:41:23 AM UTC 24
Peak memory	224008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304858950 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.3304858950
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.494102814
Short name	T44
Test name
Test status
Simulation time	686647120 ps
CPU time	16.13 seconds
Started	Sep 11 08:41:08 AM UTC 24
Finished	Sep 11 08:41:33 AM UTC 24
Peak memory	224008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494102814 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.494102814
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2378020814
Short name	T394
Test name
Test status
Simulation time	43376937866 ps
CPU time	1413.98 seconds
Started	Sep 11 08:40:56 AM UTC 24
Finished	Sep 11 09:04:52 AM UTC 24
Peak memory	382668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378020814 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.2378020814
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1328008915
Short name	T113
Test name
Test status
Simulation time	803859964 ps
CPU time	16.28 seconds
Started	Sep 11 08:40:59 AM UTC 24
Finished	Sep 11 08:41:20 AM UTC 24
Peak memory	276592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328008915 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.1328008915
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.88498296
Short name	T193
Test name
Test status
Simulation time	3766842001 ps
CPU time	263.01 seconds
Started	Sep 11 08:40:59 AM UTC 24
Finished	Sep 11 08:45:29 AM UTC 24
Peak memory	213940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88498296 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access _b2b.88498296
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.217604351
Short name	T110
Test name
Test status
Simulation time	27156672 ps
CPU time	1.12 seconds
Started	Sep 11 08:41:07 AM UTC 24
Finished	Sep 11 08:41:10 AM UTC 24
Peak memory	212564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217604351 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.217604351
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.4238662786
Short name	T168
Test name
Test status
Simulation time	644040710 ps
CPU time	14.03 seconds
Started	Sep 11 08:40:55 AM UTC 24
Finished	Sep 11 08:41:31 AM UTC 24
Peak memory	213720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238662786 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4238662786
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.295566323
Short name	T599
Test name
Test status
Simulation time	107273592333 ps
CPU time	2457.59 seconds
Started	Sep 11 08:41:14 AM UTC 24
Finished	Sep 11 09:22:37 AM UTC 24
Peak memory	386992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295566323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.295566323
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3527649324
Short name	T47
Test name
Test status
Simulation time	4081506588 ps
CPU time	227.73 seconds
Started	Sep 11 08:41:13 AM UTC 24
Finished	Sep 11 08:45:04 AM UTC 24
Peak memory	393188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527649324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3527649324
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3581645489
Short name	T217
Test name
Test status
Simulation time	3333376571 ps
CPU time	376.95 seconds
Started	Sep 11 08:40:57 AM UTC 24
Finished	Sep 11 08:47:38 AM UTC 24
Peak memory	214160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581645489 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.3581645489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1399338146
Short name	T149
Test name
Test status
Simulation time	151542407 ps
CPU time	44 seconds
Started	Sep 11 08:41:01 AM UTC 24
Finished	Sep 11 08:41:48 AM UTC 24
Peak memory	321308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1399338146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th roughput_w_partial_write.1399338146
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2883910488
Short name	T290
Test name
Test status
Simulation time	2728782365 ps
CPU time	810.94 seconds
Started	Sep 11 08:41:32 AM UTC 24
Finished	Sep 11 08:55:12 AM UTC 24
Peak memory	386900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883910488 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_ key_req.2883910488
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.4026670397
Short name	T164
Test name
Test status
Simulation time	59008520 ps
CPU time	0.93 seconds
Started	Sep 11 08:41:48 AM UTC 24
Finished	Sep 11 08:41:50 AM UTC 24
Peak memory	212628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026670397 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.4026670397
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1345854612
Short name	T176
Test name
Test status
Simulation time	1454682372 ps
CPU time	46.57 seconds
Started	Sep 11 08:41:20 AM UTC 24
Finished	Sep 11 08:42:08 AM UTC 24
Peak memory	213920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345854612 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.1345854612
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.443829555
Short name	T135
Test name
Test status
Simulation time	4599841770 ps
CPU time	251.14 seconds
Started	Sep 11 08:41:33 AM UTC 24
Finished	Sep 11 08:45:48 AM UTC 24
Peak memory	381092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443829555 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.443829555
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2405524408
Short name	T118
Test name
Test status
Simulation time	606047025 ps
CPU time	6.71 seconds
Started	Sep 11 08:41:32 AM UTC 24
Finished	Sep 11 08:41:40 AM UTC 24
Peak memory	224048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405524408 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2405524408
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.515333257
Short name	T169
Test name
Test status
Simulation time	112686283 ps
CPU time	10.19 seconds
Started	Sep 11 08:41:25 AM UTC 24
Finished	Sep 11 08:41:36 AM UTC 24
Peak memory	249712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 15333257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_ throughput.515333257
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3515159739
Short name	T80
Test name
Test status
Simulation time	64714981 ps
CPU time	6.32 seconds
Started	Sep 11 08:41:44 AM UTC 24
Finished	Sep 11 08:41:52 AM UTC 24
Peak memory	223964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515159739 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.3515159739
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3316819027
Short name	T175
Test name
Test status
Simulation time	268575839 ps
CPU time	11.79 seconds
Started	Sep 11 08:41:41 AM UTC 24
Finished	Sep 11 08:41:54 AM UTC 24
Peak memory	223984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316819027 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.3316819027
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.624704159
Short name	T154
Test name
Test status
Simulation time	42783504795 ps
CPU time	471.39 seconds
Started	Sep 11 08:41:20 AM UTC 24
Finished	Sep 11 08:49:17 AM UTC 24
Peak memory	366452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624704159 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.624704159
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1238245065
Short name	T174
Test name
Test status
Simulation time	1288169542 ps
CPU time	24.8 seconds
Started	Sep 11 08:41:22 AM UTC 24
Finished	Sep 11 08:41:48 AM UTC 24
Peak memory	213848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238245065 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1238245065
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1233059468
Short name	T144
Test name
Test status
Simulation time	29330632979 ps
CPU time	286.19 seconds
Started	Sep 11 08:41:24 AM UTC 24
Finished	Sep 11 08:46:14 AM UTC 24
Peak memory	214140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233059468 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce ss_b2b.1233059468
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1456045234
Short name	T171
Test name
Test status
Simulation time	96161260 ps
CPU time	1.29 seconds
Started	Sep 11 08:41:41 AM UTC 24
Finished	Sep 11 08:41:44 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456045234 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1456045234
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.2027407234
Short name	T134
Test name
Test status
Simulation time	40141608774 ps
CPU time	538.57 seconds
Started	Sep 11 08:41:37 AM UTC 24
Finished	Sep 11 08:50:42 AM UTC 24
Peak memory	366472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027407234 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2027407234
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1401598634
Short name	T167
Test name
Test status
Simulation time	161318051 ps
CPU time	4.55 seconds
Started	Sep 11 08:41:18 AM UTC 24
Finished	Sep 11 08:41:24 AM UTC 24
Peak memory	213904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401598634 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1401598634
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2140476238
Short name	T307
Test name
Test status
Simulation time	9151947868 ps
CPU time	860.53 seconds
Started	Sep 11 08:41:47 AM UTC 24
Finished	Sep 11 08:56:18 AM UTC 24
Peak memory	384940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214047623 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.2140476238
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2777225233
Short name	T60
Test name
Test status
Simulation time	3959249455 ps
CPU time	438.55 seconds
Started	Sep 11 08:41:45 AM UTC 24
Finished	Sep 11 08:49:08 AM UTC 24
Peak memory	395496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777225233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2777225233
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3597725976
Short name	T95
Test name
Test status
Simulation time	2606781945 ps
CPU time	122.81 seconds
Started	Sep 11 08:41:20 AM UTC 24
Finished	Sep 11 08:43:25 AM UTC 24
Peak memory	214228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597725976 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.3597725976
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3322715160
Short name	T152
Test name
Test status
Simulation time	175991011 ps
CPU time	28.38 seconds
Started	Sep 11 08:41:28 AM UTC 24
Finished	Sep 11 08:41:58 AM UTC 24
Peak memory	296932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3322715160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th roughput_w_partial_write.3322715160
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.4264668365
Short name	T34
Test name
Test status
Simulation time	434028030 ps
CPU time	109.98 seconds
Started	Sep 11 08:42:10 AM UTC 24
Finished	Sep 11 08:44:02 AM UTC 24
Peak memory	337704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264668365 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_ key_req.4264668365
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1338620263
Short name	T180
Test name
Test status
Simulation time	11583226 ps
CPU time	0.93 seconds
Started	Sep 11 08:42:26 AM UTC 24
Finished	Sep 11 08:42:28 AM UTC 24
Peak memory	212628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338620263 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.1338620263
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2329476059
Short name	T163
Test name
Test status
Simulation time	3468853969 ps
CPU time	90.26 seconds
Started	Sep 11 08:41:51 AM UTC 24
Finished	Sep 11 08:43:23 AM UTC 24
Peak memory	213984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329476059 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.2329476059
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2998479240
Short name	T325
Test name
Test status
Simulation time	2594456277 ps
CPU time	935.32 seconds
Started	Sep 11 08:42:10 AM UTC 24
Finished	Sep 11 08:57:56 AM UTC 24
Peak memory	385192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998479240 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2998479240
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.277320143
Short name	T160
Test name
Test status
Simulation time	311882994 ps
CPU time	4.77 seconds
Started	Sep 11 08:42:09 AM UTC 24
Finished	Sep 11 08:42:15 AM UTC 24
Peak memory	214072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277320143 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.277320143
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1505183738
Short name	T178
Test name
Test status
Simulation time	66158754 ps
CPU time	10.05 seconds
Started	Sep 11 08:42:00 AM UTC 24
Finished	Sep 11 08:42:11 AM UTC 24
Peak memory	252064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 505183738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max _throughput.1505183738
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1163997893
Short name	T81
Test name
Test status
Simulation time	1024059912 ps
CPU time	7.62 seconds
Started	Sep 11 08:42:16 AM UTC 24
Finished	Sep 11 08:42:24 AM UTC 24
Peak memory	224088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163997893 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.1163997893
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.281697691
Short name	T45
Test name
Test status
Simulation time	95619695 ps
CPU time	7.4 seconds
Started	Sep 11 08:42:16 AM UTC 24
Finished	Sep 11 08:42:24 AM UTC 24
Peak memory	213816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281697691 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.281697691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2579955344
Short name	T222
Test name
Test status
Simulation time	2925174895 ps
CPU time	388.29 seconds
Started	Sep 11 08:41:49 AM UTC 24
Finished	Sep 11 08:48:22 AM UTC 24
Peak memory	387236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579955344 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.2579955344
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2795037840
Short name	T177
Test name
Test status
Simulation time	182377788 ps
CPU time	12.41 seconds
Started	Sep 11 08:41:55 AM UTC 24
Finished	Sep 11 08:42:09 AM UTC 24
Peak memory	213824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795037840 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.2795037840
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3481321974
Short name	T266
Test name
Test status
Simulation time	39519630395 ps
CPU time	631.93 seconds
Started	Sep 11 08:41:59 AM UTC 24
Finished	Sep 11 08:52:39 AM UTC 24
Peak memory	213852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481321974 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acce ss_b2b.3481321974
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2653854592
Short name	T179
Test name
Test status
Simulation time	27769487 ps
CPU time	1.28 seconds
Started	Sep 11 08:42:13 AM UTC 24
Finished	Sep 11 08:42:15 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653854592 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2653854592
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.767873637
Short name	T19
Test name
Test status
Simulation time	9491616599 ps
CPU time	597.65 seconds
Started	Sep 11 08:42:12 AM UTC 24
Finished	Sep 11 08:52:16 AM UTC 24
Peak memory	380780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767873637 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.767873637
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.880493059
Short name	T165
Test name
Test status
Simulation time	2867777270 ps
CPU time	122.1 seconds
Started	Sep 11 08:41:49 AM UTC 24
Finished	Sep 11 08:43:53 AM UTC 24
Peak memory	378992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880493059 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.880493059
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3187858356
Short name	T348
Test name
Test status
Simulation time	27101740481 ps
CPU time	1034.81 seconds
Started	Sep 11 08:42:25 AM UTC 24
Finished	Sep 11 08:59:52 AM UTC 24
Peak memory	354220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318785835 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.3187858356
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3630031385
Short name	T46
Test name
Test status
Simulation time	1129671634 ps
CPU time	142.91 seconds
Started	Sep 11 08:42:25 AM UTC 24
Finished	Sep 11 08:44:50 AM UTC 24
Peak memory	358240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630031385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3630031385
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.4172230487
Short name	T205
Test name
Test status
Simulation time	5442643676 ps
CPU time	298.45 seconds
Started	Sep 11 08:41:53 AM UTC 24
Finished	Sep 11 08:46:56 AM UTC 24
Peak memory	213796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172230487 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.4172230487
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1131790812
Short name	T183
Test name
Test status
Simulation time	533002450 ps
CPU time	95.37 seconds
Started	Sep 11 08:42:08 AM UTC 24
Finished	Sep 11 08:43:46 AM UTC 24
Peak memory	362276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1131790812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th roughput_w_partial_write.1131790812
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2376559382
Short name	T299
Test name
Test status
Simulation time	5988834376 ps
CPU time	703.74 seconds
Started	Sep 11 08:43:40 AM UTC 24
Finished	Sep 11 08:55:32 AM UTC 24
Peak memory	352096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376559382 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_ key_req.2376559382
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.132738935
Short name	T187
Test name
Test status
Simulation time	93029490 ps
CPU time	0.94 seconds
Started	Sep 11 08:44:08 AM UTC 24
Finished	Sep 11 08:44:10 AM UTC 24
Peak memory	212576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132738935 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.132738935
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2624792241
Short name	T185
Test name
Test status
Simulation time	3805174422 ps
CPU time	74.61 seconds
Started	Sep 11 08:42:43 AM UTC 24
Finished	Sep 11 08:44:00 AM UTC 24
Peak memory	213880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624792241 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.2624792241
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3552622164
Short name	T158
Test name
Test status
Simulation time	46484677676 ps
CPU time	514.76 seconds
Started	Sep 11 08:43:41 AM UTC 24
Finished	Sep 11 08:52:22 AM UTC 24
Peak memory	385180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552622164 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3552622164
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3400081579
Short name	T182
Test name
Test status
Simulation time	826411686 ps
CPU time	4.54 seconds
Started	Sep 11 08:43:34 AM UTC 24
Finished	Sep 11 08:43:40 AM UTC 24
Peak memory	213828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400081579 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.3400081579
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.125040994
Short name	T190
Test name
Test status
Simulation time	134104048 ps
CPU time	77.44 seconds
Started	Sep 11 08:43:24 AM UTC 24
Finished	Sep 11 08:44:43 AM UTC 24
Peak memory	380784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 25040994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max_ throughput.125040994
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.29346679
Short name	T82
Test name
Test status
Simulation time	88245265 ps
CPU time	4.26 seconds
Started	Sep 11 08:44:01 AM UTC 24
Finished	Sep 11 08:44:07 AM UTC 24
Peak memory	224444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29346679 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.29346679
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1589545535
Short name	T186
Test name
Test status
Simulation time	486065934 ps
CPU time	7.65 seconds
Started	Sep 11 08:43:57 AM UTC 24
Finished	Sep 11 08:44:06 AM UTC 24
Peak memory	224116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589545535 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.1589545535
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.319536098
Short name	T288
Test name
Test status
Simulation time	6410568514 ps
CPU time	707.61 seconds
Started	Sep 11 08:42:42 AM UTC 24
Finished	Sep 11 08:54:38 AM UTC 24
Peak memory	384892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319536098 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.319536098
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1032534874
Short name	T166
Test name
Test status
Simulation time	204028512 ps
CPU time	5.83 seconds
Started	Sep 11 08:43:02 AM UTC 24
Finished	Sep 11 08:43:09 AM UTC 24
Peak memory	213824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032534874 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.1032534874
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3388975631
Short name	T255
Test name
Test status
Simulation time	24509815808 ps
CPU time	495.15 seconds
Started	Sep 11 08:43:10 AM UTC 24
Finished	Sep 11 08:51:31 AM UTC 24
Peak memory	214228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388975631 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce ss_b2b.3388975631
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3412345940
Short name	T184
Test name
Test status
Simulation time	38090973 ps
CPU time	1.18 seconds
Started	Sep 11 08:43:54 AM UTC 24
Finished	Sep 11 08:43:56 AM UTC 24
Peak memory	212404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412345940 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3412345940
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3490030507
Short name	T133
Test name
Test status
Simulation time	4591663475 ps
CPU time	372.06 seconds
Started	Sep 11 08:43:47 AM UTC 24
Finished	Sep 11 08:50:04 AM UTC 24
Peak memory	384876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490030507 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3490030507
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1944722000
Short name	T181
Test name
Test status
Simulation time	237638548 ps
CPU time	10.81 seconds
Started	Sep 11 08:42:29 AM UTC 24
Finished	Sep 11 08:42:41 AM UTC 24
Peak memory	214108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944722000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1944722000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2970105314
Short name	T886
Test name
Test status
Simulation time	13116476826 ps
CPU time	4141.06 seconds
Started	Sep 11 08:44:07 AM UTC 24
Finished	Sep 11 09:53:49 AM UTC 24
Peak memory	387248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297010531 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.2970105314
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.107801546
Short name	T59
Test name
Test status
Simulation time	4426990425 ps
CPU time	165.22 seconds
Started	Sep 11 08:44:02 AM UTC 24
Finished	Sep 11 08:46:51 AM UTC 24
Peak memory	337828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107801546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.107801546
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.666972984
Short name	T203
Test name
Test status
Simulation time	3515968574 ps
CPU time	222.08 seconds
Started	Sep 11 08:42:59 AM UTC 24
Finished	Sep 11 08:46:45 AM UTC 24
Peak memory	214220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666972984 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.666972984
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4160647638
Short name	T189
Test name
Test status
Simulation time	494754014 ps
CPU time	62.47 seconds
Started	Sep 11 08:43:27 AM UTC 24
Finished	Sep 11 08:44:31 AM UTC 24
Peak memory	339812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4160647638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th roughput_w_partial_write.4160647638
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1132096675
Short name	T308
Test name
Test status
Simulation time	12415287675 ps
CPU time	640.84 seconds
Started	Sep 11 08:45:30 AM UTC 24
Finished	Sep 11 08:56:18 AM UTC 24
Peak memory	386904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132096675 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_ key_req.1132096675
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.810005909
Short name	T199
Test name
Test status
Simulation time	44171321 ps
CPU time	0.87 seconds
Started	Sep 11 08:45:58 AM UTC 24
Finished	Sep 11 08:46:00 AM UTC 24
Peak memory	212636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810005909 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.810005909
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3997724302
Short name	T197
Test name
Test status
Simulation time	1757993240 ps
CPU time	77.87 seconds
Started	Sep 11 08:44:32 AM UTC 24
Finished	Sep 11 08:45:52 AM UTC 24
Peak memory	213768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997724302 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.3997724302
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.525541869
Short name	T486
Test name
Test status
Simulation time	27825225270 ps
CPU time	1657.34 seconds
Started	Sep 11 08:45:30 AM UTC 24
Finished	Sep 11 09:13:24 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525541869 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.525541869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3581849308
Short name	T192
Test name
Test status
Simulation time	596972370 ps
CPU time	6.18 seconds
Started	Sep 11 08:45:22 AM UTC 24
Finished	Sep 11 08:45:29 AM UTC 24
Peak memory	213796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581849308 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.3581849308
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2228721448
Short name	T195
Test name
Test status
Simulation time	102367385 ps
CPU time	40.65 seconds
Started	Sep 11 08:45:05 AM UTC 24
Finished	Sep 11 08:45:47 AM UTC 24
Peak memory	301096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 228721448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max _throughput.2228721448
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1020204330
Short name	T200
Test name
Test status
Simulation time	583359709 ps
CPU time	11.34 seconds
Started	Sep 11 08:45:49 AM UTC 24
Finished	Sep 11 08:46:01 AM UTC 24
Peak memory	224064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020204330 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1020204330
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1944255706
Short name	T292
Test name
Test status
Simulation time	9698760719 ps
CPU time	644.11 seconds
Started	Sep 11 08:44:28 AM UTC 24
Finished	Sep 11 08:55:20 AM UTC 24
Peak memory	382828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944255706 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.1944255706
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.414124043
Short name	T191
Test name
Test status
Simulation time	1489596197 ps
CPU time	19.51 seconds
Started	Sep 11 08:44:49 AM UTC 24
Finished	Sep 11 08:45:10 AM UTC 24
Peak memory	213864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414124043 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.414124043
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1147310654
Short name	T243
Test name
Test status
Simulation time	58449140908 ps
CPU time	356.03 seconds
Started	Sep 11 08:44:51 AM UTC 24
Finished	Sep 11 08:50:52 AM UTC 24
Peak memory	214092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147310654 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acce ss_b2b.1147310654
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2036481783
Short name	T196
Test name
Test status
Simulation time	110674184 ps
CPU time	1.06 seconds
Started	Sep 11 08:45:48 AM UTC 24
Finished	Sep 11 08:45:50 AM UTC 24
Peak memory	212620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036481783 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2036481783
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2567528762
Short name	T139
Test name
Test status
Simulation time	1972222826 ps
CPU time	847.46 seconds
Started	Sep 11 08:45:41 AM UTC 24
Finished	Sep 11 08:59:58 AM UTC 24
Peak memory	384888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567528762 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2567528762
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2175166616
Short name	T188
Test name
Test status
Simulation time	540643276 ps
CPU time	14.91 seconds
Started	Sep 11 08:44:11 AM UTC 24
Finished	Sep 11 08:44:27 AM UTC 24
Peak memory	214104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175166616 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2175166616
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2691339186
Short name	T721
Test name
Test status
Simulation time	9531817889 ps
CPU time	2970.78 seconds
Started	Sep 11 08:45:54 AM UTC 24
Finished	Sep 11 09:35:57 AM UTC 24
Peak memory	395112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269133918 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.2691339186
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1902349719
Short name	T227
Test name
Test status
Simulation time	10496251020 ps
CPU time	272.09 seconds
Started	Sep 11 08:44:44 AM UTC 24
Finished	Sep 11 08:49:20 AM UTC 24
Peak memory	213936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902349719 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.1902349719
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4280504770
Short name	T194
Test name
Test status
Simulation time	104975373 ps
CPU time	28.36 seconds
Started	Sep 11 08:45:10 AM UTC 24
Finished	Sep 11 08:45:40 AM UTC 24
Peak memory	313116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4280504770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th roughput_w_partial_write.4280504770
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest

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