| T800 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.461074815 |
|
|
Sep 11 09:37:08 AM UTC 24 |
Sep 11 09:43:33 AM UTC 24 |
11773348323 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.3858047122 |
|
|
Sep 11 09:29:22 AM UTC 24 |
Sep 11 09:43:34 AM UTC 24 |
39923111191 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.559668909 |
|
|
Sep 11 09:29:57 AM UTC 24 |
Sep 11 09:43:42 AM UTC 24 |
18078784767 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1818376920 |
|
|
Sep 11 09:43:43 AM UTC 24 |
Sep 11 09:43:55 AM UTC 24 |
132080442 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.346700109 |
|
|
Sep 11 09:43:56 AM UTC 24 |
Sep 11 09:43:59 AM UTC 24 |
87696391 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3352351520 |
|
|
Sep 11 09:42:23 AM UTC 24 |
Sep 11 09:44:06 AM UTC 24 |
2553256258 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.546349770 |
|
|
Sep 11 09:27:22 AM UTC 24 |
Sep 11 09:52:19 AM UTC 24 |
19939781602 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3414917911 |
|
|
Sep 11 09:43:36 AM UTC 24 |
Sep 11 09:44:08 AM UTC 24 |
381166168 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.2999279181 |
|
|
Sep 11 09:42:56 AM UTC 24 |
Sep 11 09:44:28 AM UTC 24 |
4414052526 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3363490509 |
|
|
Sep 11 09:31:56 AM UTC 24 |
Sep 11 09:44:28 AM UTC 24 |
5639254207 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.125799454 |
|
|
Sep 11 09:44:29 AM UTC 24 |
Sep 11 09:44:32 AM UTC 24 |
81231450 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1724475309 |
|
|
Sep 11 09:44:33 AM UTC 24 |
Sep 11 09:44:41 AM UTC 24 |
65143991 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3699348178 |
|
|
Sep 11 09:44:30 AM UTC 24 |
Sep 11 09:44:47 AM UTC 24 |
475112630 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.3310583689 |
|
|
Sep 11 09:40:08 AM UTC 24 |
Sep 11 09:44:49 AM UTC 24 |
3047644004 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3279689375 |
|
|
Sep 11 09:43:34 AM UTC 24 |
Sep 11 09:44:50 AM UTC 24 |
1888796117 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2276090734 |
|
|
Sep 11 09:44:50 AM UTC 24 |
Sep 11 09:44:52 AM UTC 24 |
46735931 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.1055283186 |
|
|
Sep 11 09:44:51 AM UTC 24 |
Sep 11 09:45:19 AM UTC 24 |
1887736787 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2308080162 |
|
|
Sep 11 09:41:02 AM UTC 24 |
Sep 11 09:45:22 AM UTC 24 |
1543753707 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3520297546 |
|
|
Sep 11 09:39:50 AM UTC 24 |
Sep 11 09:45:28 AM UTC 24 |
1004327603 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.2880489870 |
|
|
Sep 11 09:44:00 AM UTC 24 |
Sep 11 09:45:33 AM UTC 24 |
1757023375 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.474206489 |
|
|
Sep 11 09:40:31 AM UTC 24 |
Sep 11 09:45:42 AM UTC 24 |
47266105909 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.4290209647 |
|
|
Sep 11 09:03:15 AM UTC 24 |
Sep 11 09:45:56 AM UTC 24 |
76962044807 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3873041526 |
|
|
Sep 11 09:45:30 AM UTC 24 |
Sep 11 09:46:02 AM UTC 24 |
610709627 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3327313335 |
|
|
Sep 11 09:44:42 AM UTC 24 |
Sep 11 09:46:08 AM UTC 24 |
1669726428 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.3963286152 |
|
|
Sep 11 09:41:11 AM UTC 24 |
Sep 11 09:46:09 AM UTC 24 |
5175755371 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1463922270 |
|
|
Sep 11 09:41:50 AM UTC 24 |
Sep 11 09:46:09 AM UTC 24 |
2419001191 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.915813490 |
|
|
Sep 11 09:46:03 AM UTC 24 |
Sep 11 09:46:10 AM UTC 24 |
998191507 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.155951205 |
|
|
Sep 11 09:46:11 AM UTC 24 |
Sep 11 09:46:13 AM UTC 24 |
89187671 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2090526353 |
|
|
Sep 11 09:46:14 AM UTC 24 |
Sep 11 09:46:22 AM UTC 24 |
189331376 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2130271672 |
|
|
Sep 11 09:46:23 AM UTC 24 |
Sep 11 09:46:32 AM UTC 24 |
219795068 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1078788965 |
|
|
Sep 11 09:45:43 AM UTC 24 |
Sep 11 09:46:32 AM UTC 24 |
198285637 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.4085187490 |
|
|
Sep 11 09:45:20 AM UTC 24 |
Sep 11 09:46:32 AM UTC 24 |
1532804382 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2158885216 |
|
|
Sep 11 09:45:57 AM UTC 24 |
Sep 11 09:46:33 AM UTC 24 |
237441708 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2030687818 |
|
|
Sep 11 09:46:33 AM UTC 24 |
Sep 11 09:46:35 AM UTC 24 |
30836583 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2605800240 |
|
|
Sep 11 09:17:23 AM UTC 24 |
Sep 11 09:46:37 AM UTC 24 |
67939518376 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.325008277 |
|
|
Sep 11 09:46:34 AM UTC 24 |
Sep 11 09:46:41 AM UTC 24 |
190539432 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2829786745 |
|
|
Sep 11 09:39:15 AM UTC 24 |
Sep 11 09:46:45 AM UTC 24 |
10688689272 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3208358301 |
|
|
Sep 11 09:10:41 AM UTC 24 |
Sep 11 09:46:52 AM UTC 24 |
7609545911 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1242038692 |
|
|
Sep 11 09:46:37 AM UTC 24 |
Sep 11 09:46:58 AM UTC 24 |
329325500 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.947297328 |
|
|
Sep 11 09:42:05 AM UTC 24 |
Sep 11 09:47:06 AM UTC 24 |
3183314478 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2492269365 |
|
|
Sep 11 09:46:59 AM UTC 24 |
Sep 11 09:47:08 AM UTC 24 |
63038869 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3220659091 |
|
|
Sep 11 09:46:33 AM UTC 24 |
Sep 11 09:47:08 AM UTC 24 |
985934437 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.622204551 |
|
|
Sep 11 09:26:48 AM UTC 24 |
Sep 11 09:47:10 AM UTC 24 |
38641099299 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2670087537 |
|
|
Sep 11 09:35:51 AM UTC 24 |
Sep 11 09:47:13 AM UTC 24 |
2744172287 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.486565761 |
|
|
Sep 11 09:41:07 AM UTC 24 |
Sep 11 09:47:18 AM UTC 24 |
30499888996 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.884741834 |
|
|
Sep 11 09:47:09 AM UTC 24 |
Sep 11 09:47:19 AM UTC 24 |
378573898 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.372289167 |
|
|
Sep 11 09:47:19 AM UTC 24 |
Sep 11 09:47:22 AM UTC 24 |
136512356 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3549746973 |
|
|
Sep 11 09:47:21 AM UTC 24 |
Sep 11 09:47:29 AM UTC 24 |
234923877 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2525102157 |
|
|
Sep 11 09:47:23 AM UTC 24 |
Sep 11 09:47:30 AM UTC 24 |
848033948 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1409194355 |
|
|
Sep 11 09:46:46 AM UTC 24 |
Sep 11 09:47:39 AM UTC 24 |
423282457 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1430676894 |
|
|
Sep 11 08:40:31 AM UTC 24 |
Sep 11 09:47:39 AM UTC 24 |
54752914473 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3476397079 |
|
|
Sep 11 09:47:40 AM UTC 24 |
Sep 11 09:47:42 AM UTC 24 |
17131075 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1424530496 |
|
|
Sep 11 09:41:44 AM UTC 24 |
Sep 11 09:47:56 AM UTC 24 |
12638420036 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1448684064 |
|
|
Sep 11 09:28:02 AM UTC 24 |
Sep 11 09:48:06 AM UTC 24 |
40076581153 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.570171825 |
|
|
Sep 11 09:29:16 AM UTC 24 |
Sep 11 09:48:10 AM UTC 24 |
19177321115 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2831044319 |
|
|
Sep 11 09:43:04 AM UTC 24 |
Sep 11 09:48:20 AM UTC 24 |
9416888523 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.778592571 |
|
|
Sep 11 09:48:11 AM UTC 24 |
Sep 11 09:48:25 AM UTC 24 |
91714666 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2434390775 |
|
|
Sep 11 09:33:29 AM UTC 24 |
Sep 11 09:48:25 AM UTC 24 |
4493011707 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.411628644 |
|
|
Sep 11 09:21:38 AM UTC 24 |
Sep 11 09:48:29 AM UTC 24 |
66994689267 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1195974322 |
|
|
Sep 11 09:48:26 AM UTC 24 |
Sep 11 09:48:32 AM UTC 24 |
177887019 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2320261386 |
|
|
Sep 11 09:35:54 AM UTC 24 |
Sep 11 09:48:36 AM UTC 24 |
33926967955 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.770108825 |
|
|
Sep 11 09:26:49 AM UTC 24 |
Sep 11 09:48:39 AM UTC 24 |
8965518969 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1500405319 |
|
|
Sep 11 09:48:30 AM UTC 24 |
Sep 11 09:48:41 AM UTC 24 |
2604269892 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.304963755 |
|
|
Sep 11 09:47:07 AM UTC 24 |
Sep 11 09:48:44 AM UTC 24 |
154015911 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1669364312 |
|
|
Sep 11 09:48:42 AM UTC 24 |
Sep 11 09:48:45 AM UTC 24 |
126007015 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.3764385954 |
|
|
Sep 11 09:47:40 AM UTC 24 |
Sep 11 09:48:46 AM UTC 24 |
631266335 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2946868 |
|
|
Sep 11 09:47:56 AM UTC 24 |
Sep 11 09:48:48 AM UTC 24 |
815281096 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3598004926 |
|
|
Sep 11 09:48:46 AM UTC 24 |
Sep 11 09:48:52 AM UTC 24 |
345599964 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2638420003 |
|
|
Sep 11 09:48:53 AM UTC 24 |
Sep 11 09:48:55 AM UTC 24 |
23431138 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3346264338 |
|
|
Sep 11 09:48:44 AM UTC 24 |
Sep 11 09:49:00 AM UTC 24 |
3154872093 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1496046561 |
|
|
Sep 11 09:48:47 AM UTC 24 |
Sep 11 09:49:02 AM UTC 24 |
161186674 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1575416687 |
|
|
Sep 11 09:46:43 AM UTC 24 |
Sep 11 09:49:41 AM UTC 24 |
11556818008 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.381550168 |
|
|
Sep 11 09:34:55 AM UTC 24 |
Sep 11 09:49:52 AM UTC 24 |
3433557817 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2449519141 |
|
|
Sep 11 09:48:26 AM UTC 24 |
Sep 11 09:49:59 AM UTC 24 |
521220759 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.879297732 |
|
|
Sep 11 09:46:09 AM UTC 24 |
Sep 11 09:50:05 AM UTC 24 |
16650662930 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.2976749403 |
|
|
Sep 11 09:39:34 AM UTC 24 |
Sep 11 09:50:25 AM UTC 24 |
34435475599 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1932951877 |
|
|
Sep 11 09:45:23 AM UTC 24 |
Sep 11 09:50:34 AM UTC 24 |
27907118192 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2489509482 |
|
|
Sep 11 09:46:53 AM UTC 24 |
Sep 11 09:51:15 AM UTC 24 |
35371230584 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2870648456 |
|
|
Sep 11 09:30:43 AM UTC 24 |
Sep 11 09:51:29 AM UTC 24 |
9865650836 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.2906438165 |
|
|
Sep 11 09:48:40 AM UTC 24 |
Sep 11 09:51:51 AM UTC 24 |
6636196690 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1872126817 |
|
|
Sep 11 09:44:06 AM UTC 24 |
Sep 11 09:52:01 AM UTC 24 |
21148335588 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2695370275 |
|
|
Sep 11 09:41:53 AM UTC 24 |
Sep 11 09:52:06 AM UTC 24 |
83436517470 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.4256982575 |
|
|
Sep 11 09:37:45 AM UTC 24 |
Sep 11 09:52:06 AM UTC 24 |
133521656948 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.387310686 |
|
|
Sep 11 09:32:53 AM UTC 24 |
Sep 11 09:52:28 AM UTC 24 |
6643744597 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3153328346 |
|
|
Sep 11 09:42:05 AM UTC 24 |
Sep 11 09:52:29 AM UTC 24 |
63195913938 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3595798113 |
|
|
Sep 11 09:38:21 AM UTC 24 |
Sep 11 09:53:01 AM UTC 24 |
4288876502 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3044471514 |
|
|
Sep 11 09:16:04 AM UTC 24 |
Sep 11 09:53:27 AM UTC 24 |
57737057011 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2659215463 |
|
|
Sep 11 09:43:36 AM UTC 24 |
Sep 11 09:53:35 AM UTC 24 |
22302298262 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2970105314 |
|
|
Sep 11 08:44:07 AM UTC 24 |
Sep 11 09:53:49 AM UTC 24 |
13116476826 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.3767628002 |
|
|
Sep 11 09:48:37 AM UTC 24 |
Sep 11 09:53:51 AM UTC 24 |
3118613103 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.935850405 |
|
|
Sep 11 09:40:03 AM UTC 24 |
Sep 11 09:53:52 AM UTC 24 |
24635902816 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1702585054 |
|
|
Sep 11 09:45:34 AM UTC 24 |
Sep 11 09:54:19 AM UTC 24 |
89163312729 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3373368682 |
|
|
Sep 11 09:05:55 AM UTC 24 |
Sep 11 09:54:23 AM UTC 24 |
38869668539 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.4235094488 |
|
|
Sep 11 09:48:21 AM UTC 24 |
Sep 11 09:55:12 AM UTC 24 |
9335663785 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3960704988 |
|
|
Sep 11 09:48:32 AM UTC 24 |
Sep 11 09:55:26 AM UTC 24 |
5322676431 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3354127300 |
|
|
Sep 11 09:48:06 AM UTC 24 |
Sep 11 09:55:45 AM UTC 24 |
3691902429 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1552334462 |
|
|
Sep 11 09:42:33 AM UTC 24 |
Sep 11 09:55:51 AM UTC 24 |
14869471252 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3129860409 |
|
|
Sep 11 09:31:06 AM UTC 24 |
Sep 11 09:56:12 AM UTC 24 |
60833174439 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1987712024 |
|
|
Sep 11 09:47:09 AM UTC 24 |
Sep 11 09:56:13 AM UTC 24 |
2091395698 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2669561062 |
|
|
Sep 11 09:44:48 AM UTC 24 |
Sep 11 09:56:48 AM UTC 24 |
14839136563 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2112732077 |
|
|
Sep 11 09:46:33 AM UTC 24 |
Sep 11 09:56:48 AM UTC 24 |
16472958426 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3389387633 |
|
|
Sep 11 09:46:09 AM UTC 24 |
Sep 11 09:56:53 AM UTC 24 |
5703212200 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2784278466 |
|
|
Sep 11 09:44:08 AM UTC 24 |
Sep 11 09:57:19 AM UTC 24 |
47532664029 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.426420060 |
|
|
Sep 11 09:47:43 AM UTC 24 |
Sep 11 09:57:22 AM UTC 24 |
67354386025 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.23323804 |
|
|
Sep 11 09:25:42 AM UTC 24 |
Sep 11 09:57:22 AM UTC 24 |
29402295646 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3373694750 |
|
|
Sep 11 09:42:03 AM UTC 24 |
Sep 11 09:58:00 AM UTC 24 |
11053455727 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3847505392 |
|
|
Sep 11 09:22:10 AM UTC 24 |
Sep 11 09:58:17 AM UTC 24 |
220328045720 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.4202034858 |
|
|
Sep 11 09:44:53 AM UTC 24 |
Sep 11 09:58:18 AM UTC 24 |
14864853163 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1570975633 |
|
|
Sep 11 09:39:12 AM UTC 24 |
Sep 11 09:58:19 AM UTC 24 |
14389979452 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.4197878989 |
|
|
Sep 11 09:22:44 AM UTC 24 |
Sep 11 09:58:27 AM UTC 24 |
33235059916 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.3161289320 |
|
|
Sep 11 09:47:10 AM UTC 24 |
Sep 11 09:58:53 AM UTC 24 |
34119806064 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2922646027 |
|
|
Sep 11 09:46:10 AM UTC 24 |
Sep 11 09:58:58 AM UTC 24 |
2104111402 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2157288085 |
|
|
Sep 11 09:34:25 AM UTC 24 |
Sep 11 09:59:33 AM UTC 24 |
40940661902 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1747263982 |
|
|
Sep 11 09:41:34 AM UTC 24 |
Sep 11 10:01:14 AM UTC 24 |
10248553819 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.1814855123 |
|
|
Sep 11 09:47:13 AM UTC 24 |
Sep 11 10:01:52 AM UTC 24 |
5882687685 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2698183498 |
|
|
Sep 11 09:14:23 AM UTC 24 |
Sep 11 10:03:03 AM UTC 24 |
64148834252 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.4050520177 |
|
|
Sep 11 09:46:36 AM UTC 24 |
Sep 11 10:05:17 AM UTC 24 |
24110474262 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2193791090 |
|
|
Sep 11 09:04:49 AM UTC 24 |
Sep 11 10:06:20 AM UTC 24 |
40621537636 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.239091354 |
|
|
Sep 11 09:19:06 AM UTC 24 |
Sep 11 10:09:24 AM UTC 24 |
134885954893 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.602693633 |
|
|
Sep 11 09:29:39 AM UTC 24 |
Sep 11 10:09:41 AM UTC 24 |
41304915770 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1058606986 |
|
|
Sep 11 08:56:33 AM UTC 24 |
Sep 11 10:12:22 AM UTC 24 |
13686846958 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3145385119 |
|
|
Sep 11 09:23:58 AM UTC 24 |
Sep 11 10:13:24 AM UTC 24 |
11989636382 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1631234223 |
|
|
Sep 11 09:38:09 AM UTC 24 |
Sep 11 10:14:24 AM UTC 24 |
42622360367 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3746567866 |
|
|
Sep 11 09:48:49 AM UTC 24 |
Sep 11 10:18:22 AM UTC 24 |
24518375875 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2738118721 |
|
|
Sep 11 09:39:59 AM UTC 24 |
Sep 11 10:18:59 AM UTC 24 |
166017857591 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3639984800 |
|
|
Sep 11 08:57:57 AM UTC 24 |
Sep 11 10:20:36 AM UTC 24 |
31818407505 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1751697953 |
|
|
Sep 11 09:36:05 AM UTC 24 |
Sep 11 10:20:38 AM UTC 24 |
52951006403 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.947068204 |
|
|
Sep 11 09:47:31 AM UTC 24 |
Sep 11 10:23:28 AM UTC 24 |
110514338639 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.90039089 |
|
|
Sep 11 09:42:27 AM UTC 24 |
Sep 11 10:50:37 AM UTC 24 |
52005871376 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4206017025 |
|
|
Sep 11 09:48:56 AM UTC 24 |
Sep 11 09:49:01 AM UTC 24 |
1301934540 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.750659009 |
|
|
Sep 11 09:49:02 AM UTC 24 |
Sep 11 09:49:04 AM UTC 24 |
57717679 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1378479320 |
|
|
Sep 11 09:49:01 AM UTC 24 |
Sep 11 09:49:05 AM UTC 24 |
270373494 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.399492785 |
|
|
Sep 11 09:49:06 AM UTC 24 |
Sep 11 09:49:08 AM UTC 24 |
43004195 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3815635305 |
|
|
Sep 11 09:49:01 AM UTC 24 |
Sep 11 09:49:08 AM UTC 24 |
234256457 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3863386915 |
|
|
Sep 11 09:49:06 AM UTC 24 |
Sep 11 09:49:10 AM UTC 24 |
458698085 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.144622271 |
|
|
Sep 11 09:49:09 AM UTC 24 |
Sep 11 09:49:11 AM UTC 24 |
75961254 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.468182028 |
|
|
Sep 11 09:49:09 AM UTC 24 |
Sep 11 09:49:11 AM UTC 24 |
32770454 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2605405981 |
|
|
Sep 11 09:49:11 AM UTC 24 |
Sep 11 09:49:13 AM UTC 24 |
51922307 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3512848856 |
|
|
Sep 11 09:49:12 AM UTC 24 |
Sep 11 09:49:17 AM UTC 24 |
853258300 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1670846745 |
|
|
Sep 11 09:49:12 AM UTC 24 |
Sep 11 09:49:18 AM UTC 24 |
111648951 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2064683323 |
|
|
Sep 11 09:49:14 AM UTC 24 |
Sep 11 09:49:19 AM UTC 24 |
174085841 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1807113365 |
|
|
Sep 11 09:49:18 AM UTC 24 |
Sep 11 09:49:20 AM UTC 24 |
13895319 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1542955422 |
|
|
Sep 11 09:49:18 AM UTC 24 |
Sep 11 09:49:20 AM UTC 24 |
27480091 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4006135341 |
|
|
Sep 11 09:49:20 AM UTC 24 |
Sep 11 09:49:23 AM UTC 24 |
128474616 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.369246708 |
|
|
Sep 11 09:49:21 AM UTC 24 |
Sep 11 09:49:23 AM UTC 24 |
18252732 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.184872934 |
|
|
Sep 11 09:49:21 AM UTC 24 |
Sep 11 09:49:23 AM UTC 24 |
16766407 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1677679361 |
|
|
Sep 11 09:49:23 AM UTC 24 |
Sep 11 09:49:26 AM UTC 24 |
54606369 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1265211279 |
|
|
Sep 11 09:49:24 AM UTC 24 |
Sep 11 09:49:29 AM UTC 24 |
112572611 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3670137604 |
|
|
Sep 11 09:49:24 AM UTC 24 |
Sep 11 09:49:29 AM UTC 24 |
770497102 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.651012327 |
|
|
Sep 11 09:49:30 AM UTC 24 |
Sep 11 09:49:32 AM UTC 24 |
36435866 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1906589055 |
|
|
Sep 11 09:49:31 AM UTC 24 |
Sep 11 09:49:33 AM UTC 24 |
31288454 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.823265222 |
|
|
Sep 11 09:49:28 AM UTC 24 |
Sep 11 09:49:33 AM UTC 24 |
578326940 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3356188280 |
|
|
Sep 11 09:49:33 AM UTC 24 |
Sep 11 09:49:36 AM UTC 24 |
293073479 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1671768308 |
|
|
Sep 11 09:49:35 AM UTC 24 |
Sep 11 09:49:37 AM UTC 24 |
40609562 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1892226400 |
|
|
Sep 11 09:49:35 AM UTC 24 |
Sep 11 09:49:37 AM UTC 24 |
44395626 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3348109899 |
|
|
Sep 11 09:49:37 AM UTC 24 |
Sep 11 09:49:40 AM UTC 24 |
41554031 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2372183583 |
|
|
Sep 11 09:49:37 AM UTC 24 |
Sep 11 09:49:43 AM UTC 24 |
401607833 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3107252038 |
|
|
Sep 11 09:49:41 AM UTC 24 |
Sep 11 09:49:43 AM UTC 24 |
444345287 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2304090643 |
|
|
Sep 11 09:49:42 AM UTC 24 |
Sep 11 09:49:44 AM UTC 24 |
101313010 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2519102056 |
|
|
Sep 11 09:49:44 AM UTC 24 |
Sep 11 09:49:46 AM UTC 24 |
43570388 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1504428291 |
|
|
Sep 11 09:49:38 AM UTC 24 |
Sep 11 09:49:46 AM UTC 24 |
577131108 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1551565294 |
|
|
Sep 11 09:49:44 AM UTC 24 |
Sep 11 09:49:46 AM UTC 24 |
29508340 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.333147965 |
|
|
Sep 11 09:49:45 AM UTC 24 |
Sep 11 09:49:47 AM UTC 24 |
17362484 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.844425413 |
|
|
Sep 11 09:49:46 AM UTC 24 |
Sep 11 09:49:48 AM UTC 24 |
55803855 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.121701392 |
|
|
Sep 11 09:49:47 AM UTC 24 |
Sep 11 09:49:50 AM UTC 24 |
63176064 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3444468291 |
|
|
Sep 11 09:49:48 AM UTC 24 |
Sep 11 09:49:52 AM UTC 24 |
288405090 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1962245111 |
|
|
Sep 11 09:49:51 AM UTC 24 |
Sep 11 09:49:53 AM UTC 24 |
39715695 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.27682610 |
|
|
Sep 11 09:49:50 AM UTC 24 |
Sep 11 09:49:53 AM UTC 24 |
362252776 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3073906974 |
|
|
Sep 11 09:49:48 AM UTC 24 |
Sep 11 09:49:54 AM UTC 24 |
528947579 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.503224326 |
|
|
Sep 11 09:49:53 AM UTC 24 |
Sep 11 09:49:55 AM UTC 24 |
103255683 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1711158336 |
|
|
Sep 11 09:49:55 AM UTC 24 |
Sep 11 09:49:56 AM UTC 24 |
16519699 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2241442960 |
|
|
Sep 11 09:49:55 AM UTC 24 |
Sep 11 09:49:57 AM UTC 24 |
167478376 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3095350796 |
|
|
Sep 11 09:49:53 AM UTC 24 |
Sep 11 09:49:57 AM UTC 24 |
309329460 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2439454859 |
|
|
Sep 11 09:49:55 AM UTC 24 |
Sep 11 09:49:58 AM UTC 24 |
129537707 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3768655390 |
|
|
Sep 11 09:49:56 AM UTC 24 |
Sep 11 09:50:00 AM UTC 24 |
394463593 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1866564627 |
|
|
Sep 11 09:49:58 AM UTC 24 |
Sep 11 09:50:00 AM UTC 24 |
76894031 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3022738991 |
|
|
Sep 11 09:49:58 AM UTC 24 |
Sep 11 09:50:00 AM UTC 24 |
96066174 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3786260433 |
|
|
Sep 11 09:49:57 AM UTC 24 |
Sep 11 09:50:01 AM UTC 24 |
506778241 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.453833295 |
|
|
Sep 11 09:49:57 AM UTC 24 |
Sep 11 09:50:03 AM UTC 24 |
139164653 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1450449942 |
|
|
Sep 11 09:50:02 AM UTC 24 |
Sep 11 09:50:04 AM UTC 24 |
36192236 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.122638312 |
|
|
Sep 11 09:50:01 AM UTC 24 |
Sep 11 09:50:05 AM UTC 24 |
49427656 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2436769601 |
|
|
Sep 11 09:50:01 AM UTC 24 |
Sep 11 09:50:05 AM UTC 24 |
693794852 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3125152794 |
|
|
Sep 11 09:50:01 AM UTC 24 |
Sep 11 09:50:06 AM UTC 24 |
319887394 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2590425003 |
|
|
Sep 11 09:50:04 AM UTC 24 |
Sep 11 09:50:06 AM UTC 24 |
12983008 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3267166841 |
|
|
Sep 11 09:50:01 AM UTC 24 |
Sep 11 09:50:07 AM UTC 24 |
141024176 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.958410089 |
|
|
Sep 11 09:50:06 AM UTC 24 |
Sep 11 09:50:09 AM UTC 24 |
70165779 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1263165373 |
|
|
Sep 11 09:50:07 AM UTC 24 |
Sep 11 09:50:09 AM UTC 24 |
16371846 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.731943195 |
|
|
Sep 11 09:50:07 AM UTC 24 |
Sep 11 09:50:10 AM UTC 24 |
18147881 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.180237708 |
|
|
Sep 11 09:50:06 AM UTC 24 |
Sep 11 09:50:10 AM UTC 24 |
249078915 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3749481620 |
|
|
Sep 11 09:50:07 AM UTC 24 |
Sep 11 09:50:11 AM UTC 24 |
350625632 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.762557230 |
|
|
Sep 11 09:50:06 AM UTC 24 |
Sep 11 09:50:11 AM UTC 24 |
1605697479 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3018567669 |
|
|
Sep 11 09:50:09 AM UTC 24 |
Sep 11 09:50:12 AM UTC 24 |
38875499 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1510142049 |
|
|
Sep 11 09:50:10 AM UTC 24 |
Sep 11 09:50:12 AM UTC 24 |
77678065 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1333556602 |
|
|
Sep 11 09:50:10 AM UTC 24 |
Sep 11 09:50:14 AM UTC 24 |
228941392 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3139247242 |
|
|
Sep 11 09:50:12 AM UTC 24 |
Sep 11 09:50:14 AM UTC 24 |
80104063 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3662783780 |
|
|
Sep 11 09:50:10 AM UTC 24 |
Sep 11 09:50:16 AM UTC 24 |
1559693381 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1420809897 |
|
|
Sep 11 09:50:13 AM UTC 24 |
Sep 11 09:50:17 AM UTC 24 |
444599886 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3372151308 |
|
|
Sep 11 09:50:15 AM UTC 24 |
Sep 11 09:50:17 AM UTC 24 |
20899051 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2340853811 |
|
|
Sep 11 09:50:15 AM UTC 24 |
Sep 11 09:50:17 AM UTC 24 |
33431985 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1972033176 |
|
|
Sep 11 09:50:13 AM UTC 24 |
Sep 11 09:50:17 AM UTC 24 |
67093026 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.356313987 |
|
|
Sep 11 09:50:10 AM UTC 24 |
Sep 11 09:50:17 AM UTC 24 |
131470080 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2538565504 |
|
|
Sep 11 09:50:12 AM UTC 24 |
Sep 11 09:50:18 AM UTC 24 |
400646006 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1754521819 |
|
|
Sep 11 09:50:16 AM UTC 24 |
Sep 11 09:50:18 AM UTC 24 |
154616491 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1565855985 |
|
|
Sep 11 09:50:18 AM UTC 24 |
Sep 11 09:50:20 AM UTC 24 |
121517754 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2063605074 |
|
|
Sep 11 09:50:18 AM UTC 24 |
Sep 11 09:50:21 AM UTC 24 |
232606700 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4056440270 |
|
|
Sep 11 09:50:19 AM UTC 24 |
Sep 11 09:50:22 AM UTC 24 |
19295057 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1973827751 |
|
|
Sep 11 09:50:18 AM UTC 24 |
Sep 11 09:50:22 AM UTC 24 |
48910212 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4178493917 |
|
|
Sep 11 09:50:18 AM UTC 24 |
Sep 11 09:50:22 AM UTC 24 |
221630802 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2674360027 |
|
|
Sep 11 09:50:19 AM UTC 24 |
Sep 11 09:50:23 AM UTC 24 |
164311094 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1398677619 |
|
|
Sep 11 09:50:19 AM UTC 24 |
Sep 11 09:50:24 AM UTC 24 |
824897733 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2513183758 |
|
|
Sep 11 09:50:21 AM UTC 24 |
Sep 11 09:50:24 AM UTC 24 |
173509914 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2585096692 |
|
|
Sep 11 09:50:20 AM UTC 24 |
Sep 11 09:50:25 AM UTC 24 |
152941161 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3448913760 |
|
|
Sep 11 09:50:24 AM UTC 24 |
Sep 11 09:50:26 AM UTC 24 |
21614311 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2997059177 |
|
|
Sep 11 09:50:24 AM UTC 24 |
Sep 11 09:50:26 AM UTC 24 |
56341327 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1050617585 |
|
|
Sep 11 09:50:25 AM UTC 24 |
Sep 11 09:50:27 AM UTC 24 |
22351517 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.201573811 |
|
|
Sep 11 09:50:24 AM UTC 24 |
Sep 11 09:50:28 AM UTC 24 |
341582645 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1452965846 |
|
|
Sep 11 09:50:24 AM UTC 24 |
Sep 11 09:50:29 AM UTC 24 |
399948425 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3050061249 |
|
|
Sep 11 09:50:27 AM UTC 24 |
Sep 11 09:50:29 AM UTC 24 |
197372487 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1301196289 |
|
|
Sep 11 09:50:25 AM UTC 24 |
Sep 11 09:50:29 AM UTC 24 |
531834897 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3282626213 |
|
|
Sep 11 09:50:24 AM UTC 24 |
Sep 11 09:50:30 AM UTC 24 |
5022020323 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1071918466 |
|
|
Sep 11 09:50:27 AM UTC 24 |
Sep 11 09:50:31 AM UTC 24 |
62456750 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.587104185 |
|
|
Sep 11 09:50:29 AM UTC 24 |
Sep 11 09:50:31 AM UTC 24 |
32902661 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2696895486 |
|
|
Sep 11 09:50:28 AM UTC 24 |
Sep 11 09:50:32 AM UTC 24 |
491003809 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1606894986 |
|
|
Sep 11 09:50:31 AM UTC 24 |
Sep 11 09:50:33 AM UTC 24 |
41653303 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3071425753 |
|
|
Sep 11 09:50:27 AM UTC 24 |
Sep 11 09:50:33 AM UTC 24 |
132904377 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2645041878 |
|
|
Sep 11 09:50:27 AM UTC 24 |
Sep 11 09:50:34 AM UTC 24 |
1511187144 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2023854698 |
|
|
Sep 11 09:50:32 AM UTC 24 |
Sep 11 09:50:35 AM UTC 24 |
31571741 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4132286384 |
|
|
Sep 11 09:50:34 AM UTC 24 |
Sep 11 09:50:36 AM UTC 24 |
42349194 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.757974320 |
|
|
Sep 11 09:50:31 AM UTC 24 |
Sep 11 09:50:37 AM UTC 24 |
927993929 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1939616087 |
|
|
Sep 11 09:50:32 AM UTC 24 |
Sep 11 09:50:37 AM UTC 24 |
204591189 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.185730631 |
|
|
Sep 11 09:50:34 AM UTC 24 |
Sep 11 09:50:38 AM UTC 24 |
160985752 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3111921209 |
|
|
Sep 11 09:50:35 AM UTC 24 |
Sep 11 09:50:38 AM UTC 24 |
21955964 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1412851676 |
|
|
Sep 11 09:50:35 AM UTC 24 |
Sep 11 09:50:38 AM UTC 24 |
173253677 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2670761185 |
|
|
Sep 11 09:50:37 AM UTC 24 |
Sep 11 09:50:39 AM UTC 24 |
14554020 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1210656393 |
|
|
Sep 11 09:50:37 AM UTC 24 |
Sep 11 09:50:39 AM UTC 24 |
316962449 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2181863170 |
|
|
Sep 11 09:50:31 AM UTC 24 |
Sep 11 09:50:39 AM UTC 24 |
155654489 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1985845613 |
|
|
Sep 11 09:50:38 AM UTC 24 |
Sep 11 09:50:41 AM UTC 24 |
13799457 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2359739310 |
|
|
Sep 11 09:50:35 AM UTC 24 |
Sep 11 09:50:42 AM UTC 24 |
423676388 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3168480337 |
|
|
Sep 11 09:50:40 AM UTC 24 |
Sep 11 09:50:42 AM UTC 24 |
92985038 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.496283631 |
|
|
Sep 11 09:50:40 AM UTC 24 |
Sep 11 09:50:42 AM UTC 24 |
34531407 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3243655794 |
|
|
Sep 11 09:50:38 AM UTC 24 |
Sep 11 09:50:43 AM UTC 24 |
452851636 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.197879529 |
|
|
Sep 11 09:50:35 AM UTC 24 |
Sep 11 09:50:43 AM UTC 24 |
125724833 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3426980668 |
|
|
Sep 11 09:50:38 AM UTC 24 |
Sep 11 09:50:43 AM UTC 24 |
804082031 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3861251397 |
|
|
Sep 11 09:50:40 AM UTC 24 |
Sep 11 09:50:43 AM UTC 24 |
227663165 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2219070532 |
|
|
Sep 11 09:50:43 AM UTC 24 |
Sep 11 09:50:45 AM UTC 24 |
13368297 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2460794518 |
|
|
Sep 11 09:50:43 AM UTC 24 |
Sep 11 09:50:45 AM UTC 24 |
13219720 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2255974555 |
|
|
Sep 11 09:50:41 AM UTC 24 |
Sep 11 09:50:45 AM UTC 24 |
545567261 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1834368899 |
|
|
Sep 11 09:50:41 AM UTC 24 |
Sep 11 09:50:45 AM UTC 24 |
74770906 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3868113100 |
|
|
Sep 11 09:50:44 AM UTC 24 |
Sep 11 09:50:47 AM UTC 24 |
28798682 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1220564384 |
|
|
Sep 11 09:50:38 AM UTC 24 |
Sep 11 09:50:47 AM UTC 24 |
605552456 ps |