| T301 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2946058568 |
|
|
Sep 18 08:41:50 AM UTC 24 |
Sep 18 08:45:24 AM UTC 24 |
16433394405 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3754691086 |
|
|
Sep 18 08:45:25 AM UTC 24 |
Sep 18 08:45:27 AM UTC 24 |
56177324 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2067603953 |
|
|
Sep 18 08:40:51 AM UTC 24 |
Sep 18 08:45:32 AM UTC 24 |
2225347232 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1915000597 |
|
|
Sep 18 08:45:28 AM UTC 24 |
Sep 18 08:45:36 AM UTC 24 |
229293154 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2306749634 |
|
|
Sep 18 08:45:33 AM UTC 24 |
Sep 18 08:45:39 AM UTC 24 |
94170050 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2043644410 |
|
|
Sep 18 08:26:34 AM UTC 24 |
Sep 18 08:45:42 AM UTC 24 |
77581795589 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3683030330 |
|
|
Sep 18 08:45:44 AM UTC 24 |
Sep 18 08:45:45 AM UTC 24 |
84648294 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1035392277 |
|
|
Sep 18 08:44:22 AM UTC 24 |
Sep 18 08:45:48 AM UTC 24 |
19007686936 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.2192259112 |
|
|
Sep 18 08:45:47 AM UTC 24 |
Sep 18 08:45:56 AM UTC 24 |
237505053 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3216546970 |
|
|
Sep 18 08:44:35 AM UTC 24 |
Sep 18 08:45:58 AM UTC 24 |
130157934 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2992467350 |
|
|
Sep 18 08:36:29 AM UTC 24 |
Sep 18 08:46:01 AM UTC 24 |
6835725683 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.1046445103 |
|
|
Sep 18 08:41:25 AM UTC 24 |
Sep 18 08:46:19 AM UTC 24 |
2481671052 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1035015965 |
|
|
Sep 18 08:46:02 AM UTC 24 |
Sep 18 08:46:21 AM UTC 24 |
1286080197 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.4156011393 |
|
|
Sep 18 08:37:50 AM UTC 24 |
Sep 18 08:46:25 AM UTC 24 |
75932414993 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2472709029 |
|
|
Sep 18 08:46:21 AM UTC 24 |
Sep 18 08:46:34 AM UTC 24 |
123149594 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1202050379 |
|
|
Sep 18 08:46:35 AM UTC 24 |
Sep 18 08:46:44 AM UTC 24 |
2228386727 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3057300848 |
|
|
Sep 18 08:39:54 AM UTC 24 |
Sep 18 08:47:15 AM UTC 24 |
13550956148 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.3141917698 |
|
|
Sep 18 08:45:57 AM UTC 24 |
Sep 18 08:47:17 AM UTC 24 |
1062696472 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3934340400 |
|
|
Sep 18 08:33:27 AM UTC 24 |
Sep 18 08:47:27 AM UTC 24 |
72205058311 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1986232062 |
|
|
Sep 18 08:47:28 AM UTC 24 |
Sep 18 08:47:31 AM UTC 24 |
79023373 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.399337940 |
|
|
Sep 18 08:45:37 AM UTC 24 |
Sep 18 08:47:34 AM UTC 24 |
4481460908 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2933127521 |
|
|
Sep 18 08:47:31 AM UTC 24 |
Sep 18 08:47:37 AM UTC 24 |
97998740 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.686045435 |
|
|
Sep 18 08:47:38 AM UTC 24 |
Sep 18 08:47:39 AM UTC 24 |
32710460 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1881428758 |
|
|
Sep 18 08:47:31 AM UTC 24 |
Sep 18 08:47:41 AM UTC 24 |
617461591 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1837632012 |
|
|
Sep 18 08:46:25 AM UTC 24 |
Sep 18 08:48:06 AM UTC 24 |
1153756957 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.4064718845 |
|
|
Sep 18 08:46:45 AM UTC 24 |
Sep 18 08:48:13 AM UTC 24 |
1005603856 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.143079936 |
|
|
Sep 18 08:32:56 AM UTC 24 |
Sep 18 08:48:15 AM UTC 24 |
3826148150 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.1120409671 |
|
|
Sep 18 08:48:07 AM UTC 24 |
Sep 18 08:48:29 AM UTC 24 |
2383510639 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2728307018 |
|
|
Sep 18 08:29:44 AM UTC 24 |
Sep 18 08:48:30 AM UTC 24 |
44119376496 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1831461273 |
|
|
Sep 18 08:23:44 AM UTC 24 |
Sep 18 08:48:48 AM UTC 24 |
19021688092 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.342391074 |
|
|
Sep 18 08:48:49 AM UTC 24 |
Sep 18 08:48:59 AM UTC 24 |
409175177 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1479191843 |
|
|
Sep 18 08:48:16 AM UTC 24 |
Sep 18 08:49:04 AM UTC 24 |
331941314 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.403910959 |
|
|
Sep 18 08:48:30 AM UTC 24 |
Sep 18 08:49:04 AM UTC 24 |
84567584 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.2153002882 |
|
|
Sep 18 08:23:53 AM UTC 24 |
Sep 18 08:49:21 AM UTC 24 |
97311493748 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.2987440553 |
|
|
Sep 18 08:47:41 AM UTC 24 |
Sep 18 08:49:22 AM UTC 24 |
741112224 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3169391140 |
|
|
Sep 18 08:42:54 AM UTC 24 |
Sep 18 08:49:23 AM UTC 24 |
14258124969 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1043334001 |
|
|
Sep 18 08:49:22 AM UTC 24 |
Sep 18 08:49:24 AM UTC 24 |
31265731 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.323588045 |
|
|
Sep 18 08:49:23 AM UTC 24 |
Sep 18 08:49:28 AM UTC 24 |
181832076 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3156614980 |
|
|
Sep 18 08:45:03 AM UTC 24 |
Sep 18 08:49:33 AM UTC 24 |
6854078456 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.943043817 |
|
|
Sep 18 08:49:35 AM UTC 24 |
Sep 18 08:49:36 AM UTC 24 |
33714583 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.719743304 |
|
|
Sep 18 08:49:23 AM UTC 24 |
Sep 18 08:49:37 AM UTC 24 |
181656022 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1450819971 |
|
|
Sep 18 08:48:30 AM UTC 24 |
Sep 18 08:49:44 AM UTC 24 |
621624336 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2857538794 |
|
|
Sep 18 08:49:38 AM UTC 24 |
Sep 18 08:50:01 AM UTC 24 |
892572583 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.336151122 |
|
|
Sep 18 08:31:49 AM UTC 24 |
Sep 18 08:50:07 AM UTC 24 |
14604342342 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.451305392 |
|
|
Sep 18 08:35:26 AM UTC 24 |
Sep 18 08:50:14 AM UTC 24 |
38108943644 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2144922680 |
|
|
Sep 18 08:32:57 AM UTC 24 |
Sep 18 08:50:20 AM UTC 24 |
20486352193 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3710710269 |
|
|
Sep 18 08:50:08 AM UTC 24 |
Sep 18 08:50:22 AM UTC 24 |
635062218 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.4192994124 |
|
|
Sep 18 08:49:45 AM UTC 24 |
Sep 18 08:50:24 AM UTC 24 |
2410642221 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.73426659 |
|
|
Sep 18 08:42:46 AM UTC 24 |
Sep 18 08:50:29 AM UTC 24 |
4972902197 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.450308703 |
|
|
Sep 18 08:50:26 AM UTC 24 |
Sep 18 08:50:35 AM UTC 24 |
1877698785 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3425929846 |
|
|
Sep 18 08:44:22 AM UTC 24 |
Sep 18 08:50:51 AM UTC 24 |
7109534025 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.3799308106 |
|
|
Sep 18 08:50:22 AM UTC 24 |
Sep 18 08:50:54 AM UTC 24 |
591774878 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.2077281332 |
|
|
Sep 18 08:50:55 AM UTC 24 |
Sep 18 08:50:57 AM UTC 24 |
55057015 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3107040859 |
|
|
Sep 18 08:50:58 AM UTC 24 |
Sep 18 08:51:07 AM UTC 24 |
365903733 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3361797167 |
|
|
Sep 18 08:45:59 AM UTC 24 |
Sep 18 08:51:14 AM UTC 24 |
5957000721 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1387301475 |
|
|
Sep 18 08:51:07 AM UTC 24 |
Sep 18 08:51:16 AM UTC 24 |
425567567 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2855713790 |
|
|
Sep 18 08:44:14 AM UTC 24 |
Sep 18 08:51:32 AM UTC 24 |
4276269527 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.949748290 |
|
|
Sep 18 08:53:16 AM UTC 24 |
Sep 18 08:53:25 AM UTC 24 |
532466761 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3598171036 |
|
|
Sep 18 08:51:34 AM UTC 24 |
Sep 18 08:51:36 AM UTC 24 |
43067491 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2437177088 |
|
|
Sep 18 08:51:37 AM UTC 24 |
Sep 18 08:51:52 AM UTC 24 |
244196151 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2021972523 |
|
|
Sep 18 08:49:25 AM UTC 24 |
Sep 18 08:51:52 AM UTC 24 |
1946473785 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2340762674 |
|
|
Sep 18 08:48:14 AM UTC 24 |
Sep 18 08:52:07 AM UTC 24 |
1993581559 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1668424603 |
|
|
Sep 18 08:40:35 AM UTC 24 |
Sep 18 08:52:08 AM UTC 24 |
8847651837 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3752641128 |
|
|
Sep 18 08:50:20 AM UTC 24 |
Sep 18 08:52:13 AM UTC 24 |
506567774 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1451340901 |
|
|
Sep 18 08:51:14 AM UTC 24 |
Sep 18 08:52:14 AM UTC 24 |
1598255401 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2496191386 |
|
|
Sep 18 08:42:20 AM UTC 24 |
Sep 18 08:52:15 AM UTC 24 |
5199544729 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.1088257002 |
|
|
Sep 18 08:51:53 AM UTC 24 |
Sep 18 08:52:19 AM UTC 24 |
3668006798 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.470862183 |
|
|
Sep 18 08:38:17 AM UTC 24 |
Sep 18 08:52:23 AM UTC 24 |
2146076952 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2812081145 |
|
|
Sep 18 08:52:21 AM UTC 24 |
Sep 18 08:52:30 AM UTC 24 |
736165367 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.117199278 |
|
|
Sep 18 08:52:08 AM UTC 24 |
Sep 18 08:52:43 AM UTC 24 |
476274718 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3695221347 |
|
|
Sep 18 08:52:14 AM UTC 24 |
Sep 18 08:52:45 AM UTC 24 |
89864140 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2107625849 |
|
|
Sep 18 08:52:46 AM UTC 24 |
Sep 18 08:52:48 AM UTC 24 |
82374701 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2325797628 |
|
|
Sep 18 08:52:49 AM UTC 24 |
Sep 18 08:52:56 AM UTC 24 |
88884204 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1521259006 |
|
|
Sep 18 08:52:57 AM UTC 24 |
Sep 18 08:53:06 AM UTC 24 |
340999305 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3315828719 |
|
|
Sep 18 08:48:22 AM UTC 24 |
Sep 18 08:53:07 AM UTC 24 |
3806913816 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.341613155 |
|
|
Sep 18 08:44:32 AM UTC 24 |
Sep 18 08:53:12 AM UTC 24 |
39964432805 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.597898115 |
|
|
Sep 18 08:53:13 AM UTC 24 |
Sep 18 08:53:15 AM UTC 24 |
11464853 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.400648537 |
|
|
Sep 18 08:52:16 AM UTC 24 |
Sep 18 08:53:20 AM UTC 24 |
127359708 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.395699716 |
|
|
Sep 18 08:53:07 AM UTC 24 |
Sep 18 08:53:32 AM UTC 24 |
4110907569 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.3632554138 |
|
|
Sep 18 08:52:44 AM UTC 24 |
Sep 18 08:54:00 AM UTC 24 |
5038202516 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3407732306 |
|
|
Sep 18 08:24:34 AM UTC 24 |
Sep 18 08:54:21 AM UTC 24 |
24592219187 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2797835741 |
|
|
Sep 18 08:53:26 AM UTC 24 |
Sep 18 08:54:21 AM UTC 24 |
738817337 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2621123594 |
|
|
Sep 18 08:54:00 AM UTC 24 |
Sep 18 08:54:35 AM UTC 24 |
498853694 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.880258831 |
|
|
Sep 18 08:42:48 AM UTC 24 |
Sep 18 08:54:38 AM UTC 24 |
21165363824 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2331502470 |
|
|
Sep 18 08:52:08 AM UTC 24 |
Sep 18 08:54:44 AM UTC 24 |
6656036309 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.622993441 |
|
|
Sep 18 08:54:36 AM UTC 24 |
Sep 18 08:54:45 AM UTC 24 |
2005835786 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1209346594 |
|
|
Sep 18 08:54:23 AM UTC 24 |
Sep 18 08:54:53 AM UTC 24 |
371889046 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2569689 |
|
|
Sep 18 08:54:29 AM UTC 24 |
Sep 18 08:54:55 AM UTC 24 |
401047444 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.678089514 |
|
|
Sep 18 08:54:54 AM UTC 24 |
Sep 18 08:54:56 AM UTC 24 |
28088270 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2846846809 |
|
|
Sep 18 08:47:34 AM UTC 24 |
Sep 18 08:54:58 AM UTC 24 |
6209490785 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3390051360 |
|
|
Sep 18 08:54:58 AM UTC 24 |
Sep 18 08:55:02 AM UTC 24 |
164026742 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2772752165 |
|
|
Sep 18 08:54:56 AM UTC 24 |
Sep 18 08:55:04 AM UTC 24 |
271305608 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.2821821579 |
|
|
Sep 18 08:29:46 AM UTC 24 |
Sep 18 08:55:04 AM UTC 24 |
8222000599 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2774231255 |
|
|
Sep 18 08:55:05 AM UTC 24 |
Sep 18 08:55:07 AM UTC 24 |
17596975 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.1137928387 |
|
|
Sep 18 08:55:05 AM UTC 24 |
Sep 18 08:55:09 AM UTC 24 |
34208526 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.1516047472 |
|
|
Sep 18 08:50:02 AM UTC 24 |
Sep 18 08:55:17 AM UTC 24 |
5019875991 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1180068615 |
|
|
Sep 18 08:43:35 AM UTC 24 |
Sep 18 08:55:48 AM UTC 24 |
8771448619 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2274912478 |
|
|
Sep 18 08:55:20 AM UTC 24 |
Sep 18 08:55:54 AM UTC 24 |
1926705189 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1424169377 |
|
|
Sep 18 08:46:19 AM UTC 24 |
Sep 18 08:56:04 AM UTC 24 |
27435129770 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.630355585 |
|
|
Sep 18 08:49:05 AM UTC 24 |
Sep 18 08:56:16 AM UTC 24 |
14175614055 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.817775471 |
|
|
Sep 18 08:49:28 AM UTC 24 |
Sep 18 08:56:28 AM UTC 24 |
5696915462 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3404294913 |
|
|
Sep 18 08:56:16 AM UTC 24 |
Sep 18 08:56:30 AM UTC 24 |
923370165 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3683759666 |
|
|
Sep 18 08:55:09 AM UTC 24 |
Sep 18 08:56:31 AM UTC 24 |
1075856326 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2231984110 |
|
|
Sep 18 08:45:49 AM UTC 24 |
Sep 18 08:56:33 AM UTC 24 |
49183744281 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.862466375 |
|
|
Sep 18 08:56:34 AM UTC 24 |
Sep 18 08:56:36 AM UTC 24 |
109265438 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.575963813 |
|
|
Sep 18 08:42:59 AM UTC 24 |
Sep 18 08:56:37 AM UTC 24 |
207429375988 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2084964455 |
|
|
Sep 18 08:53:33 AM UTC 24 |
Sep 18 08:56:39 AM UTC 24 |
7192409584 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2734741478 |
|
|
Sep 18 08:56:05 AM UTC 24 |
Sep 18 08:56:40 AM UTC 24 |
225034227 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.557694175 |
|
|
Sep 18 08:56:38 AM UTC 24 |
Sep 18 08:56:42 AM UTC 24 |
957961124 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2958012810 |
|
|
Sep 18 08:56:43 AM UTC 24 |
Sep 18 08:56:45 AM UTC 24 |
81195965 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1363993813 |
|
|
Sep 18 08:56:38 AM UTC 24 |
Sep 18 08:56:46 AM UTC 24 |
354371956 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.862245834 |
|
|
Sep 18 08:28:18 AM UTC 24 |
Sep 18 08:56:48 AM UTC 24 |
100218196897 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.3680645868 |
|
|
Sep 18 08:56:46 AM UTC 24 |
Sep 18 08:56:59 AM UTC 24 |
503840475 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2046660396 |
|
|
Sep 18 08:50:14 AM UTC 24 |
Sep 18 08:57:04 AM UTC 24 |
26993969486 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1019954395 |
|
|
Sep 18 08:54:45 AM UTC 24 |
Sep 18 08:57:06 AM UTC 24 |
5834262239 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3324244881 |
|
|
Sep 18 08:42:24 AM UTC 24 |
Sep 18 08:57:10 AM UTC 24 |
3266786062 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.564408710 |
|
|
Sep 18 08:52:24 AM UTC 24 |
Sep 18 08:57:13 AM UTC 24 |
5686217507 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1303453300 |
|
|
Sep 18 08:57:14 AM UTC 24 |
Sep 18 08:57:17 AM UTC 24 |
42209896 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2782094971 |
|
|
Sep 18 08:56:41 AM UTC 24 |
Sep 18 08:57:17 AM UTC 24 |
3745536459 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2056509945 |
|
|
Sep 18 08:57:04 AM UTC 24 |
Sep 18 08:57:26 AM UTC 24 |
2831096117 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2836884359 |
|
|
Sep 18 08:57:18 AM UTC 24 |
Sep 18 08:57:27 AM UTC 24 |
363330450 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.541116169 |
|
|
Sep 18 08:55:55 AM UTC 24 |
Sep 18 08:57:49 AM UTC 24 |
340607746 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3436648136 |
|
|
Sep 18 08:57:49 AM UTC 24 |
Sep 18 08:57:51 AM UTC 24 |
79355671 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.1087817954 |
|
|
Sep 18 08:57:52 AM UTC 24 |
Sep 18 08:58:09 AM UTC 24 |
1921412097 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1313430861 |
|
|
Sep 18 08:49:38 AM UTC 24 |
Sep 18 08:58:11 AM UTC 24 |
9565098460 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.1079974827 |
|
|
Sep 18 08:56:49 AM UTC 24 |
Sep 18 08:58:12 AM UTC 24 |
16372440978 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3889860935 |
|
|
Sep 18 08:52:31 AM UTC 24 |
Sep 18 08:58:15 AM UTC 24 |
3143280355 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3768318693 |
|
|
Sep 18 08:58:09 AM UTC 24 |
Sep 18 08:58:15 AM UTC 24 |
210639992 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2509398578 |
|
|
Sep 18 08:58:16 AM UTC 24 |
Sep 18 08:58:18 AM UTC 24 |
24263197 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3892280000 |
|
|
Sep 18 08:58:16 AM UTC 24 |
Sep 18 08:58:25 AM UTC 24 |
374099332 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3760415879 |
|
|
Sep 18 08:47:18 AM UTC 24 |
Sep 18 08:58:25 AM UTC 24 |
2405187197 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1186012790 |
|
|
Sep 18 08:57:11 AM UTC 24 |
Sep 18 08:58:31 AM UTC 24 |
715891612 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3349534333 |
|
|
Sep 18 08:34:34 AM UTC 24 |
Sep 18 08:58:38 AM UTC 24 |
25842024525 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.1426435781 |
|
|
Sep 18 08:38:44 AM UTC 24 |
Sep 18 08:59:06 AM UTC 24 |
21366365377 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1109720382 |
|
|
Sep 18 08:43:23 AM UTC 24 |
Sep 18 08:59:02 AM UTC 24 |
3249112297 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.247295263 |
|
|
Sep 18 08:59:03 AM UTC 24 |
Sep 18 08:59:08 AM UTC 24 |
104729084 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.139482539 |
|
|
Sep 18 08:37:13 AM UTC 24 |
Sep 18 08:59:12 AM UTC 24 |
60317782598 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.984640359 |
|
|
Sep 18 08:59:07 AM UTC 24 |
Sep 18 08:59:13 AM UTC 24 |
969078250 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1748464433 |
|
|
Sep 18 08:58:26 AM UTC 24 |
Sep 18 08:59:31 AM UTC 24 |
4369376480 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2717916914 |
|
|
Sep 18 08:58:53 AM UTC 24 |
Sep 18 08:59:32 AM UTC 24 |
705173208 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.37395900 |
|
|
Sep 18 08:59:32 AM UTC 24 |
Sep 18 08:59:34 AM UTC 24 |
29133162 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2332794090 |
|
|
Sep 18 08:41:20 AM UTC 24 |
Sep 18 08:59:38 AM UTC 24 |
2848719719 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3003699863 |
|
|
Sep 18 08:59:36 AM UTC 24 |
Sep 18 08:59:41 AM UTC 24 |
863982461 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3247420494 |
|
|
Sep 18 08:59:42 AM UTC 24 |
Sep 18 08:59:44 AM UTC 24 |
37315768 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3215651088 |
|
|
Sep 18 08:47:42 AM UTC 24 |
Sep 18 08:59:45 AM UTC 24 |
6893751570 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3792555218 |
|
|
Sep 18 08:59:32 AM UTC 24 |
Sep 18 08:59:49 AM UTC 24 |
470164738 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1525627795 |
|
|
Sep 18 08:47:17 AM UTC 24 |
Sep 18 08:59:50 AM UTC 24 |
15868863924 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2108286842 |
|
|
Sep 18 08:59:13 AM UTC 24 |
Sep 18 08:59:57 AM UTC 24 |
435568115 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1856539621 |
|
|
Sep 18 08:58:31 AM UTC 24 |
Sep 18 08:59:58 AM UTC 24 |
385097307 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2194006385 |
|
|
Sep 18 08:59:45 AM UTC 24 |
Sep 18 09:00:02 AM UTC 24 |
261243954 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2005688807 |
|
|
Sep 18 09:00:03 AM UTC 24 |
Sep 18 09:00:14 AM UTC 24 |
423481416 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2176720158 |
|
|
Sep 18 08:42:51 AM UTC 24 |
Sep 18 09:00:17 AM UTC 24 |
57840900114 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3265154053 |
|
|
Sep 18 08:50:30 AM UTC 24 |
Sep 18 09:00:20 AM UTC 24 |
6374350953 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3734406940 |
|
|
Sep 18 08:59:57 AM UTC 24 |
Sep 18 09:00:23 AM UTC 24 |
529742894 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.714452095 |
|
|
Sep 18 09:00:18 AM UTC 24 |
Sep 18 09:00:29 AM UTC 24 |
2559422432 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2602863395 |
|
|
Sep 18 08:59:49 AM UTC 24 |
Sep 18 09:00:32 AM UTC 24 |
588983010 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2877614851 |
|
|
Sep 18 08:52:13 AM UTC 24 |
Sep 18 09:00:36 AM UTC 24 |
15384438263 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.261383984 |
|
|
Sep 18 09:00:33 AM UTC 24 |
Sep 18 09:00:36 AM UTC 24 |
48315787 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2348858214 |
|
|
Sep 18 09:00:15 AM UTC 24 |
Sep 18 09:00:38 AM UTC 24 |
335137160 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4148259700 |
|
|
Sep 18 09:00:37 AM UTC 24 |
Sep 18 09:00:42 AM UTC 24 |
345097906 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1989169212 |
|
|
Sep 18 09:00:37 AM UTC 24 |
Sep 18 09:00:53 AM UTC 24 |
653980162 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2688369255 |
|
|
Sep 18 09:00:54 AM UTC 24 |
Sep 18 09:00:56 AM UTC 24 |
16053390 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2681646383 |
|
|
Sep 18 08:57:00 AM UTC 24 |
Sep 18 09:01:01 AM UTC 24 |
2324275098 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.869949832 |
|
|
Sep 18 08:54:21 AM UTC 24 |
Sep 18 09:01:03 AM UTC 24 |
5352821908 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.3362792556 |
|
|
Sep 18 08:55:18 AM UTC 24 |
Sep 18 09:01:15 AM UTC 24 |
6744878847 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.524466667 |
|
|
Sep 18 08:58:12 AM UTC 24 |
Sep 18 09:01:15 AM UTC 24 |
4218120092 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.85419734 |
|
|
Sep 18 09:00:40 AM UTC 24 |
Sep 18 09:01:21 AM UTC 24 |
4644613321 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.1981820708 |
|
|
Sep 18 09:00:57 AM UTC 24 |
Sep 18 09:01:40 AM UTC 24 |
7662881028 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2119482047 |
|
|
Sep 18 08:51:53 AM UTC 24 |
Sep 18 09:01:43 AM UTC 24 |
52848147789 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1669834671 |
|
|
Sep 18 08:54:59 AM UTC 24 |
Sep 18 09:01:44 AM UTC 24 |
8926460459 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2469951112 |
|
|
Sep 18 09:01:45 AM UTC 24 |
Sep 18 09:01:50 AM UTC 24 |
635835336 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2290360003 |
|
|
Sep 18 08:39:27 AM UTC 24 |
Sep 18 09:02:10 AM UTC 24 |
28006441394 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.91992246 |
|
|
Sep 18 08:23:58 AM UTC 24 |
Sep 18 09:02:22 AM UTC 24 |
84406458447 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1764799044 |
|
|
Sep 18 09:01:04 AM UTC 24 |
Sep 18 09:02:24 AM UTC 24 |
3989322270 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.4292786387 |
|
|
Sep 18 09:01:17 AM UTC 24 |
Sep 18 09:02:26 AM UTC 24 |
1989802858 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3910216436 |
|
|
Sep 18 09:02:25 AM UTC 24 |
Sep 18 09:02:27 AM UTC 24 |
136023740 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.581627974 |
|
|
Sep 18 09:02:27 AM UTC 24 |
Sep 18 09:02:33 AM UTC 24 |
76951339 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.619754927 |
|
|
Sep 18 09:02:28 AM UTC 24 |
Sep 18 09:02:33 AM UTC 24 |
67767757 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.2663568115 |
|
|
Sep 18 09:02:22 AM UTC 24 |
Sep 18 09:03:05 AM UTC 24 |
2032378104 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2446861235 |
|
|
Sep 18 09:03:06 AM UTC 24 |
Sep 18 09:03:08 AM UTC 24 |
15914663 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.4184327570 |
|
|
Sep 18 09:01:44 AM UTC 24 |
Sep 18 09:03:11 AM UTC 24 |
672696979 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.446664926 |
|
|
Sep 18 08:59:39 AM UTC 24 |
Sep 18 09:03:27 AM UTC 24 |
3297336259 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1987025019 |
|
|
Sep 18 09:03:09 AM UTC 24 |
Sep 18 09:03:28 AM UTC 24 |
1260120110 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3175972335 |
|
|
Sep 18 08:59:09 AM UTC 24 |
Sep 18 09:03:32 AM UTC 24 |
476020672 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.666552751 |
|
|
Sep 18 09:01:41 AM UTC 24 |
Sep 18 09:03:32 AM UTC 24 |
1596848062 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3134509190 |
|
|
Sep 18 08:49:01 AM UTC 24 |
Sep 18 09:03:38 AM UTC 24 |
2840621719 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2611060751 |
|
|
Sep 18 09:03:33 AM UTC 24 |
Sep 18 09:03:42 AM UTC 24 |
113541148 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.776409997 |
|
|
Sep 18 08:50:52 AM UTC 24 |
Sep 18 09:03:44 AM UTC 24 |
10880532110 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.256014461 |
|
|
Sep 18 08:58:39 AM UTC 24 |
Sep 18 09:03:48 AM UTC 24 |
20852250237 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.613556456 |
|
|
Sep 18 08:58:26 AM UTC 24 |
Sep 18 09:03:49 AM UTC 24 |
3120954050 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3392385572 |
|
|
Sep 18 09:03:44 AM UTC 24 |
Sep 18 09:03:52 AM UTC 24 |
2258673524 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.3596926949 |
|
|
Sep 18 08:50:36 AM UTC 24 |
Sep 18 09:03:57 AM UTC 24 |
65734566571 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3310913425 |
|
|
Sep 18 08:33:23 AM UTC 24 |
Sep 18 09:03:59 AM UTC 24 |
112805059183 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2638306051 |
|
|
Sep 18 09:03:59 AM UTC 24 |
Sep 18 09:04:01 AM UTC 24 |
139273314 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.815591269 |
|
|
Sep 18 08:55:49 AM UTC 24 |
Sep 18 09:04:01 AM UTC 24 |
52470226592 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1274558230 |
|
|
Sep 18 09:04:02 AM UTC 24 |
Sep 18 09:04:07 AM UTC 24 |
353835930 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3393052889 |
|
|
Sep 18 08:59:50 AM UTC 24 |
Sep 18 09:04:07 AM UTC 24 |
8848845924 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3747187623 |
|
|
Sep 18 09:04:08 AM UTC 24 |
Sep 18 09:04:10 AM UTC 24 |
21074032 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3933651188 |
|
|
Sep 18 09:04:01 AM UTC 24 |
Sep 18 09:04:11 AM UTC 24 |
462434748 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2407378506 |
|
|
Sep 18 09:04:11 AM UTC 24 |
Sep 18 09:04:13 AM UTC 24 |
89710145 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3359534703 |
|
|
Sep 18 09:04:02 AM UTC 24 |
Sep 18 09:04:21 AM UTC 24 |
1657721507 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.820083784 |
|
|
Sep 18 09:03:28 AM UTC 24 |
Sep 18 09:04:28 AM UTC 24 |
19711367615 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1197014814 |
|
|
Sep 18 09:01:22 AM UTC 24 |
Sep 18 09:04:30 AM UTC 24 |
2454208007 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4169374958 |
|
|
Sep 18 09:02:34 AM UTC 24 |
Sep 18 09:04:32 AM UTC 24 |
2917876906 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3874580102 |
|
|
Sep 18 08:57:07 AM UTC 24 |
Sep 18 09:04:32 AM UTC 24 |
22145265094 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1041970979 |
|
|
Sep 18 08:54:46 AM UTC 24 |
Sep 18 09:04:32 AM UTC 24 |
1264097630 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.608368739 |
|
|
Sep 18 09:04:29 AM UTC 24 |
Sep 18 09:04:36 AM UTC 24 |
243576006 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1576719152 |
|
|
Sep 18 09:04:33 AM UTC 24 |
Sep 18 09:04:39 AM UTC 24 |
4379478206 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.715994074 |
|
|
Sep 18 09:05:13 AM UTC 24 |
Sep 18 09:05:31 AM UTC 24 |
179543203 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.3849409515 |
|
|
Sep 18 09:04:15 AM UTC 24 |
Sep 18 09:04:46 AM UTC 24 |
892816709 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3853802926 |
|
|
Sep 18 08:59:59 AM UTC 24 |
Sep 18 09:04:54 AM UTC 24 |
3694601478 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1460676955 |
|
|
Sep 18 09:04:55 AM UTC 24 |
Sep 18 09:04:58 AM UTC 24 |
26431763 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2274134133 |
|
|
Sep 18 08:43:29 AM UTC 24 |
Sep 18 09:05:05 AM UTC 24 |
14855713917 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2695482394 |
|
|
Sep 18 09:03:38 AM UTC 24 |
Sep 18 09:05:08 AM UTC 24 |
136548022 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3010857314 |
|
|
Sep 18 09:03:43 AM UTC 24 |
Sep 18 09:05:10 AM UTC 24 |
1684711270 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3658746569 |
|
|
Sep 18 09:04:59 AM UTC 24 |
Sep 18 09:05:11 AM UTC 24 |
263344967 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.92503331 |
|
|
Sep 18 09:05:06 AM UTC 24 |
Sep 18 09:05:12 AM UTC 24 |
104149507 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.917928761 |
|
|
Sep 18 09:05:12 AM UTC 24 |
Sep 18 09:05:14 AM UTC 24 |
141773266 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3987585105 |
|
|
Sep 18 09:04:33 AM UTC 24 |
Sep 18 09:05:22 AM UTC 24 |
542594155 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.24226597 |
|
|
Sep 18 08:58:19 AM UTC 24 |
Sep 18 09:05:37 AM UTC 24 |
11357936868 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.231571918 |
|
|
Sep 18 09:05:34 AM UTC 24 |
Sep 18 09:05:47 AM UTC 24 |
1442318960 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.40018634 |
|
|
Sep 18 09:05:09 AM UTC 24 |
Sep 18 09:05:47 AM UTC 24 |
365409847 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3922562722 |
|
|
Sep 18 09:03:12 AM UTC 24 |
Sep 18 09:06:01 AM UTC 24 |
3759719946 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.937383546 |
|
|
Sep 18 09:04:32 AM UTC 24 |
Sep 18 09:06:01 AM UTC 24 |
133852085 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2891227674 |
|
|
Sep 18 09:06:01 AM UTC 24 |
Sep 18 09:06:08 AM UTC 24 |
228702743 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2573854685 |
|
|
Sep 18 09:05:48 AM UTC 24 |
Sep 18 09:06:15 AM UTC 24 |
384463927 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2287661785 |
|
|
Sep 18 09:01:15 AM UTC 24 |
Sep 18 09:06:15 AM UTC 24 |
2949002694 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.351667814 |
|
|
Sep 18 08:44:54 AM UTC 24 |
Sep 18 09:06:17 AM UTC 24 |
4131592298 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.2964639914 |
|
|
Sep 18 09:06:17 AM UTC 24 |
Sep 18 09:06:18 AM UTC 24 |
208181133 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3830278819 |
|
|
Sep 18 08:59:46 AM UTC 24 |
Sep 18 09:06:19 AM UTC 24 |
6092225351 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3927406608 |
|
|
Sep 18 09:05:48 AM UTC 24 |
Sep 18 09:06:19 AM UTC 24 |
809712158 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.35510248 |
|
|
Sep 18 09:00:24 AM UTC 24 |
Sep 18 09:06:24 AM UTC 24 |
1332737789 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.813974754 |
|
|
Sep 18 09:06:17 AM UTC 24 |
Sep 18 09:06:26 AM UTC 24 |
2588990356 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1953369735 |
|
|
Sep 18 09:06:25 AM UTC 24 |
Sep 18 09:06:27 AM UTC 24 |
43708281 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3857645180 |
|
|
Sep 18 09:06:18 AM UTC 24 |
Sep 18 09:06:27 AM UTC 24 |
1384835926 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2192049001 |
|
|
Sep 18 09:06:20 AM UTC 24 |
Sep 18 09:06:29 AM UTC 24 |
386249180 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.1056015820 |
|
|
Sep 18 08:57:18 AM UTC 24 |
Sep 18 09:06:50 AM UTC 24 |
5232667385 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.4125483953 |
|
|
Sep 18 09:06:27 AM UTC 24 |
Sep 18 09:06:52 AM UTC 24 |
1095391079 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.776338930 |
|
|
Sep 18 09:04:47 AM UTC 24 |
Sep 18 09:06:52 AM UTC 24 |
8611505753 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2415459223 |
|
|
Sep 18 09:06:51 AM UTC 24 |
Sep 18 09:06:55 AM UTC 24 |
223059028 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.3439302978 |
|
|
Sep 18 08:57:27 AM UTC 24 |
Sep 18 09:07:02 AM UTC 24 |
3273435566 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.4039010816 |
|
|
Sep 18 09:05:23 AM UTC 24 |
Sep 18 09:07:05 AM UTC 24 |
3869546876 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.262294061 |
|
|
Sep 18 08:56:29 AM UTC 24 |
Sep 18 09:07:15 AM UTC 24 |
10174610564 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.919693415 |
|
|
Sep 18 09:07:03 AM UTC 24 |
Sep 18 09:07:16 AM UTC 24 |
1178436372 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2369721308 |
|
|
Sep 18 09:06:56 AM UTC 24 |
Sep 18 09:07:30 AM UTC 24 |
1786726981 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.129926355 |
|
|
Sep 18 09:07:31 AM UTC 24 |
Sep 18 09:07:33 AM UTC 24 |
37072511 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2757844611 |
|
|
Sep 18 09:06:28 AM UTC 24 |
Sep 18 09:07:36 AM UTC 24 |
3331832753 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1019370545 |
|
|
Sep 18 09:07:34 AM UTC 24 |
Sep 18 09:07:42 AM UTC 24 |
450525280 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1463404466 |
|
|
Sep 18 08:53:21 AM UTC 24 |
Sep 18 09:07:43 AM UTC 24 |
10126412835 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3369160521 |
|
|
Sep 18 09:07:36 AM UTC 24 |
Sep 18 09:07:45 AM UTC 24 |
665901163 ps |