| T545 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.195165548 |
|
|
Sep 18 09:07:45 AM UTC 24 |
Sep 18 09:07:47 AM UTC 24 |
47911372 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3475999874 |
|
|
Sep 18 08:55:07 AM UTC 24 |
Sep 18 09:07:53 AM UTC 24 |
103663211937 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.899928568 |
|
|
Sep 18 08:56:30 AM UTC 24 |
Sep 18 09:08:10 AM UTC 24 |
1972987829 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3080951589 |
|
|
Sep 18 09:03:30 AM UTC 24 |
Sep 18 09:08:11 AM UTC 24 |
9574926064 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2229802349 |
|
|
Sep 18 09:06:53 AM UTC 24 |
Sep 18 09:08:14 AM UTC 24 |
498646179 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2438446156 |
|
|
Sep 18 09:03:33 AM UTC 24 |
Sep 18 09:08:17 AM UTC 24 |
9205547346 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.2906734304 |
|
|
Sep 18 08:57:28 AM UTC 24 |
Sep 18 09:08:22 AM UTC 24 |
12578244164 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1053145763 |
|
|
Sep 18 09:08:22 AM UTC 24 |
Sep 18 09:08:37 AM UTC 24 |
263566268 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.4110495883 |
|
|
Sep 18 09:08:11 AM UTC 24 |
Sep 18 09:08:37 AM UTC 24 |
913737842 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3113349359 |
|
|
Sep 18 09:08:16 AM UTC 24 |
Sep 18 09:08:46 AM UTC 24 |
4088110603 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.91632215 |
|
|
Sep 18 09:04:31 AM UTC 24 |
Sep 18 09:08:50 AM UTC 24 |
9331202984 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3551360814 |
|
|
Sep 18 09:08:38 AM UTC 24 |
Sep 18 09:08:55 AM UTC 24 |
3680669934 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1217023533 |
|
|
Sep 18 09:05:32 AM UTC 24 |
Sep 18 09:09:05 AM UTC 24 |
1820103742 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3630325281 |
|
|
Sep 18 09:09:06 AM UTC 24 |
Sep 18 09:09:08 AM UTC 24 |
93788655 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.1003599909 |
|
|
Sep 18 09:03:49 AM UTC 24 |
Sep 18 09:09:13 AM UTC 24 |
5317619084 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.439722636 |
|
|
Sep 18 09:09:09 AM UTC 24 |
Sep 18 09:09:18 AM UTC 24 |
459196363 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1956914162 |
|
|
Sep 18 09:09:14 AM UTC 24 |
Sep 18 09:09:21 AM UTC 24 |
508881823 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.4202412690 |
|
|
Sep 18 09:07:48 AM UTC 24 |
Sep 18 09:09:30 AM UTC 24 |
631440440 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3444758253 |
|
|
Sep 18 09:09:31 AM UTC 24 |
Sep 18 09:09:34 AM UTC 24 |
51403152 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.2793052331 |
|
|
Sep 18 09:09:35 AM UTC 24 |
Sep 18 09:09:43 AM UTC 24 |
143290942 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2105140438 |
|
|
Sep 18 08:25:37 AM UTC 24 |
Sep 18 09:09:50 AM UTC 24 |
70083257473 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.4262252995 |
|
|
Sep 18 09:05:38 AM UTC 24 |
Sep 18 09:09:50 AM UTC 24 |
11866979573 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.802906199 |
|
|
Sep 18 09:06:53 AM UTC 24 |
Sep 18 09:09:55 AM UTC 24 |
8879246609 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3990911696 |
|
|
Sep 18 09:09:56 AM UTC 24 |
Sep 18 09:10:08 AM UTC 24 |
710585398 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.642905794 |
|
|
Sep 18 09:09:51 AM UTC 24 |
Sep 18 09:10:19 AM UTC 24 |
1328260545 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1708544082 |
|
|
Sep 18 09:08:38 AM UTC 24 |
Sep 18 09:10:24 AM UTC 24 |
157246160 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1837952982 |
|
|
Sep 18 09:10:25 AM UTC 24 |
Sep 18 09:10:35 AM UTC 24 |
1364889988 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.2170396725 |
|
|
Sep 18 08:44:10 AM UTC 24 |
Sep 18 09:10:44 AM UTC 24 |
115099712327 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2848265020 |
|
|
Sep 18 09:10:20 AM UTC 24 |
Sep 18 09:10:53 AM UTC 24 |
191401735 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3899372349 |
|
|
Sep 18 09:06:20 AM UTC 24 |
Sep 18 09:11:22 AM UTC 24 |
900951474 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3857441593 |
|
|
Sep 18 08:31:23 AM UTC 24 |
Sep 18 09:11:25 AM UTC 24 |
34791005673 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1097339452 |
|
|
Sep 18 09:11:23 AM UTC 24 |
Sep 18 09:11:25 AM UTC 24 |
226697741 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3236284273 |
|
|
Sep 18 09:04:22 AM UTC 24 |
Sep 18 09:11:28 AM UTC 24 |
15739222450 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2841156223 |
|
|
Sep 18 09:11:26 AM UTC 24 |
Sep 18 09:11:33 AM UTC 24 |
335627926 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3612034287 |
|
|
Sep 18 09:10:17 AM UTC 24 |
Sep 18 09:11:39 AM UTC 24 |
471538794 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2412682351 |
|
|
Sep 18 09:11:25 AM UTC 24 |
Sep 18 09:11:40 AM UTC 24 |
912693527 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.3698592065 |
|
|
Sep 18 09:11:41 AM UTC 24 |
Sep 18 09:11:43 AM UTC 24 |
45672467 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2624519049 |
|
|
Sep 18 09:10:54 AM UTC 24 |
Sep 18 09:12:03 AM UTC 24 |
286875701 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.3849218917 |
|
|
Sep 18 08:56:32 AM UTC 24 |
Sep 18 09:12:35 AM UTC 24 |
112070776508 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.3682145305 |
|
|
Sep 18 09:12:03 AM UTC 24 |
Sep 18 09:12:40 AM UTC 24 |
9637419935 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3808747999 |
|
|
Sep 18 09:12:41 AM UTC 24 |
Sep 18 09:12:46 AM UTC 24 |
43719635 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1011901378 |
|
|
Sep 18 09:00:30 AM UTC 24 |
Sep 18 09:12:52 AM UTC 24 |
1927861290 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.981683494 |
|
|
Sep 18 09:01:51 AM UTC 24 |
Sep 18 09:12:59 AM UTC 24 |
12919890079 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2105080416 |
|
|
Sep 18 09:12:57 AM UTC 24 |
Sep 18 09:13:02 AM UTC 24 |
181713385 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1547759734 |
|
|
Sep 18 09:12:53 AM UTC 24 |
Sep 18 09:13:07 AM UTC 24 |
142438505 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.330880228 |
|
|
Sep 18 08:44:58 AM UTC 24 |
Sep 18 09:13:20 AM UTC 24 |
28607216155 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3903654410 |
|
|
Sep 18 09:13:20 AM UTC 24 |
Sep 18 09:13:22 AM UTC 24 |
28367510 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2588010747 |
|
|
Sep 18 09:09:51 AM UTC 24 |
Sep 18 09:13:24 AM UTC 24 |
6870078748 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3022953432 |
|
|
Sep 18 09:12:53 AM UTC 24 |
Sep 18 09:13:26 AM UTC 24 |
107463159 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2928081709 |
|
|
Sep 18 08:54:39 AM UTC 24 |
Sep 18 09:13:29 AM UTC 24 |
3642302040 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3516723724 |
|
|
Sep 18 09:13:24 AM UTC 24 |
Sep 18 09:13:33 AM UTC 24 |
338242518 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.357158550 |
|
|
Sep 18 09:13:34 AM UTC 24 |
Sep 18 09:13:36 AM UTC 24 |
13418444 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3743606946 |
|
|
Sep 18 09:02:11 AM UTC 24 |
Sep 18 09:13:37 AM UTC 24 |
12124561152 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3417381145 |
|
|
Sep 18 09:13:23 AM UTC 24 |
Sep 18 09:13:41 AM UTC 24 |
1527619189 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.2966343314 |
|
|
Sep 18 09:13:37 AM UTC 24 |
Sep 18 09:13:47 AM UTC 24 |
95062160 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.2339384999 |
|
|
Sep 18 09:11:41 AM UTC 24 |
Sep 18 09:13:49 AM UTC 24 |
2697929380 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.1524871138 |
|
|
Sep 18 08:59:14 AM UTC 24 |
Sep 18 09:13:52 AM UTC 24 |
6371131311 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2971531290 |
|
|
Sep 18 09:06:28 AM UTC 24 |
Sep 18 09:14:08 AM UTC 24 |
12496326049 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3610690980 |
|
|
Sep 18 09:13:54 AM UTC 24 |
Sep 18 09:14:15 AM UTC 24 |
149478567 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2267533143 |
|
|
Sep 18 09:14:16 AM UTC 24 |
Sep 18 09:14:23 AM UTC 24 |
459482639 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2825415033 |
|
|
Sep 18 09:13:42 AM UTC 24 |
Sep 18 09:14:24 AM UTC 24 |
975986237 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1805473047 |
|
|
Sep 18 08:49:05 AM UTC 24 |
Sep 18 09:14:36 AM UTC 24 |
137443717864 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.449074709 |
|
|
Sep 18 09:08:18 AM UTC 24 |
Sep 18 09:14:49 AM UTC 24 |
19325799704 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.711357788 |
|
|
Sep 18 09:08:13 AM UTC 24 |
Sep 18 09:14:51 AM UTC 24 |
12323335670 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3410732301 |
|
|
Sep 18 09:14:49 AM UTC 24 |
Sep 18 09:14:52 AM UTC 24 |
84920981 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1848248068 |
|
|
Sep 18 09:13:49 AM UTC 24 |
Sep 18 09:14:54 AM UTC 24 |
4235708266 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2200343349 |
|
|
Sep 18 08:56:47 AM UTC 24 |
Sep 18 09:14:57 AM UTC 24 |
14875399249 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.1239275856 |
|
|
Sep 18 09:10:45 AM UTC 24 |
Sep 18 09:14:57 AM UTC 24 |
6971090371 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2496580736 |
|
|
Sep 18 09:14:53 AM UTC 24 |
Sep 18 09:14:57 AM UTC 24 |
119770516 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.303736586 |
|
|
Sep 18 09:14:58 AM UTC 24 |
Sep 18 09:15:00 AM UTC 24 |
20819189 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1525640015 |
|
|
Sep 18 09:14:51 AM UTC 24 |
Sep 18 09:15:07 AM UTC 24 |
766673272 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2914671110 |
|
|
Sep 18 08:23:46 AM UTC 24 |
Sep 18 09:15:14 AM UTC 24 |
19044584840 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.2333321575 |
|
|
Sep 18 09:14:58 AM UTC 24 |
Sep 18 09:15:14 AM UTC 24 |
400634056 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.394103439 |
|
|
Sep 18 09:14:09 AM UTC 24 |
Sep 18 09:15:16 AM UTC 24 |
133094928 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.4046818899 |
|
|
Sep 18 09:14:25 AM UTC 24 |
Sep 18 09:15:20 AM UTC 24 |
2014089232 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.4034770467 |
|
|
Sep 18 09:15:21 AM UTC 24 |
Sep 18 09:15:33 AM UTC 24 |
1106251359 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1054271177 |
|
|
Sep 18 09:15:15 AM UTC 24 |
Sep 18 09:15:33 AM UTC 24 |
821173516 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2110773934 |
|
|
Sep 18 09:06:30 AM UTC 24 |
Sep 18 09:15:35 AM UTC 24 |
4220056173 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1920306529 |
|
|
Sep 18 09:15:33 AM UTC 24 |
Sep 18 09:15:38 AM UTC 24 |
316624578 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.4242825933 |
|
|
Sep 18 09:15:34 AM UTC 24 |
Sep 18 09:15:41 AM UTC 24 |
283658538 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3497829188 |
|
|
Sep 18 09:15:42 AM UTC 24 |
Sep 18 09:15:44 AM UTC 24 |
28160567 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.4180373381 |
|
|
Sep 18 09:00:21 AM UTC 24 |
Sep 18 09:15:47 AM UTC 24 |
3225537720 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3563018416 |
|
|
Sep 18 09:15:48 AM UTC 24 |
Sep 18 09:15:54 AM UTC 24 |
108397692 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2131259115 |
|
|
Sep 18 09:15:45 AM UTC 24 |
Sep 18 09:15:59 AM UTC 24 |
461631065 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.319541451 |
|
|
Sep 18 09:15:55 AM UTC 24 |
Sep 18 09:16:06 AM UTC 24 |
860141162 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1418551686 |
|
|
Sep 18 09:16:07 AM UTC 24 |
Sep 18 09:16:09 AM UTC 24 |
14057430 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.1842819439 |
|
|
Sep 18 09:15:07 AM UTC 24 |
Sep 18 09:16:19 AM UTC 24 |
9688962937 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2007537766 |
|
|
Sep 18 09:10:09 AM UTC 24 |
Sep 18 09:16:20 AM UTC 24 |
18223400722 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.1530178455 |
|
|
Sep 18 09:16:09 AM UTC 24 |
Sep 18 09:16:24 AM UTC 24 |
555067213 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1702935851 |
|
|
Sep 18 09:09:45 AM UTC 24 |
Sep 18 09:16:30 AM UTC 24 |
8699931162 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2807574119 |
|
|
Sep 18 09:07:15 AM UTC 24 |
Sep 18 09:16:35 AM UTC 24 |
2550702197 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4247724812 |
|
|
Sep 18 09:16:31 AM UTC 24 |
Sep 18 09:16:37 AM UTC 24 |
213450063 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.983037263 |
|
|
Sep 18 09:08:51 AM UTC 24 |
Sep 18 09:16:41 AM UTC 24 |
9155717313 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3478653525 |
|
|
Sep 18 09:01:01 AM UTC 24 |
Sep 18 09:16:53 AM UTC 24 |
13722164693 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3767731153 |
|
|
Sep 18 09:16:43 AM UTC 24 |
Sep 18 09:16:55 AM UTC 24 |
1008227943 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3135531269 |
|
|
Sep 18 09:16:50 AM UTC 24 |
Sep 18 09:16:55 AM UTC 24 |
206281389 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1161871613 |
|
|
Sep 18 09:07:53 AM UTC 24 |
Sep 18 09:16:57 AM UTC 24 |
28179446056 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2960909669 |
|
|
Sep 18 09:14:55 AM UTC 24 |
Sep 18 09:16:59 AM UTC 24 |
6932617798 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.481232560 |
|
|
Sep 18 09:16:21 AM UTC 24 |
Sep 18 09:17:00 AM UTC 24 |
5465559098 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.689368550 |
|
|
Sep 18 09:16:59 AM UTC 24 |
Sep 18 09:17:01 AM UTC 24 |
166543642 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.1886147616 |
|
|
Sep 18 09:17:01 AM UTC 24 |
Sep 18 09:17:07 AM UTC 24 |
228845534 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1664104022 |
|
|
Sep 18 09:17:01 AM UTC 24 |
Sep 18 09:17:08 AM UTC 24 |
1313906387 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.4255864330 |
|
|
Sep 18 09:17:08 AM UTC 24 |
Sep 18 09:17:10 AM UTC 24 |
11502178 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2405709706 |
|
|
Sep 18 09:12:36 AM UTC 24 |
Sep 18 09:17:18 AM UTC 24 |
40457879569 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.1786034240 |
|
|
Sep 18 09:10:36 AM UTC 24 |
Sep 18 09:17:34 AM UTC 24 |
35098305635 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1698066036 |
|
|
Sep 18 09:17:03 AM UTC 24 |
Sep 18 09:17:35 AM UTC 24 |
1152760056 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2859718949 |
|
|
Sep 18 09:17:12 AM UTC 24 |
Sep 18 09:17:39 AM UTC 24 |
407387309 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3055517060 |
|
|
Sep 18 09:17:36 AM UTC 24 |
Sep 18 09:17:45 AM UTC 24 |
606540201 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1022929340 |
|
|
Sep 18 09:15:01 AM UTC 24 |
Sep 18 09:17:51 AM UTC 24 |
3115726544 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.722973220 |
|
|
Sep 18 09:13:07 AM UTC 24 |
Sep 18 09:17:52 AM UTC 24 |
26488450324 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.4199509306 |
|
|
Sep 18 09:17:52 AM UTC 24 |
Sep 18 09:17:57 AM UTC 24 |
141228843 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.803822850 |
|
|
Sep 18 09:16:38 AM UTC 24 |
Sep 18 09:18:15 AM UTC 24 |
521053190 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1253941942 |
|
|
Sep 18 09:17:46 AM UTC 24 |
Sep 18 09:18:22 AM UTC 24 |
912059040 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2537905567 |
|
|
Sep 18 09:17:19 AM UTC 24 |
Sep 18 09:18:22 AM UTC 24 |
3024052905 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3442035205 |
|
|
Sep 18 09:06:02 AM UTC 24 |
Sep 18 09:18:25 AM UTC 24 |
4411346845 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2409204120 |
|
|
Sep 18 09:18:23 AM UTC 24 |
Sep 18 09:18:25 AM UTC 24 |
72437091 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1802611919 |
|
|
Sep 18 09:18:25 AM UTC 24 |
Sep 18 09:18:29 AM UTC 24 |
86233974 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2334535459 |
|
|
Sep 18 09:13:47 AM UTC 24 |
Sep 18 09:18:30 AM UTC 24 |
5383649467 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2162610649 |
|
|
Sep 18 09:18:23 AM UTC 24 |
Sep 18 09:18:32 AM UTC 24 |
4135297107 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1741860009 |
|
|
Sep 18 09:18:31 AM UTC 24 |
Sep 18 09:18:33 AM UTC 24 |
11146315 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.678913458 |
|
|
Sep 18 09:17:51 AM UTC 24 |
Sep 18 09:18:50 AM UTC 24 |
853200173 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.275967509 |
|
|
Sep 18 09:18:26 AM UTC 24 |
Sep 18 09:18:51 AM UTC 24 |
200430086 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.213120406 |
|
|
Sep 18 09:04:12 AM UTC 24 |
Sep 18 09:19:09 AM UTC 24 |
4238633347 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1247311475 |
|
|
Sep 18 09:03:49 AM UTC 24 |
Sep 18 09:19:11 AM UTC 24 |
3784988528 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.3897397617 |
|
|
Sep 18 09:18:33 AM UTC 24 |
Sep 18 09:19:25 AM UTC 24 |
424073863 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.2741447112 |
|
|
Sep 18 09:15:15 AM UTC 24 |
Sep 18 09:19:27 AM UTC 24 |
3916252033 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2846761997 |
|
|
Sep 18 09:19:09 AM UTC 24 |
Sep 18 09:19:31 AM UTC 24 |
535481473 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1177379114 |
|
|
Sep 18 09:19:25 AM UTC 24 |
Sep 18 09:19:32 AM UTC 24 |
175644413 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1086793061 |
|
|
Sep 18 09:19:33 AM UTC 24 |
Sep 18 09:19:41 AM UTC 24 |
1989508628 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2448753889 |
|
|
Sep 18 09:16:54 AM UTC 24 |
Sep 18 09:19:55 AM UTC 24 |
6564524408 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2633664854 |
|
|
Sep 18 09:17:35 AM UTC 24 |
Sep 18 09:20:15 AM UTC 24 |
22442511538 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2131359487 |
|
|
Sep 18 09:20:16 AM UTC 24 |
Sep 18 09:20:18 AM UTC 24 |
70973630 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2131138211 |
|
|
Sep 18 09:20:19 AM UTC 24 |
Sep 18 09:20:29 AM UTC 24 |
1391082665 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.4018201357 |
|
|
Sep 18 09:18:51 AM UTC 24 |
Sep 18 09:20:31 AM UTC 24 |
4049775100 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.3249082850 |
|
|
Sep 18 09:19:28 AM UTC 24 |
Sep 18 09:20:32 AM UTC 24 |
364423035 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.4212693062 |
|
|
Sep 18 09:20:29 AM UTC 24 |
Sep 18 09:20:38 AM UTC 24 |
92567533 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.279910836 |
|
|
Sep 18 09:04:37 AM UTC 24 |
Sep 18 09:20:40 AM UTC 24 |
13732585087 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.935971930 |
|
|
Sep 18 09:20:39 AM UTC 24 |
Sep 18 09:20:41 AM UTC 24 |
60373700 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.4233301343 |
|
|
Sep 18 09:15:18 AM UTC 24 |
Sep 18 09:20:46 AM UTC 24 |
56362880348 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3863127818 |
|
|
Sep 18 09:13:38 AM UTC 24 |
Sep 18 09:20:51 AM UTC 24 |
5900620628 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3882155080 |
|
|
Sep 18 09:20:31 AM UTC 24 |
Sep 18 09:21:12 AM UTC 24 |
3340316748 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.4293131790 |
|
|
Sep 18 09:13:00 AM UTC 24 |
Sep 18 09:21:19 AM UTC 24 |
5447917700 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1404555018 |
|
|
Sep 18 09:21:13 AM UTC 24 |
Sep 18 09:21:24 AM UTC 24 |
511635913 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1024428479 |
|
|
Sep 18 09:13:54 AM UTC 24 |
Sep 18 09:21:29 AM UTC 24 |
65001983044 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3154287289 |
|
|
Sep 18 09:21:25 AM UTC 24 |
Sep 18 09:21:31 AM UTC 24 |
101710693 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.4261965881 |
|
|
Sep 18 09:20:47 AM UTC 24 |
Sep 18 09:21:33 AM UTC 24 |
8608702574 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2098290976 |
|
|
Sep 18 09:21:33 AM UTC 24 |
Sep 18 09:21:45 AM UTC 24 |
2042570840 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2468399675 |
|
|
Sep 18 09:21:46 AM UTC 24 |
Sep 18 09:22:08 AM UTC 24 |
2873154032 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1231319461 |
|
|
Sep 18 09:20:41 AM UTC 24 |
Sep 18 09:22:09 AM UTC 24 |
134235005 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2099241046 |
|
|
Sep 18 09:22:10 AM UTC 24 |
Sep 18 09:22:13 AM UTC 24 |
127094658 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3278137760 |
|
|
Sep 18 09:22:13 AM UTC 24 |
Sep 18 09:22:26 AM UTC 24 |
278585583 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.829934463 |
|
|
Sep 18 09:22:27 AM UTC 24 |
Sep 18 09:22:32 AM UTC 24 |
220562140 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3170953527 |
|
|
Sep 18 09:16:25 AM UTC 24 |
Sep 18 09:22:33 AM UTC 24 |
6524425561 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.4159182424 |
|
|
Sep 18 09:21:30 AM UTC 24 |
Sep 18 09:22:48 AM UTC 24 |
289568408 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1097570514 |
|
|
Sep 18 09:08:47 AM UTC 24 |
Sep 18 09:22:50 AM UTC 24 |
10899751659 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2287050208 |
|
|
Sep 18 09:22:49 AM UTC 24 |
Sep 18 09:22:51 AM UTC 24 |
18336614 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1150589038 |
|
|
Sep 18 09:16:36 AM UTC 24 |
Sep 18 09:23:04 AM UTC 24 |
14940738059 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3637175195 |
|
|
Sep 18 09:22:51 AM UTC 24 |
Sep 18 09:23:10 AM UTC 24 |
2114058491 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.2722890137 |
|
|
Sep 18 09:07:17 AM UTC 24 |
Sep 18 09:23:13 AM UTC 24 |
29748825721 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.2568561912 |
|
|
Sep 18 09:23:05 AM UTC 24 |
Sep 18 09:23:28 AM UTC 24 |
1180950068 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3017462172 |
|
|
Sep 18 09:23:15 AM UTC 24 |
Sep 18 09:23:28 AM UTC 24 |
176568165 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.767778711 |
|
|
Sep 18 09:17:12 AM UTC 24 |
Sep 18 09:23:30 AM UTC 24 |
7447144157 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2860825878 |
|
|
Sep 18 09:22:33 AM UTC 24 |
Sep 18 09:23:33 AM UTC 24 |
3476128603 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.39442209 |
|
|
Sep 18 09:23:31 AM UTC 24 |
Sep 18 09:23:35 AM UTC 24 |
146483869 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1961594606 |
|
|
Sep 18 09:15:34 AM UTC 24 |
Sep 18 09:23:37 AM UTC 24 |
2312181813 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1566439678 |
|
|
Sep 18 09:23:33 AM UTC 24 |
Sep 18 09:23:42 AM UTC 24 |
649543979 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2384355154 |
|
|
Sep 18 09:23:29 AM UTC 24 |
Sep 18 09:23:42 AM UTC 24 |
125309051 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.70085601 |
|
|
Sep 18 09:18:52 AM UTC 24 |
Sep 18 09:23:44 AM UTC 24 |
2919105840 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3755406397 |
|
|
Sep 18 09:23:43 AM UTC 24 |
Sep 18 09:23:46 AM UTC 24 |
52700141 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.520308150 |
|
|
Sep 18 09:23:44 AM UTC 24 |
Sep 18 09:23:51 AM UTC 24 |
1397391562 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1991393750 |
|
|
Sep 18 09:12:46 AM UTC 24 |
Sep 18 09:23:53 AM UTC 24 |
168346042733 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2283599385 |
|
|
Sep 18 09:23:47 AM UTC 24 |
Sep 18 09:23:55 AM UTC 24 |
177710265 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1532949784 |
|
|
Sep 18 09:23:56 AM UTC 24 |
Sep 18 09:23:58 AM UTC 24 |
22746934 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.4199322355 |
|
|
Sep 18 09:16:19 AM UTC 24 |
Sep 18 09:24:11 AM UTC 24 |
2737186436 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.1498598902 |
|
|
Sep 18 09:06:08 AM UTC 24 |
Sep 18 09:24:20 AM UTC 24 |
59773468132 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1581810456 |
|
|
Sep 18 08:58:14 AM UTC 24 |
Sep 18 09:24:45 AM UTC 24 |
5274077463 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1572645316 |
|
|
Sep 18 09:23:59 AM UTC 24 |
Sep 18 09:24:46 AM UTC 24 |
459601180 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.3141052713 |
|
|
Sep 18 09:04:39 AM UTC 24 |
Sep 18 09:24:52 AM UTC 24 |
84739922019 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3928453764 |
|
|
Sep 18 09:24:20 AM UTC 24 |
Sep 18 09:24:52 AM UTC 24 |
503182549 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2327221168 |
|
|
Sep 18 09:24:48 AM UTC 24 |
Sep 18 09:24:53 AM UTC 24 |
132585066 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2414426653 |
|
|
Sep 18 09:13:03 AM UTC 24 |
Sep 18 09:24:53 AM UTC 24 |
11712024462 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.860164113 |
|
|
Sep 18 09:24:54 AM UTC 24 |
Sep 18 09:24:56 AM UTC 24 |
40530626 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2346638218 |
|
|
Sep 18 09:24:54 AM UTC 24 |
Sep 18 09:25:23 AM UTC 24 |
89730241 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.751106490 |
|
|
Sep 18 09:14:36 AM UTC 24 |
Sep 18 09:25:25 AM UTC 24 |
80111476342 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2060564174 |
|
|
Sep 18 09:05:10 AM UTC 24 |
Sep 18 09:25:30 AM UTC 24 |
6109029464 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1304551670 |
|
|
Sep 18 09:25:30 AM UTC 24 |
Sep 18 09:25:32 AM UTC 24 |
31729994 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.624585554 |
|
|
Sep 18 09:21:20 AM UTC 24 |
Sep 18 09:25:35 AM UTC 24 |
11451131240 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.4072777399 |
|
|
Sep 18 09:15:39 AM UTC 24 |
Sep 18 09:25:36 AM UTC 24 |
2924336423 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.282977935 |
|
|
Sep 18 09:23:10 AM UTC 24 |
Sep 18 09:25:37 AM UTC 24 |
1916724583 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.814173784 |
|
|
Sep 18 09:25:36 AM UTC 24 |
Sep 18 09:25:44 AM UTC 24 |
342130562 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1310357127 |
|
|
Sep 18 09:25:34 AM UTC 24 |
Sep 18 09:25:44 AM UTC 24 |
252887312 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2922477269 |
|
|
Sep 18 08:36:55 AM UTC 24 |
Sep 18 09:25:47 AM UTC 24 |
72291048681 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.865202768 |
|
|
Sep 18 09:25:45 AM UTC 24 |
Sep 18 09:25:47 AM UTC 24 |
23635348 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2538859089 |
|
|
Sep 18 09:25:45 AM UTC 24 |
Sep 18 09:26:03 AM UTC 24 |
2251292941 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.974671062 |
|
|
Sep 18 09:24:11 AM UTC 24 |
Sep 18 09:26:13 AM UTC 24 |
3519803267 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1415616271 |
|
|
Sep 18 09:24:53 AM UTC 24 |
Sep 18 09:26:14 AM UTC 24 |
244744000 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2913468601 |
|
|
Sep 18 09:19:12 AM UTC 24 |
Sep 18 09:26:15 AM UTC 24 |
58427303688 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.4101157835 |
|
|
Sep 18 09:17:54 AM UTC 24 |
Sep 18 09:26:26 AM UTC 24 |
3491278087 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.48655103 |
|
|
Sep 18 09:26:16 AM UTC 24 |
Sep 18 09:26:28 AM UTC 24 |
66191301 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1256057290 |
|
|
Sep 18 09:26:15 AM UTC 24 |
Sep 18 09:26:31 AM UTC 24 |
608915998 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.4100640333 |
|
|
Sep 18 09:25:48 AM UTC 24 |
Sep 18 09:26:35 AM UTC 24 |
1711255082 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1243930567 |
|
|
Sep 18 09:26:29 AM UTC 24 |
Sep 18 09:26:38 AM UTC 24 |
991516951 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2085864137 |
|
|
Sep 18 09:07:06 AM UTC 24 |
Sep 18 09:26:48 AM UTC 24 |
23681827444 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.265903731 |
|
|
Sep 18 09:26:48 AM UTC 24 |
Sep 18 09:26:51 AM UTC 24 |
28118878 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2222827096 |
|
|
Sep 18 09:05:15 AM UTC 24 |
Sep 18 09:26:55 AM UTC 24 |
3628203194 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1362422468 |
|
|
Sep 18 09:26:52 AM UTC 24 |
Sep 18 09:26:57 AM UTC 24 |
73192848 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2856156644 |
|
|
Sep 18 09:17:40 AM UTC 24 |
Sep 18 09:27:01 AM UTC 24 |
26640467185 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3441162466 |
|
|
Sep 18 09:26:57 AM UTC 24 |
Sep 18 09:27:02 AM UTC 24 |
113890797 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3843407384 |
|
|
Sep 18 09:27:03 AM UTC 24 |
Sep 18 09:27:05 AM UTC 24 |
13377820 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4029294492 |
|
|
Sep 18 09:26:58 AM UTC 24 |
Sep 18 09:27:10 AM UTC 24 |
2241985657 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.4088255434 |
|
|
Sep 18 08:59:42 AM UTC 24 |
Sep 18 09:27:16 AM UTC 24 |
6152425635 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.1337414457 |
|
|
Sep 18 09:27:06 AM UTC 24 |
Sep 18 09:27:23 AM UTC 24 |
197271252 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.1047987935 |
|
|
Sep 18 09:22:09 AM UTC 24 |
Sep 18 09:27:24 AM UTC 24 |
1759954709 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1130195681 |
|
|
Sep 18 09:26:28 AM UTC 24 |
Sep 18 09:27:38 AM UTC 24 |
662938672 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.660412906 |
|
|
Sep 18 09:27:26 AM UTC 24 |
Sep 18 09:27:43 AM UTC 24 |
3113609642 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.335081761 |
|
|
Sep 18 09:27:44 AM UTC 24 |
Sep 18 09:27:55 AM UTC 24 |
80572919 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2805393508 |
|
|
Sep 18 09:14:24 AM UTC 24 |
Sep 18 09:28:05 AM UTC 24 |
16195366631 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.200541826 |
|
|
Sep 18 09:24:45 AM UTC 24 |
Sep 18 09:28:06 AM UTC 24 |
7633229848 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2845563671 |
|
|
Sep 18 09:28:06 AM UTC 24 |
Sep 18 09:28:15 AM UTC 24 |
614957873 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.631368152 |
|
|
Sep 18 09:27:17 AM UTC 24 |
Sep 18 09:28:21 AM UTC 24 |
4008026542 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2767064118 |
|
|
Sep 18 09:18:16 AM UTC 24 |
Sep 18 09:28:22 AM UTC 24 |
1767026065 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1575690593 |
|
|
Sep 18 09:09:22 AM UTC 24 |
Sep 18 09:28:22 AM UTC 24 |
53054474283 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.259686367 |
|
|
Sep 18 09:17:58 AM UTC 24 |
Sep 18 09:28:25 AM UTC 24 |
17274966399 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1032043070 |
|
|
Sep 18 09:28:24 AM UTC 24 |
Sep 18 09:28:26 AM UTC 24 |
29441184 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3078060380 |
|
|
Sep 18 09:28:26 AM UTC 24 |
Sep 18 09:28:31 AM UTC 24 |
113258382 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2144054422 |
|
|
Sep 18 09:28:24 AM UTC 24 |
Sep 18 09:28:32 AM UTC 24 |
228924515 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1550644379 |
|
|
Sep 18 09:28:33 AM UTC 24 |
Sep 18 09:28:35 AM UTC 24 |
16830720 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.884797049 |
|
|
Sep 18 09:28:36 AM UTC 24 |
Sep 18 09:28:39 AM UTC 24 |
33059080 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.833669580 |
|
|
Sep 18 09:28:27 AM UTC 24 |
Sep 18 09:28:54 AM UTC 24 |
1702794543 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.314075776 |
|
|
Sep 18 09:27:56 AM UTC 24 |
Sep 18 09:28:57 AM UTC 24 |
288834402 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3070498831 |
|
|
Sep 18 09:20:51 AM UTC 24 |
Sep 18 09:29:08 AM UTC 24 |
4094410319 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3659128408 |
|
|
Sep 18 09:18:35 AM UTC 24 |
Sep 18 09:29:11 AM UTC 24 |
4839059114 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1437814722 |
|
|
Sep 18 08:56:41 AM UTC 24 |
Sep 18 09:29:32 AM UTC 24 |
101136380530 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.109018301 |
|
|
Sep 18 09:23:29 AM UTC 24 |
Sep 18 09:29:38 AM UTC 24 |
4671708273 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.125883479 |
|
|
Sep 18 09:02:34 AM UTC 24 |
Sep 18 09:29:44 AM UTC 24 |
40060166451 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.2032629533 |
|
|
Sep 18 09:16:57 AM UTC 24 |
Sep 18 09:29:58 AM UTC 24 |
77424907610 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.362669543 |
|
|
Sep 18 09:28:55 AM UTC 24 |
Sep 18 09:30:01 AM UTC 24 |
3131189231 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3609840676 |
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|
Sep 18 09:29:45 AM UTC 24 |
Sep 18 09:30:04 AM UTC 24 |
1010234322 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.4183029912 |
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Sep 18 09:29:39 AM UTC 24 |
Sep 18 09:30:11 AM UTC 24 |
395196918 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3749763905 |
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Sep 18 09:30:12 AM UTC 24 |
Sep 18 09:30:14 AM UTC 24 |
30170128 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1092122854 |
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Sep 18 09:30:15 AM UTC 24 |
Sep 18 09:30:29 AM UTC 24 |
449517331 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.4275094670 |
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Sep 18 09:16:57 AM UTC 24 |
Sep 18 09:30:32 AM UTC 24 |
53112351519 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.1146603822 |
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Sep 18 09:08:57 AM UTC 24 |
Sep 18 09:30:33 AM UTC 24 |
16931785569 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2807754697 |
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Sep 18 09:30:31 AM UTC 24 |
Sep 18 09:30:37 AM UTC 24 |
374385317 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1236154158 |
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Sep 18 09:30:37 AM UTC 24 |
Sep 18 09:30:39 AM UTC 24 |
42850669 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1151680047 |
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Sep 18 09:29:10 AM UTC 24 |
Sep 18 09:30:43 AM UTC 24 |
421384498 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.915089427 |
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Sep 18 09:26:03 AM UTC 24 |
Sep 18 09:31:14 AM UTC 24 |
11623753960 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.689470995 |
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Sep 18 09:25:37 AM UTC 24 |
Sep 18 09:31:14 AM UTC 24 |
1969985741 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1796889207 |
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Sep 18 09:13:28 AM UTC 24 |
Sep 18 09:31:20 AM UTC 24 |
5801408085 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.769214072 |
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Sep 18 09:29:33 AM UTC 24 |
Sep 18 09:31:24 AM UTC 24 |
268972902 ps |