| T792 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.3181746423 |
|
|
Sep 18 09:19:57 AM UTC 24 |
Sep 18 09:31:31 AM UTC 24 |
42221302649 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1511444506 |
|
|
Sep 18 08:53:09 AM UTC 24 |
Sep 18 09:31:46 AM UTC 24 |
70145600399 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.217609287 |
|
|
Sep 18 09:31:46 AM UTC 24 |
Sep 18 09:31:58 AM UTC 24 |
267116396 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3370119771 |
|
|
Sep 18 09:19:33 AM UTC 24 |
Sep 18 09:32:03 AM UTC 24 |
11695407243 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.542485284 |
|
|
Sep 18 09:31:56 AM UTC 24 |
Sep 18 09:32:04 AM UTC 24 |
345463368 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1048084435 |
|
|
Sep 18 09:11:44 AM UTC 24 |
Sep 18 09:32:19 AM UTC 24 |
47118224728 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2160158172 |
|
|
Sep 18 09:32:20 AM UTC 24 |
Sep 18 09:32:23 AM UTC 24 |
27947903 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3647724285 |
|
|
Sep 18 08:55:03 AM UTC 24 |
Sep 18 09:32:34 AM UTC 24 |
35613638370 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2438837570 |
|
|
Sep 18 09:32:24 AM UTC 24 |
Sep 18 09:32:34 AM UTC 24 |
1337900896 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.4220939440 |
|
|
Sep 18 09:30:40 AM UTC 24 |
Sep 18 09:32:39 AM UTC 24 |
305819002 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.4105244571 |
|
|
Sep 18 09:27:23 AM UTC 24 |
Sep 18 09:32:41 AM UTC 24 |
21511774632 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3913587118 |
|
|
Sep 18 09:32:34 AM UTC 24 |
Sep 18 09:32:41 AM UTC 24 |
181303206 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2929538758 |
|
|
Sep 18 09:32:41 AM UTC 24 |
Sep 18 09:32:43 AM UTC 24 |
18533030 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3742907208 |
|
|
Sep 18 09:31:15 AM UTC 24 |
Sep 18 09:32:47 AM UTC 24 |
13845368429 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1136736922 |
|
|
Sep 18 09:31:31 AM UTC 24 |
Sep 18 09:32:47 AM UTC 24 |
126698382 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1375858578 |
|
|
Sep 18 09:21:34 AM UTC 24 |
Sep 18 09:32:59 AM UTC 24 |
13841715386 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.957988809 |
|
|
Sep 18 09:32:43 AM UTC 24 |
Sep 18 09:33:05 AM UTC 24 |
2950920205 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.910282345 |
|
|
Sep 18 09:32:59 AM UTC 24 |
Sep 18 09:33:18 AM UTC 24 |
2897769854 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2826039364 |
|
|
Sep 18 09:31:21 AM UTC 24 |
Sep 18 09:33:19 AM UTC 24 |
2675961025 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.4199366673 |
|
|
Sep 18 09:19:42 AM UTC 24 |
Sep 18 09:33:26 AM UTC 24 |
79749667092 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2133077926 |
|
|
Sep 18 09:33:27 AM UTC 24 |
Sep 18 09:33:33 AM UTC 24 |
311688819 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.498828417 |
|
|
Sep 18 09:15:35 AM UTC 24 |
Sep 18 09:33:35 AM UTC 24 |
48142560473 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.2199234723 |
|
|
Sep 18 09:27:02 AM UTC 24 |
Sep 18 09:33:41 AM UTC 24 |
51242236055 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.399850724 |
|
|
Sep 18 09:20:42 AM UTC 24 |
Sep 18 09:33:50 AM UTC 24 |
10772174009 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3374296970 |
|
|
Sep 18 09:33:19 AM UTC 24 |
Sep 18 09:33:52 AM UTC 24 |
96788845 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.102434298 |
|
|
Sep 18 09:33:51 AM UTC 24 |
Sep 18 09:33:53 AM UTC 24 |
48743552 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.4022907565 |
|
|
Sep 18 09:32:48 AM UTC 24 |
Sep 18 09:33:54 AM UTC 24 |
6057912793 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3188199581 |
|
|
Sep 18 09:33:19 AM UTC 24 |
Sep 18 09:33:55 AM UTC 24 |
226531280 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4207878581 |
|
|
Sep 18 09:33:53 AM UTC 24 |
Sep 18 09:34:01 AM UTC 24 |
189342203 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2561810230 |
|
|
Sep 18 09:33:54 AM UTC 24 |
Sep 18 09:34:02 AM UTC 24 |
174891530 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2861634931 |
|
|
Sep 18 09:34:02 AM UTC 24 |
Sep 18 09:34:03 AM UTC 24 |
69076952 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3060342630 |
|
|
Sep 18 09:24:53 AM UTC 24 |
Sep 18 09:34:16 AM UTC 24 |
68759078288 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.4032552372 |
|
|
Sep 18 09:34:03 AM UTC 24 |
Sep 18 09:34:21 AM UTC 24 |
928126024 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2452164727 |
|
|
Sep 18 09:25:24 AM UTC 24 |
Sep 18 09:34:25 AM UTC 24 |
20265685322 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1940691221 |
|
|
Sep 18 09:28:59 AM UTC 24 |
Sep 18 09:34:29 AM UTC 24 |
10688530551 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2114834511 |
|
|
Sep 18 09:13:30 AM UTC 24 |
Sep 18 09:34:43 AM UTC 24 |
29160522740 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2028661008 |
|
|
Sep 18 09:34:25 AM UTC 24 |
Sep 18 09:34:46 AM UTC 24 |
753112760 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.309045919 |
|
|
Sep 18 09:23:36 AM UTC 24 |
Sep 18 09:34:52 AM UTC 24 |
6868868759 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2158996740 |
|
|
Sep 18 09:34:47 AM UTC 24 |
Sep 18 09:34:55 AM UTC 24 |
1180447901 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.495136310 |
|
|
Sep 18 09:23:53 AM UTC 24 |
Sep 18 09:34:56 AM UTC 24 |
5685490050 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2725784957 |
|
|
Sep 18 09:26:31 AM UTC 24 |
Sep 18 09:34:57 AM UTC 24 |
2805512744 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2991916286 |
|
|
Sep 18 09:34:56 AM UTC 24 |
Sep 18 09:34:58 AM UTC 24 |
81055138 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.192919443 |
|
|
Sep 18 09:34:59 AM UTC 24 |
Sep 18 09:35:04 AM UTC 24 |
1191219335 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2273965057 |
|
|
Sep 18 09:31:15 AM UTC 24 |
Sep 18 09:35:09 AM UTC 24 |
30385954659 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.4211443761 |
|
|
Sep 18 09:34:58 AM UTC 24 |
Sep 18 09:35:14 AM UTC 24 |
901956037 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.2314268961 |
|
|
Sep 18 09:32:04 AM UTC 24 |
Sep 18 09:35:15 AM UTC 24 |
10791537194 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.784224116 |
|
|
Sep 18 09:35:15 AM UTC 24 |
Sep 18 09:35:17 AM UTC 24 |
36983114 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3245747871 |
|
|
Sep 18 09:35:05 AM UTC 24 |
Sep 18 09:35:23 AM UTC 24 |
1770598621 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.1946985704 |
|
|
Sep 18 09:35:16 AM UTC 24 |
Sep 18 09:35:28 AM UTC 24 |
456080990 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.710736479 |
|
|
Sep 18 09:34:37 AM UTC 24 |
Sep 18 09:35:30 AM UTC 24 |
425070622 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.4106685791 |
|
|
Sep 18 09:35:30 AM UTC 24 |
Sep 18 09:35:34 AM UTC 24 |
231535395 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3280001033 |
|
|
Sep 18 09:34:17 AM UTC 24 |
Sep 18 09:35:40 AM UTC 24 |
3748222612 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.2299903740 |
|
|
Sep 18 09:26:39 AM UTC 24 |
Sep 18 09:35:43 AM UTC 24 |
17311324687 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.4003078841 |
|
|
Sep 18 09:30:43 AM UTC 24 |
Sep 18 09:36:06 AM UTC 24 |
5315934443 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.1605946306 |
|
|
Sep 18 09:28:15 AM UTC 24 |
Sep 18 09:36:17 AM UTC 24 |
1429696061 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.3664375568 |
|
|
Sep 18 09:35:24 AM UTC 24 |
Sep 18 09:36:18 AM UTC 24 |
641513053 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.437744576 |
|
|
Sep 18 09:36:07 AM UTC 24 |
Sep 18 09:36:20 AM UTC 24 |
906243637 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3772208801 |
|
|
Sep 18 09:22:52 AM UTC 24 |
Sep 18 09:36:25 AM UTC 24 |
29909232007 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2245063168 |
|
|
Sep 18 09:36:25 AM UTC 24 |
Sep 18 09:36:27 AM UTC 24 |
81427552 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.275788880 |
|
|
Sep 18 09:35:42 AM UTC 24 |
Sep 18 09:36:28 AM UTC 24 |
508408546 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3345616581 |
|
|
Sep 18 09:34:43 AM UTC 24 |
Sep 18 09:36:33 AM UTC 24 |
297392215 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2527389682 |
|
|
Sep 18 09:36:29 AM UTC 24 |
Sep 18 09:36:36 AM UTC 24 |
240970363 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2413560629 |
|
|
Sep 18 09:25:48 AM UTC 24 |
Sep 18 09:36:36 AM UTC 24 |
10715916338 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3334151642 |
|
|
Sep 18 09:36:38 AM UTC 24 |
Sep 18 09:36:40 AM UTC 24 |
34742493 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.616219359 |
|
|
Sep 18 09:35:45 AM UTC 24 |
Sep 18 09:36:44 AM UTC 24 |
146928800 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.778162456 |
|
|
Sep 18 09:32:48 AM UTC 24 |
Sep 18 09:36:46 AM UTC 24 |
2072485388 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3733450849 |
|
|
Sep 18 09:36:28 AM UTC 24 |
Sep 18 09:36:46 AM UTC 24 |
2384229680 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.1569527774 |
|
|
Sep 18 09:36:41 AM UTC 24 |
Sep 18 09:36:51 AM UTC 24 |
503008997 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1164712892 |
|
|
Sep 18 09:36:35 AM UTC 24 |
Sep 18 09:36:52 AM UTC 24 |
328494061 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3694584424 |
|
|
Sep 18 09:33:54 AM UTC 24 |
Sep 18 09:36:53 AM UTC 24 |
745595710 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1821358341 |
|
|
Sep 18 09:25:26 AM UTC 24 |
Sep 18 09:36:57 AM UTC 24 |
11494506880 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2614283608 |
|
|
Sep 18 09:27:39 AM UTC 24 |
Sep 18 09:37:07 AM UTC 24 |
37154200529 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.62947304 |
|
|
Sep 18 09:28:40 AM UTC 24 |
Sep 18 09:37:08 AM UTC 24 |
80486491786 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2843936379 |
|
|
Sep 18 09:36:51 AM UTC 24 |
Sep 18 09:37:08 AM UTC 24 |
482855833 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1342810497 |
|
|
Sep 18 09:31:25 AM UTC 24 |
Sep 18 09:37:12 AM UTC 24 |
14922291485 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.603157197 |
|
|
Sep 18 09:37:09 AM UTC 24 |
Sep 18 09:37:20 AM UTC 24 |
830252492 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3468812744 |
|
|
Sep 18 09:37:20 AM UTC 24 |
Sep 18 09:37:23 AM UTC 24 |
46548765 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.4163905048 |
|
|
Sep 18 09:36:55 AM UTC 24 |
Sep 18 09:37:35 AM UTC 24 |
373179639 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3986336928 |
|
|
Sep 18 08:28:45 AM UTC 24 |
Sep 18 09:37:38 AM UTC 24 |
47238242324 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3458809335 |
|
|
Sep 18 09:36:58 AM UTC 24 |
Sep 18 09:37:39 AM UTC 24 |
130147955 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4026053379 |
|
|
Sep 18 09:37:37 AM UTC 24 |
Sep 18 09:37:41 AM UTC 24 |
53153627 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.671007225 |
|
|
Sep 18 09:37:23 AM UTC 24 |
Sep 18 09:37:41 AM UTC 24 |
663314649 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.737023645 |
|
|
Sep 18 09:37:42 AM UTC 24 |
Sep 18 09:37:44 AM UTC 24 |
14780087 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1377774473 |
|
|
Sep 18 09:34:22 AM UTC 24 |
Sep 18 09:37:47 AM UTC 24 |
17777128500 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.1924318173 |
|
|
Sep 18 09:36:46 AM UTC 24 |
Sep 18 09:37:48 AM UTC 24 |
819690013 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.537553566 |
|
|
Sep 18 09:29:12 AM UTC 24 |
Sep 18 09:37:58 AM UTC 24 |
24530764717 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.601687120 |
|
|
Sep 18 09:37:39 AM UTC 24 |
Sep 18 09:38:02 AM UTC 24 |
563607390 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.318178949 |
|
|
Sep 18 09:00:43 AM UTC 24 |
Sep 18 09:38:11 AM UTC 24 |
15545372729 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3186364778 |
|
|
Sep 18 09:33:06 AM UTC 24 |
Sep 18 09:38:16 AM UTC 24 |
67796166354 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1416275208 |
|
|
Sep 18 08:41:09 AM UTC 24 |
Sep 18 09:38:21 AM UTC 24 |
47256344851 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3951273979 |
|
|
Sep 18 09:36:47 AM UTC 24 |
Sep 18 09:38:33 AM UTC 24 |
1077479300 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2412864370 |
|
|
Sep 18 08:45:39 AM UTC 24 |
Sep 18 09:38:49 AM UTC 24 |
30003164057 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.227584729 |
|
|
Sep 18 09:34:29 AM UTC 24 |
Sep 18 09:39:39 AM UTC 24 |
7031769415 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2783320958 |
|
|
Sep 18 09:24:57 AM UTC 24 |
Sep 18 09:39:39 AM UTC 24 |
2593256647 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.172086572 |
|
|
Sep 18 09:36:53 AM UTC 24 |
Sep 18 09:40:02 AM UTC 24 |
14614823464 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2616070746 |
|
|
Sep 18 09:27:11 AM UTC 24 |
Sep 18 09:40:02 AM UTC 24 |
46545680177 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.690811386 |
|
|
Sep 18 09:22:34 AM UTC 24 |
Sep 18 09:40:04 AM UTC 24 |
25949953536 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1921838132 |
|
|
Sep 18 09:26:16 AM UTC 24 |
Sep 18 09:40:14 AM UTC 24 |
91914121274 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3355506457 |
|
|
Sep 18 08:47:36 AM UTC 24 |
Sep 18 09:40:31 AM UTC 24 |
68006702029 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.538416429 |
|
|
Sep 18 09:33:36 AM UTC 24 |
Sep 18 09:40:38 AM UTC 24 |
4329078522 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2594849746 |
|
|
Sep 18 09:29:59 AM UTC 24 |
Sep 18 09:40:46 AM UTC 24 |
14944381015 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1788741721 |
|
|
Sep 18 09:35:29 AM UTC 24 |
Sep 18 09:41:09 AM UTC 24 |
10614636068 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1426402567 |
|
|
Sep 18 09:35:18 AM UTC 24 |
Sep 18 09:42:12 AM UTC 24 |
20301445537 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2809657516 |
|
|
Sep 18 09:20:33 AM UTC 24 |
Sep 18 09:42:19 AM UTC 24 |
39249611536 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.780807023 |
|
|
Sep 18 09:26:35 AM UTC 24 |
Sep 18 09:42:28 AM UTC 24 |
62436373017 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.4060571959 |
|
|
Sep 18 09:34:05 AM UTC 24 |
Sep 18 09:42:50 AM UTC 24 |
43233593608 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2890181489 |
|
|
Sep 18 09:36:45 AM UTC 24 |
Sep 18 09:42:56 AM UTC 24 |
5474691089 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2270823980 |
|
|
Sep 18 09:35:35 AM UTC 24 |
Sep 18 09:43:35 AM UTC 24 |
17060381819 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2481935133 |
|
|
Sep 18 09:31:59 AM UTC 24 |
Sep 18 09:43:45 AM UTC 24 |
3398665147 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3361381098 |
|
|
Sep 18 09:33:35 AM UTC 24 |
Sep 18 09:44:38 AM UTC 24 |
3351014110 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.2933856650 |
|
|
Sep 18 09:23:38 AM UTC 24 |
Sep 18 09:45:09 AM UTC 24 |
58929041369 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.336818378 |
|
|
Sep 18 09:34:55 AM UTC 24 |
Sep 18 09:45:56 AM UTC 24 |
103379284439 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3299224136 |
|
|
Sep 18 09:32:05 AM UTC 24 |
Sep 18 09:46:08 AM UTC 24 |
66027976742 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1920239485 |
|
|
Sep 18 09:37:09 AM UTC 24 |
Sep 18 09:47:02 AM UTC 24 |
40348628173 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1584315703 |
|
|
Sep 18 09:28:32 AM UTC 24 |
Sep 18 09:47:13 AM UTC 24 |
5967684434 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.283455994 |
|
|
Sep 18 09:37:09 AM UTC 24 |
Sep 18 09:47:23 AM UTC 24 |
13038286872 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3913947099 |
|
|
Sep 18 09:06:20 AM UTC 24 |
Sep 18 09:47:43 AM UTC 24 |
41099536630 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1621509889 |
|
|
Sep 18 09:28:22 AM UTC 24 |
Sep 18 09:47:51 AM UTC 24 |
45008519717 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.2128315785 |
|
|
Sep 18 09:36:21 AM UTC 24 |
Sep 18 09:47:59 AM UTC 24 |
11212235492 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.258311401 |
|
|
Sep 18 09:28:07 AM UTC 24 |
Sep 18 09:48:12 AM UTC 24 |
3180567957 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1697459894 |
|
|
Sep 18 09:36:18 AM UTC 24 |
Sep 18 09:48:32 AM UTC 24 |
2736046293 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.70594145 |
|
|
Sep 18 09:34:48 AM UTC 24 |
Sep 18 09:48:50 AM UTC 24 |
7199014753 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1396861792 |
|
|
Sep 18 09:16:00 AM UTC 24 |
Sep 18 09:50:12 AM UTC 24 |
11615077809 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1768147003 |
|
|
Sep 18 09:23:42 AM UTC 24 |
Sep 18 09:50:22 AM UTC 24 |
70425837028 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.3959150858 |
|
|
Sep 18 09:37:12 AM UTC 24 |
Sep 18 09:50:24 AM UTC 24 |
61419163751 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.210010975 |
|
|
Sep 18 09:34:53 AM UTC 24 |
Sep 18 09:51:10 AM UTC 24 |
4620308065 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.2832627950 |
|
|
Sep 18 09:36:19 AM UTC 24 |
Sep 18 09:52:04 AM UTC 24 |
14152857718 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.1856061421 |
|
|
Sep 18 09:30:02 AM UTC 24 |
Sep 18 09:52:23 AM UTC 24 |
75525920101 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.1177474887 |
|
|
Sep 18 09:33:42 AM UTC 24 |
Sep 18 09:53:57 AM UTC 24 |
24518111229 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.706536837 |
|
|
Sep 18 09:32:45 AM UTC 24 |
Sep 18 09:57:32 AM UTC 24 |
78217840331 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3356852132 |
|
|
Sep 18 09:37:40 AM UTC 24 |
Sep 18 10:00:14 AM UTC 24 |
24220458310 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.4256213960 |
|
|
Sep 18 09:35:10 AM UTC 24 |
Sep 18 10:00:20 AM UTC 24 |
123106492843 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3702662743 |
|
|
Sep 18 09:30:34 AM UTC 24 |
Sep 18 10:00:35 AM UTC 24 |
89867357661 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1316442433 |
|
|
Sep 18 09:17:08 AM UTC 24 |
Sep 18 10:00:49 AM UTC 24 |
14587543442 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.545391018 |
|
|
Sep 18 09:23:54 AM UTC 24 |
Sep 18 10:02:08 AM UTC 24 |
77348583235 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3298036618 |
|
|
Sep 18 08:51:16 AM UTC 24 |
Sep 18 10:03:25 AM UTC 24 |
74263139961 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2901693053 |
|
|
Sep 18 09:11:33 AM UTC 24 |
Sep 18 10:03:58 AM UTC 24 |
164896659274 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1645731553 |
|
|
Sep 18 09:25:38 AM UTC 24 |
Sep 18 10:04:31 AM UTC 24 |
46705094444 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.766022453 |
|
|
Sep 18 09:36:37 AM UTC 24 |
Sep 18 10:07:58 AM UTC 24 |
32632692030 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3328733125 |
|
|
Sep 18 09:04:08 AM UTC 24 |
Sep 18 10:10:32 AM UTC 24 |
261285799088 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3592815867 |
|
|
Sep 18 09:33:56 AM UTC 24 |
Sep 18 10:13:56 AM UTC 24 |
111809495287 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1453553248 |
|
|
Sep 18 09:14:58 AM UTC 24 |
Sep 18 10:20:44 AM UTC 24 |
142723281173 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2863685705 |
|
|
Sep 18 09:18:30 AM UTC 24 |
Sep 18 10:32:28 AM UTC 24 |
19185705266 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1037798825 |
|
|
Sep 18 09:07:44 AM UTC 24 |
Sep 18 10:39:13 AM UTC 24 |
297804843624 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3328888098 |
|
|
Sep 18 09:32:39 AM UTC 24 |
Sep 18 10:53:28 AM UTC 24 |
559551487489 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.518453484 |
|
|
Sep 18 12:49:13 PM UTC 24 |
Sep 18 12:49:15 PM UTC 24 |
46954457 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2761473848 |
|
|
Sep 18 12:49:13 PM UTC 24 |
Sep 18 12:49:15 PM UTC 24 |
19422454 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.119520606 |
|
|
Sep 18 12:49:13 PM UTC 24 |
Sep 18 12:49:15 PM UTC 24 |
70957007 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.915168486 |
|
|
Sep 18 12:49:13 PM UTC 24 |
Sep 18 12:49:15 PM UTC 24 |
1429580243 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4185707305 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
53996327 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1763977557 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
22544077 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2070708647 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
26101563 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3876146002 |
|
|
Sep 18 12:49:12 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
220225613 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2912482982 |
|
|
Sep 18 12:49:13 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
469926689 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.664179607 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
16520022 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3960173007 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
80235888 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3730562819 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
13896813 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.424097279 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
16708716 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2509446619 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:16 PM UTC 24 |
37937861 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3959327345 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:17 PM UTC 24 |
141244981 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4074402747 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:17 PM UTC 24 |
267368960 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2845976093 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:17 PM UTC 24 |
50397904 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3875487763 |
|
|
Sep 18 12:49:49 PM UTC 24 |
Sep 18 12:49:59 PM UTC 24 |
284069050 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.402940463 |
|
|
Sep 18 12:49:15 PM UTC 24 |
Sep 18 12:49:17 PM UTC 24 |
39042508 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2950480462 |
|
|
Sep 18 12:49:15 PM UTC 24 |
Sep 18 12:49:17 PM UTC 24 |
15326964 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3250214165 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
146462340 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.815155293 |
|
|
Sep 18 12:49:16 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
54981520 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2909540271 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
866122351 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3507134293 |
|
|
Sep 18 12:49:16 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
41276144 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2814813104 |
|
|
Sep 18 12:49:16 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
109271923 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3965348728 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
1399850349 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4068546933 |
|
|
Sep 18 12:49:13 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
252058678 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2512759768 |
|
|
Sep 18 12:49:16 PM UTC 24 |
Sep 18 12:49:18 PM UTC 24 |
104527854 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.524179018 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:19 PM UTC 24 |
912472615 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.928754592 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:19 PM UTC 24 |
816020185 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.752052868 |
|
|
Sep 18 12:49:14 PM UTC 24 |
Sep 18 12:49:19 PM UTC 24 |
1600606394 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2617462923 |
|
|
Sep 18 12:49:16 PM UTC 24 |
Sep 18 12:49:19 PM UTC 24 |
122673754 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4171681907 |
|
|
Sep 18 12:49:16 PM UTC 24 |
Sep 18 12:49:20 PM UTC 24 |
489958300 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3650621494 |
|
|
Sep 18 12:49:17 PM UTC 24 |
Sep 18 12:49:22 PM UTC 24 |
48734078 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2713021768 |
|
|
Sep 18 12:49:17 PM UTC 24 |
Sep 18 12:49:22 PM UTC 24 |
77063602 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.829578499 |
|
|
Sep 18 12:49:17 PM UTC 24 |
Sep 18 12:49:23 PM UTC 24 |
144288917 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.335497063 |
|
|
Sep 18 12:49:17 PM UTC 24 |
Sep 18 12:49:24 PM UTC 24 |
347292667 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.771360730 |
|
|
Sep 18 12:49:17 PM UTC 24 |
Sep 18 12:49:24 PM UTC 24 |
296487482 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.303161130 |
|
|
Sep 18 12:49:17 PM UTC 24 |
Sep 18 12:49:35 PM UTC 24 |
755276342 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3719410638 |
|
|
Sep 18 12:49:35 PM UTC 24 |
Sep 18 12:49:38 PM UTC 24 |
13611569 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1216671706 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:38 PM UTC 24 |
74935759 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1196425478 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:38 PM UTC 24 |
13097211 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2013159584 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:38 PM UTC 24 |
86994845 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2096548390 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:39 PM UTC 24 |
16669583 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2657204339 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:39 PM UTC 24 |
28473613 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1000741536 |
|
|
Sep 18 12:49:49 PM UTC 24 |
Sep 18 12:49:58 PM UTC 24 |
15637285 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2846568786 |
|
|
Sep 18 12:49:25 PM UTC 24 |
Sep 18 12:49:39 PM UTC 24 |
44569817 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1950998328 |
|
|
Sep 18 12:49:24 PM UTC 24 |
Sep 18 12:49:39 PM UTC 24 |
15853875 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.54005215 |
|
|
Sep 18 12:49:35 PM UTC 24 |
Sep 18 12:49:39 PM UTC 24 |
107252123 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3931522175 |
|
|
Sep 18 12:49:24 PM UTC 24 |
Sep 18 12:49:39 PM UTC 24 |
33119989 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4026348835 |
|
|
Sep 18 12:49:23 PM UTC 24 |
Sep 18 12:49:40 PM UTC 24 |
50959498 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2791369011 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:40 PM UTC 24 |
649046653 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1926304234 |
|
|
Sep 18 12:49:23 PM UTC 24 |
Sep 18 12:49:40 PM UTC 24 |
759705302 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4242423798 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:40 PM UTC 24 |
104944857 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1646664249 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:40 PM UTC 24 |
358495015 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.411570657 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:40 PM UTC 24 |
286854189 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2183400664 |
|
|
Sep 18 12:49:30 PM UTC 24 |
Sep 18 12:49:41 PM UTC 24 |
130681989 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1577508727 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:41 PM UTC 24 |
403153567 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1693282272 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:41 PM UTC 24 |
4263062373 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3064141605 |
|
|
Sep 18 12:49:19 PM UTC 24 |
Sep 18 12:49:41 PM UTC 24 |
1580469636 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.308552912 |
|
|
Sep 18 12:49:20 PM UTC 24 |
Sep 18 12:49:41 PM UTC 24 |
800475292 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.30946532 |
|
|
Sep 18 12:49:43 PM UTC 24 |
Sep 18 12:49:48 PM UTC 24 |
146048511 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3819635127 |
|
|
Sep 18 12:49:43 PM UTC 24 |
Sep 18 12:49:48 PM UTC 24 |
47046118 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.554929443 |
|
|
Sep 18 12:49:43 PM UTC 24 |
Sep 18 12:49:49 PM UTC 24 |
320594354 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.791707921 |
|
|
Sep 18 12:49:40 PM UTC 24 |
Sep 18 12:49:51 PM UTC 24 |
123038901 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.857025882 |
|
|
Sep 18 12:49:40 PM UTC 24 |
Sep 18 12:49:51 PM UTC 24 |
380348134 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2522752658 |
|
|
Sep 18 12:49:21 PM UTC 24 |
Sep 18 12:49:51 PM UTC 24 |
225770057 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.638610364 |
|
|
Sep 18 12:49:28 PM UTC 24 |
Sep 18 12:49:51 PM UTC 24 |
650252004 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1906664998 |
|
|
Sep 18 12:49:40 PM UTC 24 |
Sep 18 12:49:53 PM UTC 24 |
5410858424 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1335521488 |
|
|
Sep 18 12:49:40 PM UTC 24 |
Sep 18 12:49:53 PM UTC 24 |
29087467 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3952304343 |
|
|
Sep 18 12:49:48 PM UTC 24 |
Sep 18 12:49:53 PM UTC 24 |
661512453 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3601501944 |
|
|
Sep 18 12:49:40 PM UTC 24 |
Sep 18 12:49:54 PM UTC 24 |
33622477 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3278542627 |
|
|
Sep 18 12:49:39 PM UTC 24 |
Sep 18 12:49:57 PM UTC 24 |
28298937 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3875736711 |
|
|
Sep 18 12:49:49 PM UTC 24 |
Sep 18 12:49:58 PM UTC 24 |
11957024 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.86167087 |
|
|
Sep 18 12:49:53 PM UTC 24 |
Sep 18 12:49:58 PM UTC 24 |
237607545 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4234809795 |
|
|
Sep 18 12:49:55 PM UTC 24 |
Sep 18 12:49:58 PM UTC 24 |
386824502 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1147342669 |
|
|
Sep 18 12:49:53 PM UTC 24 |
Sep 18 12:49:59 PM UTC 24 |
236022140 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.931134148 |
|
|
Sep 18 12:49:53 PM UTC 24 |
Sep 18 12:50:00 PM UTC 24 |
309650404 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3493177964 |
|
|
Sep 18 12:49:54 PM UTC 24 |
Sep 18 12:50:03 PM UTC 24 |
16151831 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1261315102 |
|
|
Sep 18 12:49:54 PM UTC 24 |
Sep 18 12:50:04 PM UTC 24 |
309083278 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2577509761 |
|
|
Sep 18 12:49:54 PM UTC 24 |
Sep 18 12:50:04 PM UTC 24 |
14223482 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1547127230 |
|
|
Sep 18 12:50:00 PM UTC 24 |
Sep 18 12:50:04 PM UTC 24 |
743549619 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1643429458 |
|
|
Sep 18 12:49:59 PM UTC 24 |
Sep 18 12:50:04 PM UTC 24 |
381346823 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1219540029 |
|
|
Sep 18 12:49:50 PM UTC 24 |
Sep 18 12:50:04 PM UTC 24 |
41411217 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.605134685 |
|
|
Sep 18 12:50:01 PM UTC 24 |
Sep 18 12:50:04 PM UTC 24 |
168945157 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1938281047 |
|
|
Sep 18 12:49:57 PM UTC 24 |
Sep 18 12:50:05 PM UTC 24 |
788735428 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2861088547 |
|
|
Sep 18 12:49:50 PM UTC 24 |
Sep 18 12:50:05 PM UTC 24 |
400827543 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.227730606 |
|
|
Sep 18 12:50:00 PM UTC 24 |
Sep 18 12:50:06 PM UTC 24 |
129746057 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3336355523 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:07 PM UTC 24 |
83643899 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4193028357 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:07 PM UTC 24 |
22915320 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1955180075 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:08 PM UTC 24 |
15964955 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1351150074 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:08 PM UTC 24 |
50359991 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.895736536 |
|
|
Sep 18 12:49:59 PM UTC 24 |
Sep 18 12:50:08 PM UTC 24 |
41471226 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2733353762 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:08 PM UTC 24 |
134021558 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1334845700 |
|
|
Sep 18 12:49:49 PM UTC 24 |
Sep 18 12:50:09 PM UTC 24 |
115459638 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1206535395 |
|
|
Sep 18 12:50:04 PM UTC 24 |
Sep 18 12:50:09 PM UTC 24 |
45138544 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4232243847 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:09 PM UTC 24 |
110317505 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2860720328 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:09 PM UTC 24 |
46309040 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2785203547 |
|
|
Sep 18 12:49:59 PM UTC 24 |
Sep 18 12:50:10 PM UTC 24 |
973931773 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3595239121 |
|
|
Sep 18 12:49:42 PM UTC 24 |
Sep 18 12:50:10 PM UTC 24 |
48859540 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2607289383 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:10 PM UTC 24 |
1604753353 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3229597391 |
|
|
Sep 18 12:49:52 PM UTC 24 |
Sep 18 12:50:10 PM UTC 24 |
43322861 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.486399628 |
|
|
Sep 18 12:49:52 PM UTC 24 |
Sep 18 12:50:10 PM UTC 24 |
16368813 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.689162858 |
|
|
Sep 18 12:49:42 PM UTC 24 |
Sep 18 12:50:10 PM UTC 24 |
15707114 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1352025589 |
|
|
Sep 18 12:50:05 PM UTC 24 |
Sep 18 12:50:11 PM UTC 24 |
114458339 ps |