Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	99.13	94.27	99.72	100.00	95.81	99.12	97.44

Total test records in report: 1014

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1002	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3768855026			Sep 18 12:50:05 PM UTC 24	Sep 18 12:50:11 PM UTC 24	503173620 ps
T1003	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2047922105			Sep 18 12:50:05 PM UTC 24	Sep 18 12:50:11 PM UTC 24	145532121 ps
T1004	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2980409469			Sep 18 12:49:42 PM UTC 24	Sep 18 12:50:11 PM UTC 24	41210437 ps
T1005	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1526700517			Sep 18 12:49:59 PM UTC 24	Sep 18 12:50:11 PM UTC 24	93877365 ps
T1006	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1512870470			Sep 18 12:49:59 PM UTC 24	Sep 18 12:50:11 PM UTC 24	30359150 ps
T1007	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1230866140			Sep 18 12:50:05 PM UTC 24	Sep 18 12:50:11 PM UTC 24	1604310140 ps
T1008	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3198464411			Sep 18 12:50:02 PM UTC 24	Sep 18 12:50:11 PM UTC 24	30030741 ps
T1009	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3959814578			Sep 18 12:49:42 PM UTC 24	Sep 18 12:50:12 PM UTC 24	89062731 ps
T1010	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.390667620			Sep 18 12:50:05 PM UTC 24	Sep 18 12:50:12 PM UTC 24	684723127 ps
T1011	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.418919394			Sep 18 12:49:42 PM UTC 24	Sep 18 12:50:12 PM UTC 24	31654245 ps
T1012	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2638254589			Sep 18 12:49:42 PM UTC 24	Sep 18 12:50:12 PM UTC 24	498001133 ps
T1013	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3558590160			Sep 18 12:49:42 PM UTC 24	Sep 18 12:50:12 PM UTC 24	1412436267 ps
T1014	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3329147671			Sep 18 12:49:52 PM UTC 24	Sep 18 12:50:12 PM UTC 24	253605232 ps
T118	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4200448257			Sep 18 12:49:42 PM UTC 24	Sep 18 12:50:13 PM UTC 24	5302805555 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.4034856180
Short name	T6
Test name
Test status
Simulation time	465807203 ps
CPU time	8.23 seconds
Started	Sep 18 08:23:49 AM UTC 24
Finished	Sep 18 08:24:00 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034856180 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.4034856180
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3845005500
Short name	T26
Test name
Test status
Simulation time	13207962917 ps
CPU time	192.57 seconds
Started	Sep 18 08:23:46 AM UTC 24
Finished	Sep 18 08:27:01 AM UTC 24
Peak memory	391140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845005500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3845005500
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2856653244
Short name	T25
Test name
Test status
Simulation time	4004513137 ps
CPU time	119.41 seconds
Started	Sep 18 08:23:57 AM UTC 24
Finished	Sep 18 08:25:59 AM UTC 24
Peak memory	298956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856653244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2856653244
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3875487763
Short name	T55
Test name
Test status
Simulation time	284069050 ps
CPU time	1.88 seconds
Started	Sep 18 12:49:49 PM UTC 24
Finished	Sep 18 12:49:59 PM UTC 24
Peak memory	220280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38754 87763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i ntg_err.3875487763
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.4115637579
Short name	T9
Test name
Test status
Simulation time	832211158 ps
CPU time	5.56 seconds
Started	Sep 18 08:23:56 AM UTC 24
Finished	Sep 18 08:24:04 AM UTC 24
Peak memory	222176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115637579 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.4115637579
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1910844806
Short name	T4
Test name
Test status
Simulation time	246680089 ps
CPU time	3.67 seconds
Started	Sep 18 08:23:46 AM UTC 24
Finished	Sep 18 08:23:50 AM UTC 24
Peak memory	247732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910844806 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1910844806
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.252544532
Short name	T131
Test name
Test status
Simulation time	3806421699 ps
CPU time	872.38 seconds
Started	Sep 18 08:25:11 AM UTC 24
Finished	Sep 18 08:39:52 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252544532 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.252544532
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3876146002
Short name	T76
Test name
Test status
Simulation time	220225613 ps
CPU time	2.24 seconds
Started	Sep 18 12:49:12 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	211004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 76146002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa ssthru_mem_tl_intg_err.3876146002
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1686268105
Short name	T146
Test name
Test status
Simulation time	85459470806 ps
CPU time	636.44 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:34:27 AM UTC 24
Peak memory	212188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686268105 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce ss_b2b.1686268105
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3150760885
Short name	T135
Test name
Test status
Simulation time	4043651343 ps
CPU time	918.3 seconds
Started	Sep 18 08:26:21 AM UTC 24
Finished	Sep 18 08:41:49 AM UTC 24
Peak memory	376492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150760885 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3150760885
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.408240026
Short name	T1
Test name
Test status
Simulation time	27465781 ps
CPU time	0.94 seconds
Started	Sep 18 08:23:44 AM UTC 24
Finished	Sep 18 08:23:46 AM UTC 24
Peak memory	211392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408240026 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.408240026
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.28060057
Short name	T102
Test name
Test status
Simulation time	5265924015 ps
CPU time	166.71 seconds
Started	Sep 18 08:24:53 AM UTC 24
Finished	Sep 18 08:27:42 AM UTC 24
Peak memory	211920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28060057 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.28060057
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1451340901
Short name	T46
Test name
Test status
Simulation time	1598255401 ps
CPU time	57.78 seconds
Started	Sep 18 08:51:14 AM UTC 24
Finished	Sep 18 08:52:14 AM UTC 24
Peak memory	222256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451340901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1451340901
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.411570657
Short name	T121
Test name
Test status
Simulation time	286854189 ps
CPU time	2.52 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:40 PM UTC 24
Peak memory	211228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41157 0657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_int g_err.411570657
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3020185713
Short name	T3
Test name
Test status
Simulation time	29742562 ps
CPU time	1.01 seconds
Started	Sep 18 08:23:47 AM UTC 24
Finished	Sep 18 08:23:49 AM UTC 24
Peak memory	210648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020185713 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3020185713
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4200448257
Short name	T118
Test name
Test status
Simulation time	5302805555 ps
CPU time	2.85 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:13 PM UTC 24
Peak memory	211344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42004 48257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i ntg_err.4200448257
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2438676910
Short name	T239
Test name
Test status
Simulation time	747257841 ps
CPU time	11.15 seconds
Started	Sep 18 08:38:15 AM UTC 24
Finished	Sep 18 08:38:28 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438676910 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.2438676910
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2607289383
Short name	T125
Test name
Test status
Simulation time	1604753353 ps
CPU time	1.75 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:10 PM UTC 24
Peak memory	220280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26072 89383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i ntg_err.2607289383
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.424097279
Short name	T79
Test name
Test status
Simulation time	16708716 ps
CPU time	0.88 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	209920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42409727 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alias ing.424097279
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.119520606
Short name	T62
Test name
Test status
Simulation time	70957007 ps
CPU time	0.79 seconds
Started	Sep 18 12:49:13 PM UTC 24
Finished	Sep 18 12:49:15 PM UTC 24
Peak memory	209976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11952060 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alias ing.119520606
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2912482982
Short name	T77
Test name
Test status
Simulation time	469926689 ps
CPU time	2.19 seconds
Started	Sep 18 12:49:13 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	211040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29124829 82 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_ bash.2912482982
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.518453484
Short name	T60
Test name
Test status
Simulation time	46954457 ps
CPU time	0.75 seconds
Started	Sep 18 12:49:13 PM UTC 24
Finished	Sep 18 12:49:15 PM UTC 24
Peak memory	210356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51845348 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_re set.518453484
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3960173007
Short name	T937
Test name
Test status
Simulation time	80235888 ps
CPU time	1.17 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	222208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3960173007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3960173007
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2761473848
Short name	T61
Test name
Test status
Simulation time	19422454 ps
CPU time	0.83 seconds
Started	Sep 18 12:49:13 PM UTC 24
Finished	Sep 18 12:49:15 PM UTC 24
Peak memory	207960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761473848 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2761473848
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4185707305
Short name	T75
Test name
Test status
Simulation time	53996327 ps
CPU time	0.74 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	210424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4185707305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c trl_same_csr_outstanding.4185707305
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4068546933
Short name	T943
Test name
Test status
Simulation time	252058678 ps
CPU time	4.55 seconds
Started	Sep 18 12:49:13 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	221448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068546933 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.4068546933
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.915168486
Short name	T54
Test name
Test status
Simulation time	1429580243 ps
CPU time	1.53 seconds
Started	Sep 18 12:49:13 PM UTC 24
Finished	Sep 18 12:49:15 PM UTC 24
Peak memory	220276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91516 8486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_int g_err.915168486
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2845976093
Short name	T940
Test name
Test status
Simulation time	50397904 ps
CPU time	1.95 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:17 PM UTC 24
Peak memory	210400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28459760 93 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_ bash.2845976093
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2070708647
Short name	T105
Test name
Test status
Simulation time	26101563 ps
CPU time	0.76 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	207960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20707086 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r eset.2070708647
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3959327345
Short name	T938
Test name
Test status
Simulation time	141244981 ps
CPU time	1.24 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:17 PM UTC 24
Peak memory	220160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3959327345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3959327345
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1763977557
Short name	T128
Test name
Test status
Simulation time	22544077 ps
CPU time	0.69 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	209908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763977557 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.1763977557
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.752052868
Short name	T85
Test name
Test status
Simulation time	1600606394 ps
CPU time	3.85 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:19 PM UTC 24
Peak memory	211300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75 2052868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pas sthru_mem_tl_intg_err.752052868
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.664179607
Short name	T98
Test name
Test status
Simulation time	16520022 ps
CPU time	0.78 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	210036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=664179607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ct rl_same_csr_outstanding.664179607
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.928754592
Short name	T944
Test name
Test status
Simulation time	816020185 ps
CPU time	3.57 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:19 PM UTC 24
Peak memory	221464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928754592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.928754592
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.524179018
Short name	T120
Test name
Test status
Simulation time	912472615 ps
CPU time	3.46 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:19 PM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52417 9018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_int g_err.524179018
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1906664998
Short name	T94
Test name
Test status
Simulation time	5410858424 ps
CPU time	3.68 seconds
Started	Sep 18 12:49:40 PM UTC 24
Finished	Sep 18 12:49:53 PM UTC 24
Peak memory	211308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 06664998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p assthru_mem_tl_intg_err.1906664998
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1335521488
Short name	T972
Test name
Test status
Simulation time	29087467 ps
CPU time	0.73 seconds
Started	Sep 18 12:49:40 PM UTC 24
Finished	Sep 18 12:49:53 PM UTC 24
Peak memory	210032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1335521488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ ctrl_same_csr_outstanding.1335521488
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3601501944
Short name	T974
Test name
Test status
Simulation time	33622477 ps
CPU time	1.89 seconds
Started	Sep 18 12:49:40 PM UTC 24
Finished	Sep 18 12:49:54 PM UTC 24
Peak memory	220340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601501944 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.3601501944
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.857025882
Short name	T969
Test name
Test status
Simulation time	380348134 ps
CPU time	1.48 seconds
Started	Sep 18 12:49:40 PM UTC 24
Finished	Sep 18 12:49:51 PM UTC 24
Peak memory	220804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85702 5882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_in tg_err.857025882
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3959814578
Short name	T1009
Test name
Test status
Simulation time	89062731 ps
CPU time	1.97 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:12 PM UTC 24
Peak memory	222212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3959814578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3959814578
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.689162858
Short name	T1000
Test name
Test status
Simulation time	15707114 ps
CPU time	0.84 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:10 PM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689162858 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.689162858
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3595239121
Short name	T997
Test name
Test status
Simulation time	48859540 ps
CPU time	0.65 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:10 PM UTC 24
Peak memory	210384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3595239121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ ctrl_same_csr_outstanding.3595239121
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2638254589
Short name	T1012
Test name
Test status
Simulation time	498001133 ps
CPU time	2.24 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:12 PM UTC 24
Peak memory	221488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26382 54589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_i ntg_err.2638254589
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3819635127
Short name	T966
Test name
Test status
Simulation time	47046118 ps
CPU time	0.82 seconds
Started	Sep 18 12:49:43 PM UTC 24
Finished	Sep 18 12:49:48 PM UTC 24
Peak memory	210424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3819635127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3819635127
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2980409469
Short name	T1004
Test name
Test status
Simulation time	41210437 ps
CPU time	0.67 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	209976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980409469 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.2980409469
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3558590160
Short name	T1013
Test name
Test status
Simulation time	1412436267 ps
CPU time	2.23 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:12 PM UTC 24
Peak memory	211092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 58590160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p assthru_mem_tl_intg_err.3558590160
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.30946532
Short name	T965
Test name
Test status
Simulation time	146048511 ps
CPU time	0.65 seconds
Started	Sep 18 12:49:43 PM UTC 24
Finished	Sep 18 12:49:48 PM UTC 24
Peak memory	210436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=30946532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ct rl_same_csr_outstanding.30946532
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.418919394
Short name	T1011
Test name
Test status
Simulation time	31654245 ps
CPU time	1.96 seconds
Started	Sep 18 12:49:42 PM UTC 24
Finished	Sep 18 12:50:12 PM UTC 24
Peak memory	210504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418919394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.418919394
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1334845700
Short name	T992
Test name
Test status
Simulation time	115459638 ps
CPU time	1.72 seconds
Started	Sep 18 12:49:49 PM UTC 24
Finished	Sep 18 12:50:09 PM UTC 24
Peak memory	220484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1334845700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1334845700
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3875736711
Short name	T976
Test name
Test status
Simulation time	11957024 ps
CPU time	0.56 seconds
Started	Sep 18 12:49:49 PM UTC 24
Finished	Sep 18 12:49:58 PM UTC 24
Peak memory	210420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875736711 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.3875736711
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.554929443
Short name	T967
Test name
Test status
Simulation time	320594354 ps
CPU time	2.05 seconds
Started	Sep 18 12:49:43 PM UTC 24
Finished	Sep 18 12:49:49 PM UTC 24
Peak memory	211100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55 4929443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_pa ssthru_mem_tl_intg_err.554929443
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1000741536
Short name	T954
Test name
Test status
Simulation time	15637285 ps
CPU time	0.68 seconds
Started	Sep 18 12:49:49 PM UTC 24
Finished	Sep 18 12:49:58 PM UTC 24
Peak memory	210360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1000741536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ ctrl_same_csr_outstanding.1000741536
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3952304343
Short name	T973
Test name
Test status
Simulation time	661512453 ps
CPU time	4.22 seconds
Started	Sep 18 12:49:48 PM UTC 24
Finished	Sep 18 12:49:53 PM UTC 24
Peak memory	211268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952304343 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.3952304343
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.86167087
Short name	T977
Test name
Test status
Simulation time	237607545 ps
CPU time	1.26 seconds
Started	Sep 18 12:49:53 PM UTC 24
Finished	Sep 18 12:49:58 PM UTC 24
Peak memory	220532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=86167087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.86167087
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.486399628
Short name	T999
Test name
Test status
Simulation time	16368813 ps
CPU time	0.65 seconds
Started	Sep 18 12:49:52 PM UTC 24
Finished	Sep 18 12:50:10 PM UTC 24
Peak memory	210420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486399628 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.486399628
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2861088547
Short name	T97
Test name
Test status
Simulation time	400827543 ps
CPU time	2.87 seconds
Started	Sep 18 12:49:50 PM UTC 24
Finished	Sep 18 12:50:05 PM UTC 24
Peak memory	211296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28 61088547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_p assthru_mem_tl_intg_err.2861088547
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3229597391
Short name	T998
Test name
Test status
Simulation time	43322861 ps
CPU time	0.69 seconds
Started	Sep 18 12:49:52 PM UTC 24
Finished	Sep 18 12:50:10 PM UTC 24
Peak memory	210032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3229597391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ ctrl_same_csr_outstanding.3229597391
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1219540029
Short name	T984
Test name
Test status
Simulation time	41411217 ps
CPU time	1.56 seconds
Started	Sep 18 12:49:50 PM UTC 24
Finished	Sep 18 12:50:04 PM UTC 24
Peak memory	210100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219540029 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.1219540029
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3329147671
Short name	T1014
Test name
Test status
Simulation time	253605232 ps
CPU time	2.25 seconds
Started	Sep 18 12:49:52 PM UTC 24
Finished	Sep 18 12:50:12 PM UTC 24
Peak memory	221472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33291 47671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i ntg_err.3329147671
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4234809795
Short name	T978
Test name
Test status
Simulation time	386824502 ps
CPU time	1.19 seconds
Started	Sep 18 12:49:55 PM UTC 24
Finished	Sep 18 12:49:58 PM UTC 24
Peak memory	220528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4234809795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.4234809795
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3493177964
Short name	T981
Test name
Test status
Simulation time	16151831 ps
CPU time	0.63 seconds
Started	Sep 18 12:49:54 PM UTC 24
Finished	Sep 18 12:50:03 PM UTC 24
Peak memory	210240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493177964 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.3493177964
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1147342669
Short name	T979
Test name
Test status
Simulation time	236022140 ps
CPU time	2.04 seconds
Started	Sep 18 12:49:53 PM UTC 24
Finished	Sep 18 12:49:59 PM UTC 24
Peak memory	211092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 47342669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p assthru_mem_tl_intg_err.1147342669
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2577509761
Short name	T982
Test name
Test status
Simulation time	14223482 ps
CPU time	0.63 seconds
Started	Sep 18 12:49:54 PM UTC 24
Finished	Sep 18 12:50:04 PM UTC 24
Peak memory	210032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2577509761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ ctrl_same_csr_outstanding.2577509761
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.931134148
Short name	T980
Test name
Test status
Simulation time	309650404 ps
CPU time	2.82 seconds
Started	Sep 18 12:49:53 PM UTC 24
Finished	Sep 18 12:50:00 PM UTC 24
Peak memory	211208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931134148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.931134148
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1261315102
Short name	T126
Test name
Test status
Simulation time	309083278 ps
CPU time	1.45 seconds
Started	Sep 18 12:49:54 PM UTC 24
Finished	Sep 18 12:50:04 PM UTC 24
Peak memory	220280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12613 15102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i ntg_err.1261315102
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.895736536
Short name	T990
Test name
Test status
Simulation time	41471226 ps
CPU time	1.12 seconds
Started	Sep 18 12:49:59 PM UTC 24
Finished	Sep 18 12:50:08 PM UTC 24
Peak memory	220468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=895736536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.895736536
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1526700517
Short name	T1005
Test name
Test status
Simulation time	93877365 ps
CPU time	0.67 seconds
Started	Sep 18 12:49:59 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526700517 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1526700517
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1938281047
Short name	T96
Test name
Test status
Simulation time	788735428 ps
CPU time	3.2 seconds
Started	Sep 18 12:49:57 PM UTC 24
Finished	Sep 18 12:50:05 PM UTC 24
Peak memory	211156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 38281047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p assthru_mem_tl_intg_err.1938281047
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1512870470
Short name	T1006
Test name
Test status
Simulation time	30359150 ps
CPU time	0.85 seconds
Started	Sep 18 12:49:59 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	210360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1512870470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ ctrl_same_csr_outstanding.1512870470
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1643429458
Short name	T983
Test name
Test status
Simulation time	381346823 ps
CPU time	4.22 seconds
Started	Sep 18 12:49:59 PM UTC 24
Finished	Sep 18 12:50:04 PM UTC 24
Peak memory	221540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643429458 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.1643429458
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2785203547
Short name	T996
Test name
Test status
Simulation time	973931773 ps
CPU time	2.85 seconds
Started	Sep 18 12:49:59 PM UTC 24
Finished	Sep 18 12:50:10 PM UTC 24
Peak memory	211236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27852 03547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i ntg_err.2785203547
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1352025589
Short name	T1001
Test name
Test status
Simulation time	114458339 ps
CPU time	1.93 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	220472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1352025589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1352025589
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3198464411
Short name	T1008
Test name
Test status
Simulation time	30030741 ps
CPU time	0.65 seconds
Started	Sep 18 12:50:02 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198464411 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.3198464411
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1547127230
Short name	T95
Test name
Test status
Simulation time	743549619 ps
CPU time	1.98 seconds
Started	Sep 18 12:50:00 PM UTC 24
Finished	Sep 18 12:50:04 PM UTC 24
Peak memory	210428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 47127230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_p assthru_mem_tl_intg_err.1547127230
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1206535395
Short name	T993
Test name
Test status
Simulation time	45138544 ps
CPU time	0.66 seconds
Started	Sep 18 12:50:04 PM UTC 24
Finished	Sep 18 12:50:09 PM UTC 24
Peak memory	210360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1206535395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ ctrl_same_csr_outstanding.1206535395
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.227730606
Short name	T985
Test name
Test status
Simulation time	129746057 ps
CPU time	4.24 seconds
Started	Sep 18 12:50:00 PM UTC 24
Finished	Sep 18 12:50:06 PM UTC 24
Peak memory	221464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227730606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.227730606
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.605134685
Short name	T127
Test name
Test status
Simulation time	168945157 ps
CPU time	2.13 seconds
Started	Sep 18 12:50:01 PM UTC 24
Finished	Sep 18 12:50:04 PM UTC 24
Peak memory	221392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60513 4685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_in tg_err.605134685
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2047922105
Short name	T1003
Test name
Test status
Simulation time	145532121 ps
CPU time	1.82 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	220172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2047922105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2047922105
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2860720328
Short name	T995
Test name
Test status
Simulation time	46309040 ps
CPU time	0.63 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:09 PM UTC 24
Peak memory	210064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860720328 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.2860720328
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.390667620
Short name	T1010
Test name
Test status
Simulation time	684723127 ps
CPU time	3.27 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:12 PM UTC 24
Peak memory	211280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 0667620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_pa ssthru_mem_tl_intg_err.390667620
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3336355523
Short name	T986
Test name
Test status
Simulation time	83643899 ps
CPU time	0.75 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:07 PM UTC 24
Peak memory	210360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3336355523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ ctrl_same_csr_outstanding.3336355523
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4232243847
Short name	T994
Test name
Test status
Simulation time	110317505 ps
CPU time	2.73 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:09 PM UTC 24
Peak memory	211284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232243847 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.4232243847
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1351150074
Short name	T989
Test name
Test status
Simulation time	50359991 ps
CPU time	0.93 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:08 PM UTC 24
Peak memory	220168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1351150074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1351150074
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4193028357
Short name	T987
Test name
Test status
Simulation time	22915320 ps
CPU time	0.66 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:07 PM UTC 24
Peak memory	210420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193028357 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.4193028357
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1230866140
Short name	T1007
Test name
Test status
Simulation time	1604310140 ps
CPU time	2.09 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	211080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12 30866140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_p assthru_mem_tl_intg_err.1230866140
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1955180075
Short name	T988
Test name
Test status
Simulation time	15964955 ps
CPU time	0.61 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:08 PM UTC 24
Peak memory	210032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1955180075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ ctrl_same_csr_outstanding.1955180075
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3768855026
Short name	T1002
Test name
Test status
Simulation time	503173620 ps
CPU time	3.74 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:11 PM UTC 24
Peak memory	221524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768855026 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.3768855026
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2733353762
Short name	T991
Test name
Test status
Simulation time	134021558 ps
CPU time	1.45 seconds
Started	Sep 18 12:50:05 PM UTC 24
Finished	Sep 18 12:50:08 PM UTC 24
Peak memory	220280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27333 53762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i ntg_err.2733353762
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2950480462
Short name	T81
Test name
Test status
Simulation time	15326964 ps
CPU time	0.84 seconds
Started	Sep 18 12:49:15 PM UTC 24
Finished	Sep 18 12:49:17 PM UTC 24
Peak memory	210208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29504804 62 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alia sing.2950480462
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4074402747
Short name	T939
Test name
Test status
Simulation time	267368960 ps
CPU time	1.64 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:17 PM UTC 24
Peak memory	210380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40744027 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_ bash.4074402747
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2509446619
Short name	T80
Test name
Test status
Simulation time	37937861 ps
CPU time	0.79 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25094466 19 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r eset.2509446619
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2814813104
Short name	T942
Test name
Test status
Simulation time	109271923 ps
CPU time	1.48 seconds
Started	Sep 18 12:49:16 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	220428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2814813104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2814813104
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3730562819
Short name	T78
Test name
Test status
Simulation time	13896813 ps
CPU time	0.64 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:16 PM UTC 24
Peak memory	210324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730562819 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.3730562819
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2909540271
Short name	T83
Test name
Test status
Simulation time	866122351 ps
CPU time	2.3 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	211008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 09540271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa ssthru_mem_tl_intg_err.2909540271
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.402940463
Short name	T99
Test name
Test status
Simulation time	39042508 ps
CPU time	0.83 seconds
Started	Sep 18 12:49:15 PM UTC 24
Finished	Sep 18 12:49:17 PM UTC 24
Peak memory	210036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=402940463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ct rl_same_csr_outstanding.402940463
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3250214165
Short name	T941
Test name
Test status
Simulation time	146462340 ps
CPU time	2.17 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	211264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250214165 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.3250214165
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3965348728
Short name	T56
Test name
Test status
Simulation time	1399850349 ps
CPU time	2.82 seconds
Started	Sep 18 12:49:14 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	211344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39653 48728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_in tg_err.3965348728
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3650621494
Short name	T87
Test name
Test status
Simulation time	48734078 ps
CPU time	0.81 seconds
Started	Sep 18 12:49:17 PM UTC 24
Finished	Sep 18 12:49:22 PM UTC 24
Peak memory	208792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36506214 94 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia sing.3650621494
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.335497063
Short name	T92
Test name
Test status
Simulation time	347292667 ps
CPU time	2.18 seconds
Started	Sep 18 12:49:17 PM UTC 24
Finished	Sep 18 12:49:24 PM UTC 24
Peak memory	211096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33549706 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_b ash.335497063
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.815155293
Short name	T82
Test name
Test status
Simulation time	54981520 ps
CPU time	0.98 seconds
Started	Sep 18 12:49:16 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	210424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81515529 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_re set.815155293
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.829578499
Short name	T946
Test name
Test status
Simulation time	144288917 ps
CPU time	1.84 seconds
Started	Sep 18 12:49:17 PM UTC 24
Finished	Sep 18 12:49:23 PM UTC 24
Peak memory	220476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=829578499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.829578499
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3507134293
Short name	T84
Test name
Test status
Simulation time	41276144 ps
CPU time	0.94 seconds
Started	Sep 18 12:49:16 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	210300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507134293 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.3507134293
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4171681907
Short name	T86
Test name
Test status
Simulation time	489958300 ps
CPU time	3.37 seconds
Started	Sep 18 12:49:16 PM UTC 24
Finished	Sep 18 12:49:20 PM UTC 24
Peak memory	211228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 71681907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pa ssthru_mem_tl_intg_err.4171681907
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2713021768
Short name	T100
Test name
Test status
Simulation time	77063602 ps
CPU time	0.78 seconds
Started	Sep 18 12:49:17 PM UTC 24
Finished	Sep 18 12:49:22 PM UTC 24
Peak memory	210032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2713021768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c trl_same_csr_outstanding.2713021768
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2617462923
Short name	T945
Test name
Test status
Simulation time	122673754 ps
CPU time	2.25 seconds
Started	Sep 18 12:49:16 PM UTC 24
Finished	Sep 18 12:49:19 PM UTC 24
Peak memory	211268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617462923 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.2617462923
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2512759768
Short name	T119
Test name
Test status
Simulation time	104527854 ps
CPU time	1.71 seconds
Started	Sep 18 12:49:16 PM UTC 24
Finished	Sep 18 12:49:18 PM UTC 24
Peak memory	220280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25127 59768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in tg_err.2512759768
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.303161130
Short name	T88
Test name
Test status
Simulation time	755276342 ps
CPU time	3.41 seconds
Started	Sep 18 12:49:17 PM UTC 24
Finished	Sep 18 12:49:35 PM UTC 24
Peak memory	211244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 3161130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pas sthru_mem_tl_intg_err.303161130
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.771360730
Short name	T947
Test name
Test status
Simulation time	296487482 ps
CPU time	2.5 seconds
Started	Sep 18 12:49:17 PM UTC 24
Finished	Sep 18 12:49:24 PM UTC 24
Peak memory	220328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771360730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.771360730
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2791369011
Short name	T959
Test name
Test status
Simulation time	649046653 ps
CPU time	1.91 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:40 PM UTC 24
Peak memory	220156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2791369011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2791369011
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1196425478
Short name	T950
Test name
Test status
Simulation time	13097211 ps
CPU time	0.71 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:38 PM UTC 24
Peak memory	210332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196425478 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.1196425478
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1693282272
Short name	T962
Test name
Test status
Simulation time	4263062373 ps
CPU time	3.4 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:41 PM UTC 24
Peak memory	210948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 93282272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa ssthru_mem_tl_intg_err.1693282272
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2013159584
Short name	T951
Test name
Test status
Simulation time	86994845 ps
CPU time	0.79 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:38 PM UTC 24
Peak memory	210036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2013159584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_c trl_same_csr_outstanding.2013159584
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3064141605
Short name	T963
Test name
Test status
Simulation time	1580469636 ps
CPU time	3.48 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:41 PM UTC 24
Peak memory	211220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064141605 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3064141605
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1646664249
Short name	T122
Test name
Test status
Simulation time	358495015 ps
CPU time	2.57 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:40 PM UTC 24
Peak memory	221404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16466 64249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in tg_err.1646664249
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2657204339
Short name	T953
Test name
Test status
Simulation time	28473613 ps
CPU time	1.22 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:39 PM UTC 24
Peak memory	220160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2657204339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2657204339
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2096548390
Short name	T952
Test name
Test status
Simulation time	16669583 ps
CPU time	0.69 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:39 PM UTC 24
Peak memory	209980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096548390 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.2096548390
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1577508727
Short name	T93
Test name
Test status
Simulation time	403153567 ps
CPU time	3.18 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:41 PM UTC 24
Peak memory	211312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 77508727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa ssthru_mem_tl_intg_err.1577508727
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1216671706
Short name	T949
Test name
Test status
Simulation time	74935759 ps
CPU time	0.71 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:38 PM UTC 24
Peak memory	210364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1216671706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c trl_same_csr_outstanding.1216671706
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4242423798
Short name	T960
Test name
Test status
Simulation time	104944857 ps
CPU time	2.15 seconds
Started	Sep 18 12:49:19 PM UTC 24
Finished	Sep 18 12:49:40 PM UTC 24
Peak memory	211304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242423798 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.4242423798
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.308552912
Short name	T964
Test name
Test status
Simulation time	800475292 ps
CPU time	3.57 seconds
Started	Sep 18 12:49:20 PM UTC 24
Finished	Sep 18 12:49:41 PM UTC 24
Peak memory	211288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 8552912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pas sthru_mem_tl_intg_err.308552912
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2846568786
Short name	T955
Test name
Test status
Simulation time	44569817 ps
CPU time	1.02 seconds
Started	Sep 18 12:49:25 PM UTC 24
Finished	Sep 18 12:49:39 PM UTC 24
Peak memory	220160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2846568786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2846568786
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1950998328
Short name	T956
Test name
Test status
Simulation time	15853875 ps
CPU time	0.61 seconds
Started	Sep 18 12:49:24 PM UTC 24
Finished	Sep 18 12:49:39 PM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950998328 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.1950998328
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2522752658
Short name	T970
Test name
Test status
Simulation time	225770057 ps
CPU time	2.03 seconds
Started	Sep 18 12:49:21 PM UTC 24
Finished	Sep 18 12:49:51 PM UTC 24
Peak memory	211224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 22752658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa ssthru_mem_tl_intg_err.2522752658
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3931522175
Short name	T957
Test name
Test status
Simulation time	33119989 ps
CPU time	0.69 seconds
Started	Sep 18 12:49:24 PM UTC 24
Finished	Sep 18 12:49:39 PM UTC 24
Peak memory	210360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3931522175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c trl_same_csr_outstanding.3931522175
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4026348835
Short name	T958
Test name
Test status
Simulation time	50959498 ps
CPU time	1.88 seconds
Started	Sep 18 12:49:23 PM UTC 24
Finished	Sep 18 12:49:40 PM UTC 24
Peak memory	209372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026348835 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.4026348835
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1926304234
Short name	T123
Test name
Test status
Simulation time	759705302 ps
CPU time	2.31 seconds
Started	Sep 18 12:49:23 PM UTC 24
Finished	Sep 18 12:49:40 PM UTC 24
Peak memory	211248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19263 04234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in tg_err.1926304234
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.791707921
Short name	T968
Test name
Test status
Simulation time	123038901 ps
CPU time	1.57 seconds
Started	Sep 18 12:49:40 PM UTC 24
Finished	Sep 18 12:49:51 PM UTC 24
Peak memory	220160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=791707921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.791707921
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3719410638
Short name	T948
Test name
Test status
Simulation time	13611569 ps
CPU time	0.59 seconds
Started	Sep 18 12:49:35 PM UTC 24
Finished	Sep 18 12:49:38 PM UTC 24
Peak memory	210420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719410638 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.3719410638
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.638610364
Short name	T971
Test name
Test status
Simulation time	650252004 ps
CPU time	2.24 seconds
Started	Sep 18 12:49:28 PM UTC 24
Finished	Sep 18 12:49:51 PM UTC 24
Peak memory	211020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63 8610364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pas sthru_mem_tl_intg_err.638610364
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3278542627
Short name	T975
Test name
Test status
Simulation time	28298937 ps
CPU time	0.78 seconds
Started	Sep 18 12:49:39 PM UTC 24
Finished	Sep 18 12:49:57 PM UTC 24
Peak memory	210364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3278542627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c trl_same_csr_outstanding.3278542627
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2183400664
Short name	T961
Test name
Test status
Simulation time	130681989 ps
CPU time	2.6 seconds
Started	Sep 18 12:49:30 PM UTC 24
Finished	Sep 18 12:49:41 PM UTC 24
Peak memory	211340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183400664 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.2183400664
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.54005215
Short name	T124
Test name
Test status
Simulation time	107252123 ps
CPU time	1.61 seconds
Started	Sep 18 12:49:35 PM UTC 24
Finished	Sep 18 12:49:39 PM UTC 24
Peak memory	220288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54005 215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_intg _err.54005215
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.3231237016
Short name	T233
Test name
Test status
Simulation time	5336493905 ps
CPU time	820.6 seconds
Started	Sep 18 08:23:44 AM UTC 24
Finished	Sep 18 08:37:34 AM UTC 24
Peak memory	382928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231237016 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_ key_req.3231237016
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.2463976747
Short name	T149
Test name
Test status
Simulation time	4286146203 ps
CPU time	78.12 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:25:03 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463976747 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.2463976747
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1831461273
Short name	T329
Test name
Test status
Simulation time	19021688092 ps
CPU time	1489.83 seconds
Started	Sep 18 08:23:44 AM UTC 24
Finished	Sep 18 08:48:48 AM UTC 24
Peak memory	382872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831461273 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.1831461273
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1193755673
Short name	T2
Test name
Test status
Simulation time	408128629 ps
CPU time	3.06 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:23:47 AM UTC 24
Peak memory	211948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193755673 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.1193755673
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1767684724
Short name	T159
Test name
Test status
Simulation time	1161536576 ps
CPU time	106.24 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:25:31 AM UTC 24
Peak memory	372652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 767684724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max _throughput.1767684724
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3289130457
Short name	T5
Test name
Test status
Simulation time	91369942 ps
CPU time	7.49 seconds
Started	Sep 18 08:23:44 AM UTC 24
Finished	Sep 18 08:23:53 AM UTC 24
Peak memory	222244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289130457 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.3289130457
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1292706055
Short name	T12
Test name
Test status
Simulation time	455663017 ps
CPU time	15.84 seconds
Started	Sep 18 08:23:44 AM UTC 24
Finished	Sep 18 08:24:01 AM UTC 24
Peak memory	222364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292706055 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.1292706055
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.34482074
Short name	T267
Test name
Test status
Simulation time	11733791849 ps
CPU time	1108.66 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:42:23 AM UTC 24
Peak memory	382884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34482074 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.34482074
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.371783430
Short name	T143
Test name
Test status
Simulation time	1511902548 ps
CPU time	83.87 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:25:08 AM UTC 24
Peak memory	352168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371783430 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.371783430
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.423481682
Short name	T19
Test name
Test status
Simulation time	5227712307 ps
CPU time	311.58 seconds
Started	Sep 18 08:23:44 AM UTC 24
Finished	Sep 18 08:29:00 AM UTC 24
Peak memory	376936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423481682 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.423481682
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2706498141
Short name	T7
Test name
Test status
Simulation time	981745327 ps
CPU time	14.17 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:23:58 AM UTC 24
Peak memory	212020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706498141 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2706498141
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2914671110
Short name	T616
Test name
Test status
Simulation time	19044584840 ps
CPU time	3059.15 seconds
Started	Sep 18 08:23:46 AM UTC 24
Finished	Sep 18 09:15:14 AM UTC 24
Peak memory	385140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291467111 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.2914671110
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2878760376
Short name	T72
Test name
Test status
Simulation time	1357978719 ps
CPU time	155.17 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:26:21 AM UTC 24
Peak memory	211928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878760376 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.2878760376
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2891119097
Short name	T142
Test name
Test status
Simulation time	1350513186 ps
CPU time	69.65 seconds
Started	Sep 18 08:23:43 AM UTC 24
Finished	Sep 18 08:24:54 AM UTC 24
Peak memory	366484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2891119097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th roughput_w_partial_write.2891119097
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1844180260
Short name	T38
Test name
Test status
Simulation time	1227900747 ps
CPU time	160.49 seconds
Started	Sep 18 08:23:52 AM UTC 24
Finished	Sep 18 08:26:35 AM UTC 24
Peak memory	366632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844180260 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_ key_req.1844180260
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.518734222
Short name	T13
Test name
Test status
Simulation time	22708996 ps
CPU time	0.96 seconds
Started	Sep 18 08:24:00 AM UTC 24
Finished	Sep 18 08:24:02 AM UTC 24
Peak memory	210820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518734222 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.518734222
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.466773746
Short name	T17
Test name
Test status
Simulation time	1904917213 ps
CPU time	36.75 seconds
Started	Sep 18 08:23:47 AM UTC 24
Finished	Sep 18 08:24:25 AM UTC 24
Peak memory	211936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466773746 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.466773746
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.2153002882
Short name	T333
Test name
Test status
Simulation time	97311493748 ps
CPU time	1513.17 seconds
Started	Sep 18 08:23:53 AM UTC 24
Finished	Sep 18 08:49:21 AM UTC 24
Peak memory	382940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153002882 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.2153002882
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.463101633
Short name	T157
Test name
Test status
Simulation time	131313988 ps
CPU time	69.75 seconds
Started	Sep 18 08:23:49 AM UTC 24
Finished	Sep 18 08:25:01 AM UTC 24
Peak memory	370724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 63101633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max_ throughput.463101633
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2982444666
Short name	T11
Test name
Test status
Simulation time	75745702 ps
CPU time	4.8 seconds
Started	Sep 18 08:23:55 AM UTC 24
Finished	Sep 18 08:24:01 AM UTC 24
Peak memory	212000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982444666 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2982444666
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2294245643
Short name	T206
Test name
Test status
Simulation time	13812653552 ps
CPU time	600.66 seconds
Started	Sep 18 08:23:47 AM UTC 24
Finished	Sep 18 08:33:55 AM UTC 24
Peak memory	376912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294245643 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.2294245643
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1525826569
Short name	T47
Test name
Test status
Simulation time	137814632 ps
CPU time	48.24 seconds
Started	Sep 18 08:23:48 AM UTC 24
Finished	Sep 18 08:24:38 AM UTC 24
Peak memory	304972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525826569 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.1525826569
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3414719203
Short name	T192
Test name
Test status
Simulation time	11829291820 ps
CPU time	527.03 seconds
Started	Sep 18 08:23:48 AM UTC 24
Finished	Sep 18 08:32:42 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414719203 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce ss_b2b.3414719203
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1999911930
Short name	T10
Test name
Test status
Simulation time	28659281 ps
CPU time	1.26 seconds
Started	Sep 18 08:23:54 AM UTC 24
Finished	Sep 18 08:23:56 AM UTC 24
Peak memory	210632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999911930 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1999911930
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.40731741
Short name	T42
Test name
Test status
Simulation time	11750675255 ps
CPU time	268.17 seconds
Started	Sep 18 08:23:54 AM UTC 24
Finished	Sep 18 08:28:26 AM UTC 24
Peak memory	378772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40731741 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.40731741
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1306684393
Short name	T15
Test name
Test status
Simulation time	361990082 ps
CPU time	2.9 seconds
Started	Sep 18 08:24:00 AM UTC 24
Finished	Sep 18 08:24:04 AM UTC 24
Peak memory	247796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306684393 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1306684393
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.1910479210
Short name	T34
Test name
Test status
Simulation time	1047425251 ps
CPU time	54.9 seconds
Started	Sep 18 08:23:47 AM UTC 24
Finished	Sep 18 08:24:43 AM UTC 24
Peak memory	352276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910479210 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1910479210
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.91992246
Short name	T468
Test name
Test status
Simulation time	84406458447 ps
CPU time	2278 seconds
Started	Sep 18 08:23:58 AM UTC 24
Finished	Sep 18 09:02:22 AM UTC 24
Peak memory	384936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91992246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.91992246
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3605787783
Short name	T101
Test name
Test status
Simulation time	3805866670 ps
CPU time	196.63 seconds
Started	Sep 18 08:23:48 AM UTC 24
Finished	Sep 18 08:27:08 AM UTC 24
Peak memory	212048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605787783 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.3605787783
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2695254423
Short name	T144
Test name
Test status
Simulation time	619687797 ps
CPU time	93.56 seconds
Started	Sep 18 08:23:49 AM UTC 24
Finished	Sep 18 08:25:25 AM UTC 24
Peak memory	378708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2695254423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th roughput_w_partial_write.2695254423
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3589295733
Short name	T288
Test name
Test status
Simulation time	12895354054 ps
CPU time	595.48 seconds
Started	Sep 18 08:34:05 AM UTC 24
Finished	Sep 18 08:44:08 AM UTC 24
Peak memory	380884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589295733 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during _key_req.3589295733
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2063576504
Short name	T215
Test name
Test status
Simulation time	21632925 ps
CPU time	1 seconds
Started	Sep 18 08:34:35 AM UTC 24
Finished	Sep 18 08:34:37 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063576504 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2063576504
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1742432457
Short name	T214
Test name
Test status
Simulation time	2861338669 ps
CPU time	63.55 seconds
Started	Sep 18 08:33:30 AM UTC 24
Finished	Sep 18 08:34:35 AM UTC 24
Peak memory	212200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742432457 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.1742432457
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2409628770
Short name	T262
Test name
Test status
Simulation time	7651928179 ps
CPU time	466.32 seconds
Started	Sep 18 08:34:07 AM UTC 24
Finished	Sep 18 08:41:59 AM UTC 24
Peak memory	372640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409628770 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2409628770
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.288581368
Short name	T208
Test name
Test status
Simulation time	665144671 ps
CPU time	8.98 seconds
Started	Sep 18 08:33:55 AM UTC 24
Finished	Sep 18 08:34:06 AM UTC 24
Peak memory	212016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288581368 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.288581368
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3875109627
Short name	T207
Test name
Test status
Simulation time	125283388 ps
CPU time	16.51 seconds
Started	Sep 18 08:33:47 AM UTC 24
Finished	Sep 18 08:34:05 AM UTC 24
Peak memory	262048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 875109627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma x_throughput.3875109627
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1541695234
Short name	T213
Test name
Test status
Simulation time	175761738 ps
CPU time	4.71 seconds
Started	Sep 18 08:34:28 AM UTC 24
Finished	Sep 18 08:34:34 AM UTC 24
Peak memory	222356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541695234 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.1541695234
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1227884752
Short name	T212
Test name
Test status
Simulation time	189066777 ps
CPU time	5.82 seconds
Started	Sep 18 08:34:26 AM UTC 24
Finished	Sep 18 08:34:33 AM UTC 24
Peak memory	222108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227884752 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.1227884752
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3934340400
Short name	T318
Test name
Test status
Simulation time	72205058311 ps
CPU time	831.43 seconds
Started	Sep 18 08:33:27 AM UTC 24
Finished	Sep 18 08:47:27 AM UTC 24
Peak memory	378848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934340400 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.3934340400
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.499683981
Short name	T203
Test name
Test status
Simulation time	56412171 ps
CPU time	2.34 seconds
Started	Sep 18 08:33:38 AM UTC 24
Finished	Sep 18 08:33:41 AM UTC 24
Peak memory	212124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499683981 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.499683981
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3165404518
Short name	T277
Test name
Test status
Simulation time	8220634725 ps
CPU time	549.59 seconds
Started	Sep 18 08:33:42 AM UTC 24
Finished	Sep 18 08:42:59 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165404518 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc ess_b2b.3165404518
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3832845490
Short name	T210
Test name
Test status
Simulation time	71926801 ps
CPU time	1.21 seconds
Started	Sep 18 08:34:22 AM UTC 24
Finished	Sep 18 08:34:25 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832845490 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3832845490
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.119201262
Short name	T138
Test name
Test status
Simulation time	1971351233 ps
CPU time	339.06 seconds
Started	Sep 18 08:34:17 AM UTC 24
Finished	Sep 18 08:40:01 AM UTC 24
Peak memory	376664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119201262 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.119201262
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2574281685
Short name	T202
Test name
Test status
Simulation time	718987583 ps
CPU time	10.06 seconds
Started	Sep 18 08:33:25 AM UTC 24
Finished	Sep 18 08:33:37 AM UTC 24
Peak memory	211872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574281685 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2574281685
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3349534333
Short name	T430
Test name
Test status
Simulation time	25842024525 ps
CPU time	1429.14 seconds
Started	Sep 18 08:34:34 AM UTC 24
Finished	Sep 18 08:58:38 AM UTC 24
Peak memory	387040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334953433 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.3349534333
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3937845594
Short name	T64
Test name
Test status
Simulation time	554351763 ps
CPU time	33.15 seconds
Started	Sep 18 08:34:30 AM UTC 24
Finished	Sep 18 08:35:04 AM UTC 24
Peak memory	295004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937845594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3937845594
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3918571868
Short name	T231
Test name
Test status
Simulation time	15915088832 ps
CPU time	218.31 seconds
Started	Sep 18 08:33:31 AM UTC 24
Finished	Sep 18 08:37:12 AM UTC 24
Peak memory	212076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918571868 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3918571868
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2353052075
Short name	T219
Test name
Test status
Simulation time	279846008 ps
CPU time	71.92 seconds
Started	Sep 18 08:33:49 AM UTC 24
Finished	Sep 18 08:35:03 AM UTC 24
Peak memory	337732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2353052075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t hroughput_w_partial_write.2353052075
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.451305392
Short name	T344
Test name
Test status
Simulation time	38108943644 ps
CPU time	877.87 seconds
Started	Sep 18 08:35:26 AM UTC 24
Finished	Sep 18 08:50:14 AM UTC 24
Peak memory	385000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451305392 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_ key_req.451305392
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1604494915
Short name	T230
Test name
Test status
Simulation time	18411107 ps
CPU time	0.82 seconds
Started	Sep 18 08:36:58 AM UTC 24
Finished	Sep 18 08:36:59 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604494915 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1604494915
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3319179707
Short name	T222
Test name
Test status
Simulation time	1926903018 ps
CPU time	76.15 seconds
Started	Sep 18 08:34:41 AM UTC 24
Finished	Sep 18 08:35:59 AM UTC 24
Peak memory	212148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319179707 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.3319179707
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.3467175780
Short name	T263
Test name
Test status
Simulation time	5651807639 ps
CPU time	356.14 seconds
Started	Sep 18 08:36:00 AM UTC 24
Finished	Sep 18 08:42:01 AM UTC 24
Peak memory	356448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467175780 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.3467175780
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1869241278
Short name	T221
Test name
Test status
Simulation time	1619977453 ps
CPU time	7.68 seconds
Started	Sep 18 08:35:17 AM UTC 24
Finished	Sep 18 08:35:25 AM UTC 24
Peak memory	226260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869241278 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.1869241278
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2208973958
Short name	T220
Test name
Test status
Simulation time	344726789 ps
CPU time	1.62 seconds
Started	Sep 18 08:35:05 AM UTC 24
Finished	Sep 18 08:35:08 AM UTC 24
Peak memory	210700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 208973958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ma x_throughput.2208973958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1009951906
Short name	T228
Test name
Test status
Simulation time	645071810 ps
CPU time	3.25 seconds
Started	Sep 18 08:36:50 AM UTC 24
Finished	Sep 18 08:36:55 AM UTC 24
Peak memory	222352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009951906 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.1009951906
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3436269539
Short name	T226
Test name
Test status
Simulation time	79374272 ps
CPU time	6.52 seconds
Started	Sep 18 08:36:42 AM UTC 24
Finished	Sep 18 08:36:50 AM UTC 24
Peak memory	222164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436269539 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.3436269539
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3149774412
Short name	T261
Test name
Test status
Simulation time	2040342212 ps
CPU time	414.76 seconds
Started	Sep 18 08:34:38 AM UTC 24
Finished	Sep 18 08:41:38 AM UTC 24
Peak memory	382944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149774412 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.3149774412
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1319048603
Short name	T223
Test name
Test status
Simulation time	1159800916 ps
CPU time	89.3 seconds
Started	Sep 18 08:34:57 AM UTC 24
Finished	Sep 18 08:36:28 AM UTC 24
Peak memory	360272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319048603 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.1319048603
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.398974346
Short name	T273
Test name
Test status
Simulation time	11103191268 ps
CPU time	460.97 seconds
Started	Sep 18 08:35:03 AM UTC 24
Finished	Sep 18 08:42:50 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398974346 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acce ss_b2b.398974346
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.2205639275
Short name	T225
Test name
Test status
Simulation time	102126254 ps
CPU time	1.28 seconds
Started	Sep 18 08:36:39 AM UTC 24
Finished	Sep 18 08:36:41 AM UTC 24
Peak memory	211140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205639275 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2205639275
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2992467350
Short name	T310
Test name
Test status
Simulation time	6835725683 ps
CPU time	566 seconds
Started	Sep 18 08:36:29 AM UTC 24
Finished	Sep 18 08:46:01 AM UTC 24
Peak memory	384920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992467350 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2992467350
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.2623225586
Short name	T218
Test name
Test status
Simulation time	1674221804 ps
CPU time	19.49 seconds
Started	Sep 18 08:34:36 AM UTC 24
Finished	Sep 18 08:34:57 AM UTC 24
Peak memory	212144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623225586 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2623225586
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2922477269
Short name	T733
Test name
Test status
Simulation time	72291048681 ps
CPU time	2903.62 seconds
Started	Sep 18 08:36:55 AM UTC 24
Finished	Sep 18 09:25:47 AM UTC 24
Peak memory	386488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292247726 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.2922477269
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4057634785
Short name	T65
Test name
Test status
Simulation time	3660995718 ps
CPU time	185.89 seconds
Started	Sep 18 08:36:53 AM UTC 24
Finished	Sep 18 08:40:02 AM UTC 24
Peak memory	352496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057634785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.4057634785
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3526009253
Short name	T246
Test name
Test status
Simulation time	8691635776 ps
CPU time	303.63 seconds
Started	Sep 18 08:34:56 AM UTC 24
Finished	Sep 18 08:40:04 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526009253 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.3526009253
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.365362044
Short name	T224
Test name
Test status
Simulation time	458079703 ps
CPU time	88.07 seconds
Started	Sep 18 08:35:09 AM UTC 24
Finished	Sep 18 08:36:39 AM UTC 24
Peak memory	372636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 365362044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_th roughput_w_partial_write.365362044
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.470862183
Short name	T366
Test name
Test status
Simulation time	2146076952 ps
CPU time	837.67 seconds
Started	Sep 18 08:38:17 AM UTC 24
Finished	Sep 18 08:52:23 AM UTC 24
Peak memory	383008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470862183 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_ key_req.470862183
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1341584642
Short name	T244
Test name
Test status
Simulation time	22984866 ps
CPU time	0.92 seconds
Started	Sep 18 08:39:41 AM UTC 24
Finished	Sep 18 08:39:43 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341584642 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1341584642
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.2861356145
Short name	T237
Test name
Test status
Simulation time	760469868 ps
CPU time	56.61 seconds
Started	Sep 18 08:37:16 AM UTC 24
Finished	Sep 18 08:38:14 AM UTC 24
Peak memory	212120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861356145 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.2861356145
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.320532188
Short name	T290
Test name
Test status
Simulation time	26699613211 ps
CPU time	337.26 seconds
Started	Sep 18 08:38:29 AM UTC 24
Finished	Sep 18 08:44:10 AM UTC 24
Peak memory	366556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320532188 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.320532188
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.402288053
Short name	T240
Test name
Test status
Simulation time	171026906 ps
CPU time	33.38 seconds
Started	Sep 18 08:38:08 AM UTC 24
Finished	Sep 18 08:38:43 AM UTC 24
Peak memory	300972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 02288053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_max _throughput.402288053
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3627032958
Short name	T243
Test name
Test status
Simulation time	312665518 ps
CPU time	3.59 seconds
Started	Sep 18 08:39:03 AM UTC 24
Finished	Sep 18 08:39:08 AM UTC 24
Peak memory	222376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627032958 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.3627032958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.188834827
Short name	T242
Test name
Test status
Simulation time	139033756 ps
CPU time	12.05 seconds
Started	Sep 18 08:38:49 AM UTC 24
Finished	Sep 18 08:39:02 AM UTC 24
Peak memory	222160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188834827 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.188834827
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.139482539
Short name	T434
Test name
Test status
Simulation time	60317782598 ps
CPU time	1305.77 seconds
Started	Sep 18 08:37:13 AM UTC 24
Finished	Sep 18 08:59:12 AM UTC 24
Peak memory	382932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139482539 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.139482539
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.77841953
Short name	T234
Test name
Test status
Simulation time	1578512542 ps
CPU time	12.98 seconds
Started	Sep 18 08:37:35 AM UTC 24
Finished	Sep 18 08:37:49 AM UTC 24
Peak memory	211912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77841953 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.77841953
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.4156011393
Short name	T313
Test name
Test status
Simulation time	75932414993 ps
CPU time	507.94 seconds
Started	Sep 18 08:37:50 AM UTC 24
Finished	Sep 18 08:46:25 AM UTC 24
Peak memory	212060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156011393 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acc ess_b2b.4156011393
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1064652166
Short name	T241
Test name
Test status
Simulation time	93101930 ps
CPU time	1.12 seconds
Started	Sep 18 08:38:46 AM UTC 24
Finished	Sep 18 08:38:48 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064652166 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1064652166
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.1426435781
Short name	T431
Test name
Test status
Simulation time	21366365377 ps
CPU time	1209.24 seconds
Started	Sep 18 08:38:44 AM UTC 24
Finished	Sep 18 08:59:06 AM UTC 24
Peak memory	383072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426435781 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1426435781
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.560861890
Short name	T235
Test name
Test status
Simulation time	414709925 ps
CPU time	66.28 seconds
Started	Sep 18 08:37:00 AM UTC 24
Finished	Sep 18 08:38:08 AM UTC 24
Peak memory	337832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560861890 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.560861890
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2290360003
Short name	T467
Test name
Test status
Simulation time	28006441394 ps
CPU time	1349.18 seconds
Started	Sep 18 08:39:27 AM UTC 24
Finished	Sep 18 09:02:10 AM UTC 24
Peak memory	378848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229036000 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.2290360003
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3291288550
Short name	T254
Test name
Test status
Simulation time	7965830510 ps
CPU time	110.21 seconds
Started	Sep 18 08:39:08 AM UTC 24
Finished	Sep 18 08:41:00 AM UTC 24
Peak memory	311324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291288550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3291288550
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.221159866
Short name	T276
Test name
Test status
Simulation time	7877107808 ps
CPU time	318.15 seconds
Started	Sep 18 08:37:34 AM UTC 24
Finished	Sep 18 08:42:57 AM UTC 24
Peak memory	212180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221159866 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.221159866
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2250842546
Short name	T238
Test name
Test status
Simulation time	199120634 ps
CPU time	4.98 seconds
Started	Sep 18 08:38:09 AM UTC 24
Finished	Sep 18 08:38:15 AM UTC 24
Peak memory	233376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2250842546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t hroughput_w_partial_write.2250842546
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3217061068
Short name	T300
Test name
Test status
Simulation time	1482122453 ps
CPU time	276.51 seconds
Started	Sep 18 08:40:22 AM UTC 24
Finished	Sep 18 08:45:02 AM UTC 24
Peak memory	383020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217061068 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during _key_req.3217061068
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3018673443
Short name	T258
Test name
Test status
Simulation time	51200398 ps
CPU time	0.97 seconds
Started	Sep 18 08:41:12 AM UTC 24
Finished	Sep 18 08:41:14 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018673443 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3018673443
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.4117633139
Short name	T251
Test name
Test status
Simulation time	5691940029 ps
CPU time	32.41 seconds
Started	Sep 18 08:40:01 AM UTC 24
Finished	Sep 18 08:40:34 AM UTC 24
Peak memory	212056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117633139 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.4117633139
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1668424603
Short name	T362
Test name
Test status
Simulation time	8847651837 ps
CPU time	683.38 seconds
Started	Sep 18 08:40:35 AM UTC 24
Finished	Sep 18 08:52:08 AM UTC 24
Peak memory	382956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668424603 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.1668424603
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1570888716
Short name	T250
Test name
Test status
Simulation time	206497119 ps
CPU time	1.84 seconds
Started	Sep 18 08:40:18 AM UTC 24
Finished	Sep 18 08:40:21 AM UTC 24
Peak memory	220520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570888716 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.1570888716
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.958954349
Short name	T249
Test name
Test status
Simulation time	64071672 ps
CPU time	7.53 seconds
Started	Sep 18 08:40:09 AM UTC 24
Finished	Sep 18 08:40:17 AM UTC 24
Peak memory	245800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 58954349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_max _throughput.958954349
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1106201653
Short name	T257
Test name
Test status
Simulation time	1190063256 ps
CPU time	8.1 seconds
Started	Sep 18 08:41:02 AM UTC 24
Finished	Sep 18 08:41:11 AM UTC 24
Peak memory	222160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106201653 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.1106201653
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3787701505
Short name	T256
Test name
Test status
Simulation time	899400707 ps
CPU time	12.67 seconds
Started	Sep 18 08:40:55 AM UTC 24
Finished	Sep 18 08:41:08 AM UTC 24
Peak memory	222368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787701505 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3787701505
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3057300848
Short name	T316
Test name
Test status
Simulation time	13550956148 ps
CPU time	436.78 seconds
Started	Sep 18 08:39:54 AM UTC 24
Finished	Sep 18 08:47:15 AM UTC 24
Peak memory	376712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057300848 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.3057300848
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.211518026
Short name	T247
Test name
Test status
Simulation time	1508178511 ps
CPU time	4.02 seconds
Started	Sep 18 08:40:03 AM UTC 24
Finished	Sep 18 08:40:08 AM UTC 24
Peak memory	212188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211518026 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.211518026
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2911990414
Short name	T294
Test name
Test status
Simulation time	31588213945 ps
CPU time	253.95 seconds
Started	Sep 18 08:40:05 AM UTC 24
Finished	Sep 18 08:44:22 AM UTC 24
Peak memory	211976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911990414 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc ess_b2b.2911990414
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4124603287
Short name	T253
Test name
Test status
Simulation time	27981090 ps
CPU time	1.2 seconds
Started	Sep 18 08:40:52 AM UTC 24
Finished	Sep 18 08:40:54 AM UTC 24
Peak memory	211024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124603287 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.4124603287
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2067603953
Short name	T137
Test name
Test status
Simulation time	2225347232 ps
CPU time	277.24 seconds
Started	Sep 18 08:40:51 AM UTC 24
Finished	Sep 18 08:45:32 AM UTC 24
Peak memory	364528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067603953 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2067603953
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2088793794
Short name	T245
Test name
Test status
Simulation time	1824918298 ps
CPU time	13.8 seconds
Started	Sep 18 08:39:44 AM UTC 24
Finished	Sep 18 08:39:59 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088793794 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2088793794
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1416275208
Short name	T881
Test name
Test status
Simulation time	47256344851 ps
CPU time	3397.76 seconds
Started	Sep 18 08:41:09 AM UTC 24
Finished	Sep 18 09:38:21 AM UTC 24
Peak memory	386648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141627520 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.1416275208
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2574595215
Short name	T287
Test name
Test status
Simulation time	3910415740 ps
CPU time	239.66 seconds
Started	Sep 18 08:40:02 AM UTC 24
Finished	Sep 18 08:44:05 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574595215 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2574595215
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2603994582
Short name	T252
Test name
Test status
Simulation time	466471545 ps
CPU time	34.78 seconds
Started	Sep 18 08:40:14 AM UTC 24
Finished	Sep 18 08:40:50 AM UTC 24
Peak memory	333868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2603994582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t hroughput_w_partial_write.2603994582
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2496191386
Short name	T364
Test name
Test status
Simulation time	5199544729 ps
CPU time	588.48 seconds
Started	Sep 18 08:42:20 AM UTC 24
Finished	Sep 18 08:52:15 AM UTC 24
Peak memory	378840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496191386 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during _key_req.2496191386
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.4002237084
Short name	T274
Test name
Test status
Simulation time	15286128 ps
CPU time	0.97 seconds
Started	Sep 18 08:42:50 AM UTC 24
Finished	Sep 18 08:42:52 AM UTC 24
Peak memory	210820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002237084 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.4002237084
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.2566801661
Short name	T268
Test name
Test status
Simulation time	2319279238 ps
CPU time	58.64 seconds
Started	Sep 18 08:41:25 AM UTC 24
Finished	Sep 18 08:42:25 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566801661 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.2566801661
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3324244881
Short name	T414
Test name
Test status
Simulation time	3266786062 ps
CPU time	876.91 seconds
Started	Sep 18 08:42:24 AM UTC 24
Finished	Sep 18 08:57:10 AM UTC 24
Peak memory	380828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324244881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.3324244881
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3983309479
Short name	T266
Test name
Test status
Simulation time	658341827 ps
CPU time	5.05 seconds
Started	Sep 18 08:42:17 AM UTC 24
Finished	Sep 18 08:42:23 AM UTC 24
Peak memory	211920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983309479 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.3983309479
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.714210020
Short name	T279
Test name
Test status
Simulation time	134171576 ps
CPU time	66.94 seconds
Started	Sep 18 08:42:01 AM UTC 24
Finished	Sep 18 08:43:09 AM UTC 24
Peak memory	370740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 14210020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_max _throughput.714210020
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2972864742
Short name	T271
Test name
Test status
Simulation time	577411384 ps
CPU time	7.81 seconds
Started	Sep 18 08:42:38 AM UTC 24
Finished	Sep 18 08:42:47 AM UTC 24
Peak memory	222172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972864742 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2972864742
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3717430588
Short name	T270
Test name
Test status
Simulation time	519766165 ps
CPU time	7.06 seconds
Started	Sep 18 08:42:29 AM UTC 24
Finished	Sep 18 08:42:37 AM UTC 24
Peak memory	222308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717430588 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.3717430588
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2332794090
Short name	T439
Test name
Test status
Simulation time	2848719719 ps
CPU time	1085.76 seconds
Started	Sep 18 08:41:20 AM UTC 24
Finished	Sep 18 08:59:38 AM UTC 24
Peak memory	380800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332794090 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.2332794090
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3172780933
Short name	T280
Test name
Test status
Simulation time	4091412519 ps
CPU time	88.96 seconds
Started	Sep 18 08:41:38 AM UTC 24
Finished	Sep 18 08:43:09 AM UTC 24
Peak memory	362384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172780933 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.3172780933
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2946058568
Short name	T301
Test name
Test status
Simulation time	16433394405 ps
CPU time	210.15 seconds
Started	Sep 18 08:41:50 AM UTC 24
Finished	Sep 18 08:45:24 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946058568 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acc ess_b2b.2946058568
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.890292425
Short name	T269
Test name
Test status
Simulation time	78806975 ps
CPU time	1.06 seconds
Started	Sep 18 08:42:26 AM UTC 24
Finished	Sep 18 08:42:28 AM UTC 24
Peak memory	211080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890292425 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.890292425
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.2672106464
Short name	T297
Test name
Test status
Simulation time	3781998831 ps
CPU time	137.03 seconds
Started	Sep 18 08:42:24 AM UTC 24
Finished	Sep 18 08:44:44 AM UTC 24
Peak memory	309084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672106464 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2672106464
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.691573982
Short name	T260
Test name
Test status
Simulation time	63975555 ps
CPU time	8.73 seconds
Started	Sep 18 08:41:15 AM UTC 24
Finished	Sep 18 08:41:25 AM UTC 24
Peak memory	243596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691573982 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.691573982
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.880258831
Short name	T382
Test name
Test status
Simulation time	21165363824 ps
CPU time	702.55 seconds
Started	Sep 18 08:42:48 AM UTC 24
Finished	Sep 18 08:54:38 AM UTC 24
Peak memory	382888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880258831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.880258831
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.73426659
Short name	T348
Test name
Test status
Simulation time	4972902197 ps
CPU time	457.9 seconds
Started	Sep 18 08:42:46 AM UTC 24
Finished	Sep 18 08:50:29 AM UTC 24
Peak memory	389296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73426659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.73426659
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.1046445103
Short name	T311
Test name
Test status
Simulation time	2481671052 ps
CPU time	289.17 seconds
Started	Sep 18 08:41:25 AM UTC 24
Finished	Sep 18 08:46:19 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046445103 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.1046445103
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.3205434555
Short name	T265
Test name
Test status
Simulation time	642488167 ps
CPU time	16.71 seconds
Started	Sep 18 08:42:02 AM UTC 24
Finished	Sep 18 08:42:20 AM UTC 24
Peak memory	268124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3205434555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_t hroughput_w_partial_write.3205434555
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1109720382
Short name	T432
Test name
Test status
Simulation time	3249112297 ps
CPU time	926.84 seconds
Started	Sep 18 08:43:23 AM UTC 24
Finished	Sep 18 08:59:02 AM UTC 24
Peak memory	383008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109720382 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during _key_req.1109720382
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2232507599
Short name	T292
Test name
Test status
Simulation time	41144596 ps
CPU time	0.95 seconds
Started	Sep 18 08:44:11 AM UTC 24
Finished	Sep 18 08:44:13 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232507599 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2232507599
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.500120791
Short name	T283
Test name
Test status
Simulation time	6944953430 ps
CPU time	40.53 seconds
Started	Sep 18 08:42:52 AM UTC 24
Finished	Sep 18 08:43:34 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500120791 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.500120791
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2274134133
Short name	T507
Test name
Test status
Simulation time	14855713917 ps
CPU time	1281.87 seconds
Started	Sep 18 08:43:29 AM UTC 24
Finished	Sep 18 09:05:05 AM UTC 24
Peak memory	385004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274134133 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.2274134133
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2336988391
Short name	T281
Test name
Test status
Simulation time	1532084738 ps
CPU time	9.88 seconds
Started	Sep 18 08:43:11 AM UTC 24
Finished	Sep 18 08:43:22 AM UTC 24
Peak memory	212008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336988391 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.2336988391
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1879305602
Short name	T285
Test name
Test status
Simulation time	119668214 ps
CPU time	44.3 seconds
Started	Sep 18 08:43:02 AM UTC 24
Finished	Sep 18 08:43:48 AM UTC 24
Peak memory	339888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 879305602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma x_throughput.1879305602
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1799644893
Short name	T291
Test name
Test status
Simulation time	92416449 ps
CPU time	4.6 seconds
Started	Sep 18 08:44:05 AM UTC 24
Finished	Sep 18 08:44:11 AM UTC 24
Peak memory	222236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799644893 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.1799644893
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.601424659
Short name	T289
Test name
Test status
Simulation time	254211074 ps
CPU time	15.22 seconds
Started	Sep 18 08:43:52 AM UTC 24
Finished	Sep 18 08:44:09 AM UTC 24
Peak memory	222112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601424659 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.601424659
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2176720158
Short name	T449
Test name
Test status
Simulation time	57840900114 ps
CPU time	1035.29 seconds
Started	Sep 18 08:42:51 AM UTC 24
Finished	Sep 18 09:00:17 AM UTC 24
Peak memory	383060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176720158 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.2176720158
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1834408475
Short name	T282
Test name
Test status
Simulation time	1261046689 ps
CPU time	29.39 seconds
Started	Sep 18 08:42:57 AM UTC 24
Finished	Sep 18 08:43:28 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834408475 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.1834408475
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.575963813
Short name	T404
Test name
Test status
Simulation time	207429375988 ps
CPU time	807.44 seconds
Started	Sep 18 08:42:59 AM UTC 24
Finished	Sep 18 08:56:37 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575963813 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acce ss_b2b.575963813
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.407943916
Short name	T286
Test name
Test status
Simulation time	25687001 ps
CPU time	1.09 seconds
Started	Sep 18 08:43:49 AM UTC 24
Finished	Sep 18 08:43:51 AM UTC 24
Peak memory	210700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407943916 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.407943916
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1180068615
Short name	T395
Test name
Test status
Simulation time	8771448619 ps
CPU time	724.92 seconds
Started	Sep 18 08:43:35 AM UTC 24
Finished	Sep 18 08:55:48 AM UTC 24
Peak memory	385000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180068615 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1180068615
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.1524254268
Short name	T278
Test name
Test status
Simulation time	295837513 ps
CPU time	9.8 seconds
Started	Sep 18 08:42:51 AM UTC 24
Finished	Sep 18 08:43:02 AM UTC 24
Peak memory	211944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524254268 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1524254268
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.2170396725
Short name	T572
Test name
Test status
Simulation time	115099712327 ps
CPU time	1578.18 seconds
Started	Sep 18 08:44:10 AM UTC 24
Finished	Sep 18 09:10:44 AM UTC 24
Peak memory	393184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217039672 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.2170396725
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3341430610
Short name	T106
Test name
Test status
Simulation time	439574631 ps
CPU time	11.27 seconds
Started	Sep 18 08:44:08 AM UTC 24
Finished	Sep 18 08:44:21 AM UTC 24
Peak memory	222184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341430610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3341430610
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3169391140
Short name	T335
Test name
Test status
Simulation time	14258124969 ps
CPU time	383.18 seconds
Started	Sep 18 08:42:54 AM UTC 24
Finished	Sep 18 08:49:23 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169391140 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.3169391140
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1896446029
Short name	T293
Test name
Test status
Simulation time	279836928 ps
CPU time	69.23 seconds
Started	Sep 18 08:43:10 AM UTC 24
Finished	Sep 18 08:44:21 AM UTC 24
Peak memory	362328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1896446029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.1896446029
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.351667814
Short name	T522
Test name
Test status
Simulation time	4131592298 ps
CPU time	1269.56 seconds
Started	Sep 18 08:44:54 AM UTC 24
Finished	Sep 18 09:06:17 AM UTC 24
Peak memory	382880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351667814 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during_ key_req.351667814
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3683030330
Short name	T306
Test name
Test status
Simulation time	84648294 ps
CPU time	0.9 seconds
Started	Sep 18 08:45:44 AM UTC 24
Finished	Sep 18 08:45:45 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683030330 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3683030330
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1035392277
Short name	T307
Test name
Test status
Simulation time	19007686936 ps
CPU time	84.53 seconds
Started	Sep 18 08:44:22 AM UTC 24
Finished	Sep 18 08:45:48 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035392277 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1035392277
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.330880228
Short name	T590
Test name
Test status
Simulation time	28607216155 ps
CPU time	1684.58 seconds
Started	Sep 18 08:44:58 AM UTC 24
Finished	Sep 18 09:13:20 AM UTC 24
Peak memory	384920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330880228 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.330880228
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.3765770679
Short name	T298
Test name
Test status
Simulation time	1648657976 ps
CPU time	7.05 seconds
Started	Sep 18 08:44:45 AM UTC 24
Finished	Sep 18 08:44:53 AM UTC 24
Peak memory	226388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765770679 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.3765770679
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3216546970
Short name	T309
Test name
Test status
Simulation time	130157934 ps
CPU time	80.78 seconds
Started	Sep 18 08:44:35 AM UTC 24
Finished	Sep 18 08:45:58 AM UTC 24
Peak memory	362544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 216546970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ma x_throughput.3216546970
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2306749634
Short name	T304
Test name
Test status
Simulation time	94170050 ps
CPU time	4.51 seconds
Started	Sep 18 08:45:33 AM UTC 24
Finished	Sep 18 08:45:39 AM UTC 24
Peak memory	222152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306749634 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.2306749634
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1915000597
Short name	T303
Test name
Test status
Simulation time	229293154 ps
CPU time	6.82 seconds
Started	Sep 18 08:45:28 AM UTC 24
Finished	Sep 18 08:45:36 AM UTC 24
Peak memory	212124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915000597 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.1915000597
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2855713790
Short name	T356
Test name
Test status
Simulation time	4276269527 ps
CPU time	433.33 seconds
Started	Sep 18 08:44:14 AM UTC 24
Finished	Sep 18 08:51:32 AM UTC 24
Peak memory	383076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855713790 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.2855713790
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1891931392
Short name	T296
Test name
Test status
Simulation time	2463057448 ps
CPU time	17.23 seconds
Started	Sep 18 08:44:23 AM UTC 24
Finished	Sep 18 08:44:41 AM UTC 24
Peak memory	212200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891931392 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.1891931392
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.341613155
Short name	T374
Test name
Test status
Simulation time	39964432805 ps
CPU time	513.31 seconds
Started	Sep 18 08:44:32 AM UTC 24
Finished	Sep 18 08:53:12 AM UTC 24
Peak memory	212076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341613155 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acce ss_b2b.341613155
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3754691086
Short name	T302
Test name
Test status
Simulation time	56177324 ps
CPU time	1.07 seconds
Started	Sep 18 08:45:25 AM UTC 24
Finished	Sep 18 08:45:27 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754691086 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3754691086
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.3156614980
Short name	T338
Test name
Test status
Simulation time	6854078456 ps
CPU time	266.64 seconds
Started	Sep 18 08:45:03 AM UTC 24
Finished	Sep 18 08:49:33 AM UTC 24
Peak memory	309216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156614980 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3156614980
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3680085984
Short name	T295
Test name
Test status
Simulation time	675664774 ps
CPU time	18.31 seconds
Started	Sep 18 08:44:12 AM UTC 24
Finished	Sep 18 08:44:31 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680085984 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3680085984
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2412864370
Short name	T883
Test name
Test status
Simulation time	30003164057 ps
CPU time	3156.54 seconds
Started	Sep 18 08:45:39 AM UTC 24
Finished	Sep 18 09:38:49 AM UTC 24
Peak memory	394760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241286437 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.2412864370
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.399337940
Short name	T320
Test name
Test status
Simulation time	4481460908 ps
CPU time	113.65 seconds
Started	Sep 18 08:45:37 AM UTC 24
Finished	Sep 18 08:47:34 AM UTC 24
Peak memory	344092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399337940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.399337940
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3425929846
Short name	T350
Test name
Test status
Simulation time	7109534025 ps
CPU time	383.8 seconds
Started	Sep 18 08:44:22 AM UTC 24
Finished	Sep 18 08:50:51 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425929846 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.3425929846
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3250390925
Short name	T299
Test name
Test status
Simulation time	116824763 ps
CPU time	13.25 seconds
Started	Sep 18 08:44:42 AM UTC 24
Finished	Sep 18 08:44:57 AM UTC 24
Peak memory	262184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3250390925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t hroughput_w_partial_write.3250390925
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.4064718845
Short name	T325
Test name
Test status
Simulation time	1005603856 ps
CPU time	86.78 seconds
Started	Sep 18 08:46:45 AM UTC 24
Finished	Sep 18 08:48:13 AM UTC 24
Peak memory	372760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064718845 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during _key_req.4064718845
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.686045435
Short name	T322
Test name
Test status
Simulation time	32710460 ps
CPU time	0.88 seconds
Started	Sep 18 08:47:38 AM UTC 24
Finished	Sep 18 08:47:39 AM UTC 24
Peak memory	210816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686045435 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.686045435
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.3141917698
Short name	T317
Test name
Test status
Simulation time	1062696472 ps
CPU time	78.04 seconds
Started	Sep 18 08:45:57 AM UTC 24
Finished	Sep 18 08:47:17 AM UTC 24
Peak memory	212144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141917698 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.3141917698
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1525627795
Short name	T444
Test name
Test status
Simulation time	15868863924 ps
CPU time	744.72 seconds
Started	Sep 18 08:47:17 AM UTC 24
Finished	Sep 18 08:59:50 AM UTC 24
Peak memory	383052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525627795 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.1525627795
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1202050379
Short name	T315
Test name
Test status
Simulation time	2228386727 ps
CPU time	8.26 seconds
Started	Sep 18 08:46:35 AM UTC 24
Finished	Sep 18 08:46:44 AM UTC 24
Peak memory	212132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202050379 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.1202050379
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2472709029
Short name	T314
Test name
Test status
Simulation time	123149594 ps
CPU time	11.33 seconds
Started	Sep 18 08:46:21 AM UTC 24
Finished	Sep 18 08:46:34 AM UTC 24
Peak memory	262064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 472709029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma x_throughput.2472709029
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2933127521
Short name	T321
Test name
Test status
Simulation time	97998740 ps
CPU time	4.22 seconds
Started	Sep 18 08:47:31 AM UTC 24
Finished	Sep 18 08:47:37 AM UTC 24
Peak memory	222224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933127521 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.2933127521
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1881428758
Short name	T323
Test name
Test status
Simulation time	617461591 ps
CPU time	8.1 seconds
Started	Sep 18 08:47:31 AM UTC 24
Finished	Sep 18 08:47:41 AM UTC 24
Peak memory	212020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881428758 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.1881428758
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2231984110
Short name	T402
Test name
Test status
Simulation time	49183744281 ps
CPU time	637.34 seconds
Started	Sep 18 08:45:49 AM UTC 24
Finished	Sep 18 08:56:33 AM UTC 24
Peak memory	382856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231984110 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.2231984110
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1035015965
Short name	T312
Test name
Test status
Simulation time	1286080197 ps
CPU time	16.96 seconds
Started	Sep 18 08:46:02 AM UTC 24
Finished	Sep 18 08:46:21 AM UTC 24
Peak memory	212064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035015965 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1035015965
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1424169377
Short name	T397
Test name
Test status
Simulation time	27435129770 ps
CPU time	577.35 seconds
Started	Sep 18 08:46:19 AM UTC 24
Finished	Sep 18 08:56:04 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424169377 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acc ess_b2b.1424169377
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1986232062
Short name	T319
Test name
Test status
Simulation time	79023373 ps
CPU time	1.12 seconds
Started	Sep 18 08:47:28 AM UTC 24
Finished	Sep 18 08:47:31 AM UTC 24
Peak memory	211140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986232062 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1986232062
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3760415879
Short name	T428
Test name
Test status
Simulation time	2405187197 ps
CPU time	659.74 seconds
Started	Sep 18 08:47:18 AM UTC 24
Finished	Sep 18 08:58:25 AM UTC 24
Peak memory	378776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760415879 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3760415879
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.2192259112
Short name	T308
Test name
Test status
Simulation time	237505053 ps
CPU time	8.42 seconds
Started	Sep 18 08:45:47 AM UTC 24
Finished	Sep 18 08:45:56 AM UTC 24
Peak memory	211924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192259112 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2192259112
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3355506457
Short name	T890
Test name
Test status
Simulation time	68006702029 ps
CPU time	3143.84 seconds
Started	Sep 18 08:47:36 AM UTC 24
Finished	Sep 18 09:40:31 AM UTC 24
Peak memory	384660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335550645 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.3355506457
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2846846809
Short name	T388
Test name
Test status
Simulation time	6209490785 ps
CPU time	437.84 seconds
Started	Sep 18 08:47:34 AM UTC 24
Finished	Sep 18 08:54:58 AM UTC 24
Peak memory	387116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846846809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2846846809
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3361797167
Short name	T354
Test name
Test status
Simulation time	5957000721 ps
CPU time	310.39 seconds
Started	Sep 18 08:45:59 AM UTC 24
Finished	Sep 18 08:51:14 AM UTC 24
Peak memory	211980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361797167 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.3361797167
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1837632012
Short name	T324
Test name
Test status
Simulation time	1153756957 ps
CPU time	99.11 seconds
Started	Sep 18 08:46:25 AM UTC 24
Finished	Sep 18 08:48:06 AM UTC 24
Peak memory	364460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1837632012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_t hroughput_w_partial_write.1837632012
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3134509190
Short name	T481
Test name
Test status
Simulation time	2840621719 ps
CPU time	867.07 seconds
Started	Sep 18 08:49:01 AM UTC 24
Finished	Sep 18 09:03:38 AM UTC 24
Peak memory	385132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134509190 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during _key_req.3134509190
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.943043817
Short name	T339
Test name
Test status
Simulation time	33714583 ps
CPU time	0.86 seconds
Started	Sep 18 08:49:35 AM UTC 24
Finished	Sep 18 08:49:36 AM UTC 24
Peak memory	211064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943043817 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.943043817
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.1120409671
Short name	T327
Test name
Test status
Simulation time	2383510639 ps
CPU time	21.28 seconds
Started	Sep 18 08:48:07 AM UTC 24
Finished	Sep 18 08:48:29 AM UTC 24
Peak memory	212212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120409671 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.1120409671
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1805473047
Short name	T606
Test name
Test status
Simulation time	137443717864 ps
CPU time	1516.08 seconds
Started	Sep 18 08:49:05 AM UTC 24
Finished	Sep 18 09:14:36 AM UTC 24
Peak memory	384908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805473047 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.1805473047
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.342391074
Short name	T330
Test name
Test status
Simulation time	409175177 ps
CPU time	9.6 seconds
Started	Sep 18 08:48:49 AM UTC 24
Finished	Sep 18 08:48:59 AM UTC 24
Peak memory	211932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342391074 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.342391074
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.403910959
Short name	T332
Test name
Test status
Simulation time	84567584 ps
CPU time	32.4 seconds
Started	Sep 18 08:48:30 AM UTC 24
Finished	Sep 18 08:49:04 AM UTC 24
Peak memory	298908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 03910959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_max _throughput.403910959
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.323588045
Short name	T337
Test name
Test status
Simulation time	181832076 ps
CPU time	3.3 seconds
Started	Sep 18 08:49:23 AM UTC 24
Finished	Sep 18 08:49:28 AM UTC 24
Peak memory	222188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323588045 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.323588045
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.719743304
Short name	T340
Test name
Test status
Simulation time	181656022 ps
CPU time	12.37 seconds
Started	Sep 18 08:49:23 AM UTC 24
Finished	Sep 18 08:49:37 AM UTC 24
Peak memory	222112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719743304 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.719743304
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3215651088
Short name	T442
Test name
Test status
Simulation time	6893751570 ps
CPU time	715.4 seconds
Started	Sep 18 08:47:42 AM UTC 24
Finished	Sep 18 08:59:45 AM UTC 24
Peak memory	381032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215651088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.3215651088
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1479191843
Short name	T331
Test name
Test status
Simulation time	331941314 ps
CPU time	45.94 seconds
Started	Sep 18 08:48:16 AM UTC 24
Finished	Sep 18 08:49:04 AM UTC 24
Peak memory	331672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479191843 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.1479191843
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3315828719
Short name	T373
Test name
Test status
Simulation time	3806913816 ps
CPU time	281.29 seconds
Started	Sep 18 08:48:22 AM UTC 24
Finished	Sep 18 08:53:07 AM UTC 24
Peak memory	211984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315828719 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc ess_b2b.3315828719
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1043334001
Short name	T336
Test name
Test status
Simulation time	31265731 ps
CPU time	1.01 seconds
Started	Sep 18 08:49:22 AM UTC 24
Finished	Sep 18 08:49:24 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043334001 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1043334001
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.630355585
Short name	T398
Test name
Test status
Simulation time	14175614055 ps
CPU time	425.54 seconds
Started	Sep 18 08:49:05 AM UTC 24
Finished	Sep 18 08:56:16 AM UTC 24
Peak memory	382936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630355585 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.630355585
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.2987440553
Short name	T334
Test name
Test status
Simulation time	741112224 ps
CPU time	99.28 seconds
Started	Sep 18 08:47:41 AM UTC 24
Finished	Sep 18 08:49:22 AM UTC 24
Peak memory	378792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987440553 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2987440553
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.817775471
Short name	T399
Test name
Test status
Simulation time	5696915462 ps
CPU time	414.82 seconds
Started	Sep 18 08:49:28 AM UTC 24
Finished	Sep 18 08:56:28 AM UTC 24
Peak memory	379044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817775471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.817775471
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2021972523
Short name	T360
Test name
Test status
Simulation time	1946473785 ps
CPU time	144.39 seconds
Started	Sep 18 08:49:25 AM UTC 24
Finished	Sep 18 08:51:52 AM UTC 24
Peak memory	386984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021972523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2021972523
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2340762674
Short name	T361
Test name
Test status
Simulation time	1993581559 ps
CPU time	229.75 seconds
Started	Sep 18 08:48:14 AM UTC 24
Finished	Sep 18 08:52:07 AM UTC 24
Peak memory	211940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340762674 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2340762674
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1450819971
Short name	T341
Test name
Test status
Simulation time	621624336 ps
CPU time	71.85 seconds
Started	Sep 18 08:48:30 AM UTC 24
Finished	Sep 18 08:49:44 AM UTC 24
Peak memory	378784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1450819971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t hroughput_w_partial_write.1450819971
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3265154053
Short name	T450
Test name
Test status
Simulation time	6374350953 ps
CPU time	583.43 seconds
Started	Sep 18 08:50:30 AM UTC 24
Finished	Sep 18 09:00:20 AM UTC 24
Peak memory	380888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265154053 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during _key_req.3265154053
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3598171036
Short name	T358
Test name
Test status
Simulation time	43067491 ps
CPU time	0.91 seconds
Started	Sep 18 08:51:34 AM UTC 24
Finished	Sep 18 08:51:36 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598171036 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3598171036
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.4192994124
Short name	T347
Test name
Test status
Simulation time	2410642221 ps
CPU time	38.09 seconds
Started	Sep 18 08:49:45 AM UTC 24
Finished	Sep 18 08:50:24 AM UTC 24
Peak memory	212132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192994124 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.4192994124
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.3596926949
Short name	T487
Test name
Test status
Simulation time	65734566571 ps
CPU time	792.4 seconds
Started	Sep 18 08:50:36 AM UTC 24
Finished	Sep 18 09:03:57 AM UTC 24
Peak memory	376740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596926949 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.3596926949
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.450308703
Short name	T349
Test name
Test status
Simulation time	1877698785 ps
CPU time	8.49 seconds
Started	Sep 18 08:50:26 AM UTC 24
Finished	Sep 18 08:50:35 AM UTC 24
Peak memory	212012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450308703 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.450308703
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3752641128
Short name	T363
Test name
Test status
Simulation time	506567774 ps
CPU time	109.63 seconds
Started	Sep 18 08:50:20 AM UTC 24
Finished	Sep 18 08:52:13 AM UTC 24
Peak memory	366492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 752641128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma x_throughput.3752641128
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1387301475
Short name	T355
Test name
Test status
Simulation time	425567567 ps
CPU time	7.44 seconds
Started	Sep 18 08:51:07 AM UTC 24
Finished	Sep 18 08:51:16 AM UTC 24
Peak memory	222300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387301475 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1387301475
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3107040859
Short name	T353
Test name
Test status
Simulation time	365903733 ps
CPU time	7.5 seconds
Started	Sep 18 08:50:58 AM UTC 24
Finished	Sep 18 08:51:07 AM UTC 24
Peak memory	222228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107040859 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.3107040859
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1313430861
Short name	T422
Test name
Test status
Simulation time	9565098460 ps
CPU time	507.4 seconds
Started	Sep 18 08:49:38 AM UTC 24
Finished	Sep 18 08:58:11 AM UTC 24
Peak memory	384916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313430861 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1313430861
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3710710269
Short name	T346
Test name
Test status
Simulation time	635062218 ps
CPU time	12.81 seconds
Started	Sep 18 08:50:08 AM UTC 24
Finished	Sep 18 08:50:22 AM UTC 24
Peak memory	212068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710710269 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.3710710269
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2046660396
Short name	T412
Test name
Test status
Simulation time	26993969486 ps
CPU time	404.07 seconds
Started	Sep 18 08:50:14 AM UTC 24
Finished	Sep 18 08:57:04 AM UTC 24
Peak memory	211976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046660396 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc ess_b2b.2046660396
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.2077281332
Short name	T352
Test name
Test status
Simulation time	55057015 ps
CPU time	0.97 seconds
Started	Sep 18 08:50:55 AM UTC 24
Finished	Sep 18 08:50:57 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077281332 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2077281332
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.776409997
Short name	T483
Test name
Test status
Simulation time	10880532110 ps
CPU time	763.26 seconds
Started	Sep 18 08:50:52 AM UTC 24
Finished	Sep 18 09:03:44 AM UTC 24
Peak memory	374676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776409997 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.776409997
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2857538794
Short name	T342
Test name
Test status
Simulation time	892572583 ps
CPU time	22.31 seconds
Started	Sep 18 08:49:38 AM UTC 24
Finished	Sep 18 08:50:01 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857538794 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2857538794
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3298036618
Short name	T927
Test name
Test status
Simulation time	74263139961 ps
CPU time	4282.71 seconds
Started	Sep 18 08:51:16 AM UTC 24
Finished	Sep 18 10:03:25 AM UTC 24
Peak memory	386692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329803661 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.3298036618
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.1516047472
Short name	T394
Test name
Test status
Simulation time	5019875991 ps
CPU time	310.72 seconds
Started	Sep 18 08:50:02 AM UTC 24
Finished	Sep 18 08:55:17 AM UTC 24
Peak memory	212192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516047472 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.1516047472
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.3799308106
Short name	T351
Test name
Test status
Simulation time	591774878 ps
CPU time	30.36 seconds
Started	Sep 18 08:50:22 AM UTC 24
Finished	Sep 18 08:50:54 AM UTC 24
Peak memory	294960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3799308106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_t hroughput_w_partial_write.3799308106
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3225181468
Short name	T39
Test name
Test status
Simulation time	1824410050 ps
CPU time	327.07 seconds
Started	Sep 18 08:24:10 AM UTC 24
Finished	Sep 18 08:29:41 AM UTC 24
Peak memory	378660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225181468 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_ key_req.3225181468
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3991952025
Short name	T14
Test name
Test status
Simulation time	38719355 ps
CPU time	0.96 seconds
Started	Sep 18 08:24:45 AM UTC 24
Finished	Sep 18 08:24:47 AM UTC 24
Peak memory	210648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991952025 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3991952025
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2739965022
Short name	T18
Test name
Test status
Simulation time	1043889023 ps
CPU time	54.51 seconds
Started	Sep 18 08:24:02 AM UTC 24
Finished	Sep 18 08:24:58 AM UTC 24
Peak memory	211932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739965022 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.2739965022
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1281709055
Short name	T41
Test name
Test status
Simulation time	18002166883 ps
CPU time	236.03 seconds
Started	Sep 18 08:24:11 AM UTC 24
Finished	Sep 18 08:28:10 AM UTC 24
Peak memory	335780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281709055 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.1281709055
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3200928771
Short name	T8
Test name
Test status
Simulation time	516814751 ps
CPU time	2.56 seconds
Started	Sep 18 08:24:07 AM UTC 24
Finished	Sep 18 08:24:10 AM UTC 24
Peak memory	223964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200928771 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.3200928771
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1140474458
Short name	T29
Test name
Test status
Simulation time	142591992 ps
CPU time	18.15 seconds
Started	Sep 18 08:24:04 AM UTC 24
Finished	Sep 18 08:24:24 AM UTC 24
Peak memory	266288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 140474458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max _throughput.1140474458
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3019343662
Short name	T37
Test name
Test status
Simulation time	97424273 ps
CPU time	4.66 seconds
Started	Sep 18 08:24:28 AM UTC 24
Finished	Sep 18 08:24:34 AM UTC 24
Peak memory	222244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019343662 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.3019343662
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.18826112
Short name	T36
Test name
Test status
Simulation time	102533681 ps
CPU time	5.83 seconds
Started	Sep 18 08:24:26 AM UTC 24
Finished	Sep 18 08:24:33 AM UTC 24
Peak memory	211908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18826112 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.18826112
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2959376834
Short name	T141
Test name
Test status
Simulation time	16278124208 ps
CPU time	340.97 seconds
Started	Sep 18 08:24:01 AM UTC 24
Finished	Sep 18 08:29:46 AM UTC 24
Peak memory	372836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959376834 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.2959376834
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3003158993
Short name	T68
Test name
Test status
Simulation time	267777393 ps
CPU time	131.5 seconds
Started	Sep 18 08:24:02 AM UTC 24
Finished	Sep 18 08:26:16 AM UTC 24
Peak memory	378916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003158993 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.3003158993
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2813113092
Short name	T139
Test name
Test status
Simulation time	61288433747 ps
CPU time	459.7 seconds
Started	Sep 18 08:24:03 AM UTC 24
Finished	Sep 18 08:31:49 AM UTC 24
Peak memory	212056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813113092 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce ss_b2b.2813113092
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2476069673
Short name	T30
Test name
Test status
Simulation time	30584394 ps
CPU time	1.33 seconds
Started	Sep 18 08:24:25 AM UTC 24
Finished	Sep 18 08:24:27 AM UTC 24
Peak memory	210696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476069673 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2476069673
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.4270990651
Short name	T133
Test name
Test status
Simulation time	10325668788 ps
CPU time	766.83 seconds
Started	Sep 18 08:24:19 AM UTC 24
Finished	Sep 18 08:37:15 AM UTC 24
Peak memory	358376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270990651 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.4270990651
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1663792734
Short name	T16
Test name
Test status
Simulation time	372407450 ps
CPU time	4.24 seconds
Started	Sep 18 08:24:38 AM UTC 24
Finished	Sep 18 08:24:44 AM UTC 24
Peak memory	247732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663792734 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1663792734
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1621454103
Short name	T33
Test name
Test status
Simulation time	49181550 ps
CPU time	3.28 seconds
Started	Sep 18 08:24:01 AM UTC 24
Finished	Sep 18 08:24:05 AM UTC 24
Peak memory	211908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621454103 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1621454103
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3407732306
Short name	T379
Test name
Test status
Simulation time	24592219187 ps
CPU time	1768.1 seconds
Started	Sep 18 08:24:34 AM UTC 24
Finished	Sep 18 08:54:21 AM UTC 24
Peak memory	378792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340773230 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.3407732306
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2685894442
Short name	T104
Test name
Test status
Simulation time	3349812668 ps
CPU time	422.29 seconds
Started	Sep 18 08:24:02 AM UTC 24
Finished	Sep 18 08:31:10 AM UTC 24
Peak memory	212188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685894442 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.2685894442
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3393889947
Short name	T28
Test name
Test status
Simulation time	108580774 ps
CPU time	38.56 seconds
Started	Sep 18 08:24:04 AM UTC 24
Finished	Sep 18 08:24:44 AM UTC 24
Peak memory	311128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3393889947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th roughput_w_partial_write.3393889947
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.564408710
Short name	T415
Test name
Test status
Simulation time	5686217507 ps
CPU time	285.03 seconds
Started	Sep 18 08:52:24 AM UTC 24
Finished	Sep 18 08:57:13 AM UTC 24
Peak memory	382868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564408710 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during_ key_req.564408710
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.597898115
Short name	T375
Test name
Test status
Simulation time	11464853 ps
CPU time	0.81 seconds
Started	Sep 18 08:53:13 AM UTC 24
Finished	Sep 18 08:53:15 AM UTC 24
Peak memory	211064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597898115 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.597898115
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.1088257002
Short name	T365
Test name
Test status
Simulation time	3668006798 ps
CPU time	25.21 seconds
Started	Sep 18 08:51:53 AM UTC 24
Finished	Sep 18 08:52:19 AM UTC 24
Peak memory	211680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088257002 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.1088257002
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3889860935
Short name	T424
Test name
Test status
Simulation time	3143280355 ps
CPU time	339.37 seconds
Started	Sep 18 08:52:31 AM UTC 24
Finished	Sep 18 08:58:15 AM UTC 24
Peak memory	376808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889860935 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.3889860935
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2812081145
Short name	T367
Test name
Test status
Simulation time	736165367 ps
CPU time	7.38 seconds
Started	Sep 18 08:52:21 AM UTC 24
Finished	Sep 18 08:52:30 AM UTC 24
Peak memory	211928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812081145 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.2812081145
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3695221347
Short name	T369
Test name
Test status
Simulation time	89864140 ps
CPU time	28.45 seconds
Started	Sep 18 08:52:14 AM UTC 24
Finished	Sep 18 08:52:45 AM UTC 24
Peak memory	298924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 695221347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ma x_throughput.3695221347
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1521259006
Short name	T372
Test name
Test status
Simulation time	340999305 ps
CPU time	7.16 seconds
Started	Sep 18 08:52:57 AM UTC 24
Finished	Sep 18 08:53:06 AM UTC 24
Peak memory	222364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521259006 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.1521259006
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2325797628
Short name	T371
Test name
Test status
Simulation time	88884204 ps
CPU time	6.18 seconds
Started	Sep 18 08:52:49 AM UTC 24
Finished	Sep 18 08:52:56 AM UTC 24
Peak memory	222236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325797628 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.2325797628
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2119482047
Short name	T464
Test name
Test status
Simulation time	52848147789 ps
CPU time	583.92 seconds
Started	Sep 18 08:51:53 AM UTC 24
Finished	Sep 18 09:01:43 AM UTC 24
Peak memory	382548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119482047 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.2119482047
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.117199278
Short name	T368
Test name
Test status
Simulation time	476274718 ps
CPU time	33.59 seconds
Started	Sep 18 08:52:08 AM UTC 24
Finished	Sep 18 08:52:43 AM UTC 24
Peak memory	299116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117199278 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.117199278
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2877614851
Short name	T454
Test name
Test status
Simulation time	15384438263 ps
CPU time	495.94 seconds
Started	Sep 18 08:52:13 AM UTC 24
Finished	Sep 18 09:00:36 AM UTC 24
Peak memory	212076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877614851 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc ess_b2b.2877614851
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2107625849
Short name	T370
Test name
Test status
Simulation time	82374701 ps
CPU time	1.08 seconds
Started	Sep 18 08:52:46 AM UTC 24
Finished	Sep 18 08:52:48 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107625849 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2107625849
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.3632554138
Short name	T378
Test name
Test status
Simulation time	5038202516 ps
CPU time	73.73 seconds
Started	Sep 18 08:52:44 AM UTC 24
Finished	Sep 18 08:54:00 AM UTC 24
Peak memory	264148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632554138 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3632554138
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2437177088
Short name	T359
Test name
Test status
Simulation time	244196151 ps
CPU time	13.6 seconds
Started	Sep 18 08:51:37 AM UTC 24
Finished	Sep 18 08:51:52 AM UTC 24
Peak memory	212000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437177088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2437177088
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1511444506
Short name	T793
Test name
Test status
Simulation time	70145600399 ps
CPU time	2294.15 seconds
Started	Sep 18 08:53:09 AM UTC 24
Finished	Sep 18 09:31:46 AM UTC 24
Peak memory	384920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151144450 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.1511444506
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.395699716
Short name	T377
Test name
Test status
Simulation time	4110907569 ps
CPU time	24.18 seconds
Started	Sep 18 08:53:07 AM UTC 24
Finished	Sep 18 08:53:32 AM UTC 24
Peak memory	226468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395699716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.395699716
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2331502470
Short name	T383
Test name
Test status
Simulation time	6656036309 ps
CPU time	153.61 seconds
Started	Sep 18 08:52:08 AM UTC 24
Finished	Sep 18 08:54:44 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331502470 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.2331502470
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.400648537
Short name	T376
Test name
Test status
Simulation time	127359708 ps
CPU time	61.75 seconds
Started	Sep 18 08:52:16 AM UTC 24
Finished	Sep 18 08:53:20 AM UTC 24
Peak memory	337952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 400648537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_th roughput_w_partial_write.400648537
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2928081709
Short name	T594
Test name
Test status
Simulation time	3642302040 ps
CPU time	1117.99 seconds
Started	Sep 18 08:54:39 AM UTC 24
Finished	Sep 18 09:13:29 AM UTC 24
Peak memory	376736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928081709 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during _key_req.2928081709
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2774231255
Short name	T392
Test name
Test status
Simulation time	17596975 ps
CPU time	0.84 seconds
Started	Sep 18 08:55:05 AM UTC 24
Finished	Sep 18 08:55:07 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774231255 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2774231255
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2797835741
Short name	T380
Test name
Test status
Simulation time	738817337 ps
CPU time	53.77 seconds
Started	Sep 18 08:53:26 AM UTC 24
Finished	Sep 18 08:54:21 AM UTC 24
Peak memory	211924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797835741 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.2797835741
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1019954395
Short name	T413
Test name
Test status
Simulation time	5834262239 ps
CPU time	138.75 seconds
Started	Sep 18 08:54:45 AM UTC 24
Finished	Sep 18 08:57:06 AM UTC 24
Peak memory	376736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019954395 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.1019954395
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.622993441
Short name	T384
Test name
Test status
Simulation time	2005835786 ps
CPU time	8.41 seconds
Started	Sep 18 08:54:36 AM UTC 24
Finished	Sep 18 08:54:45 AM UTC 24
Peak memory	226256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622993441 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.622993441
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1209346594
Short name	T385
Test name
Test status
Simulation time	371889046 ps
CPU time	29.17 seconds
Started	Sep 18 08:54:23 AM UTC 24
Finished	Sep 18 08:54:53 AM UTC 24
Peak memory	303148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 209346594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma x_throughput.1209346594
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3390051360
Short name	T389
Test name
Test status
Simulation time	164026742 ps
CPU time	3.69 seconds
Started	Sep 18 08:54:58 AM UTC 24
Finished	Sep 18 08:55:02 AM UTC 24
Peak memory	222224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390051360 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.3390051360
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2772752165
Short name	T390
Test name
Test status
Simulation time	271305608 ps
CPU time	6.14 seconds
Started	Sep 18 08:54:56 AM UTC 24
Finished	Sep 18 08:55:04 AM UTC 24
Peak memory	222184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772752165 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.2772752165
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1463404466
Short name	T543
Test name
Test status
Simulation time	10126412835 ps
CPU time	852.74 seconds
Started	Sep 18 08:53:21 AM UTC 24
Finished	Sep 18 09:07:43 AM UTC 24
Peak memory	382936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463404466 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.1463404466
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2621123594
Short name	T381
Test name
Test status
Simulation time	498853694 ps
CPU time	33.7 seconds
Started	Sep 18 08:54:00 AM UTC 24
Finished	Sep 18 08:54:35 AM UTC 24
Peak memory	307024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621123594 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2621123594
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.869949832
Short name	T461
Test name
Test status
Simulation time	5352821908 ps
CPU time	396.19 seconds
Started	Sep 18 08:54:21 AM UTC 24
Finished	Sep 18 09:01:03 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869949832 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acce ss_b2b.869949832
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.678089514
Short name	T387
Test name
Test status
Simulation time	28088270 ps
CPU time	1.05 seconds
Started	Sep 18 08:54:54 AM UTC 24
Finished	Sep 18 08:54:56 AM UTC 24
Peak memory	210700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678089514 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.678089514
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1041970979
Short name	T500
Test name
Test status
Simulation time	1264097630 ps
CPU time	579.62 seconds
Started	Sep 18 08:54:46 AM UTC 24
Finished	Sep 18 09:04:32 AM UTC 24
Peak memory	370516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041970979 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1041970979
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.949748290
Short name	T357
Test name
Test status
Simulation time	532466761 ps
CPU time	8.09 seconds
Started	Sep 18 08:53:16 AM UTC 24
Finished	Sep 18 08:53:25 AM UTC 24
Peak memory	212000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949748290 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.949748290
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3647724285
Short name	T799
Test name
Test status
Simulation time	35613638370 ps
CPU time	2227.66 seconds
Started	Sep 18 08:55:03 AM UTC 24
Finished	Sep 18 09:32:34 AM UTC 24
Peak memory	384920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364772428 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.3647724285
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1669834671
Short name	T465
Test name
Test status
Simulation time	8926460459 ps
CPU time	400.91 seconds
Started	Sep 18 08:54:59 AM UTC 24
Finished	Sep 18 09:01:44 AM UTC 24
Peak memory	389148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669834671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1669834671
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2084964455
Short name	T405
Test name
Test status
Simulation time	7192409584 ps
CPU time	183.34 seconds
Started	Sep 18 08:53:33 AM UTC 24
Finished	Sep 18 08:56:39 AM UTC 24
Peak memory	212208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084964455 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.2084964455
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2569689
Short name	T386
Test name
Test status
Simulation time	401047444 ps
CPU time	25.32 seconds
Started	Sep 18 08:54:29 AM UTC 24
Finished	Sep 18 08:54:55 AM UTC 24
Peak memory	298908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2569689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_thro ughput_w_partial_write.2569689
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.262294061
Short name	T537
Test name
Test status
Simulation time	10174610564 ps
CPU time	638.42 seconds
Started	Sep 18 08:56:29 AM UTC 24
Finished	Sep 18 09:07:15 AM UTC 24
Peak memory	380948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262294061 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during_ key_req.262294061
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2958012810
Short name	T408
Test name
Test status
Simulation time	81195965 ps
CPU time	0.95 seconds
Started	Sep 18 08:56:43 AM UTC 24
Finished	Sep 18 08:56:45 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958012810 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2958012810
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3683759666
Short name	T401
Test name
Test status
Simulation time	1075856326 ps
CPU time	80.01 seconds
Started	Sep 18 08:55:09 AM UTC 24
Finished	Sep 18 08:56:31 AM UTC 24
Peak memory	212128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683759666 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.3683759666
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.899928568
Short name	T547
Test name
Test status
Simulation time	1972987829 ps
CPU time	690.81 seconds
Started	Sep 18 08:56:30 AM UTC 24
Finished	Sep 18 09:08:10 AM UTC 24
Peak memory	378712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899928568 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.899928568
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3404294913
Short name	T400
Test name
Test status
Simulation time	923370165 ps
CPU time	12.63 seconds
Started	Sep 18 08:56:16 AM UTC 24
Finished	Sep 18 08:56:30 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404294913 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.3404294913
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.541116169
Short name	T419
Test name
Test status
Simulation time	340607746 ps
CPU time	111.7 seconds
Started	Sep 18 08:55:55 AM UTC 24
Finished	Sep 18 08:57:49 AM UTC 24
Peak memory	378928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 41116169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max _throughput.541116169
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.557694175
Short name	T407
Test name
Test status
Simulation time	957961124 ps
CPU time	3.4 seconds
Started	Sep 18 08:56:38 AM UTC 24
Finished	Sep 18 08:56:42 AM UTC 24
Peak memory	222180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557694175 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.557694175
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1363993813
Short name	T409
Test name
Test status
Simulation time	354371956 ps
CPU time	7.12 seconds
Started	Sep 18 08:56:38 AM UTC 24
Finished	Sep 18 08:56:46 AM UTC 24
Peak memory	222316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363993813 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.1363993813
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3475999874
Short name	T546
Test name
Test status
Simulation time	103663211937 ps
CPU time	756.96 seconds
Started	Sep 18 08:55:07 AM UTC 24
Finished	Sep 18 09:07:53 AM UTC 24
Peak memory	380908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475999874 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.3475999874
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2274912478
Short name	T396
Test name
Test status
Simulation time	1926705189 ps
CPU time	32.27 seconds
Started	Sep 18 08:55:20 AM UTC 24
Finished	Sep 18 08:55:54 AM UTC 24
Peak memory	211916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274912478 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.2274912478
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.815591269
Short name	T490
Test name
Test status
Simulation time	52470226592 ps
CPU time	486.06 seconds
Started	Sep 18 08:55:49 AM UTC 24
Finished	Sep 18 09:04:01 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815591269 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acce ss_b2b.815591269
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.862466375
Short name	T403
Test name
Test status
Simulation time	109265438 ps
CPU time	1.05 seconds
Started	Sep 18 08:56:34 AM UTC 24
Finished	Sep 18 08:56:36 AM UTC 24
Peak memory	210700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862466375 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.862466375
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.3849218917
Short name	T583
Test name
Test status
Simulation time	112070776508 ps
CPU time	951.69 seconds
Started	Sep 18 08:56:32 AM UTC 24
Finished	Sep 18 09:12:35 AM UTC 24
Peak memory	376720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849218917 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3849218917
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.1137928387
Short name	T393
Test name
Test status
Simulation time	34208526 ps
CPU time	2.83 seconds
Started	Sep 18 08:55:05 AM UTC 24
Finished	Sep 18 08:55:09 AM UTC 24
Peak memory	218168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137928387 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1137928387
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1437814722
Short name	T774
Test name
Test status
Simulation time	101136380530 ps
CPU time	1949.47 seconds
Started	Sep 18 08:56:41 AM UTC 24
Finished	Sep 18 09:29:32 AM UTC 24
Peak memory	384928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143781472 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.1437814722
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2782094971
Short name	T107
Test name
Test status
Simulation time	3745536459 ps
CPU time	35.27 seconds
Started	Sep 18 08:56:41 AM UTC 24
Finished	Sep 18 08:57:17 AM UTC 24
Peak memory	237600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782094971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2782094971
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.3362792556
Short name	T462
Test name
Test status
Simulation time	6744878847 ps
CPU time	351.27 seconds
Started	Sep 18 08:55:18 AM UTC 24
Finished	Sep 18 09:01:15 AM UTC 24
Peak memory	212060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362792556 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.3362792556
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2734741478
Short name	T406
Test name
Test status
Simulation time	225034227 ps
CPU time	33.59 seconds
Started	Sep 18 08:56:05 AM UTC 24
Finished	Sep 18 08:56:40 AM UTC 24
Peak memory	311120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2734741478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t hroughput_w_partial_write.2734741478
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.1056015820
Short name	T531
Test name
Test status
Simulation time	5232667385 ps
CPU time	565.47 seconds
Started	Sep 18 08:57:18 AM UTC 24
Finished	Sep 18 09:06:50 AM UTC 24
Peak memory	381028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056015820 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during _key_req.1056015820
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2509398578
Short name	T426
Test name
Test status
Simulation time	24263197 ps
CPU time	1 seconds
Started	Sep 18 08:58:16 AM UTC 24
Finished	Sep 18 08:58:18 AM UTC 24
Peak memory	210816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509398578 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2509398578
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.1079974827
Short name	T423
Test name
Test status
Simulation time	16372440978 ps
CPU time	81.3 seconds
Started	Sep 18 08:56:49 AM UTC 24
Finished	Sep 18 08:58:12 AM UTC 24
Peak memory	212064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079974827 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.1079974827
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.3439302978
Short name	T535
Test name
Test status
Simulation time	3273435566 ps
CPU time	568.7 seconds
Started	Sep 18 08:57:27 AM UTC 24
Finished	Sep 18 09:07:02 AM UTC 24
Peak memory	376744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439302978 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.3439302978
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2836884359
Short name	T418
Test name
Test status
Simulation time	363330450 ps
CPU time	8.31 seconds
Started	Sep 18 08:57:18 AM UTC 24
Finished	Sep 18 08:57:27 AM UTC 24
Peak memory	224284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836884359 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2836884359
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1186012790
Short name	T429
Test name
Test status
Simulation time	715891612 ps
CPU time	78.37 seconds
Started	Sep 18 08:57:11 AM UTC 24
Finished	Sep 18 08:58:31 AM UTC 24
Peak memory	378728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 186012790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma x_throughput.1186012790
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3768318693
Short name	T425
Test name
Test status
Simulation time	210639992 ps
CPU time	4.91 seconds
Started	Sep 18 08:58:09 AM UTC 24
Finished	Sep 18 08:58:15 AM UTC 24
Peak memory	222104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768318693 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3768318693
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.1087817954
Short name	T421
Test name
Test status
Simulation time	1921412097 ps
CPU time	15.63 seconds
Started	Sep 18 08:57:52 AM UTC 24
Finished	Sep 18 08:58:09 AM UTC 24
Peak memory	222244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087817954 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.1087817954
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2200343349
Short name	T611
Test name
Test status
Simulation time	14875399249 ps
CPU time	1077.95 seconds
Started	Sep 18 08:56:47 AM UTC 24
Finished	Sep 18 09:14:57 AM UTC 24
Peak memory	384996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200343349 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2200343349
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2056509945
Short name	T417
Test name
Test status
Simulation time	2831096117 ps
CPU time	20.79 seconds
Started	Sep 18 08:57:04 AM UTC 24
Finished	Sep 18 08:57:26 AM UTC 24
Peak memory	212188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056509945 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2056509945
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3874580102
Short name	T499
Test name
Test status
Simulation time	22145265094 ps
CPU time	438.86 seconds
Started	Sep 18 08:57:07 AM UTC 24
Finished	Sep 18 09:04:32 AM UTC 24
Peak memory	212184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874580102 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acc ess_b2b.3874580102
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3436648136
Short name	T420
Test name
Test status
Simulation time	79355671 ps
CPU time	1.12 seconds
Started	Sep 18 08:57:49 AM UTC 24
Finished	Sep 18 08:57:51 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436648136 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3436648136
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.2906734304
Short name	T551
Test name
Test status
Simulation time	12578244164 ps
CPU time	646.37 seconds
Started	Sep 18 08:57:28 AM UTC 24
Finished	Sep 18 09:08:22 AM UTC 24
Peak memory	384984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906734304 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2906734304
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.3680645868
Short name	T411
Test name
Test status
Simulation time	503840475 ps
CPU time	12.3 seconds
Started	Sep 18 08:56:46 AM UTC 24
Finished	Sep 18 08:56:59 AM UTC 24
Peak memory	274252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680645868 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3680645868
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1581810456
Short name	T717
Test name
Test status
Simulation time	5274077463 ps
CPU time	1574.48 seconds
Started	Sep 18 08:58:14 AM UTC 24
Finished	Sep 18 09:24:45 AM UTC 24
Peak memory	382868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158181045 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.1581810456
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.524466667
Short name	T108
Test name
Test status
Simulation time	4218120092 ps
CPU time	180.74 seconds
Started	Sep 18 08:58:12 AM UTC 24
Finished	Sep 18 09:01:15 AM UTC 24
Peak memory	387224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524466667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.524466667
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2681646383
Short name	T460
Test name
Test status
Simulation time	2324275098 ps
CPU time	236.53 seconds
Started	Sep 18 08:57:00 AM UTC 24
Finished	Sep 18 09:01:01 AM UTC 24
Peak memory	212132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681646383 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.2681646383
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1303453300
Short name	T416
Test name
Test status
Simulation time	42209896 ps
CPU time	2.36 seconds
Started	Sep 18 08:57:14 AM UTC 24
Finished	Sep 18 08:57:17 AM UTC 24
Peak memory	222240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1303453300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_t hroughput_w_partial_write.1303453300
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3175972335
Short name	T479
Test name
Test status
Simulation time	476020672 ps
CPU time	258.82 seconds
Started	Sep 18 08:59:09 AM UTC 24
Finished	Sep 18 09:03:32 AM UTC 24
Peak memory	382876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175972335 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during _key_req.3175972335
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3247420494
Short name	T441
Test name
Test status
Simulation time	37315768 ps
CPU time	0.87 seconds
Started	Sep 18 08:59:42 AM UTC 24
Finished	Sep 18 08:59:44 AM UTC 24
Peak memory	210988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247420494 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3247420494
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1748464433
Short name	T436
Test name
Test status
Simulation time	4369376480 ps
CPU time	63.56 seconds
Started	Sep 18 08:58:26 AM UTC 24
Finished	Sep 18 08:59:31 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748464433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.1748464433
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2108286842
Short name	T445
Test name
Test status
Simulation time	435568115 ps
CPU time	42.08 seconds
Started	Sep 18 08:59:13 AM UTC 24
Finished	Sep 18 08:59:57 AM UTC 24
Peak memory	292764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108286842 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.2108286842
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.984640359
Short name	T435
Test name
Test status
Simulation time	969078250 ps
CPU time	5.27 seconds
Started	Sep 18 08:59:07 AM UTC 24
Finished	Sep 18 08:59:13 AM UTC 24
Peak memory	211796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984640359 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.984640359
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2717916914
Short name	T437
Test name
Test status
Simulation time	705173208 ps
CPU time	37.87 seconds
Started	Sep 18 08:58:53 AM UTC 24
Finished	Sep 18 08:59:32 AM UTC 24
Peak memory	311128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 717916914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ma x_throughput.2717916914
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3003699863
Short name	T440
Test name
Test status
Simulation time	863982461 ps
CPU time	4.21 seconds
Started	Sep 18 08:59:36 AM UTC 24
Finished	Sep 18 08:59:41 AM UTC 24
Peak memory	222160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003699863 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.3003699863
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3792555218
Short name	T443
Test name
Test status
Simulation time	470164738 ps
CPU time	15.17 seconds
Started	Sep 18 08:59:32 AM UTC 24
Finished	Sep 18 08:59:49 AM UTC 24
Peak memory	222372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792555218 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.3792555218
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.24226597
Short name	T514
Test name
Test status
Simulation time	11357936868 ps
CPU time	432.51 seconds
Started	Sep 18 08:58:19 AM UTC 24
Finished	Sep 18 09:05:37 AM UTC 24
Peak memory	378768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24226597 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.24226597
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1856539621
Short name	T446
Test name
Test status
Simulation time	385097307 ps
CPU time	84.99 seconds
Started	Sep 18 08:58:31 AM UTC 24
Finished	Sep 18 08:59:58 AM UTC 24
Peak memory	366484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856539621 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.1856539621
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.256014461
Short name	T484
Test name
Test status
Simulation time	20852250237 ps
CPU time	304.41 seconds
Started	Sep 18 08:58:39 AM UTC 24
Finished	Sep 18 09:03:48 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256014461 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acce ss_b2b.256014461
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.37395900
Short name	T438
Test name
Test status
Simulation time	29133162 ps
CPU time	1.1 seconds
Started	Sep 18 08:59:32 AM UTC 24
Finished	Sep 18 08:59:34 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37395900 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.37395900
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.1524871138
Short name	T601
Test name
Test status
Simulation time	6371131311 ps
CPU time	868.58 seconds
Started	Sep 18 08:59:14 AM UTC 24
Finished	Sep 18 09:13:52 AM UTC 24
Peak memory	374692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524871138 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1524871138
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3892280000
Short name	T427
Test name
Test status
Simulation time	374099332 ps
CPU time	7.76 seconds
Started	Sep 18 08:58:16 AM UTC 24
Finished	Sep 18 08:58:25 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892280000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3892280000
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.4088255434
Short name	T752
Test name
Test status
Simulation time	6152425635 ps
CPU time	1638.13 seconds
Started	Sep 18 08:59:42 AM UTC 24
Finished	Sep 18 09:27:16 AM UTC 24
Peak memory	384988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408825543 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.4088255434
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.446664926
Short name	T477
Test name
Test status
Simulation time	3297336259 ps
CPU time	225.25 seconds
Started	Sep 18 08:59:39 AM UTC 24
Finished	Sep 18 09:03:27 AM UTC 24
Peak memory	384972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446664926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.446664926
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.613556456
Short name	T485
Test name
Test status
Simulation time	3120954050 ps
CPU time	318.47 seconds
Started	Sep 18 08:58:26 AM UTC 24
Finished	Sep 18 09:03:49 AM UTC 24
Peak memory	211980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613556456 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.613556456
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.247295263
Short name	T433
Test name
Test status
Simulation time	104729084 ps
CPU time	4.52 seconds
Started	Sep 18 08:59:03 AM UTC 24
Finished	Sep 18 08:59:08 AM UTC 24
Peak memory	235424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 247295263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_th roughput_w_partial_write.247295263
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.4180373381
Short name	T626
Test name
Test status
Simulation time	3225537720 ps
CPU time	916.04 seconds
Started	Sep 18 09:00:21 AM UTC 24
Finished	Sep 18 09:15:47 AM UTC 24
Peak memory	380880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180373381 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during _key_req.4180373381
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2688369255
Short name	T459
Test name
Test status
Simulation time	16053390 ps
CPU time	0.94 seconds
Started	Sep 18 09:00:54 AM UTC 24
Finished	Sep 18 09:00:56 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688369255 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2688369255
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2602863395
Short name	T453
Test name
Test status
Simulation time	588983010 ps
CPU time	41.74 seconds
Started	Sep 18 08:59:49 AM UTC 24
Finished	Sep 18 09:00:32 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602863395 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.2602863395
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.35510248
Short name	T526
Test name
Test status
Simulation time	1332737789 ps
CPU time	356.18 seconds
Started	Sep 18 09:00:24 AM UTC 24
Finished	Sep 18 09:06:24 AM UTC 24
Peak memory	358456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35510248 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.35510248
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.714452095
Short name	T452
Test name
Test status
Simulation time	2559422432 ps
CPU time	10.21 seconds
Started	Sep 18 09:00:18 AM UTC 24
Finished	Sep 18 09:00:29 AM UTC 24
Peak memory	222304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714452095 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.714452095
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2005688807
Short name	T448
Test name
Test status
Simulation time	423481416 ps
CPU time	7.52 seconds
Started	Sep 18 09:00:03 AM UTC 24
Finished	Sep 18 09:00:14 AM UTC 24
Peak memory	245604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 005688807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma x_throughput.2005688807
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4148259700
Short name	T457
Test name
Test status
Simulation time	345097906 ps
CPU time	4.59 seconds
Started	Sep 18 09:00:37 AM UTC 24
Finished	Sep 18 09:00:42 AM UTC 24
Peak memory	222228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148259700 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.4148259700
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1989169212
Short name	T458
Test name
Test status
Simulation time	653980162 ps
CPU time	15.56 seconds
Started	Sep 18 09:00:37 AM UTC 24
Finished	Sep 18 09:00:53 AM UTC 24
Peak memory	211948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989169212 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1989169212
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3830278819
Short name	T524
Test name
Test status
Simulation time	6092225351 ps
CPU time	387.66 seconds
Started	Sep 18 08:59:46 AM UTC 24
Finished	Sep 18 09:06:19 AM UTC 24
Peak memory	376728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830278819 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.3830278819
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3734406940
Short name	T451
Test name
Test status
Simulation time	529742894 ps
CPU time	24.67 seconds
Started	Sep 18 08:59:57 AM UTC 24
Finished	Sep 18 09:00:23 AM UTC 24
Peak memory	296776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734406940 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3734406940
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3853802926
Short name	T505
Test name
Test status
Simulation time	3694601478 ps
CPU time	291.45 seconds
Started	Sep 18 08:59:59 AM UTC 24
Finished	Sep 18 09:04:54 AM UTC 24
Peak memory	212076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853802926 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc ess_b2b.3853802926
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.261383984
Short name	T455
Test name
Test status
Simulation time	48315787 ps
CPU time	1.14 seconds
Started	Sep 18 09:00:33 AM UTC 24
Finished	Sep 18 09:00:36 AM UTC 24
Peak memory	210636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261383984 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.261383984
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1011901378
Short name	T586
Test name
Test status
Simulation time	1927861290 ps
CPU time	733.78 seconds
Started	Sep 18 09:00:30 AM UTC 24
Finished	Sep 18 09:12:52 AM UTC 24
Peak memory	376880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011901378 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1011901378
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2194006385
Short name	T447
Test name
Test status
Simulation time	261243954 ps
CPU time	15.46 seconds
Started	Sep 18 08:59:45 AM UTC 24
Finished	Sep 18 09:00:02 AM UTC 24
Peak memory	262168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194006385 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2194006385
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.318178949
Short name	T879
Test name
Test status
Simulation time	15545372729 ps
CPU time	2223.48 seconds
Started	Sep 18 09:00:43 AM UTC 24
Finished	Sep 18 09:38:11 AM UTC 24
Peak memory	386620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318178949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.318178949
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.85419734
Short name	T109
Test name
Test status
Simulation time	4644613321 ps
CPU time	39.65 seconds
Started	Sep 18 09:00:40 AM UTC 24
Finished	Sep 18 09:01:21 AM UTC 24
Peak memory	290844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85419734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.85419734
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3393052889
Short name	T492
Test name
Test status
Simulation time	8848845924 ps
CPU time	252.84 seconds
Started	Sep 18 08:59:50 AM UTC 24
Finished	Sep 18 09:04:07 AM UTC 24
Peak memory	211936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393052889 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.3393052889
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2348858214
Short name	T456
Test name
Test status
Simulation time	335137160 ps
CPU time	22.43 seconds
Started	Sep 18 09:00:15 AM UTC 24
Finished	Sep 18 09:00:38 AM UTC 24
Peak memory	280476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2348858214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t hroughput_w_partial_write.2348858214
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.981683494
Short name	T587
Test name
Test status
Simulation time	12919890079 ps
CPU time	659.98 seconds
Started	Sep 18 09:01:51 AM UTC 24
Finished	Sep 18 09:12:59 AM UTC 24
Peak memory	385180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981683494 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_ key_req.981683494
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2446861235
Short name	T475
Test name
Test status
Simulation time	15914663 ps
CPU time	1.09 seconds
Started	Sep 18 09:03:06 AM UTC 24
Finished	Sep 18 09:03:08 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446861235 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2446861235
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1764799044
Short name	T469
Test name
Test status
Simulation time	3989322270 ps
CPU time	77.41 seconds
Started	Sep 18 09:01:04 AM UTC 24
Finished	Sep 18 09:02:24 AM UTC 24
Peak memory	211936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764799044 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.1764799044
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3743606946
Short name	T597
Test name
Test status
Simulation time	12124561152 ps
CPU time	677.15 seconds
Started	Sep 18 09:02:11 AM UTC 24
Finished	Sep 18 09:13:37 AM UTC 24
Peak memory	378784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743606946 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.3743606946
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2469951112
Short name	T466
Test name
Test status
Simulation time	635835336 ps
CPU time	3.96 seconds
Started	Sep 18 09:01:45 AM UTC 24
Finished	Sep 18 09:01:50 AM UTC 24
Peak memory	211940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469951112 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.2469951112
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.666552751
Short name	T480
Test name
Test status
Simulation time	1596848062 ps
CPU time	108.79 seconds
Started	Sep 18 09:01:41 AM UTC 24
Finished	Sep 18 09:03:32 AM UTC 24
Peak memory	378784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 66552751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_max _throughput.666552751
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.619754927
Short name	T473
Test name
Test status
Simulation time	67767757 ps
CPU time	4 seconds
Started	Sep 18 09:02:28 AM UTC 24
Finished	Sep 18 09:02:33 AM UTC 24
Peak memory	222252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619754927 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.619754927
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.581627974
Short name	T472
Test name
Test status
Simulation time	76951339 ps
CPU time	4.91 seconds
Started	Sep 18 09:02:27 AM UTC 24
Finished	Sep 18 09:02:33 AM UTC 24
Peak memory	222184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581627974 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.581627974
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3478653525
Short name	T636
Test name
Test status
Simulation time	13722164693 ps
CPU time	942.52 seconds
Started	Sep 18 09:01:01 AM UTC 24
Finished	Sep 18 09:16:53 AM UTC 24
Peak memory	385120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478653525 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3478653525
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.4292786387
Short name	T470
Test name
Test status
Simulation time	1989802858 ps
CPU time	68.18 seconds
Started	Sep 18 09:01:17 AM UTC 24
Finished	Sep 18 09:02:26 AM UTC 24
Peak memory	352164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292786387 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.4292786387
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1197014814
Short name	T497
Test name
Test status
Simulation time	2454208007 ps
CPU time	185.49 seconds
Started	Sep 18 09:01:22 AM UTC 24
Finished	Sep 18 09:04:30 AM UTC 24
Peak memory	212080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197014814 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc ess_b2b.1197014814
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3910216436
Short name	T471
Test name
Test status
Simulation time	136023740 ps
CPU time	1.22 seconds
Started	Sep 18 09:02:25 AM UTC 24
Finished	Sep 18 09:02:27 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910216436 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3910216436
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.2663568115
Short name	T474
Test name
Test status
Simulation time	2032378104 ps
CPU time	41.12 seconds
Started	Sep 18 09:02:22 AM UTC 24
Finished	Sep 18 09:03:05 AM UTC 24
Peak memory	211944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663568115 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2663568115
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.1981820708
Short name	T463
Test name
Test status
Simulation time	7662881028 ps
CPU time	41.73 seconds
Started	Sep 18 09:00:57 AM UTC 24
Finished	Sep 18 09:01:40 AM UTC 24
Peak memory	303216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981820708 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1981820708
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.125883479
Short name	T776
Test name
Test status
Simulation time	40060166451 ps
CPU time	1613.07 seconds
Started	Sep 18 09:02:34 AM UTC 24
Finished	Sep 18 09:29:44 AM UTC 24
Peak memory	384996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125883479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.125883479
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4169374958
Short name	T498
Test name
Test status
Simulation time	2917876906 ps
CPU time	114.96 seconds
Started	Sep 18 09:02:34 AM UTC 24
Finished	Sep 18 09:04:32 AM UTC 24
Peak memory	278752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169374958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.4169374958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2287661785
Short name	T521
Test name
Test status
Simulation time	2949002694 ps
CPU time	296.03 seconds
Started	Sep 18 09:01:15 AM UTC 24
Finished	Sep 18 09:06:15 AM UTC 24
Peak memory	212184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287661785 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.2287661785
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.4184327570
Short name	T476
Test name
Test status
Simulation time	672696979 ps
CPU time	85.69 seconds
Started	Sep 18 09:01:44 AM UTC 24
Finished	Sep 18 09:03:11 AM UTC 24
Peak memory	370520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4184327570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t hroughput_w_partial_write.4184327570
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1247311475
Short name	T666
Test name
Test status
Simulation time	3784988528 ps
CPU time	911.81 seconds
Started	Sep 18 09:03:49 AM UTC 24
Finished	Sep 18 09:19:11 AM UTC 24
Peak memory	383084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247311475 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during _key_req.1247311475
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3747187623
Short name	T493
Test name
Test status
Simulation time	21074032 ps
CPU time	1.01 seconds
Started	Sep 18 09:04:08 AM UTC 24
Finished	Sep 18 09:04:10 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747187623 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3747187623
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.820083784
Short name	T496
Test name
Test status
Simulation time	19711367615 ps
CPU time	58.71 seconds
Started	Sep 18 09:03:28 AM UTC 24
Finished	Sep 18 09:04:28 AM UTC 24
Peak memory	212000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820083784 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.820083784
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.1003599909
Short name	T559
Test name
Test status
Simulation time	5317619084 ps
CPU time	319.71 seconds
Started	Sep 18 09:03:49 AM UTC 24
Finished	Sep 18 09:09:13 AM UTC 24
Peak memory	382872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003599909 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.1003599909
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3392385572
Short name	T486
Test name
Test status
Simulation time	2258673524 ps
CPU time	7.22 seconds
Started	Sep 18 09:03:44 AM UTC 24
Finished	Sep 18 09:03:52 AM UTC 24
Peak memory	226324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392385572 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.3392385572
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2695482394
Short name	T508
Test name
Test status
Simulation time	136548022 ps
CPU time	88 seconds
Started	Sep 18 09:03:38 AM UTC 24
Finished	Sep 18 09:05:08 AM UTC 24
Peak memory	374700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 695482394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ma x_throughput.2695482394
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1274558230
Short name	T491
Test name
Test status
Simulation time	353835930 ps
CPU time	4.12 seconds
Started	Sep 18 09:04:02 AM UTC 24
Finished	Sep 18 09:04:07 AM UTC 24
Peak memory	222236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274558230 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1274558230
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3933651188
Short name	T494
Test name
Test status
Simulation time	462434748 ps
CPU time	9.44 seconds
Started	Sep 18 09:04:01 AM UTC 24
Finished	Sep 18 09:04:11 AM UTC 24
Peak memory	222312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933651188 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.3933651188
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3922562722
Short name	T517
Test name
Test status
Simulation time	3759719946 ps
CPU time	165.32 seconds
Started	Sep 18 09:03:12 AM UTC 24
Finished	Sep 18 09:06:01 AM UTC 24
Peak memory	362576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922562722 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.3922562722
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2611060751
Short name	T482
Test name
Test status
Simulation time	113541148 ps
CPU time	7.96 seconds
Started	Sep 18 09:03:33 AM UTC 24
Finished	Sep 18 09:03:42 AM UTC 24
Peak memory	211912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611060751 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.2611060751
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2438446156
Short name	T550
Test name
Test status
Simulation time	9205547346 ps
CPU time	280.1 seconds
Started	Sep 18 09:03:33 AM UTC 24
Finished	Sep 18 09:08:17 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438446156 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acc ess_b2b.2438446156
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2638306051
Short name	T489
Test name
Test status
Simulation time	139273314 ps
CPU time	1.35 seconds
Started	Sep 18 09:03:59 AM UTC 24
Finished	Sep 18 09:04:01 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638306051 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2638306051
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1987025019
Short name	T478
Test name
Test status
Simulation time	1260120110 ps
CPU time	17.87 seconds
Started	Sep 18 09:03:09 AM UTC 24
Finished	Sep 18 09:03:28 AM UTC 24
Peak memory	286508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987025019 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1987025019
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3328733125
Short name	T931
Test name
Test status
Simulation time	261285799088 ps
CPU time	3941.67 seconds
Started	Sep 18 09:04:08 AM UTC 24
Finished	Sep 18 10:10:32 AM UTC 24
Peak memory	396860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332873312 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.3328733125
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3359534703
Short name	T110
Test name
Test status
Simulation time	1657721507 ps
CPU time	17.83 seconds
Started	Sep 18 09:04:02 AM UTC 24
Finished	Sep 18 09:04:21 AM UTC 24
Peak memory	228320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359534703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3359534703
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3080951589
Short name	T548
Test name
Test status
Simulation time	9574926064 ps
CPU time	277.55 seconds
Started	Sep 18 09:03:30 AM UTC 24
Finished	Sep 18 09:08:11 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080951589 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.3080951589
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3010857314
Short name	T509
Test name
Test status
Simulation time	1684711270 ps
CPU time	84.58 seconds
Started	Sep 18 09:03:43 AM UTC 24
Finished	Sep 18 09:05:10 AM UTC 24
Peak memory	366504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3010857314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t hroughput_w_partial_write.3010857314
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.279910836
Short name	T678
Test name
Test status
Simulation time	13732585087 ps
CPU time	952.01 seconds
Started	Sep 18 09:04:37 AM UTC 24
Finished	Sep 18 09:20:40 AM UTC 24
Peak memory	382928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279910836 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during_ key_req.279910836
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.917928761
Short name	T512
Test name
Test status
Simulation time	141773266 ps
CPU time	0.98 seconds
Started	Sep 18 09:05:12 AM UTC 24
Finished	Sep 18 09:05:14 AM UTC 24
Peak memory	211044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917928761 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.917928761
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.3849409515
Short name	T504
Test name
Test status
Simulation time	892816709 ps
CPU time	30.3 seconds
Started	Sep 18 09:04:15 AM UTC 24
Finished	Sep 18 09:04:46 AM UTC 24
Peak memory	211928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849409515 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.3849409515
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.3141052713
Short name	T719
Test name
Test status
Simulation time	84739922019 ps
CPU time	1199.57 seconds
Started	Sep 18 09:04:39 AM UTC 24
Finished	Sep 18 09:24:52 AM UTC 24
Peak memory	378864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141052713 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.3141052713
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1576719152
Short name	T502
Test name
Test status
Simulation time	4379478206 ps
CPU time	4.23 seconds
Started	Sep 18 09:04:33 AM UTC 24
Finished	Sep 18 09:04:39 AM UTC 24
Peak memory	226468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576719152 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.1576719152
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.937383546
Short name	T518
Test name
Test status
Simulation time	133852085 ps
CPU time	87.4 seconds
Started	Sep 18 09:04:32 AM UTC 24
Finished	Sep 18 09:06:01 AM UTC 24
Peak memory	374832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 37383546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max _throughput.937383546
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.92503331
Short name	T511
Test name
Test status
Simulation time	104149507 ps
CPU time	5.23 seconds
Started	Sep 18 09:05:06 AM UTC 24
Finished	Sep 18 09:05:12 AM UTC 24
Peak memory	222260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92503331 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.92503331
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3658746569
Short name	T510
Test name
Test status
Simulation time	263344967 ps
CPU time	10.82 seconds
Started	Sep 18 09:04:59 AM UTC 24
Finished	Sep 18 09:05:11 AM UTC 24
Peak memory	222120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658746569 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.3658746569
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.213120406
Short name	T665
Test name
Test status
Simulation time	4238633347 ps
CPU time	886.69 seconds
Started	Sep 18 09:04:12 AM UTC 24
Finished	Sep 18 09:19:09 AM UTC 24
Peak memory	378784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213120406 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.213120406
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.608368739
Short name	T501
Test name
Test status
Simulation time	243576006 ps
CPU time	5.91 seconds
Started	Sep 18 09:04:29 AM UTC 24
Finished	Sep 18 09:04:36 AM UTC 24
Peak memory	211932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608368739 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.608368739
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.91632215
Short name	T555
Test name
Test status
Simulation time	9331202984 ps
CPU time	254.95 seconds
Started	Sep 18 09:04:31 AM UTC 24
Finished	Sep 18 09:08:50 AM UTC 24
Peak memory	211984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91632215 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acces s_b2b.91632215
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1460676955
Short name	T506
Test name
Test status
Simulation time	26431763 ps
CPU time	1.24 seconds
Started	Sep 18 09:04:55 AM UTC 24
Finished	Sep 18 09:04:58 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460676955 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1460676955
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.776338930
Short name	T533
Test name
Test status
Simulation time	8611505753 ps
CPU time	123.15 seconds
Started	Sep 18 09:04:47 AM UTC 24
Finished	Sep 18 09:06:52 AM UTC 24
Peak memory	382860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776338930 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.776338930
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2407378506
Short name	T495
Test name
Test status
Simulation time	89710145 ps
CPU time	1.22 seconds
Started	Sep 18 09:04:11 AM UTC 24
Finished	Sep 18 09:04:13 AM UTC 24
Peak memory	210696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407378506 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2407378506
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2060564174
Short name	T726
Test name
Test status
Simulation time	6109029464 ps
CPU time	1206.65 seconds
Started	Sep 18 09:05:10 AM UTC 24
Finished	Sep 18 09:25:30 AM UTC 24
Peak memory	382868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206056417 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.2060564174
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.40018634
Short name	T516
Test name
Test status
Simulation time	365409847 ps
CPU time	37.02 seconds
Started	Sep 18 09:05:09 AM UTC 24
Finished	Sep 18 09:05:47 AM UTC 24
Peak memory	222312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40018634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.40018634
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3236284273
Short name	T577
Test name
Test status
Simulation time	15739222450 ps
CPU time	421.13 seconds
Started	Sep 18 09:04:22 AM UTC 24
Finished	Sep 18 09:11:28 AM UTC 24
Peak memory	212184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236284273 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.3236284273
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3987585105
Short name	T513
Test name
Test status
Simulation time	542594155 ps
CPU time	47.37 seconds
Started	Sep 18 09:04:33 AM UTC 24
Finished	Sep 18 09:05:22 AM UTC 24
Peak memory	352228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3987585105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t hroughput_w_partial_write.3987585105
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3442035205
Short name	T657
Test name
Test status
Simulation time	4411346845 ps
CPU time	734.19 seconds
Started	Sep 18 09:06:02 AM UTC 24
Finished	Sep 18 09:18:25 AM UTC 24
Peak memory	384912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442035205 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.3442035205
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1953369735
Short name	T528
Test name
Test status
Simulation time	43708281 ps
CPU time	0.93 seconds
Started	Sep 18 09:06:25 AM UTC 24
Finished	Sep 18 09:06:27 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953369735 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1953369735
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.4039010816
Short name	T536
Test name
Test status
Simulation time	3869546876 ps
CPU time	100.87 seconds
Started	Sep 18 09:05:23 AM UTC 24
Finished	Sep 18 09:07:05 AM UTC 24
Peak memory	212072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039010816 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.4039010816
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.1498598902
Short name	T716
Test name
Test status
Simulation time	59773468132 ps
CPU time	1079.34 seconds
Started	Sep 18 09:06:08 AM UTC 24
Finished	Sep 18 09:24:20 AM UTC 24
Peak memory	384924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498598902 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.1498598902
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2891227674
Short name	T519
Test name
Test status
Simulation time	228702743 ps
CPU time	5.61 seconds
Started	Sep 18 09:06:01 AM UTC 24
Finished	Sep 18 09:06:08 AM UTC 24
Peak memory	226460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891227674 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.2891227674
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3927406608
Short name	T525
Test name
Test status
Simulation time	809712158 ps
CPU time	30.09 seconds
Started	Sep 18 09:05:48 AM UTC 24
Finished	Sep 18 09:06:19 AM UTC 24
Peak memory	296796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 927406608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma x_throughput.3927406608
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2192049001
Short name	T530
Test name
Test status
Simulation time	386249180 ps
CPU time	7.86 seconds
Started	Sep 18 09:06:20 AM UTC 24
Finished	Sep 18 09:06:29 AM UTC 24
Peak memory	222176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192049001 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.2192049001
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3857645180
Short name	T529
Test name
Test status
Simulation time	1384835926 ps
CPU time	8.38 seconds
Started	Sep 18 09:06:18 AM UTC 24
Finished	Sep 18 09:06:27 AM UTC 24
Peak memory	222192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857645180 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.3857645180
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2222827096
Short name	T746
Test name
Test status
Simulation time	3628203194 ps
CPU time	1286.7 seconds
Started	Sep 18 09:05:15 AM UTC 24
Finished	Sep 18 09:26:55 AM UTC 24
Peak memory	383060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222827096 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.2222827096
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.231571918
Short name	T515
Test name
Test status
Simulation time	1442318960 ps
CPU time	12.28 seconds
Started	Sep 18 09:05:34 AM UTC 24
Finished	Sep 18 09:05:47 AM UTC 24
Peak memory	243540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231571918 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.231571918
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.4262252995
Short name	T566
Test name
Test status
Simulation time	11866979573 ps
CPU time	248.74 seconds
Started	Sep 18 09:05:38 AM UTC 24
Finished	Sep 18 09:09:50 AM UTC 24
Peak memory	212008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262252995 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc ess_b2b.4262252995
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.2964639914
Short name	T523
Test name
Test status
Simulation time	208181133 ps
CPU time	1.02 seconds
Started	Sep 18 09:06:17 AM UTC 24
Finished	Sep 18 09:06:18 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964639914 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2964639914
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.813974754
Short name	T527
Test name
Test status
Simulation time	2588990356 ps
CPU time	8.66 seconds
Started	Sep 18 09:06:17 AM UTC 24
Finished	Sep 18 09:06:26 AM UTC 24
Peak memory	212064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813974754 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.813974754
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.715994074
Short name	T503
Test name
Test status
Simulation time	179543203 ps
CPU time	16.21 seconds
Started	Sep 18 09:05:13 AM UTC 24
Finished	Sep 18 09:05:31 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715994074 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.715994074
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3913947099
Short name	T908
Test name
Test status
Simulation time	41099536630 ps
CPU time	2456.9 seconds
Started	Sep 18 09:06:20 AM UTC 24
Finished	Sep 18 09:47:43 AM UTC 24
Peak memory	380476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391394709 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.3913947099
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3899372349
Short name	T574
Test name
Test status
Simulation time	900951474 ps
CPU time	298.36 seconds
Started	Sep 18 09:06:20 AM UTC 24
Finished	Sep 18 09:11:22 AM UTC 24
Peak memory	370652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899372349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3899372349
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1217023533
Short name	T557
Test name
Test status
Simulation time	1820103742 ps
CPU time	210.01 seconds
Started	Sep 18 09:05:32 AM UTC 24
Finished	Sep 18 09:09:05 AM UTC 24
Peak memory	212140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217023533 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.1217023533
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2573854685
Short name	T520
Test name
Test status
Simulation time	384463927 ps
CPU time	26.25 seconds
Started	Sep 18 09:05:48 AM UTC 24
Finished	Sep 18 09:06:15 AM UTC 24
Peak memory	300960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2573854685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t hroughput_w_partial_write.2573854685
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1244192470
Short name	T264
Test name
Test status
Simulation time	15809265236 ps
CPU time	1015.67 seconds
Started	Sep 18 08:25:09 AM UTC 24
Finished	Sep 18 08:42:16 AM UTC 24
Peak memory	384972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244192470 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_ key_req.1244192470
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.547928645
Short name	T160
Test name
Test status
Simulation time	16761956 ps
CPU time	0.99 seconds
Started	Sep 18 08:25:43 AM UTC 24
Finished	Sep 18 08:25:45 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547928645 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.547928645
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.2762518349
Short name	T71
Test name
Test status
Simulation time	22754285636 ps
CPU time	90.81 seconds
Started	Sep 18 08:24:48 AM UTC 24
Finished	Sep 18 08:26:21 AM UTC 24
Peak memory	212120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762518349 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.2762518349
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.2309038321
Short name	T27
Test name
Test status
Simulation time	7949332594 ps
CPU time	104.98 seconds
Started	Sep 18 08:25:09 AM UTC 24
Finished	Sep 18 08:26:57 AM UTC 24
Peak memory	298896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309038321 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.2309038321
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3056678349
Short name	T57
Test name
Test status
Simulation time	1344937747 ps
CPU time	2.86 seconds
Started	Sep 18 08:25:06 AM UTC 24
Finished	Sep 18 08:25:10 AM UTC 24
Peak memory	222184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056678349 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.3056678349
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.209539547
Short name	T69
Test name
Test status
Simulation time	132834190 ps
CPU time	72.7 seconds
Started	Sep 18 08:25:02 AM UTC 24
Finished	Sep 18 08:26:17 AM UTC 24
Peak memory	372648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 09539547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_ throughput.209539547
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2655216868
Short name	T35
Test name
Test status
Simulation time	189572750 ps
CPU time	5.06 seconds
Started	Sep 18 08:25:32 AM UTC 24
Finished	Sep 18 08:25:38 AM UTC 24
Peak memory	222380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655216868 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.2655216868
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1690164446
Short name	T156
Test name
Test status
Simulation time	147924375 ps
CPU time	4.58 seconds
Started	Sep 18 08:25:30 AM UTC 24
Finished	Sep 18 08:25:36 AM UTC 24
Peak memory	222192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690164446 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.1690164446
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2032759041
Short name	T259
Test name
Test status
Simulation time	12853925560 ps
CPU time	988.5 seconds
Started	Sep 18 08:24:46 AM UTC 24
Finished	Sep 18 08:41:25 AM UTC 24
Peak memory	385112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032759041 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.2032759041
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1332128378
Short name	T44
Test name
Test status
Simulation time	2102962725 ps
CPU time	45.65 seconds
Started	Sep 18 08:24:55 AM UTC 24
Finished	Sep 18 08:25:42 AM UTC 24
Peak memory	323620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332128378 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.1332128378
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2893423036
Short name	T209
Test name
Test status
Simulation time	179920223317 ps
CPU time	556.04 seconds
Started	Sep 18 08:24:59 AM UTC 24
Finished	Sep 18 08:34:22 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893423036 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce ss_b2b.2893423036
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3759390297
Short name	T158
Test name
Test status
Simulation time	57179996 ps
CPU time	1.29 seconds
Started	Sep 18 08:25:27 AM UTC 24
Finished	Sep 18 08:25:29 AM UTC 24
Peak memory	210632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759390297 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3759390297
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1763169131
Short name	T31
Test name
Test status
Simulation time	435558674 ps
CPU time	2.67 seconds
Started	Sep 18 08:25:39 AM UTC 24
Finished	Sep 18 08:25:43 AM UTC 24
Peak memory	247732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763169131 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.1763169131
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.1283853987
Short name	T59
Test name
Test status
Simulation time	181184981 ps
CPU time	6.57 seconds
Started	Sep 18 08:24:45 AM UTC 24
Finished	Sep 18 08:24:52 AM UTC 24
Peak memory	239704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283853987 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1283853987
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2105140438
Short name	T565
Test name
Test status
Simulation time	70083257473 ps
CPU time	2626.7 seconds
Started	Sep 18 08:25:37 AM UTC 24
Finished	Sep 18 09:09:50 AM UTC 24
Peak memory	384920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210514043 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.2105140438
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.4059923966
Short name	T58
Test name
Test status
Simulation time	53284681 ps
CPU time	4.8 seconds
Started	Sep 18 08:25:03 AM UTC 24
Finished	Sep 18 08:25:09 AM UTC 24
Peak memory	229288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4059923966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th roughput_w_partial_write.4059923966
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2085864137
Short name	T744
Test name
Test status
Simulation time	23681827444 ps
CPU time	1168.61 seconds
Started	Sep 18 09:07:06 AM UTC 24
Finished	Sep 18 09:26:48 AM UTC 24
Peak memory	385052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085864137 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during _key_req.2085864137
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.195165548
Short name	T545
Test name
Test status
Simulation time	47911372 ps
CPU time	1.05 seconds
Started	Sep 18 09:07:45 AM UTC 24
Finished	Sep 18 09:07:47 AM UTC 24
Peak memory	211064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195165548 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.195165548
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2757844611
Short name	T541
Test name
Test status
Simulation time	3331832753 ps
CPU time	65.12 seconds
Started	Sep 18 09:06:28 AM UTC 24
Finished	Sep 18 09:07:36 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757844611 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2757844611
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2807574119
Short name	T633
Test name
Test status
Simulation time	2550702197 ps
CPU time	553.05 seconds
Started	Sep 18 09:07:15 AM UTC 24
Finished	Sep 18 09:16:35 AM UTC 24
Peak memory	383144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807574119 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.2807574119
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.919693415
Short name	T538
Test name
Test status
Simulation time	1178436372 ps
CPU time	11.44 seconds
Started	Sep 18 09:07:03 AM UTC 24
Finished	Sep 18 09:07:16 AM UTC 24
Peak memory	212076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919693415 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.919693415
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2229802349
Short name	T549
Test name
Test status
Simulation time	498646179 ps
CPU time	79.68 seconds
Started	Sep 18 09:06:53 AM UTC 24
Finished	Sep 18 09:08:14 AM UTC 24
Peak memory	372584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 229802349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma x_throughput.2229802349
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3369160521
Short name	T544
Test name
Test status
Simulation time	665901163 ps
CPU time	7.61 seconds
Started	Sep 18 09:07:36 AM UTC 24
Finished	Sep 18 09:07:45 AM UTC 24
Peak memory	222164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369160521 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.3369160521
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1019370545
Short name	T542
Test name
Test status
Simulation time	450525280 ps
CPU time	7.43 seconds
Started	Sep 18 09:07:34 AM UTC 24
Finished	Sep 18 09:07:42 AM UTC 24
Peak memory	211924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019370545 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.1019370545
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2971531290
Short name	T602
Test name
Test status
Simulation time	12496326049 ps
CPU time	454.04 seconds
Started	Sep 18 09:06:28 AM UTC 24
Finished	Sep 18 09:14:08 AM UTC 24
Peak memory	380808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971531290 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2971531290
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2415459223
Short name	T534
Test name
Test status
Simulation time	223059028 ps
CPU time	3.02 seconds
Started	Sep 18 09:06:51 AM UTC 24
Finished	Sep 18 09:06:55 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415459223 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.2415459223
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.802906199
Short name	T567
Test name
Test status
Simulation time	8879246609 ps
CPU time	178.86 seconds
Started	Sep 18 09:06:53 AM UTC 24
Finished	Sep 18 09:09:55 AM UTC 24
Peak memory	212016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802906199 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acce ss_b2b.802906199
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.129926355
Short name	T540
Test name
Test status
Simulation time	37072511 ps
CPU time	1.03 seconds
Started	Sep 18 09:07:31 AM UTC 24
Finished	Sep 18 09:07:33 AM UTC 24
Peak memory	210636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129926355 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.129926355
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.2722890137
Short name	T700
Test name
Test status
Simulation time	29748825721 ps
CPU time	946.52 seconds
Started	Sep 18 09:07:17 AM UTC 24
Finished	Sep 18 09:23:13 AM UTC 24
Peak memory	382868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722890137 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2722890137
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.4125483953
Short name	T532
Test name
Test status
Simulation time	1095391079 ps
CPU time	23.21 seconds
Started	Sep 18 09:06:27 AM UTC 24
Finished	Sep 18 09:06:52 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125483953 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.4125483953
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1037798825
Short name	T935
Test name
Test status
Simulation time	297804843624 ps
CPU time	5431.77 seconds
Started	Sep 18 09:07:44 AM UTC 24
Finished	Sep 18 10:39:13 AM UTC 24
Peak memory	386624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103779882 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.1037798825
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2110773934
Short name	T622
Test name
Test status
Simulation time	4220056173 ps
CPU time	538.16 seconds
Started	Sep 18 09:06:30 AM UTC 24
Finished	Sep 18 09:15:35 AM UTC 24
Peak memory	212244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110773934 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.2110773934
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2369721308
Short name	T539
Test name
Test status
Simulation time	1786726981 ps
CPU time	32.35 seconds
Started	Sep 18 09:06:56 AM UTC 24
Finished	Sep 18 09:07:30 AM UTC 24
Peak memory	296992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2369721308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_t hroughput_w_partial_write.2369721308
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1097570514
Short name	T696
Test name
Test status
Simulation time	10899751659 ps
CPU time	833.57 seconds
Started	Sep 18 09:08:47 AM UTC 24
Finished	Sep 18 09:22:50 AM UTC 24
Peak memory	382856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097570514 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during _key_req.1097570514
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3444758253
Short name	T563
Test name
Test status
Simulation time	51403152 ps
CPU time	0.98 seconds
Started	Sep 18 09:09:31 AM UTC 24
Finished	Sep 18 09:09:34 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444758253 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3444758253
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.4110495883
Short name	T553
Test name
Test status
Simulation time	913737842 ps
CPU time	25.53 seconds
Started	Sep 18 09:08:11 AM UTC 24
Finished	Sep 18 09:08:37 AM UTC 24
Peak memory	211944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110495883 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.4110495883
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.983037263
Short name	T635
Test name
Test status
Simulation time	9155717313 ps
CPU time	464.2 seconds
Started	Sep 18 09:08:51 AM UTC 24
Finished	Sep 18 09:16:41 AM UTC 24
Peak memory	327592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983037263 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.983037263
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3551360814
Short name	T556
Test name
Test status
Simulation time	3680669934 ps
CPU time	15.94 seconds
Started	Sep 18 09:08:38 AM UTC 24
Finished	Sep 18 09:08:55 AM UTC 24
Peak memory	222240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551360814 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.3551360814
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1053145763
Short name	T552
Test name
Test status
Simulation time	263566268 ps
CPU time	14.27 seconds
Started	Sep 18 09:08:22 AM UTC 24
Finished	Sep 18 09:08:37 AM UTC 24
Peak memory	268116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 053145763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma x_throughput.1053145763
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1956914162
Short name	T561
Test name
Test status
Simulation time	508881823 ps
CPU time	5.63 seconds
Started	Sep 18 09:09:14 AM UTC 24
Finished	Sep 18 09:09:21 AM UTC 24
Peak memory	222248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956914162 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1956914162
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.439722636
Short name	T560
Test name
Test status
Simulation time	459196363 ps
CPU time	8.09 seconds
Started	Sep 18 09:09:09 AM UTC 24
Finished	Sep 18 09:09:18 AM UTC 24
Peak memory	222168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439722636 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.439722636
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1161871613
Short name	T639
Test name
Test status
Simulation time	28179446056 ps
CPU time	536.98 seconds
Started	Sep 18 09:07:53 AM UTC 24
Finished	Sep 18 09:16:57 AM UTC 24
Peak memory	384912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161871613 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.1161871613
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3113349359
Short name	T554
Test name
Test status
Simulation time	4088110603 ps
CPU time	29.28 seconds
Started	Sep 18 09:08:16 AM UTC 24
Finished	Sep 18 09:08:46 AM UTC 24
Peak memory	212048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113349359 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.3113349359
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.449074709
Short name	T607
Test name
Test status
Simulation time	19325799704 ps
CPU time	385.81 seconds
Started	Sep 18 09:08:18 AM UTC 24
Finished	Sep 18 09:14:49 AM UTC 24
Peak memory	212060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449074709 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acce ss_b2b.449074709
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3630325281
Short name	T558
Test name
Test status
Simulation time	93788655 ps
CPU time	0.94 seconds
Started	Sep 18 09:09:06 AM UTC 24
Finished	Sep 18 09:09:08 AM UTC 24
Peak memory	211088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630325281 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3630325281
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.1146603822
Short name	T784
Test name
Test status
Simulation time	16931785569 ps
CPU time	1282.98 seconds
Started	Sep 18 09:08:57 AM UTC 24
Finished	Sep 18 09:30:33 AM UTC 24
Peak memory	378972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146603822 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1146603822
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.4202412690
Short name	T562
Test name
Test status
Simulation time	631440440 ps
CPU time	99.91 seconds
Started	Sep 18 09:07:48 AM UTC 24
Finished	Sep 18 09:09:30 AM UTC 24
Peak memory	376856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202412690 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.4202412690
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1575690593
Short name	T763
Test name
Test status
Simulation time	53054474283 ps
CPU time	1127.64 seconds
Started	Sep 18 09:09:22 AM UTC 24
Finished	Sep 18 09:28:22 AM UTC 24
Peak memory	393176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157569059 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.1575690593
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.711357788
Short name	T608
Test name
Test status
Simulation time	12323335670 ps
CPU time	392.8 seconds
Started	Sep 18 09:08:13 AM UTC 24
Finished	Sep 18 09:14:51 AM UTC 24
Peak memory	212012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711357788 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.711357788
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1708544082
Short name	T570
Test name
Test status
Simulation time	157246160 ps
CPU time	104.29 seconds
Started	Sep 18 09:08:38 AM UTC 24
Finished	Sep 18 09:10:24 AM UTC 24
Peak memory	378724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1708544082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t hroughput_w_partial_write.1708544082
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.1786034240
Short name	T647
Test name
Test status
Simulation time	35098305635 ps
CPU time	413.58 seconds
Started	Sep 18 09:10:36 AM UTC 24
Finished	Sep 18 09:17:34 AM UTC 24
Peak memory	348124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786034240 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.1786034240
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.3698592065
Short name	T581
Test name
Test status
Simulation time	45672467 ps
CPU time	0.94 seconds
Started	Sep 18 09:11:41 AM UTC 24
Finished	Sep 18 09:11:43 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698592065 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3698592065
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.642905794
Short name	T569
Test name
Test status
Simulation time	1328260545 ps
CPU time	27.09 seconds
Started	Sep 18 09:09:51 AM UTC 24
Finished	Sep 18 09:10:19 AM UTC 24
Peak memory	212020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642905794 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.642905794
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.1239275856
Short name	T612
Test name
Test status
Simulation time	6971090371 ps
CPU time	248.73 seconds
Started	Sep 18 09:10:45 AM UTC 24
Finished	Sep 18 09:14:57 AM UTC 24
Peak memory	378784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239275856 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.1239275856
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1837952982
Short name	T571
Test name
Test status
Simulation time	1364889988 ps
CPU time	8.13 seconds
Started	Sep 18 09:10:25 AM UTC 24
Finished	Sep 18 09:10:35 AM UTC 24
Peak memory	222180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837952982 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.1837952982
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3612034287
Short name	T579
Test name
Test status
Simulation time	471538794 ps
CPU time	80.26 seconds
Started	Sep 18 09:10:17 AM UTC 24
Finished	Sep 18 09:11:39 AM UTC 24
Peak memory	358320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 612034287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma x_throughput.3612034287
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2841156223
Short name	T578
Test name
Test status
Simulation time	335627926 ps
CPU time	5.78 seconds
Started	Sep 18 09:11:26 AM UTC 24
Finished	Sep 18 09:11:33 AM UTC 24
Peak memory	222148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841156223 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2841156223
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2412682351
Short name	T580
Test name
Test status
Simulation time	912693527 ps
CPU time	13.28 seconds
Started	Sep 18 09:11:25 AM UTC 24
Finished	Sep 18 09:11:40 AM UTC 24
Peak memory	222188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412682351 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.2412682351
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1702935851
Short name	T632
Test name
Test status
Simulation time	8699931162 ps
CPU time	400.42 seconds
Started	Sep 18 09:09:45 AM UTC 24
Finished	Sep 18 09:16:30 AM UTC 24
Peak memory	384976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702935851 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.1702935851
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3990911696
Short name	T568
Test name
Test status
Simulation time	710585398 ps
CPU time	11.43 seconds
Started	Sep 18 09:09:56 AM UTC 24
Finished	Sep 18 09:10:08 AM UTC 24
Peak memory	211864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990911696 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.3990911696
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2007537766
Short name	T630
Test name
Test status
Simulation time	18223400722 ps
CPU time	365.95 seconds
Started	Sep 18 09:10:09 AM UTC 24
Finished	Sep 18 09:16:20 AM UTC 24
Peak memory	211928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007537766 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acc ess_b2b.2007537766
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1097339452
Short name	T576
Test name
Test status
Simulation time	226697741 ps
CPU time	1.09 seconds
Started	Sep 18 09:11:23 AM UTC 24
Finished	Sep 18 09:11:25 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097339452 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1097339452
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2624519049
Short name	T582
Test name
Test status
Simulation time	286875701 ps
CPU time	67.11 seconds
Started	Sep 18 09:10:54 AM UTC 24
Finished	Sep 18 09:12:03 AM UTC 24
Peak memory	335900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624519049 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2624519049
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.2793052331
Short name	T564
Test name
Test status
Simulation time	143290942 ps
CPU time	6.43 seconds
Started	Sep 18 09:09:35 AM UTC 24
Finished	Sep 18 09:09:43 AM UTC 24
Peak memory	227312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793052331 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2793052331
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2901693053
Short name	T928
Test name
Test status
Simulation time	164896659274 ps
CPU time	3109.74 seconds
Started	Sep 18 09:11:33 AM UTC 24
Finished	Sep 18 10:03:58 AM UTC 24
Peak memory	394760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290169305 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.2901693053
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2588010747
Short name	T592
Test name
Test status
Simulation time	6870078748 ps
CPU time	209.77 seconds
Started	Sep 18 09:09:51 AM UTC 24
Finished	Sep 18 09:13:24 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588010747 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.2588010747
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2848265020
Short name	T573
Test name
Test status
Simulation time	191401735 ps
CPU time	31.06 seconds
Started	Sep 18 09:10:20 AM UTC 24
Finished	Sep 18 09:10:53 AM UTC 24
Peak memory	300976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2848265020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t hroughput_w_partial_write.2848265020
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.4293131790
Short name	T683
Test name
Test status
Simulation time	5447917700 ps
CPU time	492.69 seconds
Started	Sep 18 09:13:00 AM UTC 24
Finished	Sep 18 09:21:19 AM UTC 24
Peak memory	380888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293131790 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during _key_req.4293131790
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.357158550
Short name	T596
Test name
Test status
Simulation time	13418444 ps
CPU time	0.88 seconds
Started	Sep 18 09:13:34 AM UTC 24
Finished	Sep 18 09:13:36 AM UTC 24
Peak memory	211064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357158550 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.357158550
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.3682145305
Short name	T584
Test name
Test status
Simulation time	9637419935 ps
CPU time	35.8 seconds
Started	Sep 18 09:12:03 AM UTC 24
Finished	Sep 18 09:12:40 AM UTC 24
Peak memory	211940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682145305 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.3682145305
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2414426653
Short name	T722
Test name
Test status
Simulation time	11712024462 ps
CPU time	701.5 seconds
Started	Sep 18 09:13:03 AM UTC 24
Finished	Sep 18 09:24:53 AM UTC 24
Peak memory	382872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414426653 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.2414426653
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2105080416
Short name	T588
Test name
Test status
Simulation time	181713385 ps
CPU time	4.43 seconds
Started	Sep 18 09:12:57 AM UTC 24
Finished	Sep 18 09:13:02 AM UTC 24
Peak memory	211920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105080416 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.2105080416
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1547759734
Short name	T589
Test name
Test status
Simulation time	142438505 ps
CPU time	12.89 seconds
Started	Sep 18 09:12:53 AM UTC 24
Finished	Sep 18 09:13:07 AM UTC 24
Peak memory	278580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 547759734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma x_throughput.1547759734
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3516723724
Short name	T595
Test name
Test status
Simulation time	338242518 ps
CPU time	7.11 seconds
Started	Sep 18 09:13:24 AM UTC 24
Finished	Sep 18 09:13:33 AM UTC 24
Peak memory	222252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516723724 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.3516723724
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3417381145
Short name	T598
Test name
Test status
Simulation time	1527619189 ps
CPU time	16 seconds
Started	Sep 18 09:13:23 AM UTC 24
Finished	Sep 18 09:13:41 AM UTC 24
Peak memory	222108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417381145 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.3417381145
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1048084435
Short name	T797
Test name
Test status
Simulation time	47118224728 ps
CPU time	1222.12 seconds
Started	Sep 18 09:11:44 AM UTC 24
Finished	Sep 18 09:32:19 AM UTC 24
Peak memory	384996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048084435 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.1048084435
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3808747999
Short name	T585
Test name
Test status
Simulation time	43719635 ps
CPU time	3.58 seconds
Started	Sep 18 09:12:41 AM UTC 24
Finished	Sep 18 09:12:46 AM UTC 24
Peak memory	218404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808747999 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.3808747999
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1991393750
Short name	T712
Test name
Test status
Simulation time	168346042733 ps
CPU time	657.99 seconds
Started	Sep 18 09:12:46 AM UTC 24
Finished	Sep 18 09:23:53 AM UTC 24
Peak memory	212124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991393750 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc ess_b2b.1991393750
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3903654410
Short name	T591
Test name
Test status
Simulation time	28367510 ps
CPU time	1.14 seconds
Started	Sep 18 09:13:20 AM UTC 24
Finished	Sep 18 09:13:22 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903654410 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3903654410
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.722973220
Short name	T652
Test name
Test status
Simulation time	26488450324 ps
CPU time	280.72 seconds
Started	Sep 18 09:13:07 AM UTC 24
Finished	Sep 18 09:17:52 AM UTC 24
Peak memory	348252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722973220 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.722973220
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.2339384999
Short name	T600
Test name
Test status
Simulation time	2697929380 ps
CPU time	125.92 seconds
Started	Sep 18 09:11:41 AM UTC 24
Finished	Sep 18 09:13:49 AM UTC 24
Peak memory	368620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339384999 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2339384999
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2114834511
Short name	T827
Test name
Test status
Simulation time	29160522740 ps
CPU time	1259.59 seconds
Started	Sep 18 09:13:30 AM UTC 24
Finished	Sep 18 09:34:43 AM UTC 24
Peak memory	384988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211483451 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.2114834511
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1796889207
Short name	T790
Test name
Test status
Simulation time	5801408085 ps
CPU time	1061.69 seconds
Started	Sep 18 09:13:28 AM UTC 24
Finished	Sep 18 09:31:20 AM UTC 24
Peak memory	389340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796889207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1796889207
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2405709706
Short name	T646
Test name
Test status
Simulation time	40457879569 ps
CPU time	277.95 seconds
Started	Sep 18 09:12:36 AM UTC 24
Finished	Sep 18 09:17:18 AM UTC 24
Peak memory	211984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405709706 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.2405709706
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3022953432
Short name	T593
Test name
Test status
Simulation time	107463159 ps
CPU time	32.5 seconds
Started	Sep 18 09:12:53 AM UTC 24
Finished	Sep 18 09:13:26 AM UTC 24
Peak memory	311216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3022953432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_t hroughput_w_partial_write.3022953432
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2805393508
Short name	T758
Test name
Test status
Simulation time	16195366631 ps
CPU time	812.4 seconds
Started	Sep 18 09:14:24 AM UTC 24
Finished	Sep 18 09:28:05 AM UTC 24
Peak memory	376936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805393508 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during _key_req.2805393508
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.303736586
Short name	T614
Test name
Test status
Simulation time	20819189 ps
CPU time	1.08 seconds
Started	Sep 18 09:14:58 AM UTC 24
Finished	Sep 18 09:15:00 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303736586 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.303736586
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2825415033
Short name	T605
Test name
Test status
Simulation time	975986237 ps
CPU time	40.79 seconds
Started	Sep 18 09:13:42 AM UTC 24
Finished	Sep 18 09:14:24 AM UTC 24
Peak memory	211916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825415033 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.2825415033
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.4046818899
Short name	T619
Test name
Test status
Simulation time	2014089232 ps
CPU time	52.9 seconds
Started	Sep 18 09:14:25 AM UTC 24
Finished	Sep 18 09:15:20 AM UTC 24
Peak memory	278576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046818899 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.4046818899
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2267533143
Short name	T604
Test name
Test status
Simulation time	459482639 ps
CPU time	6.35 seconds
Started	Sep 18 09:14:16 AM UTC 24
Finished	Sep 18 09:14:23 AM UTC 24
Peak memory	211916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267533143 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.2267533143
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3610690980
Short name	T603
Test name
Test status
Simulation time	149478567 ps
CPU time	19.74 seconds
Started	Sep 18 09:13:54 AM UTC 24
Finished	Sep 18 09:14:15 AM UTC 24
Peak memory	278576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 610690980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ma x_throughput.3610690980
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2496580736
Short name	T613
Test name
Test status
Simulation time	119770516 ps
CPU time	3.62 seconds
Started	Sep 18 09:14:53 AM UTC 24
Finished	Sep 18 09:14:57 AM UTC 24
Peak memory	222352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496580736 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.2496580736
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1525640015
Short name	T615
Test name
Test status
Simulation time	766673272 ps
CPU time	14.15 seconds
Started	Sep 18 09:14:51 AM UTC 24
Finished	Sep 18 09:15:07 AM UTC 24
Peak memory	222160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525640015 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.1525640015
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3863127818
Short name	T681
Test name
Test status
Simulation time	5900620628 ps
CPU time	427.49 seconds
Started	Sep 18 09:13:38 AM UTC 24
Finished	Sep 18 09:20:51 AM UTC 24
Peak memory	381016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863127818 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.3863127818
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1848248068
Short name	T610
Test name
Test status
Simulation time	4235708266 ps
CPU time	62.83 seconds
Started	Sep 18 09:13:49 AM UTC 24
Finished	Sep 18 09:14:54 AM UTC 24
Peak memory	362384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848248068 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.1848248068
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1024428479
Short name	T685
Test name
Test status
Simulation time	65001983044 ps
CPU time	449.15 seconds
Started	Sep 18 09:13:54 AM UTC 24
Finished	Sep 18 09:21:29 AM UTC 24
Peak memory	211860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024428479 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc ess_b2b.1024428479
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3410732301
Short name	T609
Test name
Test status
Simulation time	84920981 ps
CPU time	1.32 seconds
Started	Sep 18 09:14:49 AM UTC 24
Finished	Sep 18 09:14:52 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410732301 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3410732301
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.751106490
Short name	T725
Test name
Test status
Simulation time	80111476342 ps
CPU time	641.22 seconds
Started	Sep 18 09:14:36 AM UTC 24
Finished	Sep 18 09:25:25 AM UTC 24
Peak memory	378864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751106490 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.751106490
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.2966343314
Short name	T599
Test name
Test status
Simulation time	95062160 ps
CPU time	8.71 seconds
Started	Sep 18 09:13:37 AM UTC 24
Finished	Sep 18 09:13:47 AM UTC 24
Peak memory	245672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966343314 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2966343314
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1453553248
Short name	T933
Test name
Test status
Simulation time	142723281173 ps
CPU time	3904.25 seconds
Started	Sep 18 09:14:58 AM UTC 24
Finished	Sep 18 10:20:44 AM UTC 24
Peak memory	386704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145355324 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.1453553248
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2960909669
Short name	T640
Test name
Test status
Simulation time	6932617798 ps
CPU time	121.87 seconds
Started	Sep 18 09:14:55 AM UTC 24
Finished	Sep 18 09:16:59 AM UTC 24
Peak memory	384976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960909669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2960909669
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2334535459
Short name	T660
Test name
Test status
Simulation time	5383649467 ps
CPU time	278.75 seconds
Started	Sep 18 09:13:47 AM UTC 24
Finished	Sep 18 09:18:30 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334535459 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.2334535459
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.394103439
Short name	T618
Test name
Test status
Simulation time	133094928 ps
CPU time	65.58 seconds
Started	Sep 18 09:14:09 AM UTC 24
Finished	Sep 18 09:15:16 AM UTC 24
Peak memory	339864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 394103439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_th roughput_w_partial_write.394103439
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1961594606
Short name	T706
Test name
Test status
Simulation time	2312181813 ps
CPU time	476.33 seconds
Started	Sep 18 09:15:34 AM UTC 24
Finished	Sep 18 09:23:37 AM UTC 24
Peak memory	378968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961594606 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during _key_req.1961594606
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1418551686
Short name	T628
Test name
Test status
Simulation time	14057430 ps
CPU time	0.83 seconds
Started	Sep 18 09:16:07 AM UTC 24
Finished	Sep 18 09:16:09 AM UTC 24
Peak memory	210816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418551686 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1418551686
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.1842819439
Short name	T629
Test name
Test status
Simulation time	9688962937 ps
CPU time	70.02 seconds
Started	Sep 18 09:15:07 AM UTC 24
Finished	Sep 18 09:16:19 AM UTC 24
Peak memory	212064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842819439 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.1842819439
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.498828417
Short name	T813
Test name
Test status
Simulation time	48142560473 ps
CPU time	1066.87 seconds
Started	Sep 18 09:15:35 AM UTC 24
Finished	Sep 18 09:33:35 AM UTC 24
Peak memory	382952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498828417 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.498828417
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.4242825933
Short name	T624
Test name
Test status
Simulation time	283658538 ps
CPU time	4.96 seconds
Started	Sep 18 09:15:34 AM UTC 24
Finished	Sep 18 09:15:41 AM UTC 24
Peak memory	211200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242825933 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.4242825933
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.4034770467
Short name	T620
Test name
Test status
Simulation time	1106251359 ps
CPU time	10.91 seconds
Started	Sep 18 09:15:21 AM UTC 24
Finished	Sep 18 09:15:33 AM UTC 24
Peak memory	255844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 034770467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma x_throughput.4034770467
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3563018416
Short name	T90
Test name
Test status
Simulation time	108397692 ps
CPU time	5.03 seconds
Started	Sep 18 09:15:48 AM UTC 24
Finished	Sep 18 09:15:54 AM UTC 24
Peak memory	222248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563018416 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.3563018416
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2131259115
Short name	T627
Test name
Test status
Simulation time	461631065 ps
CPU time	13.7 seconds
Started	Sep 18 09:15:45 AM UTC 24
Finished	Sep 18 09:15:59 AM UTC 24
Peak memory	222116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131259115 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.2131259115
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1022929340
Short name	T651
Test name
Test status
Simulation time	3115726544 ps
CPU time	166.9 seconds
Started	Sep 18 09:15:01 AM UTC 24
Finished	Sep 18 09:17:51 AM UTC 24
Peak memory	346188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022929340 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.1022929340
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1054271177
Short name	T621
Test name
Test status
Simulation time	821173516 ps
CPU time	16.54 seconds
Started	Sep 18 09:15:15 AM UTC 24
Finished	Sep 18 09:15:33 AM UTC 24
Peak memory	211908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054271177 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.1054271177
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.4233301343
Short name	T680
Test name
Test status
Simulation time	56362880348 ps
CPU time	323.84 seconds
Started	Sep 18 09:15:18 AM UTC 24
Finished	Sep 18 09:20:46 AM UTC 24
Peak memory	212184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233301343 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acc ess_b2b.4233301343
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3497829188
Short name	T625
Test name
Test status
Simulation time	28160567 ps
CPU time	1.16 seconds
Started	Sep 18 09:15:42 AM UTC 24
Finished	Sep 18 09:15:44 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497829188 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3497829188
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.4072777399
Short name	T729
Test name
Test status
Simulation time	2924336423 ps
CPU time	590.57 seconds
Started	Sep 18 09:15:39 AM UTC 24
Finished	Sep 18 09:25:36 AM UTC 24
Peak memory	378848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072777399 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.4072777399
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.2333321575
Short name	T617
Test name
Test status
Simulation time	400634056 ps
CPU time	15.12 seconds
Started	Sep 18 09:14:58 AM UTC 24
Finished	Sep 18 09:15:14 AM UTC 24
Peak memory	212020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333321575 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2333321575
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1396861792
Short name	T914
Test name
Test status
Simulation time	11615077809 ps
CPU time	2030.53 seconds
Started	Sep 18 09:16:00 AM UTC 24
Finished	Sep 18 09:50:12 AM UTC 24
Peak memory	381072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139686179 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.1396861792
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.319541451
Short name	T111
Test name
Test status
Simulation time	860141162 ps
CPU time	9.86 seconds
Started	Sep 18 09:15:55 AM UTC 24
Finished	Sep 18 09:16:06 AM UTC 24
Peak memory	222324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319541451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.319541451
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.2741447112
Short name	T668
Test name
Test status
Simulation time	3916252033 ps
CPU time	247.98 seconds
Started	Sep 18 09:15:15 AM UTC 24
Finished	Sep 18 09:19:27 AM UTC 24
Peak memory	212008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741447112 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.2741447112
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1920306529
Short name	T623
Test name
Test status
Simulation time	316624578 ps
CPU time	4.03 seconds
Started	Sep 18 09:15:33 AM UTC 24
Finished	Sep 18 09:15:38 AM UTC 24
Peak memory	233304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1920306529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t hroughput_w_partial_write.1920306529
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2448753889
Short name	T672
Test name
Test status
Simulation time	6564524408 ps
CPU time	178.3 seconds
Started	Sep 18 09:16:54 AM UTC 24
Finished	Sep 18 09:19:55 AM UTC 24
Peak memory	337900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448753889 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during _key_req.2448753889
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.4255864330
Short name	T645
Test name
Test status
Simulation time	11502178 ps
CPU time	0.97 seconds
Started	Sep 18 09:17:08 AM UTC 24
Finished	Sep 18 09:17:10 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255864330 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.4255864330
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.481232560
Short name	T641
Test name
Test status
Simulation time	5465559098 ps
CPU time	37.01 seconds
Started	Sep 18 09:16:21 AM UTC 24
Finished	Sep 18 09:17:00 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481232560 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.481232560
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.2032629533
Short name	T777
Test name
Test status
Simulation time	77424907610 ps
CPU time	772.57 seconds
Started	Sep 18 09:16:57 AM UTC 24
Finished	Sep 18 09:29:58 AM UTC 24
Peak memory	385116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032629533 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.2032629533
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3135531269
Short name	T638
Test name
Test status
Simulation time	206281389 ps
CPU time	3.75 seconds
Started	Sep 18 09:16:50 AM UTC 24
Finished	Sep 18 09:16:55 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135531269 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.3135531269
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.803822850
Short name	T654
Test name
Test status
Simulation time	521053190 ps
CPU time	95.01 seconds
Started	Sep 18 09:16:38 AM UTC 24
Finished	Sep 18 09:18:15 AM UTC 24
Peak memory	378792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 03822850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max _throughput.803822850
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.1886147616
Short name	T643
Test name
Test status
Simulation time	228845534 ps
CPU time	5.26 seconds
Started	Sep 18 09:17:01 AM UTC 24
Finished	Sep 18 09:17:07 AM UTC 24
Peak memory	222380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886147616 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.1886147616
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1664104022
Short name	T644
Test name
Test status
Simulation time	1313906387 ps
CPU time	5.71 seconds
Started	Sep 18 09:17:01 AM UTC 24
Finished	Sep 18 09:17:08 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664104022 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.1664104022
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.4199322355
Short name	T715
Test name
Test status
Simulation time	2737186436 ps
CPU time	465.13 seconds
Started	Sep 18 09:16:19 AM UTC 24
Finished	Sep 18 09:24:11 AM UTC 24
Peak memory	376800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199322355 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.4199322355
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4247724812
Short name	T634
Test name
Test status
Simulation time	213450063 ps
CPU time	5.16 seconds
Started	Sep 18 09:16:31 AM UTC 24
Finished	Sep 18 09:16:37 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247724812 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.4247724812
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1150589038
Short name	T698
Test name
Test status
Simulation time	14940738059 ps
CPU time	383.17 seconds
Started	Sep 18 09:16:36 AM UTC 24
Finished	Sep 18 09:23:04 AM UTC 24
Peak memory	212192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150589038 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acc ess_b2b.1150589038
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.689368550
Short name	T642
Test name
Test status
Simulation time	166543642 ps
CPU time	1 seconds
Started	Sep 18 09:16:59 AM UTC 24
Finished	Sep 18 09:17:01 AM UTC 24
Peak memory	211080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689368550 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.689368550
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.4275094670
Short name	T783
Test name
Test status
Simulation time	53112351519 ps
CPU time	806.73 seconds
Started	Sep 18 09:16:57 AM UTC 24
Finished	Sep 18 09:30:32 AM UTC 24
Peak memory	381024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275094670 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.4275094670
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.1530178455
Short name	T631
Test name
Test status
Simulation time	555067213 ps
CPU time	13.11 seconds
Started	Sep 18 09:16:09 AM UTC 24
Finished	Sep 18 09:16:24 AM UTC 24
Peak memory	211920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530178455 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1530178455
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1316442433
Short name	T925
Test name
Test status
Simulation time	14587543442 ps
CPU time	2590.3 seconds
Started	Sep 18 09:17:08 AM UTC 24
Finished	Sep 18 10:00:49 AM UTC 24
Peak memory	386616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131644243 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.1316442433
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1698066036
Short name	T648
Test name
Test status
Simulation time	1152760056 ps
CPU time	30.68 seconds
Started	Sep 18 09:17:03 AM UTC 24
Finished	Sep 18 09:17:35 AM UTC 24
Peak memory	294820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698066036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1698066036
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3170953527
Short name	T694
Test name
Test status
Simulation time	6524425561 ps
CPU time	363.08 seconds
Started	Sep 18 09:16:25 AM UTC 24
Finished	Sep 18 09:22:33 AM UTC 24
Peak memory	212080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170953527 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.3170953527
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3767731153
Short name	T637
Test name
Test status
Simulation time	1008227943 ps
CPU time	11.03 seconds
Started	Sep 18 09:16:43 AM UTC 24
Finished	Sep 18 09:16:55 AM UTC 24
Peak memory	253860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3767731153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t hroughput_w_partial_write.3767731153
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.4101157835
Short name	T739
Test name
Test status
Simulation time	3491278087 ps
CPU time	507.01 seconds
Started	Sep 18 09:17:54 AM UTC 24
Finished	Sep 18 09:26:26 AM UTC 24
Peak memory	376924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101157835 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during _key_req.4101157835
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1741860009
Short name	T662
Test name
Test status
Simulation time	11146315 ps
CPU time	0.89 seconds
Started	Sep 18 09:18:31 AM UTC 24
Finished	Sep 18 09:18:33 AM UTC 24
Peak memory	210820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741860009 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1741860009
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2537905567
Short name	T656
Test name
Test status
Simulation time	3024052905 ps
CPU time	61.39 seconds
Started	Sep 18 09:17:19 AM UTC 24
Finished	Sep 18 09:18:22 AM UTC 24
Peak memory	212000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537905567 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.2537905567
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.259686367
Short name	T764
Test name
Test status
Simulation time	17274966399 ps
CPU time	620.06 seconds
Started	Sep 18 09:17:58 AM UTC 24
Finished	Sep 18 09:28:25 AM UTC 24
Peak memory	376800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259686367 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.259686367
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.4199509306
Short name	T653
Test name
Test status
Simulation time	141228843 ps
CPU time	3.69 seconds
Started	Sep 18 09:17:52 AM UTC 24
Finished	Sep 18 09:17:57 AM UTC 24
Peak memory	211916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199509306 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.4199509306
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1253941942
Short name	T655
Test name
Test status
Simulation time	912059040 ps
CPU time	34.24 seconds
Started	Sep 18 09:17:46 AM UTC 24
Finished	Sep 18 09:18:22 AM UTC 24
Peak memory	299124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 253941942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ma x_throughput.1253941942
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1802611919
Short name	T659
Test name
Test status
Simulation time	86233974 ps
CPU time	3.35 seconds
Started	Sep 18 09:18:25 AM UTC 24
Finished	Sep 18 09:18:29 AM UTC 24
Peak memory	222240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802611919 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1802611919
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2162610649
Short name	T661
Test name
Test status
Simulation time	4135297107 ps
CPU time	7.6 seconds
Started	Sep 18 09:18:23 AM UTC 24
Finished	Sep 18 09:18:32 AM UTC 24
Peak memory	222308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162610649 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.2162610649
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.767778711
Short name	T703
Test name
Test status
Simulation time	7447144157 ps
CPU time	373.47 seconds
Started	Sep 18 09:17:12 AM UTC 24
Finished	Sep 18 09:23:30 AM UTC 24
Peak memory	333908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767778711 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.767778711
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3055517060
Short name	T650
Test name
Test status
Simulation time	606540201 ps
CPU time	7.83 seconds
Started	Sep 18 09:17:36 AM UTC 24
Finished	Sep 18 09:17:45 AM UTC 24
Peak memory	211936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055517060 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3055517060
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2856156644
Short name	T748
Test name
Test status
Simulation time	26640467185 ps
CPU time	553.63 seconds
Started	Sep 18 09:17:40 AM UTC 24
Finished	Sep 18 09:27:01 AM UTC 24
Peak memory	212120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856156644 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc ess_b2b.2856156644
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2409204120
Short name	T658
Test name
Test status
Simulation time	72437091 ps
CPU time	0.99 seconds
Started	Sep 18 09:18:23 AM UTC 24
Finished	Sep 18 09:18:25 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409204120 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2409204120
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2767064118
Short name	T762
Test name
Test status
Simulation time	1767026065 ps
CPU time	599.05 seconds
Started	Sep 18 09:18:16 AM UTC 24
Finished	Sep 18 09:28:22 AM UTC 24
Peak memory	370724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767064118 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2767064118
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2859718949
Short name	T649
Test name
Test status
Simulation time	407387309 ps
CPU time	26.32 seconds
Started	Sep 18 09:17:12 AM UTC 24
Finished	Sep 18 09:17:39 AM UTC 24
Peak memory	286568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859718949 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2859718949
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2863685705
Short name	T934
Test name
Test status
Simulation time	19185705266 ps
CPU time	4390.1 seconds
Started	Sep 18 09:18:30 AM UTC 24
Finished	Sep 18 10:32:28 AM UTC 24
Peak memory	394828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286368570 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.2863685705
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.275967509
Short name	T664
Test name
Test status
Simulation time	200430086 ps
CPU time	23.08 seconds
Started	Sep 18 09:18:26 AM UTC 24
Finished	Sep 18 09:18:51 AM UTC 24
Peak memory	257936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275967509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.275967509
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2633664854
Short name	T673
Test name
Test status
Simulation time	22442511538 ps
CPU time	157.49 seconds
Started	Sep 18 09:17:35 AM UTC 24
Finished	Sep 18 09:20:15 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633664854 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2633664854
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.678913458
Short name	T663
Test name
Test status
Simulation time	853200173 ps
CPU time	57.39 seconds
Started	Sep 18 09:17:51 AM UTC 24
Finished	Sep 18 09:18:50 AM UTC 24
Peak memory	339796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 678913458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_th roughput_w_partial_write.678913458
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3370119771
Short name	T795
Test name
Test status
Simulation time	11695407243 ps
CPU time	742.02 seconds
Started	Sep 18 09:19:33 AM UTC 24
Finished	Sep 18 09:32:03 AM UTC 24
Peak memory	378788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370119771 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during _key_req.3370119771
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.935971930
Short name	T679
Test name
Test status
Simulation time	60373700 ps
CPU time	1.02 seconds
Started	Sep 18 09:20:39 AM UTC 24
Finished	Sep 18 09:20:41 AM UTC 24
Peak memory	211064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935971930 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.935971930
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.4018201357
Short name	T676
Test name
Test status
Simulation time	4049775100 ps
CPU time	97.94 seconds
Started	Sep 18 09:18:51 AM UTC 24
Finished	Sep 18 09:20:31 AM UTC 24
Peak memory	212196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018201357 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.4018201357
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.4199366673
Short name	T811
Test name
Test status
Simulation time	79749667092 ps
CPU time	815.1 seconds
Started	Sep 18 09:19:42 AM UTC 24
Finished	Sep 18 09:33:26 AM UTC 24
Peak memory	381004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199366673 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.4199366673
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1086793061
Short name	T671
Test name
Test status
Simulation time	1989508628 ps
CPU time	6.98 seconds
Started	Sep 18 09:19:33 AM UTC 24
Finished	Sep 18 09:19:41 AM UTC 24
Peak memory	226476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086793061 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.1086793061
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1177379114
Short name	T670
Test name
Test status
Simulation time	175644413 ps
CPU time	5.15 seconds
Started	Sep 18 09:19:25 AM UTC 24
Finished	Sep 18 09:19:32 AM UTC 24
Peak memory	231452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 177379114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ma x_throughput.1177379114
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.4212693062
Short name	T91
Test name
Test status
Simulation time	92567533 ps
CPU time	7.32 seconds
Started	Sep 18 09:20:29 AM UTC 24
Finished	Sep 18 09:20:38 AM UTC 24
Peak memory	222180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212693062 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.4212693062
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2131138211
Short name	T675
Test name
Test status
Simulation time	1391082665 ps
CPU time	8.64 seconds
Started	Sep 18 09:20:19 AM UTC 24
Finished	Sep 18 09:20:29 AM UTC 24
Peak memory	211868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131138211 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.2131138211
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3659128408
Short name	T773
Test name
Test status
Simulation time	4839059114 ps
CPU time	629.1 seconds
Started	Sep 18 09:18:35 AM UTC 24
Finished	Sep 18 09:29:11 AM UTC 24
Peak memory	383076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659128408 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.3659128408
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2846761997
Short name	T669
Test name
Test status
Simulation time	535481473 ps
CPU time	20.42 seconds
Started	Sep 18 09:19:09 AM UTC 24
Finished	Sep 18 09:19:31 AM UTC 24
Peak memory	211912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846761997 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.2846761997
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2913468601
Short name	T738
Test name
Test status
Simulation time	58427303688 ps
CPU time	416.96 seconds
Started	Sep 18 09:19:12 AM UTC 24
Finished	Sep 18 09:26:15 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913468601 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc ess_b2b.2913468601
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2131359487
Short name	T674
Test name
Test status
Simulation time	70973630 ps
CPU time	1.05 seconds
Started	Sep 18 09:20:16 AM UTC 24
Finished	Sep 18 09:20:18 AM UTC 24
Peak memory	211088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131359487 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2131359487
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.3181746423
Short name	T792
Test name
Test status
Simulation time	42221302649 ps
CPU time	686.02 seconds
Started	Sep 18 09:19:57 AM UTC 24
Finished	Sep 18 09:31:31 AM UTC 24
Peak memory	378844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181746423 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3181746423
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.3897397617
Short name	T667
Test name
Test status
Simulation time	424073863 ps
CPU time	50.59 seconds
Started	Sep 18 09:18:33 AM UTC 24
Finished	Sep 18 09:19:25 AM UTC 24
Peak memory	331804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897397617 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3897397617
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2809657516
Short name	T895
Test name
Test status
Simulation time	39249611536 ps
CPU time	1292.18 seconds
Started	Sep 18 09:20:33 AM UTC 24
Finished	Sep 18 09:42:19 AM UTC 24
Peak memory	382936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280965751 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.2809657516
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3882155080
Short name	T682
Test name
Test status
Simulation time	3340316748 ps
CPU time	39.19 seconds
Started	Sep 18 09:20:31 AM UTC 24
Finished	Sep 18 09:21:12 AM UTC 24
Peak memory	247984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882155080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3882155080
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.70085601
Short name	T709
Test name
Test status
Simulation time	2919105840 ps
CPU time	287.9 seconds
Started	Sep 18 09:18:52 AM UTC 24
Finished	Sep 18 09:23:44 AM UTC 24
Peak memory	212140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70085601 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.70085601
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.3249082850
Short name	T677
Test name
Test status
Simulation time	364423035 ps
CPU time	61.89 seconds
Started	Sep 18 09:19:28 AM UTC 24
Finished	Sep 18 09:20:32 AM UTC 24
Peak memory	360272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3249082850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t hroughput_w_partial_write.3249082850
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1375858578
Short name	T807
Test name
Test status
Simulation time	13841715386 ps
CPU time	677.28 seconds
Started	Sep 18 09:21:34 AM UTC 24
Finished	Sep 18 09:32:59 AM UTC 24
Peak memory	370668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375858578 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during _key_req.1375858578
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2287050208
Short name	T697
Test name
Test status
Simulation time	18336614 ps
CPU time	0.95 seconds
Started	Sep 18 09:22:49 AM UTC 24
Finished	Sep 18 09:22:51 AM UTC 24
Peak memory	210820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287050208 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2287050208
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.4261965881
Short name	T687
Test name
Test status
Simulation time	8608702574 ps
CPU time	44.55 seconds
Started	Sep 18 09:20:47 AM UTC 24
Finished	Sep 18 09:21:33 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261965881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.4261965881
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2468399675
Short name	T689
Test name
Test status
Simulation time	2873154032 ps
CPU time	21.2 seconds
Started	Sep 18 09:21:46 AM UTC 24
Finished	Sep 18 09:22:08 AM UTC 24
Peak memory	211984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468399675 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.2468399675
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2098290976
Short name	T688
Test name
Test status
Simulation time	2042570840 ps
CPU time	11.09 seconds
Started	Sep 18 09:21:33 AM UTC 24
Finished	Sep 18 09:21:45 AM UTC 24
Peak memory	211868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098290976 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2098290976
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3154287289
Short name	T686
Test name
Test status
Simulation time	101710693 ps
CPU time	5.87 seconds
Started	Sep 18 09:21:25 AM UTC 24
Finished	Sep 18 09:21:31 AM UTC 24
Peak memory	235424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 154287289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ma x_throughput.3154287289
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.829934463
Short name	T693
Test name
Test status
Simulation time	220562140 ps
CPU time	4.07 seconds
Started	Sep 18 09:22:27 AM UTC 24
Finished	Sep 18 09:22:32 AM UTC 24
Peak memory	222188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829934463 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.829934463
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3278137760
Short name	T692
Test name
Test status
Simulation time	278585583 ps
CPU time	11.16 seconds
Started	Sep 18 09:22:13 AM UTC 24
Finished	Sep 18 09:22:26 AM UTC 24
Peak memory	222164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278137760 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.3278137760
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.399850724
Short name	T815
Test name
Test status
Simulation time	10772174009 ps
CPU time	780.05 seconds
Started	Sep 18 09:20:42 AM UTC 24
Finished	Sep 18 09:33:50 AM UTC 24
Peak memory	382876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399850724 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.399850724
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1404555018
Short name	T684
Test name
Test status
Simulation time	511635913 ps
CPU time	9.23 seconds
Started	Sep 18 09:21:13 AM UTC 24
Finished	Sep 18 09:21:24 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404555018 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1404555018
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.624585554
Short name	T728
Test name
Test status
Simulation time	11451131240 ps
CPU time	250.83 seconds
Started	Sep 18 09:21:20 AM UTC 24
Finished	Sep 18 09:25:35 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624585554 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acce ss_b2b.624585554
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2099241046
Short name	T691
Test name
Test status
Simulation time	127094658 ps
CPU time	1.12 seconds
Started	Sep 18 09:22:10 AM UTC 24
Finished	Sep 18 09:22:13 AM UTC 24
Peak memory	211088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099241046 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2099241046
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.1047987935
Short name	T754
Test name
Test status
Simulation time	1759954709 ps
CPU time	310.99 seconds
Started	Sep 18 09:22:09 AM UTC 24
Finished	Sep 18 09:27:24 AM UTC 24
Peak memory	358228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047987935 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1047987935
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1231319461
Short name	T690
Test name
Test status
Simulation time	134235005 ps
CPU time	86.17 seconds
Started	Sep 18 09:20:41 AM UTC 24
Finished	Sep 18 09:22:09 AM UTC 24
Peak memory	360276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231319461 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1231319461
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.690811386
Short name	T888
Test name
Test status
Simulation time	25949953536 ps
CPU time	1037.28 seconds
Started	Sep 18 09:22:34 AM UTC 24
Finished	Sep 18 09:40:04 AM UTC 24
Peak memory	370660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690811386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.690811386
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2860825878
Short name	T704
Test name
Test status
Simulation time	3476128603 ps
CPU time	58.05 seconds
Started	Sep 18 09:22:33 AM UTC 24
Finished	Sep 18 09:23:33 AM UTC 24
Peak memory	311316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860825878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2860825878
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3070498831
Short name	T772
Test name
Test status
Simulation time	4094410319 ps
CPU time	490.77 seconds
Started	Sep 18 09:20:51 AM UTC 24
Finished	Sep 18 09:29:08 AM UTC 24
Peak memory	211980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070498831 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3070498831
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.4159182424
Short name	T695
Test name
Test status
Simulation time	289568408 ps
CPU time	76.54 seconds
Started	Sep 18 09:21:30 AM UTC 24
Finished	Sep 18 09:22:48 AM UTC 24
Peak memory	354144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4159182424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_t hroughput_w_partial_write.4159182424
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.885105604
Short name	T211
Test name
Test status
Simulation time	2646623205 ps
CPU time	486 seconds
Started	Sep 18 08:26:17 AM UTC 24
Finished	Sep 18 08:34:29 AM UTC 24
Peak memory	374752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885105604 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_k ey_req.885105604
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.402379901
Short name	T162
Test name
Test status
Simulation time	38044598 ps
CPU time	0.85 seconds
Started	Sep 18 08:26:35 AM UTC 24
Finished	Sep 18 08:26:36 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402379901 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.402379901
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.3209382555
Short name	T152
Test name
Test status
Simulation time	538754311 ps
CPU time	39.67 seconds
Started	Sep 18 08:25:58 AM UTC 24
Finished	Sep 18 08:26:40 AM UTC 24
Peak memory	211980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209382555 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.3209382555
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1445195865
Short name	T129
Test name
Test status
Simulation time	1153379374 ps
CPU time	139.43 seconds
Started	Sep 18 08:26:18 AM UTC 24
Finished	Sep 18 08:28:40 AM UTC 24
Peak memory	356172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445195865 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.1445195865
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2325448170
Short name	T22
Test name
Test status
Simulation time	716111273 ps
CPU time	8.2 seconds
Started	Sep 18 08:26:17 AM UTC 24
Finished	Sep 18 08:26:26 AM UTC 24
Peak memory	222188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325448170 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2325448170
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.303868363
Short name	T70
Test name
Test status
Simulation time	333747360 ps
CPU time	6.51 seconds
Started	Sep 18 08:26:10 AM UTC 24
Finished	Sep 18 08:26:17 AM UTC 24
Peak memory	233236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 03868363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max_ throughput.303868363
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.443695404
Short name	T43
Test name
Test status
Simulation time	98978145 ps
CPU time	5.27 seconds
Started	Sep 18 08:26:27 AM UTC 24
Finished	Sep 18 08:26:34 AM UTC 24
Peak memory	222376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443695404 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.443695404
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.2391440809
Short name	T48
Test name
Test status
Simulation time	879934883 ps
CPU time	13.36 seconds
Started	Sep 18 08:26:24 AM UTC 24
Finished	Sep 18 08:26:39 AM UTC 24
Peak memory	211932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391440809 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.2391440809
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2984399990
Short name	T229
Test name
Test status
Simulation time	12964708558 ps
CPU time	663.33 seconds
Started	Sep 18 08:25:46 AM UTC 24
Finished	Sep 18 08:36:57 AM UTC 24
Peak memory	383136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984399990 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.2984399990
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.701837307
Short name	T161
Test name
Test status
Simulation time	3259930778 ps
CPU time	26.7 seconds
Started	Sep 18 08:26:08 AM UTC 24
Finished	Sep 18 08:26:36 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701837307 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.701837307
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.1158307828
Short name	T140
Test name
Test status
Simulation time	18657153655 ps
CPU time	349.94 seconds
Started	Sep 18 08:26:09 AM UTC 24
Finished	Sep 18 08:32:04 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158307828 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce ss_b2b.1158307828
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.825090958
Short name	T73
Test name
Test status
Simulation time	29805713 ps
CPU time	1.26 seconds
Started	Sep 18 08:26:21 AM UTC 24
Finished	Sep 18 08:26:23 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825090958 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.825090958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3912323627
Short name	T32
Test name
Test status
Simulation time	240059400 ps
CPU time	4.65 seconds
Started	Sep 18 08:26:34 AM UTC 24
Finished	Sep 18 08:26:39 AM UTC 24
Peak memory	244468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912323627 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3912323627
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2901821254
Short name	T67
Test name
Test status
Simulation time	2488523794 ps
CPU time	25.69 seconds
Started	Sep 18 08:25:43 AM UTC 24
Finished	Sep 18 08:26:10 AM UTC 24
Peak memory	290772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901821254 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2901821254
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2043644410
Short name	T305
Test name
Test status
Simulation time	77581795589 ps
CPU time	1137.01 seconds
Started	Sep 18 08:26:34 AM UTC 24
Finished	Sep 18 08:45:42 AM UTC 24
Peak memory	384916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204364441 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.2043644410
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4285662025
Short name	T52
Test name
Test status
Simulation time	5082672174 ps
CPU time	215.5 seconds
Started	Sep 18 08:26:27 AM UTC 24
Finished	Sep 18 08:30:06 AM UTC 24
Peak memory	313388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285662025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.4285662025
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.4060415922
Short name	T103
Test name
Test status
Simulation time	7512246515 ps
CPU time	192.53 seconds
Started	Sep 18 08:26:01 AM UTC 24
Finished	Sep 18 08:29:16 AM UTC 24
Peak memory	212184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060415922 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.4060415922
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1567031636
Short name	T74
Test name
Test status
Simulation time	716197427 ps
CPU time	14.91 seconds
Started	Sep 18 08:26:11 AM UTC 24
Finished	Sep 18 08:26:27 AM UTC 24
Peak memory	270356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1567031636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th roughput_w_partial_write.1567031636
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.309045919
Short name	T829
Test name
Test status
Simulation time	6868868759 ps
CPU time	668.64 seconds
Started	Sep 18 09:23:36 AM UTC 24
Finished	Sep 18 09:34:52 AM UTC 24
Peak memory	382928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309045919 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during_ key_req.309045919
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1532949784
Short name	T714
Test name
Test status
Simulation time	22746934 ps
CPU time	0.99 seconds
Started	Sep 18 09:23:56 AM UTC 24
Finished	Sep 18 09:23:58 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532949784 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1532949784
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.2568561912
Short name	T701
Test name
Test status
Simulation time	1180950068 ps
CPU time	21.12 seconds
Started	Sep 18 09:23:05 AM UTC 24
Finished	Sep 18 09:23:28 AM UTC 24
Peak memory	212212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568561912 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.2568561912
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.2933856650
Short name	T902
Test name
Test status
Simulation time	58929041369 ps
CPU time	1276.91 seconds
Started	Sep 18 09:23:38 AM UTC 24
Finished	Sep 18 09:45:09 AM UTC 24
Peak memory	381036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933856650 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.2933856650
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1566439678
Short name	T707
Test name
Test status
Simulation time	649543979 ps
CPU time	7.83 seconds
Started	Sep 18 09:23:33 AM UTC 24
Finished	Sep 18 09:23:42 AM UTC 24
Peak memory	222160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566439678 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.1566439678
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2384355154
Short name	T708
Test name
Test status
Simulation time	125309051 ps
CPU time	12.69 seconds
Started	Sep 18 09:23:29 AM UTC 24
Finished	Sep 18 09:23:42 AM UTC 24
Peak memory	262048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 384355154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ma x_throughput.2384355154
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2283599385
Short name	T713
Test name
Test status
Simulation time	177710265 ps
CPU time	7.47 seconds
Started	Sep 18 09:23:47 AM UTC 24
Finished	Sep 18 09:23:55 AM UTC 24
Peak memory	222156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283599385 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.2283599385
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.520308150
Short name	T711
Test name
Test status
Simulation time	1397391562 ps
CPU time	5.93 seconds
Started	Sep 18 09:23:44 AM UTC 24
Finished	Sep 18 09:23:51 AM UTC 24
Peak memory	222116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520308150 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.520308150
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3772208801
Short name	T849
Test name
Test status
Simulation time	29909232007 ps
CPU time	802.9 seconds
Started	Sep 18 09:22:52 AM UTC 24
Finished	Sep 18 09:36:25 AM UTC 24
Peak memory	384888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772208801 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.3772208801
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3017462172
Short name	T702
Test name
Test status
Simulation time	176568165 ps
CPU time	12.13 seconds
Started	Sep 18 09:23:15 AM UTC 24
Finished	Sep 18 09:23:28 AM UTC 24
Peak memory	211920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017462172 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.3017462172
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.109018301
Short name	T775
Test name
Test status
Simulation time	4671708273 ps
CPU time	364.43 seconds
Started	Sep 18 09:23:29 AM UTC 24
Finished	Sep 18 09:29:38 AM UTC 24
Peak memory	211976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109018301 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acce ss_b2b.109018301
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3755406397
Short name	T710
Test name
Test status
Simulation time	52700141 ps
CPU time	1.24 seconds
Started	Sep 18 09:23:43 AM UTC 24
Finished	Sep 18 09:23:46 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755406397 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3755406397
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1768147003
Short name	T915
Test name
Test status
Simulation time	70425837028 ps
CPU time	1581.96 seconds
Started	Sep 18 09:23:42 AM UTC 24
Finished	Sep 18 09:50:22 AM UTC 24
Peak memory	385180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768147003 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1768147003
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3637175195
Short name	T699
Test name
Test status
Simulation time	2114058491 ps
CPU time	17.31 seconds
Started	Sep 18 09:22:51 AM UTC 24
Finished	Sep 18 09:23:10 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637175195 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3637175195
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.545391018
Short name	T926
Test name
Test status
Simulation time	77348583235 ps
CPU time	2268.9 seconds
Started	Sep 18 09:23:54 AM UTC 24
Finished	Sep 18 10:02:08 AM UTC 24
Peak memory	396852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545391018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.545391018
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.495136310
Short name	T831
Test name
Test status
Simulation time	5685490050 ps
CPU time	655.57 seconds
Started	Sep 18 09:23:53 AM UTC 24
Finished	Sep 18 09:34:56 AM UTC 24
Peak memory	385260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495136310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.495136310
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.282977935
Short name	T730
Test name
Test status
Simulation time	1916724583 ps
CPU time	144.12 seconds
Started	Sep 18 09:23:10 AM UTC 24
Finished	Sep 18 09:25:37 AM UTC 24
Peak memory	212000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282977935 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.282977935
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.39442209
Short name	T705
Test name
Test status
Simulation time	146483869 ps
CPU time	3.5 seconds
Started	Sep 18 09:23:31 AM UTC 24
Finished	Sep 18 09:23:35 AM UTC 24
Peak memory	229400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 39442209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_thr oughput_w_partial_write.39442209
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2783320958
Short name	T885
Test name
Test status
Simulation time	2593256647 ps
CPU time	872.44 seconds
Started	Sep 18 09:24:57 AM UTC 24
Finished	Sep 18 09:39:39 AM UTC 24
Peak memory	382956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783320958 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during _key_req.2783320958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.865202768
Short name	T734
Test name
Test status
Simulation time	23635348 ps
CPU time	0.91 seconds
Started	Sep 18 09:25:45 AM UTC 24
Finished	Sep 18 09:25:47 AM UTC 24
Peak memory	210636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865202768 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.865202768
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3928453764
Short name	T720
Test name
Test status
Simulation time	503182549 ps
CPU time	30.39 seconds
Started	Sep 18 09:24:20 AM UTC 24
Finished	Sep 18 09:24:52 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928453764 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.3928453764
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2452164727
Short name	T825
Test name
Test status
Simulation time	20265685322 ps
CPU time	534.19 seconds
Started	Sep 18 09:25:24 AM UTC 24
Finished	Sep 18 09:34:25 AM UTC 24
Peak memory	383060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452164727 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.2452164727
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.860164113
Short name	T723
Test name
Test status
Simulation time	40530626 ps
CPU time	1.55 seconds
Started	Sep 18 09:24:54 AM UTC 24
Finished	Sep 18 09:24:56 AM UTC 24
Peak memory	220880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860164113 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.860164113
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1415616271
Short name	T737
Test name
Test status
Simulation time	244744000 ps
CPU time	79.99 seconds
Started	Sep 18 09:24:53 AM UTC 24
Finished	Sep 18 09:26:14 AM UTC 24
Peak memory	370728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 415616271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma x_throughput.1415616271
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.814173784
Short name	T731
Test name
Test status
Simulation time	342130562 ps
CPU time	7.08 seconds
Started	Sep 18 09:25:36 AM UTC 24
Finished	Sep 18 09:25:44 AM UTC 24
Peak memory	222192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814173784 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.814173784
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1310357127
Short name	T732
Test name
Test status
Simulation time	252887312 ps
CPU time	9.51 seconds
Started	Sep 18 09:25:34 AM UTC 24
Finished	Sep 18 09:25:44 AM UTC 24
Peak memory	222184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310357127 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.1310357127
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.974671062
Short name	T736
Test name
Test status
Simulation time	3519803267 ps
CPU time	119.58 seconds
Started	Sep 18 09:24:11 AM UTC 24
Finished	Sep 18 09:26:13 AM UTC 24
Peak memory	255972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974671062 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.974671062
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2327221168
Short name	T721
Test name
Test status
Simulation time	132585066 ps
CPU time	4.54 seconds
Started	Sep 18 09:24:48 AM UTC 24
Finished	Sep 18 09:24:53 AM UTC 24
Peak memory	218144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327221168 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.2327221168
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3060342630
Short name	T823
Test name
Test status
Simulation time	68759078288 ps
CPU time	556.17 seconds
Started	Sep 18 09:24:53 AM UTC 24
Finished	Sep 18 09:34:16 AM UTC 24
Peak memory	212056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060342630 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc ess_b2b.3060342630
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1304551670
Short name	T727
Test name
Test status
Simulation time	31729994 ps
CPU time	1.08 seconds
Started	Sep 18 09:25:30 AM UTC 24
Finished	Sep 18 09:25:32 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304551670 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1304551670
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1821358341
Short name	T862
Test name
Test status
Simulation time	11494506880 ps
CPU time	682.77 seconds
Started	Sep 18 09:25:26 AM UTC 24
Finished	Sep 18 09:36:57 AM UTC 24
Peak memory	382940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821358341 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1821358341
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1572645316
Short name	T718
Test name
Test status
Simulation time	459601180 ps
CPU time	45.95 seconds
Started	Sep 18 09:23:59 AM UTC 24
Finished	Sep 18 09:24:46 AM UTC 24
Peak memory	313384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572645316 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1572645316
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1645731553
Short name	T929
Test name
Test status
Simulation time	46705094444 ps
CPU time	2306.82 seconds
Started	Sep 18 09:25:38 AM UTC 24
Finished	Sep 18 10:04:31 AM UTC 24
Peak memory	394900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164573155 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.1645731553
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.689470995
Short name	T789
Test name
Test status
Simulation time	1969985741 ps
CPU time	333.26 seconds
Started	Sep 18 09:25:37 AM UTC 24
Finished	Sep 18 09:31:14 AM UTC 24
Peak memory	362584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689470995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.689470995
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.200541826
Short name	T759
Test name
Test status
Simulation time	7633229848 ps
CPU time	197.42 seconds
Started	Sep 18 09:24:45 AM UTC 24
Finished	Sep 18 09:28:06 AM UTC 24
Peak memory	212188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200541826 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.200541826
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2346638218
Short name	T724
Test name
Test status
Simulation time	89730241 ps
CPU time	27.85 seconds
Started	Sep 18 09:24:54 AM UTC 24
Finished	Sep 18 09:25:23 AM UTC 24
Peak memory	288684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2346638218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t hroughput_w_partial_write.2346638218
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2725784957
Short name	T832
Test name
Test status
Simulation time	2805512744 ps
CPU time	500.18 seconds
Started	Sep 18 09:26:31 AM UTC 24
Finished	Sep 18 09:34:57 AM UTC 24
Peak memory	378796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725784957 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during _key_req.2725784957
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3843407384
Short name	T750
Test name
Test status
Simulation time	13377820 ps
CPU time	0.98 seconds
Started	Sep 18 09:27:03 AM UTC 24
Finished	Sep 18 09:27:05 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843407384 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3843407384
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.4100640333
Short name	T742
Test name
Test status
Simulation time	1711255082 ps
CPU time	44.82 seconds
Started	Sep 18 09:25:48 AM UTC 24
Finished	Sep 18 09:26:35 AM UTC 24
Peak memory	211864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100640333 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.4100640333
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.780807023
Short name	T896
Test name
Test status
Simulation time	62436373017 ps
CPU time	942.38 seconds
Started	Sep 18 09:26:35 AM UTC 24
Finished	Sep 18 09:42:28 AM UTC 24
Peak memory	384988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780807023 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.780807023
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1243930567
Short name	T743
Test name
Test status
Simulation time	991516951 ps
CPU time	8.34 seconds
Started	Sep 18 09:26:29 AM UTC 24
Finished	Sep 18 09:26:38 AM UTC 24
Peak memory	222176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243930567 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.1243930567
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.48655103
Short name	T740
Test name
Test status
Simulation time	66191301 ps
CPU time	11.16 seconds
Started	Sep 18 09:26:16 AM UTC 24
Finished	Sep 18 09:26:28 AM UTC 24
Peak memory	261976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 8655103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_max_ throughput.48655103
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3441162466
Short name	T749
Test name
Test status
Simulation time	113890797 ps
CPU time	4.71 seconds
Started	Sep 18 09:26:57 AM UTC 24
Finished	Sep 18 09:27:02 AM UTC 24
Peak memory	222172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441162466 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.3441162466
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1362422468
Short name	T747
Test name
Test status
Simulation time	73192848 ps
CPU time	4.61 seconds
Started	Sep 18 09:26:52 AM UTC 24
Finished	Sep 18 09:26:57 AM UTC 24
Peak memory	211948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362422468 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.1362422468
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2413560629
Short name	T854
Test name
Test status
Simulation time	10715916338 ps
CPU time	640.82 seconds
Started	Sep 18 09:25:48 AM UTC 24
Finished	Sep 18 09:36:36 AM UTC 24
Peak memory	384912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413560629 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.2413560629
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1256057290
Short name	T741
Test name
Test status
Simulation time	608915998 ps
CPU time	14.75 seconds
Started	Sep 18 09:26:15 AM UTC 24
Finished	Sep 18 09:26:31 AM UTC 24
Peak memory	211912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256057290 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.1256057290
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1921838132
Short name	T889
Test name
Test status
Simulation time	91914121274 ps
CPU time	827.95 seconds
Started	Sep 18 09:26:16 AM UTC 24
Finished	Sep 18 09:40:14 AM UTC 24
Peak memory	211396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921838132 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acc ess_b2b.1921838132
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.265903731
Short name	T745
Test name
Test status
Simulation time	28118878 ps
CPU time	1.1 seconds
Started	Sep 18 09:26:48 AM UTC 24
Finished	Sep 18 09:26:51 AM UTC 24
Peak memory	210636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265903731 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.265903731
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.2299903740
Short name	T844
Test name
Test status
Simulation time	17311324687 ps
CPU time	537.65 seconds
Started	Sep 18 09:26:39 AM UTC 24
Finished	Sep 18 09:35:43 AM UTC 24
Peak memory	376940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299903740 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2299903740
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2538859089
Short name	T735
Test name
Test status
Simulation time	2251292941 ps
CPU time	16.61 seconds
Started	Sep 18 09:25:45 AM UTC 24
Finished	Sep 18 09:26:03 AM UTC 24
Peak memory	212056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538859089 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2538859089
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.2199234723
Short name	T814
Test name
Test status
Simulation time	51242236055 ps
CPU time	393.74 seconds
Started	Sep 18 09:27:02 AM UTC 24
Finished	Sep 18 09:33:41 AM UTC 24
Peak memory	372628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219923472 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.2199234723
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4029294492
Short name	T751
Test name
Test status
Simulation time	2241985657 ps
CPU time	11.26 seconds
Started	Sep 18 09:26:58 AM UTC 24
Finished	Sep 18 09:27:10 AM UTC 24
Peak memory	228712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029294492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.4029294492
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.915089427
Short name	T788
Test name
Test status
Simulation time	11623753960 ps
CPU time	306.13 seconds
Started	Sep 18 09:26:03 AM UTC 24
Finished	Sep 18 09:31:14 AM UTC 24
Peak memory	212056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915089427 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.915089427
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1130195681
Short name	T755
Test name
Test status
Simulation time	662938672 ps
CPU time	68.37 seconds
Started	Sep 18 09:26:28 AM UTC 24
Finished	Sep 18 09:27:38 AM UTC 24
Peak memory	378796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1130195681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.1130195681
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.258311401
Short name	T911
Test name
Test status
Simulation time	3180567957 ps
CPU time	1191.3 seconds
Started	Sep 18 09:28:07 AM UTC 24
Finished	Sep 18 09:48:12 AM UTC 24
Peak memory	385132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258311401 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during_ key_req.258311401
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1550644379
Short name	T768
Test name
Test status
Simulation time	16830720 ps
CPU time	0.94 seconds
Started	Sep 18 09:28:33 AM UTC 24
Finished	Sep 18 09:28:35 AM UTC 24
Peak memory	210820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550644379 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1550644379
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.631368152
Short name	T761
Test name
Test status
Simulation time	4008026542 ps
CPU time	62.53 seconds
Started	Sep 18 09:27:17 AM UTC 24
Finished	Sep 18 09:28:21 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631368152 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.631368152
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.1605946306
Short name	T846
Test name
Test status
Simulation time	1429696061 ps
CPU time	475.85 seconds
Started	Sep 18 09:28:15 AM UTC 24
Finished	Sep 18 09:36:17 AM UTC 24
Peak memory	382896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605946306 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1605946306
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2845563671
Short name	T760
Test name
Test status
Simulation time	614957873 ps
CPU time	7.44 seconds
Started	Sep 18 09:28:06 AM UTC 24
Finished	Sep 18 09:28:15 AM UTC 24
Peak memory	211920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845563671 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.2845563671
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.335081761
Short name	T757
Test name
Test status
Simulation time	80572919 ps
CPU time	10.27 seconds
Started	Sep 18 09:27:44 AM UTC 24
Finished	Sep 18 09:27:55 AM UTC 24
Peak memory	262192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 35081761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_max _throughput.335081761
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3078060380
Short name	T766
Test name
Test status
Simulation time	113258382 ps
CPU time	3.8 seconds
Started	Sep 18 09:28:26 AM UTC 24
Finished	Sep 18 09:28:31 AM UTC 24
Peak memory	222296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078060380 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.3078060380
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2144054422
Short name	T767
Test name
Test status
Simulation time	228924515 ps
CPU time	6.82 seconds
Started	Sep 18 09:28:24 AM UTC 24
Finished	Sep 18 09:28:32 AM UTC 24
Peak memory	222240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144054422 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.2144054422
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2616070746
Short name	T887
Test name
Test status
Simulation time	46545680177 ps
CPU time	761.99 seconds
Started	Sep 18 09:27:11 AM UTC 24
Finished	Sep 18 09:40:02 AM UTC 24
Peak memory	380820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616070746 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.2616070746
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.660412906
Short name	T756
Test name
Test status
Simulation time	3113609642 ps
CPU time	16.14 seconds
Started	Sep 18 09:27:26 AM UTC 24
Finished	Sep 18 09:27:43 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660412906 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.660412906
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2614283608
Short name	T863
Test name
Test status
Simulation time	37154200529 ps
CPU time	561.61 seconds
Started	Sep 18 09:27:39 AM UTC 24
Finished	Sep 18 09:37:07 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614283608 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc ess_b2b.2614283608
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1032043070
Short name	T765
Test name
Test status
Simulation time	29441184 ps
CPU time	1.13 seconds
Started	Sep 18 09:28:24 AM UTC 24
Finished	Sep 18 09:28:26 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032043070 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1032043070
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1621509889
Short name	T909
Test name
Test status
Simulation time	45008519717 ps
CPU time	1156.16 seconds
Started	Sep 18 09:28:22 AM UTC 24
Finished	Sep 18 09:47:51 AM UTC 24
Peak memory	382944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621509889 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1621509889
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.1337414457
Short name	T753
Test name
Test status
Simulation time	197271252 ps
CPU time	15.5 seconds
Started	Sep 18 09:27:06 AM UTC 24
Finished	Sep 18 09:27:23 AM UTC 24
Peak memory	212184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337414457 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1337414457
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1584315703
Short name	T906
Test name
Test status
Simulation time	5967684434 ps
CPU time	1108.36 seconds
Started	Sep 18 09:28:32 AM UTC 24
Finished	Sep 18 09:47:13 AM UTC 24
Peak memory	393132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158431570 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.1584315703
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.833669580
Short name	T770
Test name
Test status
Simulation time	1702794543 ps
CPU time	26.29 seconds
Started	Sep 18 09:28:27 AM UTC 24
Finished	Sep 18 09:28:54 AM UTC 24
Peak memory	224224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833669580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.833669580
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.4105244571
Short name	T802
Test name
Test status
Simulation time	21511774632 ps
CPU time	312.88 seconds
Started	Sep 18 09:27:23 AM UTC 24
Finished	Sep 18 09:32:41 AM UTC 24
Peak memory	212180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105244571 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.4105244571
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.314075776
Short name	T771
Test name
Test status
Simulation time	288834402 ps
CPU time	59.82 seconds
Started	Sep 18 09:27:56 AM UTC 24
Finished	Sep 18 09:28:57 AM UTC 24
Peak memory	335772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 314075776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_th roughput_w_partial_write.314075776
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2594849746
Short name	T892
Test name
Test status
Simulation time	14944381015 ps
CPU time	639.01 seconds
Started	Sep 18 09:29:59 AM UTC 24
Finished	Sep 18 09:40:46 AM UTC 24
Peak memory	382884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594849746 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during _key_req.2594849746
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1236154158
Short name	T786
Test name
Test status
Simulation time	42850669 ps
CPU time	0.85 seconds
Started	Sep 18 09:30:37 AM UTC 24
Finished	Sep 18 09:30:39 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236154158 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1236154158
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.362669543
Short name	T778
Test name
Test status
Simulation time	3131189231 ps
CPU time	63.75 seconds
Started	Sep 18 09:28:55 AM UTC 24
Finished	Sep 18 09:30:01 AM UTC 24
Peak memory	211916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362669543 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.362669543
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.1856061421
Short name	T919
Test name
Test status
Simulation time	75525920101 ps
CPU time	1326.57 seconds
Started	Sep 18 09:30:02 AM UTC 24
Finished	Sep 18 09:52:23 AM UTC 24
Peak memory	383148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856061421 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.1856061421
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3609840676
Short name	T779
Test name
Test status
Simulation time	1010234322 ps
CPU time	17.27 seconds
Started	Sep 18 09:29:45 AM UTC 24
Finished	Sep 18 09:30:04 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609840676 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.3609840676
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.769214072
Short name	T791
Test name
Test status
Simulation time	268972902 ps
CPU time	108.89 seconds
Started	Sep 18 09:29:33 AM UTC 24
Finished	Sep 18 09:31:24 AM UTC 24
Peak memory	378780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 69214072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_max _throughput.769214072
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2807754697
Short name	T785
Test name
Test status
Simulation time	374385317 ps
CPU time	4.62 seconds
Started	Sep 18 09:30:31 AM UTC 24
Finished	Sep 18 09:30:37 AM UTC 24
Peak memory	222356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807754697 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.2807754697
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1092122854
Short name	T782
Test name
Test status
Simulation time	449517331 ps
CPU time	13.58 seconds
Started	Sep 18 09:30:15 AM UTC 24
Finished	Sep 18 09:30:29 AM UTC 24
Peak memory	222172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092122854 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.1092122854
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.62947304
Short name	T864
Test name
Test status
Simulation time	80486491786 ps
CPU time	501.72 seconds
Started	Sep 18 09:28:40 AM UTC 24
Finished	Sep 18 09:37:08 AM UTC 24
Peak memory	379052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62947304 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.62947304
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1151680047
Short name	T787
Test name
Test status
Simulation time	421384498 ps
CPU time	90.82 seconds
Started	Sep 18 09:29:10 AM UTC 24
Finished	Sep 18 09:30:43 AM UTC 24
Peak memory	378712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151680047 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.1151680047
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.537553566
Short name	T877
Test name
Test status
Simulation time	24530764717 ps
CPU time	519.63 seconds
Started	Sep 18 09:29:12 AM UTC 24
Finished	Sep 18 09:37:58 AM UTC 24
Peak memory	212180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537553566 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acce ss_b2b.537553566
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3749763905
Short name	T781
Test name
Test status
Simulation time	30170128 ps
CPU time	1.08 seconds
Started	Sep 18 09:30:12 AM UTC 24
Finished	Sep 18 09:30:14 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749763905 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3749763905
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.884797049
Short name	T769
Test name
Test status
Simulation time	33059080 ps
CPU time	2.18 seconds
Started	Sep 18 09:28:36 AM UTC 24
Finished	Sep 18 09:28:39 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884797049 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.884797049
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3702662743
Short name	T924
Test name
Test status
Simulation time	89867357661 ps
CPU time	1779.67 seconds
Started	Sep 18 09:30:34 AM UTC 24
Finished	Sep 18 10:00:35 AM UTC 24
Peak memory	385112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370266274 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.3702662743
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1940691221
Short name	T826
Test name
Test status
Simulation time	10688530551 ps
CPU time	325.47 seconds
Started	Sep 18 09:28:59 AM UTC 24
Finished	Sep 18 09:34:29 AM UTC 24
Peak memory	212064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940691221 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1940691221
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.4183029912
Short name	T780
Test name
Test status
Simulation time	395196918 ps
CPU time	30.4 seconds
Started	Sep 18 09:29:39 AM UTC 24
Finished	Sep 18 09:30:11 AM UTC 24
Peak memory	303024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4183029912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t hroughput_w_partial_write.4183029912
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2481935133
Short name	T900
Test name
Test status
Simulation time	3398665147 ps
CPU time	698.58 seconds
Started	Sep 18 09:31:59 AM UTC 24
Finished	Sep 18 09:43:45 AM UTC 24
Peak memory	378764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481935133 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during _key_req.2481935133
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2929538758
Short name	T804
Test name
Test status
Simulation time	18533030 ps
CPU time	0.97 seconds
Started	Sep 18 09:32:41 AM UTC 24
Finished	Sep 18 09:32:43 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929538758 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2929538758
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3742907208
Short name	T805
Test name
Test status
Simulation time	13845368429 ps
CPU time	89.93 seconds
Started	Sep 18 09:31:15 AM UTC 24
Finished	Sep 18 09:32:47 AM UTC 24
Peak memory	212064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742907208 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.3742907208
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.2314268961
Short name	T837
Test name
Test status
Simulation time	10791537194 ps
CPU time	188.75 seconds
Started	Sep 18 09:32:04 AM UTC 24
Finished	Sep 18 09:35:15 AM UTC 24
Peak memory	372704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314268961 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.2314268961
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.542485284
Short name	T796
Test name
Test status
Simulation time	345463368 ps
CPU time	6.8 seconds
Started	Sep 18 09:31:56 AM UTC 24
Finished	Sep 18 09:32:04 AM UTC 24
Peak memory	222176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542485284 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.542485284
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1136736922
Short name	T806
Test name
Test status
Simulation time	126698382 ps
CPU time	74.11 seconds
Started	Sep 18 09:31:31 AM UTC 24
Finished	Sep 18 09:32:47 AM UTC 24
Peak memory	370524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 136736922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ma x_throughput.1136736922
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3913587118
Short name	T803
Test name
Test status
Simulation time	181303206 ps
CPU time	6.29 seconds
Started	Sep 18 09:32:34 AM UTC 24
Finished	Sep 18 09:32:41 AM UTC 24
Peak memory	222176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913587118 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.3913587118
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2438837570
Short name	T800
Test name
Test status
Simulation time	1337900896 ps
CPU time	9.14 seconds
Started	Sep 18 09:32:24 AM UTC 24
Finished	Sep 18 09:32:34 AM UTC 24
Peak memory	222428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438837570 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2438837570
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.4003078841
Short name	T845
Test name
Test status
Simulation time	5315934443 ps
CPU time	317.85 seconds
Started	Sep 18 09:30:43 AM UTC 24
Finished	Sep 18 09:36:06 AM UTC 24
Peak memory	335840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003078841 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.4003078841
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2826039364
Short name	T810
Test name
Test status
Simulation time	2675961025 ps
CPU time	115.52 seconds
Started	Sep 18 09:31:21 AM UTC 24
Finished	Sep 18 09:33:19 AM UTC 24
Peak memory	376788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826039364 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.2826039364
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1342810497
Short name	T866
Test name
Test status
Simulation time	14922291485 ps
CPU time	341.77 seconds
Started	Sep 18 09:31:25 AM UTC 24
Finished	Sep 18 09:37:12 AM UTC 24
Peak memory	211980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342810497 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acc ess_b2b.1342810497
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2160158172
Short name	T798
Test name
Test status
Simulation time	27947903 ps
CPU time	0.98 seconds
Started	Sep 18 09:32:20 AM UTC 24
Finished	Sep 18 09:32:23 AM UTC 24
Peak memory	211088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160158172 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2160158172
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3299224136
Short name	T904
Test name
Test status
Simulation time	66027976742 ps
CPU time	833.82 seconds
Started	Sep 18 09:32:05 AM UTC 24
Finished	Sep 18 09:46:08 AM UTC 24
Peak memory	382956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299224136 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3299224136
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.4220939440
Short name	T801
Test name
Test status
Simulation time	305819002 ps
CPU time	116.47 seconds
Started	Sep 18 09:30:40 AM UTC 24
Finished	Sep 18 09:32:39 AM UTC 24
Peak memory	376936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220939440 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.4220939440
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3328888098
Short name	T936
Test name
Test status
Simulation time	559551487489 ps
CPU time	4797.36 seconds
Started	Sep 18 09:32:39 AM UTC 24
Finished	Sep 18 10:53:28 AM UTC 24
Peak memory	386696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332888809 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.3328888098
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2273965057
Short name	T835
Test name
Test status
Simulation time	30385954659 ps
CPU time	230.43 seconds
Started	Sep 18 09:31:15 AM UTC 24
Finished	Sep 18 09:35:09 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273965057 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.2273965057
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.217609287
Short name	T794
Test name
Test status
Simulation time	267116396 ps
CPU time	10.74 seconds
Started	Sep 18 09:31:46 AM UTC 24
Finished	Sep 18 09:31:58 AM UTC 24
Peak memory	262180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 217609287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_th roughput_w_partial_write.217609287
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3361381098
Short name	T901
Test name
Test status
Simulation time	3351014110 ps
CPU time	655.57 seconds
Started	Sep 18 09:33:35 AM UTC 24
Finished	Sep 18 09:44:38 AM UTC 24
Peak memory	382868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361381098 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during _key_req.3361381098
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2861634931
Short name	T822
Test name
Test status
Simulation time	69076952 ps
CPU time	1.02 seconds
Started	Sep 18 09:34:02 AM UTC 24
Finished	Sep 18 09:34:03 AM UTC 24
Peak memory	210988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861634931 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2861634931
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.4022907565
Short name	T818
Test name
Test status
Simulation time	6057912793 ps
CPU time	64.42 seconds
Started	Sep 18 09:32:48 AM UTC 24
Finished	Sep 18 09:33:54 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022907565 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.4022907565
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.538416429
Short name	T891
Test name
Test status
Simulation time	4329078522 ps
CPU time	417.37 seconds
Started	Sep 18 09:33:36 AM UTC 24
Finished	Sep 18 09:40:38 AM UTC 24
Peak memory	366768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538416429 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.538416429
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2133077926
Short name	T812
Test name
Test status
Simulation time	311688819 ps
CPU time	5.81 seconds
Started	Sep 18 09:33:27 AM UTC 24
Finished	Sep 18 09:33:33 AM UTC 24
Peak memory	212136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133077926 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.2133077926
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3374296970
Short name	T816
Test name
Test status
Simulation time	96788845 ps
CPU time	31.49 seconds
Started	Sep 18 09:33:19 AM UTC 24
Finished	Sep 18 09:33:52 AM UTC 24
Peak memory	300900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 374296970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ma x_throughput.3374296970
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2561810230
Short name	T821
Test name
Test status
Simulation time	174891530 ps
CPU time	6.73 seconds
Started	Sep 18 09:33:54 AM UTC 24
Finished	Sep 18 09:34:02 AM UTC 24
Peak memory	222224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561810230 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.2561810230
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4207878581
Short name	T820
Test name
Test status
Simulation time	189342203 ps
CPU time	6.59 seconds
Started	Sep 18 09:33:53 AM UTC 24
Finished	Sep 18 09:34:01 AM UTC 24
Peak memory	222312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207878581 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.4207878581
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.706536837
Short name	T921
Test name
Test status
Simulation time	78217840331 ps
CPU time	1469.86 seconds
Started	Sep 18 09:32:45 AM UTC 24
Finished	Sep 18 09:57:32 AM UTC 24
Peak memory	382960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706536837 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.706536837
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.910282345
Short name	T809
Test name
Test status
Simulation time	2897769854 ps
CPU time	18.02 seconds
Started	Sep 18 09:32:59 AM UTC 24
Finished	Sep 18 09:33:18 AM UTC 24
Peak memory	212188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910282345 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.910282345
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3186364778
Short name	T880
Test name
Test status
Simulation time	67796166354 ps
CPU time	305.17 seconds
Started	Sep 18 09:33:06 AM UTC 24
Finished	Sep 18 09:38:16 AM UTC 24
Peak memory	212060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186364778 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc ess_b2b.3186364778
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.102434298
Short name	T817
Test name
Test status
Simulation time	48743552 ps
CPU time	1.22 seconds
Started	Sep 18 09:33:51 AM UTC 24
Finished	Sep 18 09:33:53 AM UTC 24
Peak memory	210636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102434298 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.102434298
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.1177474887
Short name	T920
Test name
Test status
Simulation time	24518111229 ps
CPU time	1200.87 seconds
Started	Sep 18 09:33:42 AM UTC 24
Finished	Sep 18 09:53:57 AM UTC 24
Peak memory	385160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177474887 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1177474887
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.957988809
Short name	T808
Test name
Test status
Simulation time	2950920205 ps
CPU time	21.47 seconds
Started	Sep 18 09:32:43 AM UTC 24
Finished	Sep 18 09:33:05 AM UTC 24
Peak memory	212184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957988809 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.957988809
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3592815867
Short name	T932
Test name
Test status
Simulation time	111809495287 ps
CPU time	2372.7 seconds
Started	Sep 18 09:33:56 AM UTC 24
Finished	Sep 18 10:13:56 AM UTC 24
Peak memory	386612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359281586 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.3592815867
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3694584424
Short name	T861
Test name
Test status
Simulation time	745595710 ps
CPU time	176.41 seconds
Started	Sep 18 09:33:54 AM UTC 24
Finished	Sep 18 09:36:53 AM UTC 24
Peak memory	350188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694584424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3694584424
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.778162456
Short name	T857
Test name
Test status
Simulation time	2072485388 ps
CPU time	234.26 seconds
Started	Sep 18 09:32:48 AM UTC 24
Finished	Sep 18 09:36:46 AM UTC 24
Peak memory	211952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778162456 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.778162456
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3188199581
Short name	T819
Test name
Test status
Simulation time	226531280 ps
CPU time	34.71 seconds
Started	Sep 18 09:33:19 AM UTC 24
Finished	Sep 18 09:33:55 AM UTC 24
Peak memory	319528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3188199581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t hroughput_w_partial_write.3188199581
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.70594145
Short name	T913
Test name
Test status
Simulation time	7199014753 ps
CPU time	832.55 seconds
Started	Sep 18 09:34:48 AM UTC 24
Finished	Sep 18 09:48:50 AM UTC 24
Peak memory	384928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70594145 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during_k ey_req.70594145
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.784224116
Short name	T838
Test name
Test status
Simulation time	36983114 ps
CPU time	0.91 seconds
Started	Sep 18 09:35:15 AM UTC 24
Finished	Sep 18 09:35:17 AM UTC 24
Peak memory	211064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784224116 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.784224116
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3280001033
Short name	T843
Test name
Test status
Simulation time	3748222612 ps
CPU time	81.51 seconds
Started	Sep 18 09:34:17 AM UTC 24
Finished	Sep 18 09:35:40 AM UTC 24
Peak memory	212132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280001033 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.3280001033
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.210010975
Short name	T917
Test name
Test status
Simulation time	4620308065 ps
CPU time	966.89 seconds
Started	Sep 18 09:34:53 AM UTC 24
Finished	Sep 18 09:51:10 AM UTC 24
Peak memory	384988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210010975 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.210010975
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2158996740
Short name	T830
Test name
Test status
Simulation time	1180447901 ps
CPU time	6.92 seconds
Started	Sep 18 09:34:47 AM UTC 24
Finished	Sep 18 09:34:55 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158996740 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.2158996740
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.710736479
Short name	T841
Test name
Test status
Simulation time	425070622 ps
CPU time	51.03 seconds
Started	Sep 18 09:34:37 AM UTC 24
Finished	Sep 18 09:35:30 AM UTC 24
Peak memory	344096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 10736479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_max _throughput.710736479
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.192919443
Short name	T834
Test name
Test status
Simulation time	1191219335 ps
CPU time	3.85 seconds
Started	Sep 18 09:34:59 AM UTC 24
Finished	Sep 18 09:35:04 AM UTC 24
Peak memory	222388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192919443 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.192919443
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.4211443761
Short name	T836
Test name
Test status
Simulation time	901956037 ps
CPU time	14.57 seconds
Started	Sep 18 09:34:58 AM UTC 24
Finished	Sep 18 09:35:14 AM UTC 24
Peak memory	222244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211443761 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.4211443761
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.4060571959
Short name	T897
Test name
Test status
Simulation time	43233593608 ps
CPU time	519.15 seconds
Started	Sep 18 09:34:05 AM UTC 24
Finished	Sep 18 09:42:50 AM UTC 24
Peak memory	372612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060571959 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.4060571959
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2028661008
Short name	T828
Test name
Test status
Simulation time	753112760 ps
CPU time	19.28 seconds
Started	Sep 18 09:34:25 AM UTC 24
Finished	Sep 18 09:34:46 AM UTC 24
Peak memory	211928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028661008 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2028661008
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.227584729
Short name	T884
Test name
Test status
Simulation time	7031769415 ps
CPU time	305 seconds
Started	Sep 18 09:34:29 AM UTC 24
Finished	Sep 18 09:39:39 AM UTC 24
Peak memory	212180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227584729 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acce ss_b2b.227584729
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2991916286
Short name	T833
Test name
Test status
Simulation time	81055138 ps
CPU time	1.14 seconds
Started	Sep 18 09:34:56 AM UTC 24
Finished	Sep 18 09:34:58 AM UTC 24
Peak memory	210640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991916286 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2991916286
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.336818378
Short name	T903
Test name
Test status
Simulation time	103379284439 ps
CPU time	653.53 seconds
Started	Sep 18 09:34:55 AM UTC 24
Finished	Sep 18 09:45:56 AM UTC 24
Peak memory	383068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336818378 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.336818378
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.4032552372
Short name	T824
Test name
Test status
Simulation time	928126024 ps
CPU time	17.08 seconds
Started	Sep 18 09:34:03 AM UTC 24
Finished	Sep 18 09:34:21 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032552372 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.4032552372
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.4256213960
Short name	T923
Test name
Test status
Simulation time	123106492843 ps
CPU time	1493.6 seconds
Started	Sep 18 09:35:10 AM UTC 24
Finished	Sep 18 10:00:20 AM UTC 24
Peak memory	380824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425621396 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.4256213960
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3245747871
Short name	T839
Test name
Test status
Simulation time	1770598621 ps
CPU time	16.87 seconds
Started	Sep 18 09:35:05 AM UTC 24
Finished	Sep 18 09:35:23 AM UTC 24
Peak memory	229256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245747871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3245747871
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1377774473
Short name	T875
Test name
Test status
Simulation time	17777128500 ps
CPU time	201.88 seconds
Started	Sep 18 09:34:22 AM UTC 24
Finished	Sep 18 09:37:47 AM UTC 24
Peak memory	212008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377774473 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.1377774473
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3345616581
Short name	T852
Test name
Test status
Simulation time	297392215 ps
CPU time	107.95 seconds
Started	Sep 18 09:34:43 AM UTC 24
Finished	Sep 18 09:36:33 AM UTC 24
Peak memory	378720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3345616581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t hroughput_w_partial_write.3345616581
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1697459894
Short name	T912
Test name
Test status
Simulation time	2736046293 ps
CPU time	725.56 seconds
Started	Sep 18 09:36:18 AM UTC 24
Finished	Sep 18 09:48:32 AM UTC 24
Peak memory	382956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697459894 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during _key_req.1697459894
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3334151642
Short name	T855
Test name
Test status
Simulation time	34742493 ps
CPU time	1.02 seconds
Started	Sep 18 09:36:38 AM UTC 24
Finished	Sep 18 09:36:40 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334151642 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3334151642
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.3664375568
Short name	T847
Test name
Test status
Simulation time	641513053 ps
CPU time	52.61 seconds
Started	Sep 18 09:35:24 AM UTC 24
Finished	Sep 18 09:36:18 AM UTC 24
Peak memory	212216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664375568 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.3664375568
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.2832627950
Short name	T918
Test name
Test status
Simulation time	14152857718 ps
CPU time	933.72 seconds
Started	Sep 18 09:36:19 AM UTC 24
Finished	Sep 18 09:52:04 AM UTC 24
Peak memory	383084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832627950 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.2832627950
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.437744576
Short name	T848
Test name
Test status
Simulation time	906243637 ps
CPU time	12.53 seconds
Started	Sep 18 09:36:07 AM UTC 24
Finished	Sep 18 09:36:20 AM UTC 24
Peak memory	222184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437744576 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.437744576
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.275788880
Short name	T851
Test name
Test status
Simulation time	508408546 ps
CPU time	44.84 seconds
Started	Sep 18 09:35:42 AM UTC 24
Finished	Sep 18 09:36:28 AM UTC 24
Peak memory	321584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 75788880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max _throughput.275788880
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2527389682
Short name	T853
Test name
Test status
Simulation time	240970363 ps
CPU time	6.18 seconds
Started	Sep 18 09:36:29 AM UTC 24
Finished	Sep 18 09:36:36 AM UTC 24
Peak memory	222252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527389682 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2527389682
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3733450849
Short name	T858
Test name
Test status
Simulation time	2384229680 ps
CPU time	16.21 seconds
Started	Sep 18 09:36:28 AM UTC 24
Finished	Sep 18 09:36:46 AM UTC 24
Peak memory	212084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733450849 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.3733450849
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1426402567
Short name	T894
Test name
Test status
Simulation time	20301445537 ps
CPU time	408.88 seconds
Started	Sep 18 09:35:18 AM UTC 24
Finished	Sep 18 09:42:12 AM UTC 24
Peak memory	384996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426402567 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.1426402567
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.4106685791
Short name	T842
Test name
Test status
Simulation time	231535395 ps
CPU time	2.79 seconds
Started	Sep 18 09:35:30 AM UTC 24
Finished	Sep 18 09:35:34 AM UTC 24
Peak memory	211920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106685791 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.4106685791
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2270823980
Short name	T899
Test name
Test status
Simulation time	17060381819 ps
CPU time	472.34 seconds
Started	Sep 18 09:35:35 AM UTC 24
Finished	Sep 18 09:43:35 AM UTC 24
Peak memory	211984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270823980 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc ess_b2b.2270823980
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2245063168
Short name	T850
Test name
Test status
Simulation time	81427552 ps
CPU time	1.09 seconds
Started	Sep 18 09:36:25 AM UTC 24
Finished	Sep 18 09:36:27 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245063168 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2245063168
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.2128315785
Short name	T910
Test name
Test status
Simulation time	11212235492 ps
CPU time	689.32 seconds
Started	Sep 18 09:36:21 AM UTC 24
Finished	Sep 18 09:47:59 AM UTC 24
Peak memory	382864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128315785 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2128315785
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.1946985704
Short name	T840
Test name
Test status
Simulation time	456080990 ps
CPU time	10.75 seconds
Started	Sep 18 09:35:16 AM UTC 24
Finished	Sep 18 09:35:28 AM UTC 24
Peak memory	251936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946985704 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1946985704
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.766022453
Short name	T930
Test name
Test status
Simulation time	32632692030 ps
CPU time	1859.41 seconds
Started	Sep 18 09:36:37 AM UTC 24
Finished	Sep 18 10:07:58 AM UTC 24
Peak memory	385160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766022453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.766022453
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1164712892
Short name	T860
Test name
Test status
Simulation time	328494061 ps
CPU time	16.15 seconds
Started	Sep 18 09:36:35 AM UTC 24
Finished	Sep 18 09:36:52 AM UTC 24
Peak memory	222316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164712892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1164712892
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1788741721
Short name	T893
Test name
Test status
Simulation time	10614636068 ps
CPU time	335.1 seconds
Started	Sep 18 09:35:29 AM UTC 24
Finished	Sep 18 09:41:09 AM UTC 24
Peak memory	212080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788741721 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.1788741721
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.616219359
Short name	T856
Test name
Test status
Simulation time	146928800 ps
CPU time	58.02 seconds
Started	Sep 18 09:35:45 AM UTC 24
Finished	Sep 18 09:36:44 AM UTC 24
Peak memory	341924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 616219359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_th roughput_w_partial_write.616219359
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.283455994
Short name	T907
Test name
Test status
Simulation time	13038286872 ps
CPU time	606.32 seconds
Started	Sep 18 09:37:09 AM UTC 24
Finished	Sep 18 09:47:23 AM UTC 24
Peak memory	380820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283455994 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during_ key_req.283455994
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.737023645
Short name	T874
Test name
Test status
Simulation time	14780087 ps
CPU time	1.05 seconds
Started	Sep 18 09:37:42 AM UTC 24
Finished	Sep 18 09:37:44 AM UTC 24
Peak memory	210816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737023645 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.737023645
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.1924318173
Short name	T876
Test name
Test status
Simulation time	819690013 ps
CPU time	60.14 seconds
Started	Sep 18 09:36:46 AM UTC 24
Finished	Sep 18 09:37:48 AM UTC 24
Peak memory	212000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924318173 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.1924318173
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1920239485
Short name	T905
Test name
Test status
Simulation time	40348628173 ps
CPU time	585.61 seconds
Started	Sep 18 09:37:09 AM UTC 24
Finished	Sep 18 09:47:02 AM UTC 24
Peak memory	352236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920239485 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1920239485
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.603157197
Short name	T867
Test name
Test status
Simulation time	830252492 ps
CPU time	9.3 seconds
Started	Sep 18 09:37:09 AM UTC 24
Finished	Sep 18 09:37:20 AM UTC 24
Peak memory	222168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603157197 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.603157197
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.4163905048
Short name	T869
Test name
Test status
Simulation time	373179639 ps
CPU time	39.35 seconds
Started	Sep 18 09:36:55 AM UTC 24
Finished	Sep 18 09:37:35 AM UTC 24
Peak memory	303024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 163905048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma x_throughput.4163905048
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4026053379
Short name	T872
Test name
Test status
Simulation time	53153627 ps
CPU time	3.32 seconds
Started	Sep 18 09:37:37 AM UTC 24
Finished	Sep 18 09:37:41 AM UTC 24
Peak memory	222236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026053379 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.4026053379
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.671007225
Short name	T873
Test name
Test status
Simulation time	663314649 ps
CPU time	16.5 seconds
Started	Sep 18 09:37:23 AM UTC 24
Finished	Sep 18 09:37:41 AM UTC 24
Peak memory	222224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671007225 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.671007225
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2890181489
Short name	T898
Test name
Test status
Simulation time	5474691089 ps
CPU time	365.7 seconds
Started	Sep 18 09:36:45 AM UTC 24
Finished	Sep 18 09:42:56 AM UTC 24
Peak memory	374752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890181489 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.2890181489
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2843936379
Short name	T865
Test name
Test status
Simulation time	482855833 ps
CPU time	15.73 seconds
Started	Sep 18 09:36:51 AM UTC 24
Finished	Sep 18 09:37:08 AM UTC 24
Peak memory	211936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843936379 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.2843936379
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.172086572
Short name	T886
Test name
Test status
Simulation time	14614823464 ps
CPU time	186.57 seconds
Started	Sep 18 09:36:53 AM UTC 24
Finished	Sep 18 09:40:02 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172086572 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acce ss_b2b.172086572
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3468812744
Short name	T868
Test name
Test status
Simulation time	46548765 ps
CPU time	1.15 seconds
Started	Sep 18 09:37:20 AM UTC 24
Finished	Sep 18 09:37:23 AM UTC 24
Peak memory	210704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468812744 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3468812744
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.3959150858
Short name	T916
Test name
Test status
Simulation time	61419163751 ps
CPU time	782.4 seconds
Started	Sep 18 09:37:12 AM UTC 24
Finished	Sep 18 09:50:24 AM UTC 24
Peak memory	385008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959150858 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3959150858
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.1569527774
Short name	T859
Test name
Test status
Simulation time	503008997 ps
CPU time	8.82 seconds
Started	Sep 18 09:36:41 AM UTC 24
Finished	Sep 18 09:36:51 AM UTC 24
Peak memory	211868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569527774 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1569527774
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3356852132
Short name	T922
Test name
Test status
Simulation time	24220458310 ps
CPU time	1337.02 seconds
Started	Sep 18 09:37:40 AM UTC 24
Finished	Sep 18 10:00:14 AM UTC 24
Peak memory	382880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335685213 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.3356852132
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.601687120
Short name	T878
Test name
Test status
Simulation time	563607390 ps
CPU time	22.15 seconds
Started	Sep 18 09:37:39 AM UTC 24
Finished	Sep 18 09:38:02 AM UTC 24
Peak memory	222452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601687120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.601687120
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3951273979
Short name	T882
Test name
Test status
Simulation time	1077479300 ps
CPU time	104.01 seconds
Started	Sep 18 09:36:47 AM UTC 24
Finished	Sep 18 09:38:33 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951273979 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.3951273979
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3458809335
Short name	T871
Test name
Test status
Simulation time	130147955 ps
CPU time	39.9 seconds
Started	Sep 18 09:36:58 AM UTC 24
Finished	Sep 18 09:37:39 AM UTC 24
Peak memory	341856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3458809335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t hroughput_w_partial_write.3458809335
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3739665353
Short name	T236
Test name
Test status
Simulation time	2401078783 ps
CPU time	660.98 seconds
Started	Sep 18 08:27:00 AM UTC 24
Finished	Sep 18 08:38:09 AM UTC 24
Peak memory	384984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739665353 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_ key_req.3739665353
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3735511079
Short name	T116
Test name
Test status
Simulation time	14591879 ps
CPU time	1.03 seconds
Started	Sep 18 08:27:17 AM UTC 24
Finished	Sep 18 08:27:19 AM UTC 24
Peak memory	210644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735511079 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3735511079
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.3981043659
Short name	T163
Test name
Test status
Simulation time	2629116774 ps
CPU time	79.72 seconds
Started	Sep 18 08:26:37 AM UTC 24
Finished	Sep 18 08:27:58 AM UTC 24
Peak memory	212180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981043659 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.3981043659
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.3748980061
Short name	T132
Test name
Test status
Simulation time	600077309 ps
CPU time	105.11 seconds
Started	Sep 18 08:27:02 AM UTC 24
Finished	Sep 18 08:28:49 AM UTC 24
Peak memory	354192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748980061 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.3748980061
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1351856088
Short name	T23
Test name
Test status
Simulation time	458296202 ps
CPU time	8.54 seconds
Started	Sep 18 08:26:57 AM UTC 24
Finished	Sep 18 08:27:07 AM UTC 24
Peak memory	226284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351856088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.1351856088
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3592909935
Short name	T114
Test name
Test status
Simulation time	88871871 ps
CPU time	25.19 seconds
Started	Sep 18 08:26:44 AM UTC 24
Finished	Sep 18 08:27:11 AM UTC 24
Peak memory	298924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 592909935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max _throughput.3592909935
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1485316657
Short name	T49
Test name
Test status
Simulation time	67797899 ps
CPU time	3.86 seconds
Started	Sep 18 08:27:12 AM UTC 24
Finished	Sep 18 08:27:16 AM UTC 24
Peak memory	222180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485316657 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1485316657
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3299496081
Short name	T50
Test name
Test status
Simulation time	1542372863 ps
CPU time	10.17 seconds
Started	Sep 18 08:27:09 AM UTC 24
Finished	Sep 18 08:27:20 AM UTC 24
Peak memory	222248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299496081 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.3299496081
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1014024401
Short name	T168
Test name
Test status
Simulation time	2434593710 ps
CPU time	164.49 seconds
Started	Sep 18 08:26:37 AM UTC 24
Finished	Sep 18 08:29:24 AM UTC 24
Peak memory	360592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014024401 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.1014024401
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1816436190
Short name	T153
Test name
Test status
Simulation time	1797816413 ps
CPU time	14.04 seconds
Started	Sep 18 08:26:40 AM UTC 24
Finished	Sep 18 08:26:55 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816436190 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.1816436190
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.528000955
Short name	T217
Test name
Test status
Simulation time	73441883528 ps
CPU time	488.51 seconds
Started	Sep 18 08:26:40 AM UTC 24
Finished	Sep 18 08:34:55 AM UTC 24
Peak memory	212140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528000955 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acces s_b2b.528000955
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3464429218
Short name	T113
Test name
Test status
Simulation time	30650385 ps
CPU time	0.9 seconds
Started	Sep 18 08:27:08 AM UTC 24
Finished	Sep 18 08:27:10 AM UTC 24
Peak memory	210632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464429218 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3464429218
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2400212848
Short name	T130
Test name
Test status
Simulation time	4890058837 ps
CPU time	157.07 seconds
Started	Sep 18 08:27:04 AM UTC 24
Finished	Sep 18 08:29:44 AM UTC 24
Peak memory	309140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400212848 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2400212848
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3227819235
Short name	T115
Test name
Test status
Simulation time	2828117210 ps
CPU time	34.19 seconds
Started	Sep 18 08:26:36 AM UTC 24
Finished	Sep 18 08:27:11 AM UTC 24
Peak memory	296856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227819235 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3227819235
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.547705402
Short name	T173
Test name
Test status
Simulation time	18547304632 ps
CPU time	166.25 seconds
Started	Sep 18 08:27:13 AM UTC 24
Finished	Sep 18 08:30:02 AM UTC 24
Peak memory	309232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547705402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.547705402
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3384889590
Short name	T66
Test name
Test status
Simulation time	10033543990 ps
CPU time	809.7 seconds
Started	Sep 18 08:27:13 AM UTC 24
Finished	Sep 18 08:40:51 AM UTC 24
Peak memory	389096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384889590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3384889590
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3215121577
Short name	T186
Test name
Test status
Simulation time	10112303012 ps
CPU time	295.83 seconds
Started	Sep 18 08:26:40 AM UTC 24
Finished	Sep 18 08:31:40 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215121577 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.3215121577
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2630613252
Short name	T112
Test name
Test status
Simulation time	163056570 ps
CPU time	5.72 seconds
Started	Sep 18 08:26:56 AM UTC 24
Finished	Sep 18 08:27:03 AM UTC 24
Peak memory	231328 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2630613252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th roughput_w_partial_write.2630613252
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2424970037
Short name	T255
Test name
Test status
Simulation time	9582584819 ps
CPU time	764.71 seconds
Started	Sep 18 08:28:11 AM UTC 24
Finished	Sep 18 08:41:04 AM UTC 24
Peak memory	374688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424970037 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_ key_req.2424970037
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2390798686
Short name	T151
Test name
Test status
Simulation time	78995832 ps
CPU time	0.94 seconds
Started	Sep 18 08:28:48 AM UTC 24
Finished	Sep 18 08:28:51 AM UTC 24
Peak memory	210648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390798686 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.2390798686
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1516374910
Short name	T170
Test name
Test status
Simulation time	10231967806 ps
CPU time	129.73 seconds
Started	Sep 18 08:27:33 AM UTC 24
Finished	Sep 18 08:29:45 AM UTC 24
Peak memory	211932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516374910 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.1516374910
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.3224403353
Short name	T148
Test name
Test status
Simulation time	16761334176 ps
CPU time	865.74 seconds
Started	Sep 18 08:28:14 AM UTC 24
Finished	Sep 18 08:42:49 AM UTC 24
Peak memory	383072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224403353 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.3224403353
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2607777067
Short name	T117
Test name
Test status
Simulation time	536418231 ps
CPU time	5.58 seconds
Started	Sep 18 08:28:11 AM UTC 24
Finished	Sep 18 08:28:17 AM UTC 24
Peak memory	212072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607777067 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2607777067
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3292838037
Short name	T165
Test name
Test status
Simulation time	74879082 ps
CPU time	12.09 seconds
Started	Sep 18 08:28:00 AM UTC 24
Finished	Sep 18 08:28:13 AM UTC 24
Peak memory	247652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 292838037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max _throughput.3292838037
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.639827518
Short name	T51
Test name
Test status
Simulation time	1246307617 ps
CPU time	5.64 seconds
Started	Sep 18 08:28:37 AM UTC 24
Finished	Sep 18 08:28:44 AM UTC 24
Peak memory	222372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639827518 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.639827518
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1430127283
Short name	T166
Test name
Test status
Simulation time	534947539 ps
CPU time	6.14 seconds
Started	Sep 18 08:28:29 AM UTC 24
Finished	Sep 18 08:28:36 AM UTC 24
Peak memory	222244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430127283 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.1430127283
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3033128776
Short name	T188
Test name
Test status
Simulation time	14535574141 ps
CPU time	262.73 seconds
Started	Sep 18 08:27:21 AM UTC 24
Finished	Sep 18 08:31:48 AM UTC 24
Peak memory	384992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033128776 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.3033128776
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3739420279
Short name	T164
Test name
Test status
Simulation time	263768956 ps
CPU time	20.01 seconds
Started	Sep 18 08:27:43 AM UTC 24
Finished	Sep 18 08:28:04 AM UTC 24
Peak memory	212148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739420279 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.3739420279
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1236807188
Short name	T196
Test name
Test status
Simulation time	16370679240 ps
CPU time	324.86 seconds
Started	Sep 18 08:27:49 AM UTC 24
Finished	Sep 18 08:33:19 AM UTC 24
Peak memory	212204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236807188 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce ss_b2b.1236807188
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3959867822
Short name	T155
Test name
Test status
Simulation time	48655944 ps
CPU time	1.27 seconds
Started	Sep 18 08:28:26 AM UTC 24
Finished	Sep 18 08:28:28 AM UTC 24
Peak memory	210632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959867822 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3959867822
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.862245834
Short name	T410
Test name
Test status
Simulation time	100218196897 ps
CPU time	1692.96 seconds
Started	Sep 18 08:28:18 AM UTC 24
Finished	Sep 18 08:56:48 AM UTC 24
Peak memory	384988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862245834 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.862245834
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1742245503
Short name	T154
Test name
Test status
Simulation time	585185244 ps
CPU time	10.52 seconds
Started	Sep 18 08:27:21 AM UTC 24
Finished	Sep 18 08:27:33 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742245503 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1742245503
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3986336928
Short name	T870
Test name
Test status
Simulation time	47238242324 ps
CPU time	4091.28 seconds
Started	Sep 18 08:28:45 AM UTC 24
Finished	Sep 18 09:37:38 AM UTC 24
Peak memory	386608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398633692 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.3986336928
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.812977781
Short name	T20
Test name
Test status
Simulation time	1952878355 ps
CPU time	39.04 seconds
Started	Sep 18 08:28:40 AM UTC 24
Finished	Sep 18 08:29:21 AM UTC 24
Peak memory	222228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812977781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.812977781
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.451871416
Short name	T216
Test name
Test status
Simulation time	3788686375 ps
CPU time	413.97 seconds
Started	Sep 18 08:27:41 AM UTC 24
Finished	Sep 18 08:34:41 AM UTC 24
Peak memory	211996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451871416 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.451871416
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1075989577
Short name	T150
Test name
Test status
Simulation time	152951865 ps
CPU time	97.04 seconds
Started	Sep 18 08:28:06 AM UTC 24
Finished	Sep 18 08:29:45 AM UTC 24
Peak memory	378788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1075989577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th roughput_w_partial_write.1075989577
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1042419037
Short name	T248
Test name
Test status
Simulation time	3840332286 ps
CPU time	624.12 seconds
Started	Sep 18 08:29:42 AM UTC 24
Finished	Sep 18 08:40:13 AM UTC 24
Peak memory	383144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042419037 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_ key_req.1042419037
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3632764390
Short name	T174
Test name
Test status
Simulation time	12934140 ps
CPU time	1.11 seconds
Started	Sep 18 08:30:00 AM UTC 24
Finished	Sep 18 08:30:02 AM UTC 24
Peak memory	210824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632764390 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3632764390
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.1935074396
Short name	T175
Test name
Test status
Simulation time	3903725176 ps
CPU time	69.1 seconds
Started	Sep 18 08:28:56 AM UTC 24
Finished	Sep 18 08:30:07 AM UTC 24
Peak memory	212048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935074396 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.1935074396
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2728307018
Short name	T328
Test name
Test status
Simulation time	44119376496 ps
CPU time	1112.52 seconds
Started	Sep 18 08:29:44 AM UTC 24
Finished	Sep 18 08:48:30 AM UTC 24
Peak memory	376796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728307018 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2728307018
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4072624124
Short name	T24
Test name
Test status
Simulation time	401417274 ps
CPU time	8.99 seconds
Started	Sep 18 08:29:36 AM UTC 24
Finished	Sep 18 08:29:46 AM UTC 24
Peak memory	212072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072624124 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.4072624124
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.458305350
Short name	T169
Test name
Test status
Simulation time	57615548 ps
CPU time	8.97 seconds
Started	Sep 18 08:29:25 AM UTC 24
Finished	Sep 18 08:29:35 AM UTC 24
Peak memory	247720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 58305350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max_ throughput.458305350
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.800146742
Short name	T89
Test name
Test status
Simulation time	95203018 ps
CPU time	6.38 seconds
Started	Sep 18 08:29:48 AM UTC 24
Finished	Sep 18 08:29:55 AM UTC 24
Peak memory	222396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800146742 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.800146742
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.987813527
Short name	T172
Test name
Test status
Simulation time	522267465 ps
CPU time	11.14 seconds
Started	Sep 18 08:29:47 AM UTC 24
Finished	Sep 18 08:29:59 AM UTC 24
Peak memory	222116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987813527 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.987813527
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2618782902
Short name	T145
Test name
Test status
Simulation time	6632574991 ps
CPU time	320.85 seconds
Started	Sep 18 08:28:52 AM UTC 24
Finished	Sep 18 08:34:17 AM UTC 24
Peak memory	372756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618782902 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.2618782902
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.745720983
Short name	T182
Test name
Test status
Simulation time	2700149970 ps
CPU time	108.97 seconds
Started	Sep 18 08:29:17 AM UTC 24
Finished	Sep 18 08:31:08 AM UTC 24
Peak memory	378776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745720983 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.745720983
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1691121748
Short name	T198
Test name
Test status
Simulation time	6114143634 ps
CPU time	236.36 seconds
Started	Sep 18 08:29:22 AM UTC 24
Finished	Sep 18 08:33:22 AM UTC 24
Peak memory	212196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691121748 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acce ss_b2b.1691121748
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.767037459
Short name	T171
Test name
Test status
Simulation time	76705868 ps
CPU time	1.17 seconds
Started	Sep 18 08:29:47 AM UTC 24
Finished	Sep 18 08:29:49 AM UTC 24
Peak memory	211144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767037459 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.767037459
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.2821821579
Short name	T391
Test name
Test status
Simulation time	8222000599 ps
CPU time	1503.04 seconds
Started	Sep 18 08:29:46 AM UTC 24
Finished	Sep 18 08:55:04 AM UTC 24
Peak memory	385004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821821579 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2821821579
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.3430670630
Short name	T167
Test name
Test status
Simulation time	304455112 ps
CPU time	3.91 seconds
Started	Sep 18 08:28:50 AM UTC 24
Finished	Sep 18 08:28:55 AM UTC 24
Peak memory	211860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430670630 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3430670630
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1410360791
Short name	T134
Test name
Test status
Simulation time	5520211551 ps
CPU time	676 seconds
Started	Sep 18 08:29:56 AM UTC 24
Finished	Sep 18 08:41:19 AM UTC 24
Peak memory	378800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141036079 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.1410360791
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4076790
Short name	T45
Test name
Test status
Simulation time	686156031 ps
CPU time	20.73 seconds
Started	Sep 18 08:29:50 AM UTC 24
Finished	Sep 18 08:30:12 AM UTC 24
Peak memory	222236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.4076790
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.818627123
Short name	T190
Test name
Test status
Simulation time	2079943562 ps
CPU time	199.02 seconds
Started	Sep 18 08:29:01 AM UTC 24
Finished	Sep 18 08:32:23 AM UTC 24
Peak memory	212132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818627123 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.818627123
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1574936874
Short name	T176
Test name
Test status
Simulation time	645894468 ps
CPU time	37.05 seconds
Started	Sep 18 08:29:33 AM UTC 24
Finished	Sep 18 08:30:12 AM UTC 24
Peak memory	327516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1574936874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th roughput_w_partial_write.1574936874
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1291959252
Short name	T40
Test name
Test status
Simulation time	175891856 ps
CPU time	94.73 seconds
Started	Sep 18 08:30:31 AM UTC 24
Finished	Sep 18 08:32:08 AM UTC 24
Peak memory	382756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291959252 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_ key_req.1291959252
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.109647176
Short name	T187
Test name
Test status
Simulation time	14823627 ps
CPU time	0.93 seconds
Started	Sep 18 08:31:41 AM UTC 24
Finished	Sep 18 08:31:43 AM UTC 24
Peak memory	210824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109647176 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.109647176
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2315035868
Short name	T184
Test name
Test status
Simulation time	2055668781 ps
CPU time	65.43 seconds
Started	Sep 18 08:30:07 AM UTC 24
Finished	Sep 18 08:31:15 AM UTC 24
Peak memory	212004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315035868 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.2315035868
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1059393535
Short name	T136
Test name
Test status
Simulation time	39295643158 ps
CPU time	830.67 seconds
Started	Sep 18 08:30:35 AM UTC 24
Finished	Sep 18 08:44:34 AM UTC 24
Peak memory	378772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059393535 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1059393535
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3829157867
Short name	T181
Test name
Test status
Simulation time	617031947 ps
CPU time	7.35 seconds
Started	Sep 18 08:30:26 AM UTC 24
Finished	Sep 18 08:30:34 AM UTC 24
Peak memory	212012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829157867 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.3829157867
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1502788751
Short name	T179
Test name
Test status
Simulation time	73854647 ps
CPU time	2.58 seconds
Started	Sep 18 08:30:22 AM UTC 24
Finished	Sep 18 08:30:25 AM UTC 24
Peak memory	222240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 502788751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max _throughput.1502788751
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.19656514
Short name	T147
Test name
Test status
Simulation time	396300818 ps
CPU time	4.57 seconds
Started	Sep 18 08:31:15 AM UTC 24
Finished	Sep 18 08:31:21 AM UTC 24
Peak memory	222384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19656514 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.19656514
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.769799486
Short name	T185
Test name
Test status
Simulation time	100611310 ps
CPU time	6.74 seconds
Started	Sep 18 08:31:14 AM UTC 24
Finished	Sep 18 08:31:22 AM UTC 24
Peak memory	222180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769799486 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.769799486
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.731176691
Short name	T204
Test name
Test status
Simulation time	2867957070 ps
CPU time	219.78 seconds
Started	Sep 18 08:30:03 AM UTC 24
Finished	Sep 18 08:33:46 AM UTC 24
Peak memory	376732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731176691 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.731176691
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.63939072
Short name	T177
Test name
Test status
Simulation time	144845491 ps
CPU time	7.49 seconds
Started	Sep 18 08:30:12 AM UTC 24
Finished	Sep 18 08:30:21 AM UTC 24
Peak memory	235560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63939072 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.63939072
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.418710986
Short name	T199
Test name
Test status
Simulation time	2358609086 ps
CPU time	188.83 seconds
Started	Sep 18 08:30:12 AM UTC 24
Finished	Sep 18 08:33:25 AM UTC 24
Peak memory	212216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418710986 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acces s_b2b.418710986
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.4271488330
Short name	T183
Test name
Test status
Simulation time	187039685 ps
CPU time	1.31 seconds
Started	Sep 18 08:31:11 AM UTC 24
Finished	Sep 18 08:31:13 AM UTC 24
Peak memory	210632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271488330 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.4271488330
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.367246572
Short name	T284
Test name
Test status
Simulation time	21944341414 ps
CPU time	1021.25 seconds
Started	Sep 18 08:31:09 AM UTC 24
Finished	Sep 18 08:48:21 AM UTC 24
Peak memory	382936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367246572 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.367246572
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2093436625
Short name	T178
Test name
Test status
Simulation time	865970928 ps
CPU time	18.51 seconds
Started	Sep 18 08:30:02 AM UTC 24
Finished	Sep 18 08:30:22 AM UTC 24
Peak memory	212064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093436625 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2093436625
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3857441593
Short name	T575
Test name
Test status
Simulation time	34791005673 ps
CPU time	2378.68 seconds
Started	Sep 18 08:31:23 AM UTC 24
Finished	Sep 18 09:11:25 AM UTC 24
Peak memory	393124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385744159 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.3857441593
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1658284068
Short name	T63
Test name
Test status
Simulation time	1268625928 ps
CPU time	91.5 seconds
Started	Sep 18 08:31:21 AM UTC 24
Finished	Sep 18 08:32:55 AM UTC 24
Peak memory	333712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658284068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1658284068
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1152170558
Short name	T232
Test name
Test status
Simulation time	64864002218 ps
CPU time	439.51 seconds
Started	Sep 18 08:30:07 AM UTC 24
Finished	Sep 18 08:37:33 AM UTC 24
Peak memory	212052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152170558 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.1152170558
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3290415887
Short name	T180
Test name
Test status
Simulation time	236098221 ps
CPU time	6.27 seconds
Started	Sep 18 08:30:23 AM UTC 24
Finished	Sep 18 08:30:30 AM UTC 24
Peak memory	245660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3290415887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th roughput_w_partial_write.3290415887
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1600107753
Short name	T272
Test name
Test status
Simulation time	49270128246 ps
CPU time	600.74 seconds
Started	Sep 18 08:32:43 AM UTC 24
Finished	Sep 18 08:42:50 AM UTC 24
Peak memory	382936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600107753 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_ key_req.1600107753
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1619846552
Short name	T200
Test name
Test status
Simulation time	38195712 ps
CPU time	1.08 seconds
Started	Sep 18 08:33:23 AM UTC 24
Finished	Sep 18 08:33:25 AM UTC 24
Peak memory	210824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619846552 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1619846552
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2234147071
Short name	T205
Test name
Test status
Simulation time	54185092663 ps
CPU time	116.04 seconds
Started	Sep 18 08:31:50 AM UTC 24
Finished	Sep 18 08:33:48 AM UTC 24
Peak memory	211988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234147071 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.2234147071
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.143079936
Short name	T326
Test name
Test status
Simulation time	3826148150 ps
CPU time	909.64 seconds
Started	Sep 18 08:32:56 AM UTC 24
Finished	Sep 18 08:48:15 AM UTC 24
Peak memory	382952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143079936 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.143079936
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2327816940
Short name	T193
Test name
Test status
Simulation time	2772959505 ps
CPU time	12.74 seconds
Started	Sep 18 08:32:43 AM UTC 24
Finished	Sep 18 08:32:56 AM UTC 24
Peak memory	211992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327816940 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2327816940
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2720798964
Short name	T194
Test name
Test status
Simulation time	121140006 ps
CPU time	49.92 seconds
Started	Sep 18 08:32:11 AM UTC 24
Finished	Sep 18 08:33:03 AM UTC 24
Peak memory	321452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 720798964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max _throughput.2720798964
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3803938580
Short name	T53
Test name
Test status
Simulation time	183657496 ps
CPU time	8.36 seconds
Started	Sep 18 08:33:19 AM UTC 24
Finished	Sep 18 08:33:28 AM UTC 24
Peak memory	222188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803938580 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.3803938580
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1176195677
Short name	T197
Test name
Test status
Simulation time	1812445692 ps
CPU time	13.74 seconds
Started	Sep 18 08:33:07 AM UTC 24
Finished	Sep 18 08:33:22 AM UTC 24
Peak memory	222180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176195677 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1176195677
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.336151122
Short name	T343
Test name
Test status
Simulation time	14604342342 ps
CPU time	1086.49 seconds
Started	Sep 18 08:31:49 AM UTC 24
Finished	Sep 18 08:50:07 AM UTC 24
Peak memory	382852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336151122 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.336151122
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2484571010
Short name	T201
Test name
Test status
Simulation time	691853511 ps
CPU time	82.34 seconds
Started	Sep 18 08:32:05 AM UTC 24
Finished	Sep 18 08:33:29 AM UTC 24
Peak memory	360356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484571010 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.2484571010
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2146614112
Short name	T275
Test name
Test status
Simulation time	34245384444 ps
CPU time	636.05 seconds
Started	Sep 18 08:32:09 AM UTC 24
Finished	Sep 18 08:42:54 AM UTC 24
Peak memory	212060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146614112 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acce ss_b2b.2146614112
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3106053712
Short name	T195
Test name
Test status
Simulation time	84545122 ps
CPU time	1.23 seconds
Started	Sep 18 08:33:04 AM UTC 24
Finished	Sep 18 08:33:06 AM UTC 24
Peak memory	211080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106053712 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3106053712
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2144922680
Short name	T345
Test name
Test status
Simulation time	20486352193 ps
CPU time	1031.36 seconds
Started	Sep 18 08:32:57 AM UTC 24
Finished	Sep 18 08:50:20 AM UTC 24
Peak memory	354276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144922680 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2144922680
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1759603513
Short name	T189
Test name
Test status
Simulation time	226224664 ps
CPU time	19.14 seconds
Started	Sep 18 08:31:44 AM UTC 24
Finished	Sep 18 08:32:05 AM UTC 24
Peak memory	211948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759603513 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1759603513
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3310913425
Short name	T488
Test name
Test status
Simulation time	112805059183 ps
CPU time	1817.99 seconds
Started	Sep 18 08:33:23 AM UTC 24
Finished	Sep 18 09:03:59 AM UTC 24
Peak memory	384932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331091342 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.3310913425
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2906340285
Short name	T21
Test name
Test status
Simulation time	1299596531 ps
CPU time	317.82 seconds
Started	Sep 18 08:33:23 AM UTC 24
Finished	Sep 18 08:38:45 AM UTC 24
Peak memory	382872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906340285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.2906340285
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2942880266
Short name	T227
Test name
Test status
Simulation time	3061598836 ps
CPU time	283.77 seconds
Started	Sep 18 08:32:04 AM UTC 24
Finished	Sep 18 08:36:52 AM UTC 24
Peak memory	212188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942880266 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.2942880266
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3930019820
Short name	T191
Test name
Test status
Simulation time	495781438 ps
CPU time	16.13 seconds
Started	Sep 18 08:32:24 AM UTC 24
Finished	Sep 18 08:32:42 AM UTC 24
Peak memory	274240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3930019820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th roughput_w_partial_write.3930019820
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest

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