| T144 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2881891188 |
|
|
Oct 03 11:45:35 AM UTC 24 |
Oct 03 12:04:42 PM UTC 24 |
50302548556 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2291893194 |
|
|
Oct 03 11:57:02 AM UTC 24 |
Oct 03 12:04:48 PM UTC 24 |
28604285528 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.934995725 |
|
|
Oct 03 12:04:42 PM UTC 24 |
Oct 03 12:04:49 PM UTC 24 |
68325445 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1787211302 |
|
|
Oct 03 12:04:50 PM UTC 24 |
Oct 03 12:04:52 PM UTC 24 |
13717521 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3516278162 |
|
|
Oct 03 12:04:40 PM UTC 24 |
Oct 03 12:04:53 PM UTC 24 |
1193538977 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1543945731 |
|
|
Oct 03 12:04:43 PM UTC 24 |
Oct 03 12:04:56 PM UTC 24 |
1145900491 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.2353766171 |
|
|
Oct 03 11:52:06 AM UTC 24 |
Oct 03 12:08:57 PM UTC 24 |
88260558708 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.859258803 |
|
|
Oct 03 11:45:36 AM UTC 24 |
Oct 03 12:05:00 PM UTC 24 |
77884541095 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2016043218 |
|
|
Oct 03 12:05:01 PM UTC 24 |
Oct 03 12:05:14 PM UTC 24 |
534286207 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.2329847378 |
|
|
Oct 03 12:04:53 PM UTC 24 |
Oct 03 12:05:15 PM UTC 24 |
7256268555 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.2783240225 |
|
|
Oct 03 12:04:56 PM UTC 24 |
Oct 03 12:05:20 PM UTC 24 |
388334501 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.397576456 |
|
|
Oct 03 12:00:16 PM UTC 24 |
Oct 03 12:05:22 PM UTC 24 |
25234283969 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1134593922 |
|
|
Oct 03 12:05:16 PM UTC 24 |
Oct 03 12:05:25 PM UTC 24 |
1575970000 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1104726493 |
|
|
Oct 03 12:05:15 PM UTC 24 |
Oct 03 12:05:26 PM UTC 24 |
375509161 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2170344756 |
|
|
Oct 03 12:05:08 PM UTC 24 |
Oct 03 12:05:27 PM UTC 24 |
734191906 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1822998281 |
|
|
Oct 03 12:05:26 PM UTC 24 |
Oct 03 12:05:28 PM UTC 24 |
257053085 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1682888156 |
|
|
Oct 03 12:05:28 PM UTC 24 |
Oct 03 12:05:33 PM UTC 24 |
107232534 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2600305534 |
|
|
Oct 03 11:47:26 AM UTC 24 |
Oct 03 12:05:41 PM UTC 24 |
2998604713 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1555702800 |
|
|
Oct 03 11:49:38 AM UTC 24 |
Oct 03 12:05:43 PM UTC 24 |
10433592948 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3865283670 |
|
|
Oct 03 12:05:27 PM UTC 24 |
Oct 03 12:05:43 PM UTC 24 |
661210405 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1848753850 |
|
|
Oct 03 12:05:42 PM UTC 24 |
Oct 03 12:05:44 PM UTC 24 |
23052966 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1472742582 |
|
|
Oct 03 12:05:29 PM UTC 24 |
Oct 03 12:05:50 PM UTC 24 |
727870228 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2101991689 |
|
|
Oct 03 12:02:15 PM UTC 24 |
Oct 03 12:05:53 PM UTC 24 |
2328450984 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.4248913831 |
|
|
Oct 03 11:58:27 AM UTC 24 |
Oct 03 12:05:56 PM UTC 24 |
13353153219 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.409071634 |
|
|
Oct 03 12:02:19 PM UTC 24 |
Oct 03 12:06:00 PM UTC 24 |
1823803256 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1374549446 |
|
|
Oct 03 12:05:55 PM UTC 24 |
Oct 03 12:06:05 PM UTC 24 |
201059395 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3561945725 |
|
|
Oct 03 12:03:30 PM UTC 24 |
Oct 03 12:06:06 PM UTC 24 |
5801932363 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.526592005 |
|
|
Oct 03 12:06:07 PM UTC 24 |
Oct 03 12:06:10 PM UTC 24 |
306033268 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.119307817 |
|
|
Oct 03 12:06:01 PM UTC 24 |
Oct 03 12:06:11 PM UTC 24 |
195590471 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3083529626 |
|
|
Oct 03 12:05:43 PM UTC 24 |
Oct 03 12:06:12 PM UTC 24 |
4308825055 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.476748604 |
|
|
Oct 03 11:53:20 AM UTC 24 |
Oct 03 12:06:34 PM UTC 24 |
2309482964 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2476665090 |
|
|
Oct 03 12:06:34 PM UTC 24 |
Oct 03 12:06:37 PM UTC 24 |
57706655 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.516822872 |
|
|
Oct 03 12:06:06 PM UTC 24 |
Oct 03 12:06:40 PM UTC 24 |
421710475 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2848696383 |
|
|
Oct 03 11:49:11 AM UTC 24 |
Oct 03 12:06:41 PM UTC 24 |
31241737686 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.1219069729 |
|
|
Oct 03 12:05:44 PM UTC 24 |
Oct 03 12:06:44 PM UTC 24 |
3410934294 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2616709143 |
|
|
Oct 03 12:01:15 PM UTC 24 |
Oct 03 12:06:45 PM UTC 24 |
32696668278 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3865887620 |
|
|
Oct 03 12:06:41 PM UTC 24 |
Oct 03 12:06:46 PM UTC 24 |
142705272 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.4221039272 |
|
|
Oct 03 12:06:46 PM UTC 24 |
Oct 03 12:06:48 PM UTC 24 |
171776932 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.210144303 |
|
|
Oct 03 12:06:39 PM UTC 24 |
Oct 03 12:06:51 PM UTC 24 |
660666743 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.1693879682 |
|
|
Oct 03 11:57:41 AM UTC 24 |
Oct 03 12:06:59 PM UTC 24 |
33850510488 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.887071856 |
|
|
Oct 03 12:06:47 PM UTC 24 |
Oct 03 12:07:00 PM UTC 24 |
293278578 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.4061747305 |
|
|
Oct 03 12:05:43 PM UTC 24 |
Oct 03 12:07:00 PM UTC 24 |
647853399 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.1933132997 |
|
|
Oct 03 11:59:44 AM UTC 24 |
Oct 03 12:08:02 PM UTC 24 |
51014771653 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1532328240 |
|
|
Oct 03 12:07:11 PM UTC 24 |
Oct 03 12:08:07 PM UTC 24 |
106492220 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.422133770 |
|
|
Oct 03 12:06:52 PM UTC 24 |
Oct 03 12:08:07 PM UTC 24 |
3549026483 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.4004645195 |
|
|
Oct 03 12:08:07 PM UTC 24 |
Oct 03 12:08:14 PM UTC 24 |
942854630 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1441257743 |
|
|
Oct 03 12:08:03 PM UTC 24 |
Oct 03 12:08:17 PM UTC 24 |
180223416 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.484124682 |
|
|
Oct 03 12:01:44 PM UTC 24 |
Oct 03 12:08:21 PM UTC 24 |
18667216714 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1080730978 |
|
|
Oct 03 12:08:22 PM UTC 24 |
Oct 03 12:08:24 PM UTC 24 |
44760230 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3648704592 |
|
|
Oct 03 12:08:07 PM UTC 24 |
Oct 03 12:08:31 PM UTC 24 |
637569791 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1195631715 |
|
|
Oct 03 12:08:32 PM UTC 24 |
Oct 03 12:08:37 PM UTC 24 |
85755632 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1567608026 |
|
|
Oct 03 12:08:25 PM UTC 24 |
Oct 03 12:08:40 PM UTC 24 |
570521503 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.3275626725 |
|
|
Oct 03 12:06:12 PM UTC 24 |
Oct 03 12:08:50 PM UTC 24 |
3206028774 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1878056378 |
|
|
Oct 03 12:08:38 PM UTC 24 |
Oct 03 12:08:51 PM UTC 24 |
309936401 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3049420507 |
|
|
Oct 03 12:08:51 PM UTC 24 |
Oct 03 12:08:53 PM UTC 24 |
12334411 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1447146694 |
|
|
Oct 03 12:03:55 PM UTC 24 |
Oct 03 12:08:53 PM UTC 24 |
2377316920 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1247629506 |
|
|
Oct 03 12:07:01 PM UTC 24 |
Oct 03 12:09:02 PM UTC 24 |
208652796 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.295930359 |
|
|
Oct 03 12:08:52 PM UTC 24 |
Oct 03 12:09:11 PM UTC 24 |
205027488 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.786271713 |
|
|
Oct 03 12:00:46 PM UTC 24 |
Oct 03 12:09:15 PM UTC 24 |
2231666403 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2231069336 |
|
|
Oct 03 12:05:52 PM UTC 24 |
Oct 03 12:09:26 PM UTC 24 |
6139727193 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2033129217 |
|
|
Oct 03 12:05:08 PM UTC 24 |
Oct 03 12:09:27 PM UTC 24 |
32533494307 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2231221950 |
|
|
Oct 03 12:06:42 PM UTC 24 |
Oct 03 12:09:32 PM UTC 24 |
7233846676 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3407624885 |
|
|
Oct 03 12:09:28 PM UTC 24 |
Oct 03 12:09:34 PM UTC 24 |
300020412 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3117266139 |
|
|
Oct 03 12:08:54 PM UTC 24 |
Oct 03 12:10:00 PM UTC 24 |
10436760878 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3055574135 |
|
|
Oct 03 12:09:27 PM UTC 24 |
Oct 03 12:10:01 PM UTC 24 |
431573020 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.417994841 |
|
|
Oct 03 12:09:16 PM UTC 24 |
Oct 03 12:10:03 PM UTC 24 |
392645884 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.1251200666 |
|
|
Oct 03 12:10:02 PM UTC 24 |
Oct 03 12:10:04 PM UTC 24 |
29833638 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3376125441 |
|
|
Oct 03 12:10:05 PM UTC 24 |
Oct 03 12:10:11 PM UTC 24 |
318793626 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3309038607 |
|
|
Oct 03 12:10:04 PM UTC 24 |
Oct 03 12:10:15 PM UTC 24 |
271974237 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1336249393 |
|
|
Oct 03 12:09:02 PM UTC 24 |
Oct 03 12:10:35 PM UTC 24 |
431447662 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3038153755 |
|
|
Oct 03 12:10:36 PM UTC 24 |
Oct 03 12:10:38 PM UTC 24 |
71336003 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3288863373 |
|
|
Oct 03 12:05:01 PM UTC 24 |
Oct 03 12:10:43 PM UTC 24 |
3307641648 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.355252118 |
|
|
Oct 03 12:10:39 PM UTC 24 |
Oct 03 12:10:52 PM UTC 24 |
6049693720 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.343846631 |
|
|
Oct 03 12:02:48 PM UTC 24 |
Oct 03 12:10:59 PM UTC 24 |
7750718890 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2631402353 |
|
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Oct 03 11:58:11 AM UTC 24 |
Oct 03 12:11:11 PM UTC 24 |
19074123568 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2944633349 |
|
|
Oct 03 12:11:11 PM UTC 24 |
Oct 03 12:11:16 PM UTC 24 |
221410024 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3693133423 |
|
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Oct 03 11:45:39 AM UTC 24 |
Oct 03 12:11:29 PM UTC 24 |
22122580193 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1717766237 |
|
|
Oct 03 12:02:22 PM UTC 24 |
Oct 03 12:11:31 PM UTC 24 |
12987455457 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3392834602 |
|
|
Oct 03 12:11:29 PM UTC 24 |
Oct 03 12:11:35 PM UTC 24 |
179293621 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.4200971643 |
|
|
Oct 03 12:04:53 PM UTC 24 |
Oct 03 12:11:40 PM UTC 24 |
2272994959 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2641418093 |
|
|
Oct 03 11:58:58 AM UTC 24 |
Oct 03 12:11:41 PM UTC 24 |
5461159450 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.2251087510 |
|
|
Oct 03 12:11:36 PM UTC 24 |
Oct 03 12:11:41 PM UTC 24 |
423487008 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2101549918 |
|
|
Oct 03 12:11:32 PM UTC 24 |
Oct 03 12:11:43 PM UTC 24 |
662611323 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3146215967 |
|
|
Oct 03 12:06:59 PM UTC 24 |
Oct 03 12:11:44 PM UTC 24 |
2457938807 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3008893103 |
|
|
Oct 03 12:11:44 PM UTC 24 |
Oct 03 12:11:46 PM UTC 24 |
41890169 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2966783377 |
|
|
Oct 03 12:11:45 PM UTC 24 |
Oct 03 12:11:53 PM UTC 24 |
97747472 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.923438145 |
|
|
Oct 03 12:11:47 PM UTC 24 |
Oct 03 12:11:56 PM UTC 24 |
788827187 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2026249056 |
|
|
Oct 03 12:03:57 PM UTC 24 |
Oct 03 12:11:57 PM UTC 24 |
20758156955 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1205053308 |
|
|
Oct 03 12:11:57 PM UTC 24 |
Oct 03 12:11:59 PM UTC 24 |
18084100 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.3407362787 |
|
|
Oct 03 12:12:00 PM UTC 24 |
Oct 03 12:12:07 PM UTC 24 |
162515251 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.571538663 |
|
|
Oct 03 12:10:53 PM UTC 24 |
Oct 03 12:12:22 PM UTC 24 |
3706506711 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.4058191544 |
|
|
Oct 03 12:00:24 PM UTC 24 |
Oct 03 12:12:36 PM UTC 24 |
39273085727 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2053605149 |
|
|
Oct 03 12:11:53 PM UTC 24 |
Oct 03 12:12:48 PM UTC 24 |
864914235 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2875527194 |
|
|
Oct 03 12:02:52 PM UTC 24 |
Oct 03 12:12:57 PM UTC 24 |
9315059062 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.18614040 |
|
|
Oct 03 11:51:07 AM UTC 24 |
Oct 03 12:13:02 PM UTC 24 |
12927488163 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2287319200 |
|
|
Oct 03 12:12:49 PM UTC 24 |
Oct 03 12:13:12 PM UTC 24 |
342925910 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1328366942 |
|
|
Oct 03 12:13:13 PM UTC 24 |
Oct 03 12:13:31 PM UTC 24 |
157187102 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2834565172 |
|
|
Oct 03 12:13:32 PM UTC 24 |
Oct 03 12:13:36 PM UTC 24 |
134059311 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3749586645 |
|
|
Oct 03 12:08:57 PM UTC 24 |
Oct 03 12:13:37 PM UTC 24 |
8220838433 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2536257950 |
|
|
Oct 03 11:58:38 AM UTC 24 |
Oct 03 12:13:39 PM UTC 24 |
2556394385 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3454050546 |
|
|
Oct 03 12:13:40 PM UTC 24 |
Oct 03 12:13:42 PM UTC 24 |
29369783 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.1536349067 |
|
|
Oct 03 12:12:24 PM UTC 24 |
Oct 03 12:13:47 PM UTC 24 |
3997162318 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.240587732 |
|
|
Oct 03 12:13:43 PM UTC 24 |
Oct 03 12:13:51 PM UTC 24 |
239368898 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.3309304162 |
|
|
Oct 03 11:55:47 AM UTC 24 |
Oct 03 12:13:53 PM UTC 24 |
28329888500 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.532648087 |
|
|
Oct 03 12:13:48 PM UTC 24 |
Oct 03 12:13:55 PM UTC 24 |
172974653 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2038246936 |
|
|
Oct 03 12:13:56 PM UTC 24 |
Oct 03 12:13:58 PM UTC 24 |
19729548 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1459801341 |
|
|
Oct 03 12:02:05 PM UTC 24 |
Oct 03 12:14:25 PM UTC 24 |
11896332879 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1806083109 |
|
|
Oct 03 12:02:46 PM UTC 24 |
Oct 03 12:14:32 PM UTC 24 |
2697243236 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1273403463 |
|
|
Oct 03 12:06:49 PM UTC 24 |
Oct 03 12:14:39 PM UTC 24 |
11299935851 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3432846450 |
|
|
Oct 03 12:05:17 PM UTC 24 |
Oct 03 12:14:42 PM UTC 24 |
10498602845 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.854205426 |
|
|
Oct 03 12:01:50 PM UTC 24 |
Oct 03 12:14:51 PM UTC 24 |
11869394382 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2682362682 |
|
|
Oct 03 12:13:03 PM UTC 24 |
Oct 03 12:14:57 PM UTC 24 |
526170016 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.342993316 |
|
|
Oct 03 11:57:26 AM UTC 24 |
Oct 03 12:15:04 PM UTC 24 |
6836701208 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.966345345 |
|
|
Oct 03 12:14:43 PM UTC 24 |
Oct 03 12:15:14 PM UTC 24 |
225080907 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.2997884173 |
|
|
Oct 03 12:13:59 PM UTC 24 |
Oct 03 12:15:17 PM UTC 24 |
251710284 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.3637449863 |
|
|
Oct 03 12:15:15 PM UTC 24 |
Oct 03 12:15:22 PM UTC 24 |
354253617 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3267140380 |
|
|
Oct 03 12:07:01 PM UTC 24 |
Oct 03 12:15:26 PM UTC 24 |
46713993178 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2807721894 |
|
|
Oct 03 12:14:33 PM UTC 24 |
Oct 03 12:15:34 PM UTC 24 |
8880466735 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2465548558 |
|
|
Oct 03 12:15:34 PM UTC 24 |
Oct 03 12:15:37 PM UTC 24 |
29094455 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.3546805503 |
|
|
Oct 03 12:14:58 PM UTC 24 |
Oct 03 12:15:39 PM UTC 24 |
189507705 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2292495798 |
|
|
Oct 03 12:01:34 PM UTC 24 |
Oct 03 12:15:41 PM UTC 24 |
3759790427 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.3890747530 |
|
|
Oct 03 12:04:34 PM UTC 24 |
Oct 03 12:15:42 PM UTC 24 |
1816777916 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3754813750 |
|
|
Oct 03 11:50:12 AM UTC 24 |
Oct 03 12:15:45 PM UTC 24 |
9114862628 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.1635801625 |
|
|
Oct 03 12:15:41 PM UTC 24 |
Oct 03 12:15:46 PM UTC 24 |
67555513 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3099377536 |
|
|
Oct 03 12:15:46 PM UTC 24 |
Oct 03 12:15:48 PM UTC 24 |
36249326 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2628768477 |
|
|
Oct 03 12:15:05 PM UTC 24 |
Oct 03 12:15:50 PM UTC 24 |
484586220 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.419373760 |
|
|
Oct 03 12:15:37 PM UTC 24 |
Oct 03 12:15:50 PM UTC 24 |
447513089 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.16166274 |
|
|
Oct 03 11:55:40 AM UTC 24 |
Oct 03 12:15:56 PM UTC 24 |
177027105265 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3397677110 |
|
|
Oct 03 12:15:47 PM UTC 24 |
Oct 03 12:16:03 PM UTC 24 |
428511732 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.2001731414 |
|
|
Oct 03 12:11:42 PM UTC 24 |
Oct 03 12:16:06 PM UTC 24 |
705018160 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.643098580 |
|
|
Oct 03 12:10:59 PM UTC 24 |
Oct 03 12:16:07 PM UTC 24 |
2446853064 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2368936119 |
|
|
Oct 03 12:15:57 PM UTC 24 |
Oct 03 12:16:08 PM UTC 24 |
3209143854 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1846382106 |
|
|
Oct 03 11:45:31 AM UTC 24 |
Oct 03 12:16:09 PM UTC 24 |
257895990104 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3038580028 |
|
|
Oct 03 12:16:06 PM UTC 24 |
Oct 03 12:16:11 PM UTC 24 |
148428876 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2072889756 |
|
|
Oct 03 12:16:09 PM UTC 24 |
Oct 03 12:16:17 PM UTC 24 |
576105775 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1125753156 |
|
|
Oct 03 12:05:57 PM UTC 24 |
Oct 03 12:16:27 PM UTC 24 |
76871203774 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1575642737 |
|
|
Oct 03 12:16:28 PM UTC 24 |
Oct 03 12:16:31 PM UTC 24 |
43726864 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2150125294 |
|
|
Oct 03 12:16:09 PM UTC 24 |
Oct 03 12:16:33 PM UTC 24 |
88122146 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3728225801 |
|
|
Oct 03 12:15:50 PM UTC 24 |
Oct 03 12:16:38 PM UTC 24 |
2209706299 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.818280602 |
|
|
Oct 03 12:15:43 PM UTC 24 |
Oct 03 12:16:38 PM UTC 24 |
912908420 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3142811130 |
|
|
Oct 03 12:16:33 PM UTC 24 |
Oct 03 12:16:39 PM UTC 24 |
60687242 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2638390095 |
|
|
Oct 03 12:16:40 PM UTC 24 |
Oct 03 12:16:42 PM UTC 24 |
19688270 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3645717590 |
|
|
Oct 03 11:58:42 AM UTC 24 |
Oct 03 12:16:43 PM UTC 24 |
113400172183 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.901764002 |
|
|
Oct 03 12:16:31 PM UTC 24 |
Oct 03 12:16:49 PM UTC 24 |
2296073479 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1411800612 |
|
|
Oct 03 12:14:40 PM UTC 24 |
Oct 03 12:16:56 PM UTC 24 |
1251467660 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.105689958 |
|
|
Oct 03 12:14:26 PM UTC 24 |
Oct 03 12:17:08 PM UTC 24 |
2709339944 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2964909590 |
|
|
Oct 03 12:09:13 PM UTC 24 |
Oct 03 12:17:10 PM UTC 24 |
23261469230 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2831972864 |
|
|
Oct 03 12:12:37 PM UTC 24 |
Oct 03 12:17:18 PM UTC 24 |
2501579175 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.162329550 |
|
|
Oct 03 12:17:10 PM UTC 24 |
Oct 03 12:17:20 PM UTC 24 |
950993919 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.442696924 |
|
|
Oct 03 12:17:21 PM UTC 24 |
Oct 03 12:17:26 PM UTC 24 |
179760538 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1344313639 |
|
|
Oct 03 12:17:27 PM UTC 24 |
Oct 03 12:17:40 PM UTC 24 |
2473613541 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1403429436 |
|
|
Oct 03 12:16:43 PM UTC 24 |
Oct 03 12:17:42 PM UTC 24 |
367421448 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2628843119 |
|
|
Oct 03 12:14:52 PM UTC 24 |
Oct 03 12:17:47 PM UTC 24 |
4345418125 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2156240026 |
|
|
Oct 03 12:13:52 PM UTC 24 |
Oct 03 12:17:49 PM UTC 24 |
12613717997 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1958501382 |
|
|
Oct 03 12:17:51 PM UTC 24 |
Oct 03 12:17:53 PM UTC 24 |
36246993 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3683896200 |
|
|
Oct 03 12:17:54 PM UTC 24 |
Oct 03 12:18:01 PM UTC 24 |
339389482 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1881915490 |
|
|
Oct 03 12:17:19 PM UTC 24 |
Oct 03 12:18:04 PM UTC 24 |
195455596 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1419759408 |
|
|
Oct 03 12:16:50 PM UTC 24 |
Oct 03 12:18:05 PM UTC 24 |
11388409304 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4058075535 |
|
|
Oct 03 12:18:02 PM UTC 24 |
Oct 03 12:18:13 PM UTC 24 |
192673291 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.4089510251 |
|
|
Oct 03 12:09:33 PM UTC 24 |
Oct 03 12:18:15 PM UTC 24 |
2609833103 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.785376427 |
|
|
Oct 03 12:18:15 PM UTC 24 |
Oct 03 12:18:17 PM UTC 24 |
16787456 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.786794188 |
|
|
Oct 03 12:18:16 PM UTC 24 |
Oct 03 12:18:20 PM UTC 24 |
173238856 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.328402800 |
|
|
Oct 03 12:18:21 PM UTC 24 |
Oct 03 12:19:14 PM UTC 24 |
1260201573 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.2680792055 |
|
|
Oct 03 12:00:22 PM UTC 24 |
Oct 03 12:19:18 PM UTC 24 |
19222884085 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2116813422 |
|
|
Oct 03 12:11:16 PM UTC 24 |
Oct 03 12:19:28 PM UTC 24 |
20281704249 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.993380566 |
|
|
Oct 03 12:19:15 PM UTC 24 |
Oct 03 12:19:34 PM UTC 24 |
777190891 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2536166704 |
|
|
Oct 03 12:19:29 PM UTC 24 |
Oct 03 12:19:52 PM UTC 24 |
994172075 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.755326097 |
|
|
Oct 03 12:04:37 PM UTC 24 |
Oct 03 12:19:52 PM UTC 24 |
8843080542 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3684747842 |
|
|
Oct 03 12:19:52 PM UTC 24 |
Oct 03 12:20:00 PM UTC 24 |
390748446 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.977413403 |
|
|
Oct 03 12:19:35 PM UTC 24 |
Oct 03 12:20:22 PM UTC 24 |
108436676 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.996599611 |
|
|
Oct 03 12:06:13 PM UTC 24 |
Oct 03 12:20:39 PM UTC 24 |
3472365536 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.467965392 |
|
|
Oct 03 12:20:39 PM UTC 24 |
Oct 03 12:20:41 PM UTC 24 |
29514217 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3377984002 |
|
|
Oct 03 12:20:42 PM UTC 24 |
Oct 03 12:20:55 PM UTC 24 |
140616088 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2128893235 |
|
|
Oct 03 12:06:46 PM UTC 24 |
Oct 03 12:21:00 PM UTC 24 |
13846924382 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1188823755 |
|
|
Oct 03 12:20:57 PM UTC 24 |
Oct 03 12:21:06 PM UTC 24 |
254225720 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.1626423596 |
|
|
Oct 03 12:20:24 PM UTC 24 |
Oct 03 12:21:09 PM UTC 24 |
1068772640 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1124788790 |
|
|
Oct 03 12:12:58 PM UTC 24 |
Oct 03 12:21:09 PM UTC 24 |
5539470239 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2179043756 |
|
|
Oct 03 12:15:51 PM UTC 24 |
Oct 03 12:21:11 PM UTC 24 |
11323455992 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2747456214 |
|
|
Oct 03 12:21:10 PM UTC 24 |
Oct 03 12:21:12 PM UTC 24 |
40740262 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1247469240 |
|
|
Oct 03 12:21:01 PM UTC 24 |
Oct 03 12:21:13 PM UTC 24 |
869534455 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1991439442 |
|
|
Oct 03 12:05:21 PM UTC 24 |
Oct 03 12:21:13 PM UTC 24 |
3435653394 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1217648785 |
|
|
Oct 03 12:15:23 PM UTC 24 |
Oct 03 12:21:31 PM UTC 24 |
43910709438 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.2019655254 |
|
|
Oct 03 12:10:00 PM UTC 24 |
Oct 03 12:21:36 PM UTC 24 |
47795978367 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3153766580 |
|
|
Oct 03 12:21:13 PM UTC 24 |
Oct 03 12:21:46 PM UTC 24 |
882049123 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.258053919 |
|
|
Oct 03 12:21:15 PM UTC 24 |
Oct 03 12:21:47 PM UTC 24 |
6167277697 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2729378053 |
|
|
Oct 03 12:21:48 PM UTC 24 |
Oct 03 12:21:55 PM UTC 24 |
1956659734 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.2922712178 |
|
|
Oct 03 12:13:36 PM UTC 24 |
Oct 03 12:22:13 PM UTC 24 |
43392486361 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.1679149672 |
|
|
Oct 03 12:09:35 PM UTC 24 |
Oct 03 12:22:23 PM UTC 24 |
44302279889 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1173225092 |
|
|
Oct 03 12:21:48 PM UTC 24 |
Oct 03 12:22:35 PM UTC 24 |
111054917 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.500488438 |
|
|
Oct 03 12:16:57 PM UTC 24 |
Oct 03 12:22:35 PM UTC 24 |
5869779753 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2195467999 |
|
|
Oct 03 12:22:36 PM UTC 24 |
Oct 03 12:22:39 PM UTC 24 |
48994740 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.477484573 |
|
|
Oct 03 12:21:37 PM UTC 24 |
Oct 03 12:22:41 PM UTC 24 |
123133012 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1826148918 |
|
|
Oct 03 12:16:04 PM UTC 24 |
Oct 03 12:22:45 PM UTC 24 |
68589366106 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2195210857 |
|
|
Oct 03 12:22:40 PM UTC 24 |
Oct 03 12:22:45 PM UTC 24 |
90358251 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2700110908 |
|
|
Oct 03 12:22:46 PM UTC 24 |
Oct 03 12:22:48 PM UTC 24 |
19021567 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1809327595 |
|
|
Oct 03 12:22:36 PM UTC 24 |
Oct 03 12:22:49 PM UTC 24 |
346089101 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1421351244 |
|
|
Oct 03 12:21:10 PM UTC 24 |
Oct 03 12:22:49 PM UTC 24 |
108905240 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2059809935 |
|
|
Oct 03 12:17:41 PM UTC 24 |
Oct 03 12:22:59 PM UTC 24 |
4915110876 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1622860127 |
|
|
Oct 03 12:22:49 PM UTC 24 |
Oct 03 12:23:10 PM UTC 24 |
1544427965 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2089783725 |
|
|
Oct 03 12:16:11 PM UTC 24 |
Oct 03 12:23:19 PM UTC 24 |
2254044912 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1609015887 |
|
|
Oct 03 11:50:32 AM UTC 24 |
Oct 03 12:23:31 PM UTC 24 |
8932445606 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1903024841 |
|
|
Oct 03 12:22:42 PM UTC 24 |
Oct 03 12:23:35 PM UTC 24 |
2420005674 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3014602691 |
|
|
Oct 03 12:11:41 PM UTC 24 |
Oct 03 12:23:46 PM UTC 24 |
4466368982 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4096385016 |
|
|
Oct 03 12:18:05 PM UTC 24 |
Oct 03 12:23:51 PM UTC 24 |
1138128319 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.4193440322 |
|
|
Oct 03 12:23:47 PM UTC 24 |
Oct 03 12:23:58 PM UTC 24 |
929126633 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3813491055 |
|
|
Oct 03 12:23:12 PM UTC 24 |
Oct 03 12:24:17 PM UTC 24 |
212591024 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.333876565 |
|
|
Oct 03 12:23:32 PM UTC 24 |
Oct 03 12:24:23 PM UTC 24 |
401283330 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3949133199 |
|
|
Oct 03 12:24:24 PM UTC 24 |
Oct 03 12:24:26 PM UTC 24 |
33829669 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.291460642 |
|
|
Oct 03 12:18:41 PM UTC 24 |
Oct 03 12:24:32 PM UTC 24 |
2797276451 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.1532574158 |
|
|
Oct 03 12:24:33 PM UTC 24 |
Oct 03 12:24:41 PM UTC 24 |
71910709 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.950699009 |
|
|
Oct 03 12:24:27 PM UTC 24 |
Oct 03 12:24:43 PM UTC 24 |
179331665 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.832695751 |
|
|
Oct 03 12:22:50 PM UTC 24 |
Oct 03 12:24:57 PM UTC 24 |
53975117457 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.298524110 |
|
|
Oct 03 12:23:36 PM UTC 24 |
Oct 03 12:24:58 PM UTC 24 |
298688706 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3385602149 |
|
|
Oct 03 12:24:58 PM UTC 24 |
Oct 03 12:25:00 PM UTC 24 |
14703912 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.115442653 |
|
|
Oct 03 12:24:59 PM UTC 24 |
Oct 03 12:25:13 PM UTC 24 |
1907377637 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.44683019 |
|
|
Oct 03 12:17:44 PM UTC 24 |
Oct 03 12:25:17 PM UTC 24 |
995451786 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1561505242 |
|
|
Oct 03 12:21:13 PM UTC 24 |
Oct 03 12:25:34 PM UTC 24 |
2439577741 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2158982590 |
|
|
Oct 03 12:25:35 PM UTC 24 |
Oct 03 12:25:39 PM UTC 24 |
64811069 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3017931767 |
|
|
Oct 03 12:05:23 PM UTC 24 |
Oct 03 12:25:50 PM UTC 24 |
26508125749 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.1605856505 |
|
|
Oct 03 12:04:28 PM UTC 24 |
Oct 03 12:25:55 PM UTC 24 |
3386488389 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2393876759 |
|
|
Oct 03 12:25:52 PM UTC 24 |
Oct 03 12:25:58 PM UTC 24 |
260403116 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1604851197 |
|
|
Oct 03 12:19:19 PM UTC 24 |
Oct 03 12:26:01 PM UTC 24 |
45803482836 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.43870094 |
|
|
Oct 03 12:13:39 PM UTC 24 |
Oct 03 12:26:02 PM UTC 24 |
27275232985 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.309144934 |
|
|
Oct 03 12:25:56 PM UTC 24 |
Oct 03 12:26:07 PM UTC 24 |
126344218 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.894783085 |
|
|
Oct 03 12:16:12 PM UTC 24 |
Oct 03 12:26:08 PM UTC 24 |
15526701341 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1230731335 |
|
|
Oct 03 12:25:59 PM UTC 24 |
Oct 03 12:26:08 PM UTC 24 |
1178125363 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.2515417316 |
|
|
Oct 03 12:26:09 PM UTC 24 |
Oct 03 12:26:11 PM UTC 24 |
30622596 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.49333974 |
|
|
Oct 03 12:26:12 PM UTC 24 |
Oct 03 12:26:18 PM UTC 24 |
193201651 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3639859246 |
|
|
Oct 03 12:26:09 PM UTC 24 |
Oct 03 12:26:29 PM UTC 24 |
6323635897 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.1398068443 |
|
|
Oct 03 12:25:14 PM UTC 24 |
Oct 03 12:26:30 PM UTC 24 |
3615974078 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.275135686 |
|
|
Oct 03 12:26:31 PM UTC 24 |
Oct 03 12:26:33 PM UTC 24 |
20495971 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.901705144 |
|
|
Oct 03 12:16:17 PM UTC 24 |
Oct 03 12:26:41 PM UTC 24 |
1598454593 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2228512236 |
|
|
Oct 03 11:51:28 AM UTC 24 |
Oct 03 12:26:47 PM UTC 24 |
24203526142 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.971696589 |
|
|
Oct 03 12:26:34 PM UTC 24 |
Oct 03 12:26:48 PM UTC 24 |
1456051547 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3225665710 |
|
|
Oct 03 12:24:41 PM UTC 24 |
Oct 03 12:26:54 PM UTC 24 |
2231661185 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.4121391038 |
|
|
Oct 03 12:17:11 PM UTC 24 |
Oct 03 12:27:53 PM UTC 24 |
20676614974 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1423834332 |
|
|
Oct 03 12:08:54 PM UTC 24 |
Oct 03 12:28:01 PM UTC 24 |
6755858044 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.715330470 |
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Oct 03 12:28:02 PM UTC 24 |
Oct 03 12:28:19 PM UTC 24 |
128393255 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2489674525 |
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Oct 03 12:28:20 PM UTC 24 |
Oct 03 12:28:31 PM UTC 24 |
72773355 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1817836654 |
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Oct 03 12:26:48 PM UTC 24 |
Oct 03 12:28:36 PM UTC 24 |
28753761549 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4172603596 |
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Oct 03 12:08:41 PM UTC 24 |
Oct 03 12:28:36 PM UTC 24 |
27692682721 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.857662605 |
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Oct 03 12:28:32 PM UTC 24 |
Oct 03 12:28:42 PM UTC 24 |
2086799043 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.1006380420 |
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Oct 03 12:08:18 PM UTC 24 |
Oct 03 12:28:47 PM UTC 24 |
75271819549 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1176712323 |
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Oct 03 12:28:48 PM UTC 24 |
Oct 03 12:28:50 PM UTC 24 |
35568006 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2370419175 |
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Oct 03 12:26:55 PM UTC 24 |
Oct 03 12:28:55 PM UTC 24 |
208300370 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3837320176 |
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Oct 03 12:28:55 PM UTC 24 |
Oct 03 12:29:02 PM UTC 24 |
395397194 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3721190054 |
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Oct 03 12:28:51 PM UTC 24 |
Oct 03 12:29:02 PM UTC 24 |
1803701543 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.64111738 |
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Oct 03 12:23:01 PM UTC 24 |
Oct 03 12:29:12 PM UTC 24 |
23400932282 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.727773049 |
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Oct 03 12:21:57 PM UTC 24 |
Oct 03 12:29:14 PM UTC 24 |
58354922878 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3466770424 |
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Oct 03 12:29:13 PM UTC 24 |
Oct 03 12:29:15 PM UTC 24 |
18451982 ps |