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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.31 99.22 95.11 99.72 100.00 96.31 99.12 98.72


Total test records in report: 1031
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T93 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1062478066 Oct 03 11:36:35 AM UTC 24 Oct 03 11:36:40 AM UTC 24 3612067022 ps
T1005 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.949966189 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:40 AM UTC 24 37729572 ps
T1006 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.921629946 Oct 03 11:36:37 AM UTC 24 Oct 03 11:36:40 AM UTC 24 267023892 ps
T1007 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3614797012 Oct 03 11:36:37 AM UTC 24 Oct 03 11:36:40 AM UTC 24 188191309 ps
T1008 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.978795248 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:40 AM UTC 24 102885435 ps
T1009 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1952781086 Oct 03 11:36:35 AM UTC 24 Oct 03 11:36:40 AM UTC 24 132552312 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3823661580 Oct 03 11:36:37 AM UTC 24 Oct 03 11:36:40 AM UTC 24 348780103 ps
T1010 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3049588838 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:41 AM UTC 24 100057819 ps
T1011 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3880208342 Oct 03 11:36:37 AM UTC 24 Oct 03 11:36:41 AM UTC 24 810956058 ps
T1012 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.445656230 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:41 AM UTC 24 18626959 ps
T1013 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1193417767 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:41 AM UTC 24 792956457 ps
T1014 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4239088906 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:42 AM UTC 24 45285658 ps
T1015 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2241589870 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:42 AM UTC 24 13396776 ps
T1016 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2752148218 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:42 AM UTC 24 99518982 ps
T1017 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.157416725 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:42 AM UTC 24 471209472 ps
T1018 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.199441215 Oct 03 11:36:37 AM UTC 24 Oct 03 11:36:42 AM UTC 24 37704699 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.937667685 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:42 AM UTC 24 190624429 ps
T1019 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4287497020 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:42 AM UTC 24 125839593 ps
T1020 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1692108872 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:42 AM UTC 24 163067986 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2328015917 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:42 AM UTC 24 358732221 ps
T1021 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3458746434 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:43 AM UTC 24 20757784 ps
T1022 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1151029850 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:43 AM UTC 24 204869887 ps
T1023 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2236204937 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:43 AM UTC 24 32199561 ps
T1024 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4130786641 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:43 AM UTC 24 19000946 ps
T1025 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4005655633 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:43 AM UTC 24 301814803 ps
T1026 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.846241353 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:44 AM UTC 24 64674743 ps
T1027 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3942383770 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:44 AM UTC 24 36771418 ps
T1028 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1758045136 Oct 03 11:36:38 AM UTC 24 Oct 03 11:36:44 AM UTC 24 261593719 ps
T1029 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.510690511 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:45 AM UTC 24 823156182 ps
T1030 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2578398908 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:45 AM UTC 24 256763767 ps
T1031 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2153277505 Oct 03 11:36:40 AM UTC 24 Oct 03 11:36:45 AM UTC 24 149907436 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.337120951
Short name T6
Test name
Test status
Simulation time 647336235 ps
CPU time 10.52 seconds
Started Oct 03 11:45:48 AM UTC 24
Finished Oct 03 11:46:00 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337120951 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.337120951
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2028009400
Short name T25
Test name
Test status
Simulation time 25629567843 ps
CPU time 159.29 seconds
Started Oct 03 11:45:39 AM UTC 24
Finished Oct 03 11:48:21 AM UTC 24
Peak memory 321856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028009400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2028009400
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2503263268
Short name T7
Test name
Test status
Simulation time 592991625 ps
CPU time 14.13 seconds
Started Oct 03 11:45:37 AM UTC 24
Finished Oct 03 11:45:53 AM UTC 24
Peak memory 222452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503263268 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2503263268
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1233632755
Short name T156
Test name
Test status
Simulation time 1354757089 ps
CPU time 76.46 seconds
Started Oct 03 12:00:35 PM UTC 24
Finished Oct 03 12:01:53 PM UTC 24
Peak memory 299196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233632755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1233632755
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1044036681
Short name T4
Test name
Test status
Simulation time 185179297 ps
CPU time 2.39 seconds
Started Oct 03 11:45:40 AM UTC 24
Finished Oct 03 11:45:43 AM UTC 24
Peak memory 248204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044036681 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1044036681
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.2120034562
Short name T20
Test name
Test status
Simulation time 5311154428 ps
CPU time 220.01 seconds
Started Oct 03 11:50:18 AM UTC 24
Finished Oct 03 11:54:02 AM UTC 24
Peak memory 336108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120034562 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2120034562
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2272108232
Short name T122
Test name
Test status
Simulation time 270572022 ps
CPU time 2.29 seconds
Started Oct 03 11:36:28 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 221168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22721
08232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in
tg_err.2272108232
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1921938538
Short name T8
Test name
Test status
Simulation time 421089544 ps
CPU time 7.97 seconds
Started Oct 03 11:46:31 AM UTC 24
Finished Oct 03 11:46:40 AM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921938538 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.1921938538
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2896846703
Short name T150
Test name
Test status
Simulation time 176509715416 ps
CPU time 411.5 seconds
Started Oct 03 11:48:43 AM UTC 24
Finished Oct 03 11:55:40 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896846703 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce
ss_b2b.2896846703
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.698911521
Short name T74
Test name
Test status
Simulation time 22189020 ps
CPU time 1.02 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69891152
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alias
ing.698911521
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2881891188
Short name T144
Test name
Test status
Simulation time 50302548556 ps
CPU time 1134.46 seconds
Started Oct 03 11:45:35 AM UTC 24
Finished Oct 03 12:04:42 PM UTC 24
Peak memory 383168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881891188 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2881891188
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3302743595
Short name T5
Test name
Test status
Simulation time 123061429 ps
CPU time 4.55 seconds
Started Oct 03 11:45:39 AM UTC 24
Finished Oct 03 11:45:44 AM UTC 24
Peak memory 222452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302743595 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.3302743595
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1788002811
Short name T50
Test name
Test status
Simulation time 3848927234 ps
CPU time 140.59 seconds
Started Oct 03 11:58:09 AM UTC 24
Finished Oct 03 12:00:32 PM UTC 24
Peak memory 356724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788002811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1788002811
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.48826429
Short name T2
Test name
Test status
Simulation time 50915830 ps
CPU time 0.99 seconds
Started Oct 03 11:45:36 AM UTC 24
Finished Oct 03 11:45:38 AM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48826429 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.48826429
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3645717590
Short name T445
Test name
Test status
Simulation time 113400172183 ps
CPU time 1068.73 seconds
Started Oct 03 11:58:42 AM UTC 24
Finished Oct 03 12:16:43 PM UTC 24
Peak memory 385388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645717590 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.3645717590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1875330677
Short name T3
Test name
Test status
Simulation time 74810116 ps
CPU time 1.01 seconds
Started Oct 03 11:45:41 AM UTC 24
Finished Oct 03 11:45:43 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875330677 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1875330677
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1835256321
Short name T133
Test name
Test status
Simulation time 474457932 ps
CPU time 2.35 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18352
56321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_i
ntg_err.1835256321
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2328015917
Short name T131
Test name
Test status
Simulation time 358732221 ps
CPU time 2.99 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 211060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23280
15917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i
ntg_err.2328015917
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1463789118
Short name T62
Test name
Test status
Simulation time 202195416 ps
CPU time 21.05 seconds
Started Oct 03 11:58:54 AM UTC 24
Finished Oct 03 11:59:16 AM UTC 24
Peak memory 222612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463789118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1463789118
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2608769040
Short name T83
Test name
Test status
Simulation time 410422833 ps
CPU time 3.6 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:30 AM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26
08769040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pa
ssthru_mem_tl_intg_err.2608769040
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2516687557
Short name T101
Test name
Test status
Simulation time 4581505159 ps
CPU time 186.66 seconds
Started Oct 03 11:45:32 AM UTC 24
Finished Oct 03 11:48:42 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516687557 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce
ss_b2b.2516687557
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3742846147
Short name T26
Test name
Test status
Simulation time 3674734444 ps
CPU time 145 seconds
Started Oct 03 11:45:57 AM UTC 24
Finished Oct 03 11:48:25 AM UTC 24
Peak memory 366976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742846147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3742846147
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3982725571
Short name T78
Test name
Test status
Simulation time 2757063444 ps
CPU time 3.97 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:27 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
82725571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa
ssthru_mem_tl_intg_err.3982725571
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.1829681664
Short name T65
Test name
Test status
Simulation time 95161043433 ps
CPU time 108.24 seconds
Started Oct 03 11:45:45 AM UTC 24
Finished Oct 03 11:47:35 AM UTC 24
Peak memory 212168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829681664 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.1829681664
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.610265315
Short name T75
Test name
Test status
Simulation time 86258648 ps
CPU time 2.24 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:25 AM UTC 24
Peak memory 210656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61026531
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_b
ash.610265315
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3120701293
Short name T73
Test name
Test status
Simulation time 77645345 ps
CPU time 1.01 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 209648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31207012
93 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_r
eset.3120701293
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3429450253
Short name T946
Test name
Test status
Simulation time 475999956 ps
CPU time 2.86 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:26 AM UTC 24
Peak memory 221332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3429450253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3429450253
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3786140641
Short name T72
Test name
Test status
Simulation time 44950155 ps
CPU time 0.92 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786140641 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.3786140641
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.822888358
Short name T96
Test name
Test status
Simulation time 63622378 ps
CPU time 0.86 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=822888358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ct
rl_same_csr_outstanding.822888358
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2748312931
Short name T945
Test name
Test status
Simulation time 32293476 ps
CPU time 3.12 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:26 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748312931 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.2748312931
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1297196979
Short name T108
Test name
Test status
Simulation time 333021978 ps
CPU time 1.6 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 220220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12971
96979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_in
tg_err.1297196979
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.210021249
Short name T77
Test name
Test status
Simulation time 12688065 ps
CPU time 0.85 seconds
Started Oct 03 11:36:24 AM UTC 24
Finished Oct 03 11:36:26 AM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21002124
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alias
ing.210021249
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.596126278
Short name T106
Test name
Test status
Simulation time 31180840 ps
CPU time 1.34 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59612627
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_b
ash.596126278
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2722381984
Short name T105
Test name
Test status
Simulation time 34278533 ps
CPU time 0.7 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27223819
84 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r
eset.2722381984
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.770542569
Short name T97
Test name
Test status
Simulation time 16824937 ps
CPU time 0.74 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:24 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770542569 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.770542569
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.212967472
Short name T76
Test name
Test status
Simulation time 211728669 ps
CPU time 2.49 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:25 AM UTC 24
Peak memory 210900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21
2967472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pas
sthru_mem_tl_intg_err.212967472
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2462304129
Short name T98
Test name
Test status
Simulation time 30605395 ps
CPU time 0.86 seconds
Started Oct 03 11:36:24 AM UTC 24
Finished Oct 03 11:36:26 AM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2462304129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c
trl_same_csr_outstanding.2462304129
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.330674654
Short name T944
Test name
Test status
Simulation time 107486687 ps
CPU time 2.35 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:25 AM UTC 24
Peak memory 211064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330674654 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.330674654
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1583683193
Short name T109
Test name
Test status
Simulation time 218004318 ps
CPU time 2.8 seconds
Started Oct 03 11:36:22 AM UTC 24
Finished Oct 03 11:36:26 AM UTC 24
Peak memory 210928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15836
83193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_in
tg_err.1583683193
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3323939552
Short name T987
Test name
Test status
Simulation time 41192504 ps
CPU time 1.62 seconds
Started Oct 03 11:36:33 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 222148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3323939552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3323939552
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.690995652
Short name T984
Test name
Test status
Simulation time 28295792 ps
CPU time 1.02 seconds
Started Oct 03 11:36:33 AM UTC 24
Finished Oct 03 11:36:35 AM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690995652 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.690995652
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3693165361
Short name T91
Test name
Test status
Simulation time 2705794437 ps
CPU time 4.33 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:38 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36
93165361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p
assthru_mem_tl_intg_err.3693165361
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.123009340
Short name T985
Test name
Test status
Simulation time 102561893 ps
CPU time 0.98 seconds
Started Oct 03 11:36:33 AM UTC 24
Finished Oct 03 11:36:35 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=123009340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_c
trl_same_csr_outstanding.123009340
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4108858981
Short name T983
Test name
Test status
Simulation time 44110431 ps
CPU time 2.18 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 221184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108858981 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.4108858981
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.733295358
Short name T988
Test name
Test status
Simulation time 33495314 ps
CPU time 2.09 seconds
Started Oct 03 11:36:34 AM UTC 24
Finished Oct 03 11:36:37 AM UTC 24
Peak memory 221204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=733295358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.733295358
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3957909019
Short name T71
Test name
Test status
Simulation time 161137553 ps
CPU time 0.78 seconds
Started Oct 03 11:36:34 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957909019 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.3957909019
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4016159670
Short name T995
Test name
Test status
Simulation time 1040383461 ps
CPU time 3.88 seconds
Started Oct 03 11:36:34 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40
16159670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p
assthru_mem_tl_intg_err.4016159670
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2500787814
Short name T986
Test name
Test status
Simulation time 69129171 ps
CPU time 1.05 seconds
Started Oct 03 11:36:34 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2500787814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_
ctrl_same_csr_outstanding.2500787814
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.515740083
Short name T994
Test name
Test status
Simulation time 131861371 ps
CPU time 3.35 seconds
Started Oct 03 11:36:34 AM UTC 24
Finished Oct 03 11:36:38 AM UTC 24
Peak memory 221424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515740083 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.515740083
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.459561571
Short name T132
Test name
Test status
Simulation time 346943742 ps
CPU time 1.73 seconds
Started Oct 03 11:36:34 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 209980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45956
1571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_in
tg_err.459561571
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4069426529
Short name T999
Test name
Test status
Simulation time 73880408 ps
CPU time 2.72 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 221364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=4069426529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.4069426529
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3510425818
Short name T94
Test name
Test status
Simulation time 17033143 ps
CPU time 0.74 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:37 AM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510425818 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.3510425818
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3212243467
Short name T90
Test name
Test status
Simulation time 223553552 ps
CPU time 2.36 seconds
Started Oct 03 11:36:34 AM UTC 24
Finished Oct 03 11:36:37 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32
12243467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p
assthru_mem_tl_intg_err.3212243467
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4285989484
Short name T989
Test name
Test status
Simulation time 63645083 ps
CPU time 0.95 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:37 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4285989484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_
ctrl_same_csr_outstanding.4285989484
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2026571531
Short name T1003
Test name
Test status
Simulation time 294790970 ps
CPU time 3.47 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 211016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026571531 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.2026571531
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3873878242
Short name T993
Test name
Test status
Simulation time 88220687 ps
CPU time 1.83 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:38 AM UTC 24
Peak memory 220372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38738
78242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i
ntg_err.3873878242
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3381383381
Short name T1001
Test name
Test status
Simulation time 41586652 ps
CPU time 2.54 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 223500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3381383381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.3381383381
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1704999227
Short name T95
Test name
Test status
Simulation time 16973056 ps
CPU time 0.75 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:37 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704999227 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.1704999227
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1062478066
Short name T93
Test name
Test status
Simulation time 3612067022 ps
CPU time 3.75 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10
62478066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p
assthru_mem_tl_intg_err.1062478066
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3605044
Short name T990
Test name
Test status
Simulation time 191686730 ps
CPU time 0.87 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:37 AM UTC 24
Peak memory 209976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3605044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_same_csr_outstanding.3605044
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1952781086
Short name T1009
Test name
Test status
Simulation time 132552312 ps
CPU time 4.24 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 221312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952781086 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.1952781086
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3340295742
Short name T124
Test name
Test status
Simulation time 1567881594 ps
CPU time 3.45 seconds
Started Oct 03 11:36:35 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 221236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33402
95742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i
ntg_err.3340295742
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.635414736
Short name T1002
Test name
Test status
Simulation time 65301158 ps
CPU time 1.32 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 220416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=635414736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.635414736
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3213285665
Short name T997
Test name
Test status
Simulation time 26266474 ps
CPU time 0.93 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213285665 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.3213285665
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2286972112
Short name T92
Test name
Test status
Simulation time 226430515 ps
CPU time 2.3 seconds
Started Oct 03 11:36:36 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22
86972112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_p
assthru_mem_tl_intg_err.2286972112
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4237366668
Short name T996
Test name
Test status
Simulation time 27595558 ps
CPU time 0.87 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4237366668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_
ctrl_same_csr_outstanding.4237366668
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.921629946
Short name T1006
Test name
Test status
Simulation time 267023892 ps
CPU time 2.75 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 221196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921629946 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.921629946
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3614797012
Short name T1007
Test name
Test status
Simulation time 188191309 ps
CPU time 2.63 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 221268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36147
97012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i
ntg_err.3614797012
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.978795248
Short name T1008
Test name
Test status
Simulation time 102885435 ps
CPU time 1.3 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 209856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=978795248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.978795248
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.593312653
Short name T1000
Test name
Test status
Simulation time 31676955 ps
CPU time 0.92 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 209924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593312653 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.593312653
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3880208342
Short name T1011
Test name
Test status
Simulation time 810956058 ps
CPU time 3.49 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:41 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38
80208342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p
assthru_mem_tl_intg_err.3880208342
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.429932592
Short name T998
Test name
Test status
Simulation time 29326840 ps
CPU time 0.83 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:39 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=429932592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_c
trl_same_csr_outstanding.429932592
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.199441215
Short name T1018
Test name
Test status
Simulation time 37704699 ps
CPU time 4.08 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199441215 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.199441215
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3823661580
Short name T130
Test name
Test status
Simulation time 348780103 ps
CPU time 2.55 seconds
Started Oct 03 11:36:37 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 221180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38236
61580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i
ntg_err.3823661580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3049588838
Short name T1010
Test name
Test status
Simulation time 100057819 ps
CPU time 1.27 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:41 AM UTC 24
Peak memory 220356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3049588838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3049588838
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3377816189
Short name T1004
Test name
Test status
Simulation time 42871935 ps
CPU time 0.8 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377816189 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.3377816189
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1193417767
Short name T1013
Test name
Test status
Simulation time 792956457 ps
CPU time 2.38 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:41 AM UTC 24
Peak memory 210912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11
93417767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p
assthru_mem_tl_intg_err.1193417767
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.949966189
Short name T1005
Test name
Test status
Simulation time 37729572 ps
CPU time 0.96 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:40 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=949966189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_c
trl_same_csr_outstanding.949966189
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1692108872
Short name T1020
Test name
Test status
Simulation time 163067986 ps
CPU time 2.88 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692108872 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.1692108872
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4287497020
Short name T1019
Test name
Test status
Simulation time 125839593 ps
CPU time 1.34 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 220096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=4287497020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.4287497020
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.445656230
Short name T1012
Test name
Test status
Simulation time 18626959 ps
CPU time 0.81 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:41 AM UTC 24
Peak memory 207660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445656230 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.445656230
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.157416725
Short name T1017
Test name
Test status
Simulation time 471209472 ps
CPU time 2.51 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 210904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15
7416725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_pa
ssthru_mem_tl_intg_err.157416725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4239088906
Short name T1014
Test name
Test status
Simulation time 45285658 ps
CPU time 0.98 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4239088906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_
ctrl_same_csr_outstanding.4239088906
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1758045136
Short name T1028
Test name
Test status
Simulation time 261593719 ps
CPU time 4.86 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:44 AM UTC 24
Peak memory 221300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758045136 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.1758045136
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.937667685
Short name T128
Test name
Test status
Simulation time 190624429 ps
CPU time 2.49 seconds
Started Oct 03 11:36:38 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 221228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93766
7685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_in
tg_err.937667685
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2236204937
Short name T1023
Test name
Test status
Simulation time 32199561 ps
CPU time 2.16 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:43 AM UTC 24
Peak memory 223360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2236204937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2236204937
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2241589870
Short name T1015
Test name
Test status
Simulation time 13396776 ps
CPU time 0.93 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241589870 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.2241589870
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1151029850
Short name T1022
Test name
Test status
Simulation time 204869887 ps
CPU time 2.39 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:43 AM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11
51029850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p
assthru_mem_tl_intg_err.1151029850
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2752148218
Short name T1016
Test name
Test status
Simulation time 99518982 ps
CPU time 0.92 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:42 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2752148218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_
ctrl_same_csr_outstanding.2752148218
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2153277505
Short name T1031
Test name
Test status
Simulation time 149907436 ps
CPU time 4.14 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:45 AM UTC 24
Peak memory 221264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153277505 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.2153277505
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4005655633
Short name T1025
Test name
Test status
Simulation time 301814803 ps
CPU time 2.44 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:43 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40056
55633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i
ntg_err.4005655633
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3942383770
Short name T1027
Test name
Test status
Simulation time 36771418 ps
CPU time 1.5 seconds
Started Oct 03 11:36:41 AM UTC 24
Finished Oct 03 11:36:44 AM UTC 24
Peak memory 220416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3942383770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3942383770
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3458746434
Short name T1021
Test name
Test status
Simulation time 20757784 ps
CPU time 0.77 seconds
Started Oct 03 11:36:41 AM UTC 24
Finished Oct 03 11:36:43 AM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458746434 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.3458746434
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.510690511
Short name T1029
Test name
Test status
Simulation time 823156182 ps
CPU time 3.59 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:45 AM UTC 24
Peak memory 211052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51
0690511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_pa
ssthru_mem_tl_intg_err.510690511
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4130786641
Short name T1024
Test name
Test status
Simulation time 19000946 ps
CPU time 1.04 seconds
Started Oct 03 11:36:41 AM UTC 24
Finished Oct 03 11:36:43 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4130786641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_
ctrl_same_csr_outstanding.4130786641
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.846241353
Short name T1026
Test name
Test status
Simulation time 64674743 ps
CPU time 2.64 seconds
Started Oct 03 11:36:40 AM UTC 24
Finished Oct 03 11:36:44 AM UTC 24
Peak memory 221404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846241353 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.846241353
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2578398908
Short name T1030
Test name
Test status
Simulation time 256763767 ps
CPU time 2.57 seconds
Started Oct 03 11:36:41 AM UTC 24
Finished Oct 03 11:36:45 AM UTC 24
Peak memory 221224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25783
98908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i
ntg_err.2578398908
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2873613649
Short name T80
Test name
Test status
Simulation time 16243081 ps
CPU time 0.95 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:27 AM UTC 24
Peak memory 209924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28736136
49 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alia
sing.2873613649
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4265853934
Short name T949
Test name
Test status
Simulation time 240388511 ps
CPU time 1.84 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:28 AM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42658539
34 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_
bash.4265853934
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2703286602
Short name T947
Test name
Test status
Simulation time 23775122 ps
CPU time 0.78 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:26 AM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27032866
02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r
eset.2703286602
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1661213618
Short name T948
Test name
Test status
Simulation time 92413860 ps
CPU time 1.19 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:27 AM UTC 24
Peak memory 219096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1661213618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1661213618
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.653455718
Short name T79
Test name
Test status
Simulation time 26778472 ps
CPU time 0.77 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:27 AM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653455718 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.653455718
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2458612137
Short name T82
Test name
Test status
Simulation time 196986906 ps
CPU time 2.27 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:28 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24
58612137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa
ssthru_mem_tl_intg_err.2458612137
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4055932902
Short name T99
Test name
Test status
Simulation time 127201329 ps
CPU time 0.98 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:27 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4055932902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c
trl_same_csr_outstanding.4055932902
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.465310454
Short name T950
Test name
Test status
Simulation time 65382100 ps
CPU time 2.16 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:28 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465310454 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.465310454
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2963262062
Short name T110
Test name
Test status
Simulation time 1036354788 ps
CPU time 2.69 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:28 AM UTC 24
Peak memory 221224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29632
62062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_in
tg_err.2963262062
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2681501945
Short name T953
Test name
Test status
Simulation time 18913974 ps
CPU time 0.85 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26815019
45 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia
sing.2681501945
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2944053480
Short name T956
Test name
Test status
Simulation time 256707222 ps
CPU time 1.45 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29440534
80 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_
bash.2944053480
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.268234598
Short name T951
Test name
Test status
Simulation time 18328004 ps
CPU time 0.81 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26823459
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_re
set.268234598
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3850808679
Short name T959
Test name
Test status
Simulation time 538453612 ps
CPU time 1.84 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:30 AM UTC 24
Peak memory 222144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3850808679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3850808679
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.875814571
Short name T100
Test name
Test status
Simulation time 21223922 ps
CPU time 0.72 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 209992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875814571 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.875814571
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1424929300
Short name T952
Test name
Test status
Simulation time 57610527 ps
CPU time 0.76 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1424929300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c
trl_same_csr_outstanding.1424929300
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4163112949
Short name T967
Test name
Test status
Simulation time 2896098115 ps
CPU time 5.63 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 221368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163112949 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.4163112949
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1827247995
Short name T121
Test name
Test status
Simulation time 133945036 ps
CPU time 2.27 seconds
Started Oct 03 11:36:25 AM UTC 24
Finished Oct 03 11:36:28 AM UTC 24
Peak memory 221176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18272
47995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in
tg_err.1827247995
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1803230796
Short name T958
Test name
Test status
Simulation time 49699708 ps
CPU time 0.99 seconds
Started Oct 03 11:36:28 AM UTC 24
Finished Oct 03 11:36:30 AM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18032307
96 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia
sing.1803230796
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.365121232
Short name T962
Test name
Test status
Simulation time 123169616 ps
CPU time 2.3 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36512123
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_b
ash.365121232
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3798421326
Short name T957
Test name
Test status
Simulation time 48340760 ps
CPU time 0.96 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37984213
26 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_r
eset.3798421326
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3194885415
Short name T960
Test name
Test status
Simulation time 100985620 ps
CPU time 1.56 seconds
Started Oct 03 11:36:28 AM UTC 24
Finished Oct 03 11:36:30 AM UTC 24
Peak memory 220424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3194885415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3194885415
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3085116258
Short name T954
Test name
Test status
Simulation time 27594935 ps
CPU time 0.97 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085116258 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.3085116258
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2597754811
Short name T973
Test name
Test status
Simulation time 1548549810 ps
CPU time 4.17 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25
97754811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pa
ssthru_mem_tl_intg_err.2597754811
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1030485303
Short name T955
Test name
Test status
Simulation time 18483491 ps
CPU time 0.83 seconds
Started Oct 03 11:36:28 AM UTC 24
Finished Oct 03 11:36:29 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1030485303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c
trl_same_csr_outstanding.1030485303
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4121357870
Short name T969
Test name
Test status
Simulation time 116229850 ps
CPU time 3.83 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 221292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121357870 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.4121357870
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.514188604
Short name T129
Test name
Test status
Simulation time 425186045 ps
CPU time 2.92 seconds
Started Oct 03 11:36:27 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51418
8604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_int
g_err.514188604
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3709687362
Short name T974
Test name
Test status
Simulation time 79155185 ps
CPU time 2.55 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 221356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3709687362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3709687362
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2033274963
Short name T961
Test name
Test status
Simulation time 11695974 ps
CPU time 0.75 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033274963 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.2033274963
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3410483004
Short name T963
Test name
Test status
Simulation time 291917797 ps
CPU time 2.31 seconds
Started Oct 03 11:36:28 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34
10483004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa
ssthru_mem_tl_intg_err.3410483004
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2497484819
Short name T966
Test name
Test status
Simulation time 74462460 ps
CPU time 1.22 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2497484819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_c
trl_same_csr_outstanding.2497484819
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3546514612
Short name T977
Test name
Test status
Simulation time 97885104 ps
CPU time 4.67 seconds
Started Oct 03 11:36:28 AM UTC 24
Finished Oct 03 11:36:33 AM UTC 24
Peak memory 223316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546514612 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3546514612
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3804938642
Short name T968
Test name
Test status
Simulation time 117157376 ps
CPU time 1.47 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 220096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3804938642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3804938642
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1469011187
Short name T964
Test name
Test status
Simulation time 21820810 ps
CPU time 0.88 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469011187 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.1469011187
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2143411843
Short name T84
Test name
Test status
Simulation time 2058995765 ps
CPU time 3.76 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21
43411843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa
ssthru_mem_tl_intg_err.2143411843
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4240018551
Short name T965
Test name
Test status
Simulation time 31419710 ps
CPU time 0.94 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:31 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4240018551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c
trl_same_csr_outstanding.4240018551
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1645759025
Short name T978
Test name
Test status
Simulation time 1162537250 ps
CPU time 3.65 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645759025 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.1645759025
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3051635421
Short name T127
Test name
Test status
Simulation time 97161942 ps
CPU time 1.56 seconds
Started Oct 03 11:36:29 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 220220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30516
35421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in
tg_err.3051635421
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2711988385
Short name T979
Test name
Test status
Simulation time 59787743 ps
CPU time 1.9 seconds
Started Oct 03 11:36:30 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 220380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2711988385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2711988385
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3900474988
Short name T970
Test name
Test status
Simulation time 13904653 ps
CPU time 0.9 seconds
Started Oct 03 11:36:30 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900474988 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.3900474988
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4212714207
Short name T81
Test name
Test status
Simulation time 815989649 ps
CPU time 2.51 seconds
Started Oct 03 11:36:30 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
12714207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pa
ssthru_mem_tl_intg_err.4212714207
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.474455258
Short name T971
Test name
Test status
Simulation time 32146478 ps
CPU time 0.85 seconds
Started Oct 03 11:36:30 AM UTC 24
Finished Oct 03 11:36:32 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=474455258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ct
rl_same_csr_outstanding.474455258
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3010899086
Short name T972
Test name
Test status
Simulation time 175351214 ps
CPU time 4.17 seconds
Started Oct 03 11:36:30 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 211096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010899086 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.3010899086
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4045806331
Short name T123
Test name
Test status
Simulation time 193731377 ps
CPU time 1.72 seconds
Started Oct 03 11:36:30 AM UTC 24
Finished Oct 03 11:36:33 AM UTC 24
Peak memory 220220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40458
06331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in
tg_err.4045806331
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3602386837
Short name T980
Test name
Test status
Simulation time 59069563 ps
CPU time 1.19 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 220096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3602386837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3602386837
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1110993157
Short name T975
Test name
Test status
Simulation time 22749581 ps
CPU time 0.82 seconds
Started Oct 03 11:36:31 AM UTC 24
Finished Oct 03 11:36:33 AM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110993157 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.1110993157
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3953949579
Short name T88
Test name
Test status
Simulation time 377833720 ps
CPU time 2.55 seconds
Started Oct 03 11:36:31 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 210904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
53949579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa
ssthru_mem_tl_intg_err.3953949579
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2886940286
Short name T976
Test name
Test status
Simulation time 33472102 ps
CPU time 0.82 seconds
Started Oct 03 11:36:31 AM UTC 24
Finished Oct 03 11:36:33 AM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2886940286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c
trl_same_csr_outstanding.2886940286
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1065542002
Short name T991
Test name
Test status
Simulation time 157160250 ps
CPU time 5.4 seconds
Started Oct 03 11:36:31 AM UTC 24
Finished Oct 03 11:36:37 AM UTC 24
Peak memory 211160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065542002 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1065542002
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3359116759
Short name T125
Test name
Test status
Simulation time 1099604846 ps
CPU time 2.73 seconds
Started Oct 03 11:36:31 AM UTC 24
Finished Oct 03 11:36:35 AM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33591
16759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in
tg_err.3359116759
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1886787010
Short name T981
Test name
Test status
Simulation time 28421456 ps
CPU time 1.06 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 207720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886787010 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.1886787010
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2133666748
Short name T89
Test name
Test status
Simulation time 3911282518 ps
CPU time 2.81 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21
33666748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa
ssthru_mem_tl_intg_err.2133666748
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1186475926
Short name T982
Test name
Test status
Simulation time 92946780 ps
CPU time 1.11 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:34 AM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1186475926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c
trl_same_csr_outstanding.1186475926
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3640392754
Short name T992
Test name
Test status
Simulation time 528674916 ps
CPU time 4.5 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:38 AM UTC 24
Peak memory 221420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640392754 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.3640392754
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.357160726
Short name T126
Test name
Test status
Simulation time 291403209 ps
CPU time 3.08 seconds
Started Oct 03 11:36:32 AM UTC 24
Finished Oct 03 11:36:36 AM UTC 24
Peak memory 211060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35716
0726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_int
g_err.357160726
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1962891339
Short name T40
Test name
Test status
Simulation time 1213338579 ps
CPU time 348.8 seconds
Started Oct 03 11:45:34 AM UTC 24
Finished Oct 03 11:51:27 AM UTC 24
Peak memory 348328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962891339 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_
key_req.1962891339
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.4005773003
Short name T17
Test name
Test status
Simulation time 1839037510 ps
CPU time 39.94 seconds
Started Oct 03 11:45:32 AM UTC 24
Finished Oct 03 11:46:14 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005773003 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.4005773003
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.531121547
Short name T1
Test name
Test status
Simulation time 141834590 ps
CPU time 3.1 seconds
Started Oct 03 11:45:34 AM UTC 24
Finished Oct 03 11:45:38 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531121547 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.531121547
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3119727505
Short name T36
Test name
Test status
Simulation time 324205051 ps
CPU time 27.27 seconds
Started Oct 03 11:45:34 AM UTC 24
Finished Oct 03 11:46:02 AM UTC 24
Peak memory 295092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
119727505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max
_throughput.3119727505
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1846382106
Short name T436
Test name
Test status
Simulation time 257895990104 ps
CPU time 1817.23 seconds
Started Oct 03 11:45:31 AM UTC 24
Finished Oct 03 12:16:09 PM UTC 24
Peak memory 385208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846382106 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.1846382106
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1950497450
Short name T37
Test name
Test status
Simulation time 619048926 ps
CPU time 70.93 seconds
Started Oct 03 11:45:32 AM UTC 24
Finished Oct 03 11:46:45 AM UTC 24
Peak memory 364716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950497450 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.1950497450
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.859258803
Short name T116
Test name
Test status
Simulation time 77884541095 ps
CPU time 1150.94 seconds
Started Oct 03 11:45:36 AM UTC 24
Finished Oct 03 12:05:00 PM UTC 24
Peak memory 383236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859258803 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.859258803
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2600090004
Short name T10
Test name
Test status
Simulation time 499337462 ps
CPU time 21.25 seconds
Started Oct 03 11:45:31 AM UTC 24
Finished Oct 03 11:45:53 AM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600090004 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2600090004
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3693133423
Short name T118
Test name
Test status
Simulation time 22122580193 ps
CPU time 1533.4 seconds
Started Oct 03 11:45:39 AM UTC 24
Finished Oct 03 12:11:29 PM UTC 24
Peak memory 393484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369313342
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.3693133423
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2605751634
Short name T104
Test name
Test status
Simulation time 2338950950 ps
CPU time 283.31 seconds
Started Oct 03 11:45:32 AM UTC 24
Finished Oct 03 11:50:20 AM UTC 24
Peak memory 211972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605751634 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.2605751634
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2039612352
Short name T55
Test name
Test status
Simulation time 547306952 ps
CPU time 60.59 seconds
Started Oct 03 11:45:34 AM UTC 24
Finished Oct 03 11:46:36 AM UTC 24
Peak memory 332032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2039612352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th
roughput_w_partial_write.2039612352
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3353286180
Short name T235
Test name
Test status
Simulation time 2492826171 ps
CPU time 670.34 seconds
Started Oct 03 11:45:48 AM UTC 24
Finished Oct 03 11:57:06 AM UTC 24
Peak memory 383228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353286180 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_
key_req.3353286180
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2346517468
Short name T12
Test name
Test status
Simulation time 21096903 ps
CPU time 0.99 seconds
Started Oct 03 11:46:03 AM UTC 24
Finished Oct 03 11:46:05 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346517468 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2346517468
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.4074186151
Short name T27
Test name
Test status
Simulation time 630421487 ps
CPU time 175.47 seconds
Started Oct 03 11:45:48 AM UTC 24
Finished Oct 03 11:48:47 AM UTC 24
Peak memory 348288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074186151 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.4074186151
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3886787842
Short name T31
Test name
Test status
Simulation time 80751754 ps
CPU time 18.1 seconds
Started Oct 03 11:45:46 AM UTC 24
Finished Oct 03 11:46:05 AM UTC 24
Peak memory 274556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
886787842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max
_throughput.3886787842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.525624264
Short name T35
Test name
Test status
Simulation time 347368096 ps
CPU time 4.8 seconds
Started Oct 03 11:45:54 AM UTC 24
Finished Oct 03 11:46:01 AM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525624264 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.525624264
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4156801437
Short name T38
Test name
Test status
Simulation time 1224527244 ps
CPU time 16.48 seconds
Started Oct 03 11:45:53 AM UTC 24
Finished Oct 03 11:46:12 AM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156801437 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.4156801437
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.455133541
Short name T152
Test name
Test status
Simulation time 6292556438 ps
CPU time 311.81 seconds
Started Oct 03 11:45:45 AM UTC 24
Finished Oct 03 11:51:01 AM UTC 24
Peak memory 352480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455133541 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.455133541
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.527125251
Short name T30
Test name
Test status
Simulation time 1160444623 ps
CPU time 19.57 seconds
Started Oct 03 11:45:46 AM UTC 24
Finished Oct 03 11:46:07 AM UTC 24
Peak memory 212412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527125251 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.527125251
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1531622283
Short name T148
Test name
Test status
Simulation time 10645722590 ps
CPU time 296.85 seconds
Started Oct 03 11:45:46 AM UTC 24
Finished Oct 03 11:50:47 AM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531622283 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce
ss_b2b.1531622283
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2297896132
Short name T11
Test name
Test status
Simulation time 74990095 ps
CPU time 1.18 seconds
Started Oct 03 11:45:53 AM UTC 24
Finished Oct 03 11:45:56 AM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297896132 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2297896132
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.244966595
Short name T19
Test name
Test status
Simulation time 31622535675 ps
CPU time 354.23 seconds
Started Oct 03 11:45:50 AM UTC 24
Finished Oct 03 11:51:50 AM UTC 24
Peak memory 379064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244966595 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.244966595
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1841025722
Short name T15
Test name
Test status
Simulation time 636123297 ps
CPU time 5.94 seconds
Started Oct 03 11:46:02 AM UTC 24
Finished Oct 03 11:46:09 AM UTC 24
Peak memory 248076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841025722 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1841025722
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.487135890
Short name T9
Test name
Test status
Simulation time 236319653 ps
CPU time 10.45 seconds
Started Oct 03 11:45:41 AM UTC 24
Finished Oct 03 11:45:53 AM UTC 24
Peak memory 260328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487135890 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.487135890
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.544702130
Short name T712
Test name
Test status
Simulation time 37052313696 ps
CPU time 3650.92 seconds
Started Oct 03 11:46:01 AM UTC 24
Finished Oct 03 12:47:34 PM UTC 24
Peak memory 395068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544702130
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.544702130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2365236749
Short name T195
Test name
Test status
Simulation time 3644223314 ps
CPU time 370.44 seconds
Started Oct 03 11:45:45 AM UTC 24
Finished Oct 03 11:52:01 AM UTC 24
Peak memory 212332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365236749 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2365236749
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3930443443
Short name T153
Test name
Test status
Simulation time 527886969 ps
CPU time 63.46 seconds
Started Oct 03 11:45:48 AM UTC 24
Finished Oct 03 11:46:53 AM UTC 24
Peak memory 362688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3930443443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th
roughput_w_partial_write.3930443443
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2367101278
Short name T305
Test name
Test status
Simulation time 6605003118 ps
CPU time 501.16 seconds
Started Oct 03 11:55:28 AM UTC 24
Finished Oct 03 12:03:56 PM UTC 24
Peak memory 377056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367101278 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during
_key_req.2367101278
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.992503882
Short name T230
Test name
Test status
Simulation time 44605912 ps
CPU time 0.98 seconds
Started Oct 03 11:56:08 AM UTC 24
Finished Oct 03 11:56:10 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992503882 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.992503882
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.3561524064
Short name T221
Test name
Test status
Simulation time 9883901405 ps
CPU time 71.09 seconds
Started Oct 03 11:54:01 AM UTC 24
Finished Oct 03 11:55:14 AM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561524064 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.3561524064
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.16166274
Short name T431
Test name
Test status
Simulation time 177027105265 ps
CPU time 1201.05 seconds
Started Oct 03 11:55:40 AM UTC 24
Finished Oct 03 12:15:56 PM UTC 24
Peak memory 381112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16166274 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.16166274
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2077172098
Short name T223
Test name
Test status
Simulation time 560107228 ps
CPU time 6.43 seconds
Started Oct 03 11:55:20 AM UTC 24
Finished Oct 03 11:55:28 AM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077172098 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.2077172098
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1094075236
Short name T229
Test name
Test status
Simulation time 490304029 ps
CPU time 52.78 seconds
Started Oct 03 11:55:13 AM UTC 24
Finished Oct 03 11:56:07 AM UTC 24
Peak memory 366724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
094075236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma
x_throughput.1094075236
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2740691661
Short name T231
Test name
Test status
Simulation time 193906626 ps
CPU time 8.14 seconds
Started Oct 03 11:56:04 AM UTC 24
Finished Oct 03 11:56:14 AM UTC 24
Peak memory 222580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740691661 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.2740691661
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.817472333
Short name T227
Test name
Test status
Simulation time 591488680 ps
CPU time 8.45 seconds
Started Oct 03 11:55:55 AM UTC 24
Finished Oct 03 11:56:05 AM UTC 24
Peak memory 222544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817472333 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.817472333
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.589259469
Short name T232
Test name
Test status
Simulation time 3421486064 ps
CPU time 150.69 seconds
Started Oct 03 11:53:54 AM UTC 24
Finished Oct 03 11:56:27 AM UTC 24
Peak memory 381172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589259469 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.589259469
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3974636755
Short name T219
Test name
Test status
Simulation time 322510896 ps
CPU time 16.62 seconds
Started Oct 03 11:54:49 AM UTC 24
Finished Oct 03 11:55:07 AM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974636755 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.3974636755
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4173169413
Short name T247
Test name
Test status
Simulation time 16007842607 ps
CPU time 199.61 seconds
Started Oct 03 11:55:08 AM UTC 24
Finished Oct 03 11:58:31 AM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173169413 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc
ess_b2b.4173169413
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3091494650
Short name T225
Test name
Test status
Simulation time 30041406 ps
CPU time 1.32 seconds
Started Oct 03 11:55:52 AM UTC 24
Finished Oct 03 11:55:54 AM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091494650 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3091494650
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.3309304162
Short name T408
Test name
Test status
Simulation time 28329888500 ps
CPU time 1075.17 seconds
Started Oct 03 11:55:47 AM UTC 24
Finished Oct 03 12:13:53 PM UTC 24
Peak memory 385256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309304162 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3309304162
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.3225834475
Short name T218
Test name
Test status
Simulation time 189893241 ps
CPU time 7.28 seconds
Started Oct 03 11:53:51 AM UTC 24
Finished Oct 03 11:54:00 AM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225834475 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3225834475
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2518199716
Short name T651
Test name
Test status
Simulation time 44413945700 ps
CPU time 2638.69 seconds
Started Oct 03 11:56:06 AM UTC 24
Finished Oct 03 12:40:34 PM UTC 24
Peak memory 385284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251819971
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.2518199716
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.734975864
Short name T238
Test name
Test status
Simulation time 2474617217 ps
CPU time 237.97 seconds
Started Oct 03 11:54:03 AM UTC 24
Finished Oct 03 11:58:04 AM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734975864 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.734975864
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3874404036
Short name T228
Test name
Test status
Simulation time 433770763 ps
CPU time 50.9 seconds
Started Oct 03 11:55:14 AM UTC 24
Finished Oct 03 11:56:07 AM UTC 24
Peak memory 313460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3874404036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t
hroughput_w_partial_write.3874404036
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.342993316
Short name T417
Test name
Test status
Simulation time 6836701208 ps
CPU time 1046.65 seconds
Started Oct 03 11:57:26 AM UTC 24
Finished Oct 03 12:15:04 PM UTC 24
Peak memory 383204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342993316 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_
key_req.342993316
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3203442542
Short name T242
Test name
Test status
Simulation time 35923803 ps
CPU time 0.88 seconds
Started Oct 03 11:58:11 AM UTC 24
Finished Oct 03 11:58:13 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203442542 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3203442542
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.340749514
Short name T233
Test name
Test status
Simulation time 2354346720 ps
CPU time 44.68 seconds
Started Oct 03 11:56:15 AM UTC 24
Finished Oct 03 11:57:01 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340749514 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.340749514
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2486357538
Short name T267
Test name
Test status
Simulation time 9869373241 ps
CPU time 167.79 seconds
Started Oct 03 11:57:37 AM UTC 24
Finished Oct 03 12:00:27 PM UTC 24
Peak memory 372916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486357538 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2486357538
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.217920838
Short name T23
Test name
Test status
Simulation time 2354946119 ps
CPU time 15.44 seconds
Started Oct 03 11:57:09 AM UTC 24
Finished Oct 03 11:57:25 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217920838 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.217920838
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1915063801
Short name T239
Test name
Test status
Simulation time 306529700 ps
CPU time 59.82 seconds
Started Oct 03 11:57:06 AM UTC 24
Finished Oct 03 11:58:08 AM UTC 24
Peak memory 329824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
915063801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ma
x_throughput.1915063801
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1219024410
Short name T240
Test name
Test status
Simulation time 61612356 ps
CPU time 4.43 seconds
Started Oct 03 11:58:05 AM UTC 24
Finished Oct 03 11:58:11 AM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219024410 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.1219024410
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1125920685
Short name T241
Test name
Test status
Simulation time 238959353 ps
CPU time 7.66 seconds
Started Oct 03 11:58:02 AM UTC 24
Finished Oct 03 11:58:11 AM UTC 24
Peak memory 222540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125920685 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.1125920685
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1150972562
Short name T280
Test name
Test status
Simulation time 6384420279 ps
CPU time 333.92 seconds
Started Oct 03 11:56:11 AM UTC 24
Finished Oct 03 12:01:49 PM UTC 24
Peak memory 381152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150972562 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.1150972562
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.3908199363
Short name T236
Test name
Test status
Simulation time 249562535 ps
CPU time 26.71 seconds
Started Oct 03 11:56:40 AM UTC 24
Finished Oct 03 11:57:08 AM UTC 24
Peak memory 289020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908199363 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.3908199363
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2291893194
Short name T314
Test name
Test status
Simulation time 28604285528 ps
CPU time 459.2 seconds
Started Oct 03 11:57:02 AM UTC 24
Finished Oct 03 12:04:48 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291893194 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc
ess_b2b.2291893194
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1044015632
Short name T237
Test name
Test status
Simulation time 47883329 ps
CPU time 0.99 seconds
Started Oct 03 11:57:59 AM UTC 24
Finished Oct 03 11:58:01 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044015632 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1044015632
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.1693879682
Short name T117
Test name
Test status
Simulation time 33850510488 ps
CPU time 551.08 seconds
Started Oct 03 11:57:41 AM UTC 24
Finished Oct 03 12:06:59 PM UTC 24
Peak memory 374932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693879682 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1693879682
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.912394452
Short name T154
Test name
Test status
Simulation time 659797719 ps
CPU time 85.48 seconds
Started Oct 03 11:56:09 AM UTC 24
Finished Oct 03 11:57:36 AM UTC 24
Peak memory 360620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912394452 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.912394452
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2631402353
Short name T147
Test name
Test status
Simulation time 19074123568 ps
CPU time 771.03 seconds
Started Oct 03 11:58:11 AM UTC 24
Finished Oct 03 12:11:11 PM UTC 24
Peak memory 370872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263140235
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.2631402353
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1989191165
Short name T262
Test name
Test status
Simulation time 1725367901 ps
CPU time 195.67 seconds
Started Oct 03 11:56:28 AM UTC 24
Finished Oct 03 11:59:47 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989191165 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.1989191165
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2883242526
Short name T248
Test name
Test status
Simulation time 863621770 ps
CPU time 81.88 seconds
Started Oct 03 11:57:07 AM UTC 24
Finished Oct 03 11:58:31 AM UTC 24
Peak memory 381116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2883242526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t
hroughput_w_partial_write.2883242526
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2536257950
Short name T404
Test name
Test status
Simulation time 2556394385 ps
CPU time 890.55 seconds
Started Oct 03 11:58:38 AM UTC 24
Finished Oct 03 12:13:39 PM UTC 24
Peak memory 381116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536257950 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during
_key_req.2536257950
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3198755602
Short name T259
Test name
Test status
Simulation time 40527272 ps
CPU time 0.98 seconds
Started Oct 03 11:59:00 AM UTC 24
Finished Oct 03 11:59:02 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198755602 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3198755602
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.397658698
Short name T258
Test name
Test status
Simulation time 2680990764 ps
CPU time 40.06 seconds
Started Oct 03 11:58:21 AM UTC 24
Finished Oct 03 11:59:02 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397658698 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.397658698
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3041664504
Short name T251
Test name
Test status
Simulation time 4352942499 ps
CPU time 14.71 seconds
Started Oct 03 11:58:32 AM UTC 24
Finished Oct 03 11:58:48 AM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041664504 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.3041664504
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2238204911
Short name T253
Test name
Test status
Simulation time 83897985 ps
CPU time 21.17 seconds
Started Oct 03 11:58:29 AM UTC 24
Finished Oct 03 11:58:51 AM UTC 24
Peak memory 288896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
238204911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma
x_throughput.2238204911
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2864441994
Short name T256
Test name
Test status
Simulation time 177728212 ps
CPU time 5.92 seconds
Started Oct 03 11:58:53 AM UTC 24
Finished Oct 03 11:59:00 AM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864441994 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2864441994
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.793692881
Short name T257
Test name
Test status
Simulation time 908479217 ps
CPU time 8.84 seconds
Started Oct 03 11:58:52 AM UTC 24
Finished Oct 03 11:59:02 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793692881 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.793692881
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2679015686
Short name T310
Test name
Test status
Simulation time 4104307369 ps
CPU time 369.3 seconds
Started Oct 03 11:58:19 AM UTC 24
Finished Oct 03 12:04:33 PM UTC 24
Peak memory 379060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679015686 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.2679015686
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3661199781
Short name T255
Test name
Test status
Simulation time 241204308 ps
CPU time 30.39 seconds
Started Oct 03 11:58:25 AM UTC 24
Finished Oct 03 11:58:57 AM UTC 24
Peak memory 321788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661199781 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.3661199781
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.4248913831
Short name T334
Test name
Test status
Simulation time 13353153219 ps
CPU time 442.53 seconds
Started Oct 03 11:58:27 AM UTC 24
Finished Oct 03 12:05:56 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248913831 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acc
ess_b2b.4248913831
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2347880151
Short name T252
Test name
Test status
Simulation time 57372964 ps
CPU time 1.2 seconds
Started Oct 03 11:58:49 AM UTC 24
Finished Oct 03 11:58:51 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347880151 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2347880151
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.1301021932
Short name T143
Test name
Test status
Simulation time 16081684173 ps
CPU time 146.31 seconds
Started Oct 03 11:58:45 AM UTC 24
Finished Oct 03 12:01:14 PM UTC 24
Peak memory 274668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301021932 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1301021932
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.4283273589
Short name T243
Test name
Test status
Simulation time 274398087 ps
CPU time 2.11 seconds
Started Oct 03 11:58:14 AM UTC 24
Finished Oct 03 11:58:18 AM UTC 24
Peak memory 212232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283273589 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.4283273589
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2641418093
Short name T386
Test name
Test status
Simulation time 5461159450 ps
CPU time 753.66 seconds
Started Oct 03 11:58:58 AM UTC 24
Finished Oct 03 12:11:41 PM UTC 24
Peak memory 362756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264141809
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.2641418093
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2677374610
Short name T287
Test name
Test status
Simulation time 9563563921 ps
CPU time 229.95 seconds
Started Oct 03 11:58:25 AM UTC 24
Finished Oct 03 12:02:19 PM UTC 24
Peak memory 212504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677374610 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.2677374610
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1148986578
Short name T254
Test name
Test status
Simulation time 88124420 ps
CPU time 19.16 seconds
Started Oct 03 11:58:32 AM UTC 24
Finished Oct 03 11:58:52 AM UTC 24
Peak memory 280684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1148986578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t
hroughput_w_partial_write.1148986578
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.397576456
Short name T322
Test name
Test status
Simulation time 25234283969 ps
CPU time 301.59 seconds
Started Oct 03 12:00:16 PM UTC 24
Finished Oct 03 12:05:22 PM UTC 24
Peak memory 358660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397576456 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_
key_req.397576456
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2633891217
Short name T271
Test name
Test status
Simulation time 24915045 ps
CPU time 1.02 seconds
Started Oct 03 12:00:42 PM UTC 24
Finished Oct 03 12:00:44 PM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633891217 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2633891217
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.685367792
Short name T266
Test name
Test status
Simulation time 4761241168 ps
CPU time 78.54 seconds
Started Oct 03 11:59:03 AM UTC 24
Finished Oct 03 12:00:24 PM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685367792 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.685367792
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.2680792055
Short name T464
Test name
Test status
Simulation time 19222884085 ps
CPU time 1122.39 seconds
Started Oct 03 12:00:22 PM UTC 24
Finished Oct 03 12:19:18 PM UTC 24
Peak memory 383236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680792055 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.2680792055
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3947591048
Short name T265
Test name
Test status
Simulation time 1950627664 ps
CPU time 9.65 seconds
Started Oct 03 12:00:11 PM UTC 24
Finished Oct 03 12:00:22 PM UTC 24
Peak memory 212144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947591048 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.3947591048
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3112346260
Short name T264
Test name
Test status
Simulation time 249156195 ps
CPU time 26.34 seconds
Started Oct 03 11:59:48 AM UTC 24
Finished Oct 03 12:00:15 PM UTC 24
Peak memory 295088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
112346260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ma
x_throughput.3112346260
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1647993956
Short name T269
Test name
Test status
Simulation time 164775894 ps
CPU time 3.55 seconds
Started Oct 03 12:00:34 PM UTC 24
Finished Oct 03 12:00:38 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647993956 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.1647993956
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3157223268
Short name T272
Test name
Test status
Simulation time 548336640 ps
CPU time 11.59 seconds
Started Oct 03 12:00:31 PM UTC 24
Finished Oct 03 12:00:45 PM UTC 24
Peak memory 222476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157223268 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3157223268
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.4103105651
Short name T270
Test name
Test status
Simulation time 534241250 ps
CPU time 96.08 seconds
Started Oct 03 11:59:03 AM UTC 24
Finished Oct 03 12:00:41 PM UTC 24
Peak memory 362692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103105651 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.4103105651
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1918695367
Short name T260
Test name
Test status
Simulation time 892360982 ps
CPU time 18.11 seconds
Started Oct 03 11:59:22 AM UTC 24
Finished Oct 03 11:59:42 AM UTC 24
Peak memory 212228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918695367 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.1918695367
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.1933132997
Short name T351
Test name
Test status
Simulation time 51014771653 ps
CPU time 491.65 seconds
Started Oct 03 11:59:44 AM UTC 24
Finished Oct 03 12:08:02 PM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933132997 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc
ess_b2b.1933132997
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.712563248
Short name T268
Test name
Test status
Simulation time 85811966 ps
CPU time 1.04 seconds
Started Oct 03 12:00:28 PM UTC 24
Finished Oct 03 12:00:30 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712563248 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.712563248
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.4058191544
Short name T119
Test name
Test status
Simulation time 39273085727 ps
CPU time 723.5 seconds
Started Oct 03 12:00:24 PM UTC 24
Finished Oct 03 12:12:36 PM UTC 24
Peak memory 381104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058191544 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.4058191544
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3472335158
Short name T155
Test name
Test status
Simulation time 1537442470 ps
CPU time 89.34 seconds
Started Oct 03 11:59:02 AM UTC 24
Finished Oct 03 12:00:33 PM UTC 24
Peak memory 377152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472335158 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3472335158
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1515069532
Short name T291
Test name
Test status
Simulation time 6435009471 ps
CPU time 112.56 seconds
Started Oct 03 12:00:39 PM UTC 24
Finished Oct 03 12:02:34 PM UTC 24
Peak memory 303292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151506953
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.1515069532
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.3304123052
Short name T300
Test name
Test status
Simulation time 2395562421 ps
CPU time 244.19 seconds
Started Oct 03 11:59:17 AM UTC 24
Finished Oct 03 12:03:25 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304123052 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.3304123052
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1925762762
Short name T263
Test name
Test status
Simulation time 448630186 ps
CPU time 21.55 seconds
Started Oct 03 11:59:48 AM UTC 24
Finished Oct 03 12:00:10 PM UTC 24
Peak memory 286884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1925762762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t
hroughput_w_partial_write.1925762762
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2292495798
Short name T425
Test name
Test status
Simulation time 3759790427 ps
CPU time 837.27 seconds
Started Oct 03 12:01:34 PM UTC 24
Finished Oct 03 12:15:41 PM UTC 24
Peak memory 381084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292495798 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during
_key_req.2292495798
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3971209105
Short name T285
Test name
Test status
Simulation time 18965167 ps
CPU time 0.88 seconds
Started Oct 03 12:02:11 PM UTC 24
Finished Oct 03 12:02:12 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971209105 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3971209105
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.34048652
Short name T275
Test name
Test status
Simulation time 960584013 ps
CPU time 19.87 seconds
Started Oct 03 12:00:52 PM UTC 24
Finished Oct 03 12:01:13 PM UTC 24
Peak memory 212168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34048652 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.34048652
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.484124682
Short name T356
Test name
Test status
Simulation time 18667216714 ps
CPU time 391.81 seconds
Started Oct 03 12:01:44 PM UTC 24
Finished Oct 03 12:08:21 PM UTC 24
Peak memory 383240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484124682 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.484124682
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1999525873
Short name T279
Test name
Test status
Simulation time 92093025 ps
CPU time 1.88 seconds
Started Oct 03 12:01:30 PM UTC 24
Finished Oct 03 12:01:33 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999525873 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.1999525873
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4034694836
Short name T277
Test name
Test status
Simulation time 46371885 ps
CPU time 3.08 seconds
Started Oct 03 12:01:21 PM UTC 24
Finished Oct 03 12:01:25 PM UTC 24
Peak memory 228740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
034694836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma
x_throughput.4034694836
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2533074962
Short name T283
Test name
Test status
Simulation time 158233441 ps
CPU time 3.84 seconds
Started Oct 03 12:01:59 PM UTC 24
Finished Oct 03 12:02:04 PM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533074962 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2533074962
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4227898166
Short name T286
Test name
Test status
Simulation time 1308783942 ps
CPU time 16.29 seconds
Started Oct 03 12:01:57 PM UTC 24
Finished Oct 03 12:02:15 PM UTC 24
Peak memory 222480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227898166 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.4227898166
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.786271713
Short name T367
Test name
Test status
Simulation time 2231666403 ps
CPU time 502.02 seconds
Started Oct 03 12:00:46 PM UTC 24
Finished Oct 03 12:09:15 PM UTC 24
Peak memory 385344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786271713 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.786271713
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1192498956
Short name T282
Test name
Test status
Simulation time 405992037 ps
CPU time 41.75 seconds
Started Oct 03 12:01:14 PM UTC 24
Finished Oct 03 12:01:58 PM UTC 24
Peak memory 303268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192498956 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1192498956
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2616709143
Short name T345
Test name
Test status
Simulation time 32696668278 ps
CPU time 324.9 seconds
Started Oct 03 12:01:15 PM UTC 24
Finished Oct 03 12:06:45 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616709143 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acc
ess_b2b.2616709143
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1508710985
Short name T281
Test name
Test status
Simulation time 42369177 ps
CPU time 1.15 seconds
Started Oct 03 12:01:54 PM UTC 24
Finished Oct 03 12:01:56 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508710985 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1508710985
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.854205426
Short name T415
Test name
Test status
Simulation time 11869394382 ps
CPU time 771.12 seconds
Started Oct 03 12:01:50 PM UTC 24
Finished Oct 03 12:14:51 PM UTC 24
Peak memory 383212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854205426 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.854205426
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.4127088886
Short name T274
Test name
Test status
Simulation time 188296210 ps
CPU time 5.99 seconds
Started Oct 03 12:00:45 PM UTC 24
Finished Oct 03 12:00:52 PM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127088886 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.4127088886
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1459801341
Short name T411
Test name
Test status
Simulation time 11896332879 ps
CPU time 731.21 seconds
Started Oct 03 12:02:05 PM UTC 24
Finished Oct 03 12:14:25 PM UTC 24
Peak memory 385268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145980134
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.1459801341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.1709834557
Short name T294
Test name
Test status
Simulation time 1223679283 ps
CPU time 115.21 seconds
Started Oct 03 12:00:53 PM UTC 24
Finished Oct 03 12:02:51 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709834557 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.1709834557
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2553184420
Short name T278
Test name
Test status
Simulation time 68733670 ps
CPU time 1.99 seconds
Started Oct 03 12:01:26 PM UTC 24
Finished Oct 03 12:01:29 PM UTC 24
Peak memory 221416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2553184420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_t
hroughput_w_partial_write.2553184420
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1806083109
Short name T412
Test name
Test status
Simulation time 2697243236 ps
CPU time 697.55 seconds
Started Oct 03 12:02:46 PM UTC 24
Finished Oct 03 12:14:32 PM UTC 24
Peak memory 381224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806083109 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during
_key_req.1806083109
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.235466166
Short name T302
Test name
Test status
Simulation time 23737864 ps
CPU time 0.95 seconds
Started Oct 03 12:03:26 PM UTC 24
Finished Oct 03 12:03:28 PM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235466166 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.235466166
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.667914698
Short name T301
Test name
Test status
Simulation time 3614284005 ps
CPU time 70.16 seconds
Started Oct 03 12:02:16 PM UTC 24
Finished Oct 03 12:03:28 PM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667914698 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.667914698
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.343846631
Short name T145
Test name
Test status
Simulation time 7750718890 ps
CPU time 484.53 seconds
Started Oct 03 12:02:48 PM UTC 24
Finished Oct 03 12:10:59 PM UTC 24
Peak memory 360712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343846631 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.343846631
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2657434041
Short name T292
Test name
Test status
Simulation time 426118402 ps
CPU time 9.46 seconds
Started Oct 03 12:02:35 PM UTC 24
Finished Oct 03 12:02:45 PM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657434041 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.2657434041
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1633776776
Short name T293
Test name
Test status
Simulation time 352619639 ps
CPU time 22.22 seconds
Started Oct 03 12:02:23 PM UTC 24
Finished Oct 03 12:02:47 PM UTC 24
Peak memory 299184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
633776776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma
x_throughput.1633776776
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2300854986
Short name T298
Test name
Test status
Simulation time 395197671 ps
CPU time 3.36 seconds
Started Oct 03 12:03:06 PM UTC 24
Finished Oct 03 12:03:11 PM UTC 24
Peak memory 222444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300854986 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.2300854986
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1483501185
Short name T299
Test name
Test status
Simulation time 1197199222 ps
CPU time 12.42 seconds
Started Oct 03 12:03:03 PM UTC 24
Finished Oct 03 12:03:17 PM UTC 24
Peak memory 222532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483501185 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.1483501185
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2101991689
Short name T333
Test name
Test status
Simulation time 2328450984 ps
CPU time 215.41 seconds
Started Oct 03 12:02:15 PM UTC 24
Finished Oct 03 12:05:53 PM UTC 24
Peak memory 376984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101991689 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.2101991689
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1213494998
Short name T290
Test name
Test status
Simulation time 229137292 ps
CPU time 6.85 seconds
Started Oct 03 12:02:20 PM UTC 24
Finished Oct 03 12:02:28 PM UTC 24
Peak memory 237796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213494998 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.1213494998
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1717766237
Short name T383
Test name
Test status
Simulation time 12987455457 ps
CPU time 541.88 seconds
Started Oct 03 12:02:22 PM UTC 24
Finished Oct 03 12:11:31 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717766237 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acc
ess_b2b.1717766237
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3661732227
Short name T297
Test name
Test status
Simulation time 28913080 ps
CPU time 1.09 seconds
Started Oct 03 12:03:03 PM UTC 24
Finished Oct 03 12:03:05 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661732227 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3661732227
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2875527194
Short name T398
Test name
Test status
Simulation time 9315059062 ps
CPU time 597.67 seconds
Started Oct 03 12:02:52 PM UTC 24
Finished Oct 03 12:12:57 PM UTC 24
Peak memory 383340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875527194 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2875527194
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.4080942571
Short name T288
Test name
Test status
Simulation time 129392051 ps
CPU time 6.77 seconds
Started Oct 03 12:02:14 PM UTC 24
Finished Oct 03 12:02:22 PM UTC 24
Peak memory 233652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080942571 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.4080942571
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3245980457
Short name T753
Test name
Test status
Simulation time 16674777790 ps
CPU time 2971.38 seconds
Started Oct 03 12:03:17 PM UTC 24
Finished Oct 03 12:53:22 PM UTC 24
Peak memory 385288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324598045
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.3245980457
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1008613413
Short name T304
Test name
Test status
Simulation time 239378884 ps
CPU time 41.55 seconds
Started Oct 03 12:03:11 PM UTC 24
Finished Oct 03 12:03:54 PM UTC 24
Peak memory 278692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008613413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1008613413
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.409071634
Short name T335
Test name
Test status
Simulation time 1823803256 ps
CPU time 217.78 seconds
Started Oct 03 12:02:19 PM UTC 24
Finished Oct 03 12:06:00 PM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409071634 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.409071634
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.4024608362
Short name T306
Test name
Test status
Simulation time 662446227 ps
CPU time 86.21 seconds
Started Oct 03 12:02:29 PM UTC 24
Finished Oct 03 12:03:57 PM UTC 24
Peak memory 381036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4024608362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t
hroughput_w_partial_write.4024608362
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.1605856505
Short name T518
Test name
Test status
Simulation time 3386488389 ps
CPU time 1270.44 seconds
Started Oct 03 12:04:28 PM UTC 24
Finished Oct 03 12:25:55 PM UTC 24
Peak memory 383236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605856505 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during
_key_req.1605856505
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1787211302
Short name T316
Test name
Test status
Simulation time 13717521 ps
CPU time 0.89 seconds
Started Oct 03 12:04:50 PM UTC 24
Finished Oct 03 12:04:52 PM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787211302 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1787211302
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.825650891
Short name T312
Test name
Test status
Simulation time 21742602869 ps
CPU time 51.2 seconds
Started Oct 03 12:03:46 PM UTC 24
Finished Oct 03 12:04:39 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825650891 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.825650891
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.3890747530
Short name T426
Test name
Test status
Simulation time 1816777916 ps
CPU time 659.9 seconds
Started Oct 03 12:04:34 PM UTC 24
Finished Oct 03 12:15:42 PM UTC 24
Peak memory 370780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890747530 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.3890747530
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.2392767415
Short name T311
Test name
Test status
Simulation time 898941617 ps
CPU time 11.66 seconds
Started Oct 03 12:04:23 PM UTC 24
Finished Oct 03 12:04:36 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392767415 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.2392767415
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.564970606
Short name T308
Test name
Test status
Simulation time 181099347 ps
CPU time 3.33 seconds
Started Oct 03 12:04:18 PM UTC 24
Finished Oct 03 12:04:23 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5
64970606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_max
_throughput.564970606
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.934995725
Short name T315
Test name
Test status
Simulation time 68325445 ps
CPU time 5.39 seconds
Started Oct 03 12:04:42 PM UTC 24
Finished Oct 03 12:04:49 PM UTC 24
Peak memory 222544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934995725 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.934995725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3516278162
Short name T317
Test name
Test status
Simulation time 1193538977 ps
CPU time 11.76 seconds
Started Oct 03 12:04:40 PM UTC 24
Finished Oct 03 12:04:53 PM UTC 24
Peak memory 222536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516278162 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.3516278162
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3561945725
Short name T337
Test name
Test status
Simulation time 5801932363 ps
CPU time 153.99 seconds
Started Oct 03 12:03:30 PM UTC 24
Finished Oct 03 12:06:06 PM UTC 24
Peak memory 319652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561945725 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3561945725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.348105066
Short name T307
Test name
Test status
Simulation time 717592223 ps
CPU time 21.44 seconds
Started Oct 03 12:03:57 PM UTC 24
Finished Oct 03 12:04:20 PM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348105066 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.348105066
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2026249056
Short name T393
Test name
Test status
Simulation time 20758156955 ps
CPU time 473.51 seconds
Started Oct 03 12:03:57 PM UTC 24
Finished Oct 03 12:11:57 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026249056 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acc
ess_b2b.2026249056
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.4153970939
Short name T313
Test name
Test status
Simulation time 30148952 ps
CPU time 1.07 seconds
Started Oct 03 12:04:39 PM UTC 24
Finished Oct 03 12:04:41 PM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153970939 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.4153970939
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.755326097
Short name T468
Test name
Test status
Simulation time 8843080542 ps
CPU time 904.56 seconds
Started Oct 03 12:04:37 PM UTC 24
Finished Oct 03 12:19:52 PM UTC 24
Peak memory 373096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755326097 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.755326097
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.808099522
Short name T303
Test name
Test status
Simulation time 231162525 ps
CPU time 14.7 seconds
Started Oct 03 12:03:29 PM UTC 24
Finished Oct 03 12:03:44 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808099522 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.808099522
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3891831094
Short name T935
Test name
Test status
Simulation time 50601991522 ps
CPU time 5123.95 seconds
Started Oct 03 12:04:49 PM UTC 24
Finished Oct 03 01:31:11 PM UTC 24
Peak memory 386888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389183109
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.3891831094
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1543945731
Short name T53
Test name
Test status
Simulation time 1145900491 ps
CPU time 11.7 seconds
Started Oct 03 12:04:43 PM UTC 24
Finished Oct 03 12:04:56 PM UTC 24
Peak memory 224712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543945731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1543945731
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1447146694
Short name T364
Test name
Test status
Simulation time 2377316920 ps
CPU time 293.75 seconds
Started Oct 03 12:03:55 PM UTC 24
Finished Oct 03 12:08:53 PM UTC 24
Peak memory 212412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447146694 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.1447146694
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2080535278
Short name T309
Test name
Test status
Simulation time 95272704 ps
CPU time 6.19 seconds
Started Oct 03 12:04:20 PM UTC 24
Finished Oct 03 12:04:28 PM UTC 24
Peak memory 246004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2080535278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t
hroughput_w_partial_write.2080535278
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3432846450
Short name T414
Test name
Test status
Simulation time 10498602845 ps
CPU time 557.91 seconds
Started Oct 03 12:05:17 PM UTC 24
Finished Oct 03 12:14:42 PM UTC 24
Peak memory 379200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432846450 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during
_key_req.3432846450
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1848753850
Short name T331
Test name
Test status
Simulation time 23052966 ps
CPU time 0.93 seconds
Started Oct 03 12:05:42 PM UTC 24
Finished Oct 03 12:05:44 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848753850 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1848753850
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.2783240225
Short name T321
Test name
Test status
Simulation time 388334501 ps
CPU time 21.91 seconds
Started Oct 03 12:04:56 PM UTC 24
Finished Oct 03 12:05:20 PM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783240225 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.2783240225
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1991439442
Short name T480
Test name
Test status
Simulation time 3435653394 ps
CPU time 941.23 seconds
Started Oct 03 12:05:21 PM UTC 24
Finished Oct 03 12:21:13 PM UTC 24
Peak memory 385188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991439442 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.1991439442
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1134593922
Short name T323
Test name
Test status
Simulation time 1575970000 ps
CPU time 7.3 seconds
Started Oct 03 12:05:16 PM UTC 24
Finished Oct 03 12:05:25 PM UTC 24
Peak memory 222452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134593922 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.1134593922
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2170344756
Short name T325
Test name
Test status
Simulation time 734191906 ps
CPU time 17.55 seconds
Started Oct 03 12:05:08 PM UTC 24
Finished Oct 03 12:05:27 PM UTC 24
Peak memory 268416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
170344756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma
x_throughput.2170344756
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1682888156
Short name T327
Test name
Test status
Simulation time 107232534 ps
CPU time 4.33 seconds
Started Oct 03 12:05:28 PM UTC 24
Finished Oct 03 12:05:33 PM UTC 24
Peak memory 222580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682888156 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.1682888156
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3865283670
Short name T330
Test name
Test status
Simulation time 661210405 ps
CPU time 14.69 seconds
Started Oct 03 12:05:27 PM UTC 24
Finished Oct 03 12:05:43 PM UTC 24
Peak memory 222528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865283670 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.3865283670
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.4200971643
Short name T385
Test name
Test status
Simulation time 2272994959 ps
CPU time 401.42 seconds
Started Oct 03 12:04:53 PM UTC 24
Finished Oct 03 12:11:40 PM UTC 24
Peak memory 379060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200971643 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.4200971643
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2016043218
Short name T319
Test name
Test status
Simulation time 534286207 ps
CPU time 12.48 seconds
Started Oct 03 12:05:01 PM UTC 24
Finished Oct 03 12:05:14 PM UTC 24
Peak memory 212208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016043218 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.2016043218
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2033129217
Short name T369
Test name
Test status
Simulation time 32533494307 ps
CPU time 255.12 seconds
Started Oct 03 12:05:08 PM UTC 24
Finished Oct 03 12:09:27 PM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033129217 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acc
ess_b2b.2033129217
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1822998281
Short name T326
Test name
Test status
Simulation time 257053085 ps
CPU time 1.11 seconds
Started Oct 03 12:05:26 PM UTC 24
Finished Oct 03 12:05:28 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822998281 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1822998281
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3017931767
Short name T517
Test name
Test status
Simulation time 26508125749 ps
CPU time 1213.17 seconds
Started Oct 03 12:05:23 PM UTC 24
Finished Oct 03 12:25:50 PM UTC 24
Peak memory 383272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017931767 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3017931767
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.2329847378
Short name T320
Test name
Test status
Simulation time 7256268555 ps
CPU time 20.28 seconds
Started Oct 03 12:04:53 PM UTC 24
Finished Oct 03 12:05:15 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329847378 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2329847378
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.176531272
Short name T701
Test name
Test status
Simulation time 33931820870 ps
CPU time 2412.4 seconds
Started Oct 03 12:05:34 PM UTC 24
Finished Oct 03 12:46:14 PM UTC 24
Peak memory 393488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176531272
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.176531272
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1472742582
Short name T332
Test name
Test status
Simulation time 727870228 ps
CPU time 20.1 seconds
Started Oct 03 12:05:29 PM UTC 24
Finished Oct 03 12:05:50 PM UTC 24
Peak memory 222596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472742582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1472742582
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3288863373
Short name T380
Test name
Test status
Simulation time 3307641648 ps
CPU time 337.96 seconds
Started Oct 03 12:05:01 PM UTC 24
Finished Oct 03 12:10:43 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288863373 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.3288863373
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1104726493
Short name T324
Test name
Test status
Simulation time 375509161 ps
CPU time 9.24 seconds
Started Oct 03 12:05:15 PM UTC 24
Finished Oct 03 12:05:26 PM UTC 24
Peak memory 245924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1104726493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_t
hroughput_w_partial_write.1104726493
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3878152919
Short name T582
Test name
Test status
Simulation time 10766408573 ps
CPU time 1556.66 seconds
Started Oct 03 12:06:11 PM UTC 24
Finished Oct 03 12:32:26 PM UTC 24
Peak memory 377016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878152919 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during
_key_req.3878152919
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.4221039272
Short name T347
Test name
Test status
Simulation time 171776932 ps
CPU time 1.1 seconds
Started Oct 03 12:06:46 PM UTC 24
Finished Oct 03 12:06:48 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221039272 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.4221039272
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.1219069729
Short name T344
Test name
Test status
Simulation time 3410934294 ps
CPU time 58.09 seconds
Started Oct 03 12:05:44 PM UTC 24
Finished Oct 03 12:06:44 PM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219069729 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.1219069729
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.3275626725
Short name T361
Test name
Test status
Simulation time 3206028774 ps
CPU time 154.97 seconds
Started Oct 03 12:06:12 PM UTC 24
Finished Oct 03 12:08:50 PM UTC 24
Peak memory 330052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275626725 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.3275626725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.526592005
Short name T338
Test name
Test status
Simulation time 306033268 ps
CPU time 2.06 seconds
Started Oct 03 12:06:07 PM UTC 24
Finished Oct 03 12:06:10 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526592005 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.526592005
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.119307817
Short name T339
Test name
Test status
Simulation time 195590471 ps
CPU time 9.39 seconds
Started Oct 03 12:06:01 PM UTC 24
Finished Oct 03 12:06:11 PM UTC 24
Peak memory 246004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
19307817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_max
_throughput.119307817
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3865887620
Short name T346
Test name
Test status
Simulation time 142705272 ps
CPU time 4.7 seconds
Started Oct 03 12:06:41 PM UTC 24
Finished Oct 03 12:06:46 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865887620 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.3865887620
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.210144303
Short name T348
Test name
Test status
Simulation time 660666743 ps
CPU time 11.71 seconds
Started Oct 03 12:06:39 PM UTC 24
Finished Oct 03 12:06:51 PM UTC 24
Peak memory 222536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210144303 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.210144303
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3083529626
Short name T340
Test name
Test status
Simulation time 4308825055 ps
CPU time 27.4 seconds
Started Oct 03 12:05:43 PM UTC 24
Finished Oct 03 12:06:12 PM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083529626 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.3083529626
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1374549446
Short name T336
Test name
Test status
Simulation time 201059395 ps
CPU time 8.98 seconds
Started Oct 03 12:05:55 PM UTC 24
Finished Oct 03 12:06:05 PM UTC 24
Peak memory 237660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374549446 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.1374549446
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1125753156
Short name T439
Test name
Test status
Simulation time 76871203774 ps
CPU time 622.25 seconds
Started Oct 03 12:05:57 PM UTC 24
Finished Oct 03 12:16:27 PM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125753156 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc
ess_b2b.1125753156
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2476665090
Short name T342
Test name
Test status
Simulation time 57706655 ps
CPU time 1.24 seconds
Started Oct 03 12:06:34 PM UTC 24
Finished Oct 03 12:06:37 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476665090 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2476665090
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.996599611
Short name T471
Test name
Test status
Simulation time 3472365536 ps
CPU time 854.68 seconds
Started Oct 03 12:06:13 PM UTC 24
Finished Oct 03 12:20:39 PM UTC 24
Peak memory 374960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996599611 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.996599611
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.4061747305
Short name T350
Test name
Test status
Simulation time 647853399 ps
CPU time 75.35 seconds
Started Oct 03 12:05:43 PM UTC 24
Finished Oct 03 12:07:00 PM UTC 24
Peak memory 377064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061747305 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4061747305
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2128893235
Short name T474
Test name
Test status
Simulation time 13846924382 ps
CPU time 843.31 seconds
Started Oct 03 12:06:46 PM UTC 24
Finished Oct 03 12:21:00 PM UTC 24
Peak memory 387332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212889323
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.2128893235
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2231221950
Short name T370
Test name
Test status
Simulation time 7233846676 ps
CPU time 166.95 seconds
Started Oct 03 12:06:42 PM UTC 24
Finished Oct 03 12:09:32 PM UTC 24
Peak memory 328072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231221950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2231221950
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2231069336
Short name T368
Test name
Test status
Simulation time 6139727193 ps
CPU time 211.1 seconds
Started Oct 03 12:05:52 PM UTC 24
Finished Oct 03 12:09:26 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231069336 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2231069336
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.516822872
Short name T343
Test name
Test status
Simulation time 421710475 ps
CPU time 32.4 seconds
Started Oct 03 12:06:06 PM UTC 24
Finished Oct 03 12:06:40 PM UTC 24
Peak memory 295008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
516822872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_th
roughput_w_partial_write.516822872
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3648704592
Short name T358
Test name
Test status
Simulation time 637569791 ps
CPU time 22.62 seconds
Started Oct 03 12:08:07 PM UTC 24
Finished Oct 03 12:08:31 PM UTC 24
Peak memory 223192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648704592 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during
_key_req.3648704592
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3049420507
Short name T363
Test name
Test status
Simulation time 12334411 ps
CPU time 0.88 seconds
Started Oct 03 12:08:51 PM UTC 24
Finished Oct 03 12:08:53 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049420507 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3049420507
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.422133770
Short name T353
Test name
Test status
Simulation time 3549026483 ps
CPU time 72.88 seconds
Started Oct 03 12:06:52 PM UTC 24
Finished Oct 03 12:08:07 PM UTC 24
Peak memory 212208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422133770 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.422133770
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.522715244
Short name T589
Test name
Test status
Simulation time 13045576301 ps
CPU time 1470.64 seconds
Started Oct 03 12:08:14 PM UTC 24
Finished Oct 03 12:33:03 PM UTC 24
Peak memory 385224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522715244 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.522715244
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.4004645195
Short name T354
Test name
Test status
Simulation time 942854630 ps
CPU time 5.7 seconds
Started Oct 03 12:08:07 PM UTC 24
Finished Oct 03 12:08:14 PM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004645195 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.4004645195
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1532328240
Short name T352
Test name
Test status
Simulation time 106492220 ps
CPU time 54.38 seconds
Started Oct 03 12:07:11 PM UTC 24
Finished Oct 03 12:08:07 PM UTC 24
Peak memory 317568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
532328240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma
x_throughput.1532328240
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1195631715
Short name T359
Test name
Test status
Simulation time 85755632 ps
CPU time 4.55 seconds
Started Oct 03 12:08:32 PM UTC 24
Finished Oct 03 12:08:37 PM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195631715 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1195631715
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1567608026
Short name T360
Test name
Test status
Simulation time 570521503 ps
CPU time 13.87 seconds
Started Oct 03 12:08:25 PM UTC 24
Finished Oct 03 12:08:40 PM UTC 24
Peak memory 222460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567608026 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.1567608026
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1273403463
Short name T413
Test name
Test status
Simulation time 11299935851 ps
CPU time 464.02 seconds
Started Oct 03 12:06:49 PM UTC 24
Finished Oct 03 12:14:39 PM UTC 24
Peak memory 374964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273403463 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1273403463
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1247629506
Short name T365
Test name
Test status
Simulation time 208652796 ps
CPU time 117.43 seconds
Started Oct 03 12:07:01 PM UTC 24
Finished Oct 03 12:09:02 PM UTC 24
Peak memory 379188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247629506 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.1247629506
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3267140380
Short name T421
Test name
Test status
Simulation time 46713993178 ps
CPU time 497.57 seconds
Started Oct 03 12:07:01 PM UTC 24
Finished Oct 03 12:15:26 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267140380 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc
ess_b2b.3267140380
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1080730978
Short name T357
Test name
Test status
Simulation time 44760230 ps
CPU time 1.25 seconds
Started Oct 03 12:08:22 PM UTC 24
Finished Oct 03 12:08:24 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080730978 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1080730978
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.1006380420
Short name T540
Test name
Test status
Simulation time 75271819549 ps
CPU time 1216.16 seconds
Started Oct 03 12:08:18 PM UTC 24
Finished Oct 03 12:28:47 PM UTC 24
Peak memory 383140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006380420 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1006380420
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.887071856
Short name T349
Test name
Test status
Simulation time 293278578 ps
CPU time 11.95 seconds
Started Oct 03 12:06:47 PM UTC 24
Finished Oct 03 12:07:00 PM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887071856 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.887071856
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4172603596
Short name T538
Test name
Test status
Simulation time 27692682721 ps
CPU time 1181.01 seconds
Started Oct 03 12:08:41 PM UTC 24
Finished Oct 03 12:28:36 PM UTC 24
Peak memory 385256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417260359
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.4172603596
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1878056378
Short name T362
Test name
Test status
Simulation time 309936401 ps
CPU time 12.45 seconds
Started Oct 03 12:08:38 PM UTC 24
Finished Oct 03 12:08:51 PM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878056378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1878056378
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3146215967
Short name T389
Test name
Test status
Simulation time 2457938807 ps
CPU time 280.53 seconds
Started Oct 03 12:06:59 PM UTC 24
Finished Oct 03 12:11:44 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146215967 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.3146215967
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1441257743
Short name T355
Test name
Test status
Simulation time 180223416 ps
CPU time 12.25 seconds
Started Oct 03 12:08:03 PM UTC 24
Finished Oct 03 12:08:17 PM UTC 24
Peak memory 270556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1441257743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_t
hroughput_w_partial_write.1441257743
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2662441467
Short name T234
Test name
Test status
Simulation time 12986397416 ps
CPU time 622.75 seconds
Started Oct 03 11:46:35 AM UTC 24
Finished Oct 03 11:57:06 AM UTC 24
Peak memory 360624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662441467 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_
key_req.2662441467
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1904725911
Short name T13
Test name
Test status
Simulation time 18373398 ps
CPU time 1.04 seconds
Started Oct 03 11:46:54 AM UTC 24
Finished Oct 03 11:46:56 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904725911 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1904725911
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2629820543
Short name T107
Test name
Test status
Simulation time 297706404 ps
CPU time 25.98 seconds
Started Oct 03 11:46:07 AM UTC 24
Finished Oct 03 11:46:35 AM UTC 24
Peak memory 212232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629820543 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.2629820543
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.3427708088
Short name T29
Test name
Test status
Simulation time 14195524297 ps
CPU time 280.76 seconds
Started Oct 03 11:46:35 AM UTC 24
Finished Oct 03 11:51:20 AM UTC 24
Peak memory 364804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427708088 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.3427708088
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2981403708
Short name T68
Test name
Test status
Simulation time 484538569 ps
CPU time 79.46 seconds
Started Oct 03 11:46:18 AM UTC 24
Finished Oct 03 11:47:39 AM UTC 24
Peak memory 370816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
981403708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max
_throughput.2981403708
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.697647690
Short name T46
Test name
Test status
Simulation time 203228020 ps
CPU time 4.83 seconds
Started Oct 03 11:46:46 AM UTC 24
Finished Oct 03 11:46:52 AM UTC 24
Peak memory 222392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697647690 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.697647690
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3490402541
Short name T43
Test name
Test status
Simulation time 751710212 ps
CPU time 8.79 seconds
Started Oct 03 11:46:45 AM UTC 24
Finished Oct 03 11:46:55 AM UTC 24
Peak memory 222448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490402541 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.3490402541
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2068463716
Short name T284
Test name
Test status
Simulation time 43759212622 ps
CPU time 948.48 seconds
Started Oct 03 11:46:06 AM UTC 24
Finished Oct 03 12:02:05 PM UTC 24
Peak memory 385280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068463716 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.2068463716
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3889046009
Short name T159
Test name
Test status
Simulation time 5234607760 ps
CPU time 32.79 seconds
Started Oct 03 11:46:13 AM UTC 24
Finished Oct 03 11:46:48 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889046009 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.3889046009
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1506104354
Short name T102
Test name
Test status
Simulation time 10233744724 ps
CPU time 224.14 seconds
Started Oct 03 11:46:14 AM UTC 24
Finished Oct 03 11:50:02 AM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506104354 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce
ss_b2b.1506104354
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2938292628
Short name T32
Test name
Test status
Simulation time 27646911 ps
CPU time 1.22 seconds
Started Oct 03 11:46:42 AM UTC 24
Finished Oct 03 11:46:44 AM UTC 24
Peak memory 211428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938292628 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2938292628
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.1761287368
Short name T139
Test name
Test status
Simulation time 25948738979 ps
CPU time 699.64 seconds
Started Oct 03 11:46:36 AM UTC 24
Finished Oct 03 11:58:24 AM UTC 24
Peak memory 381152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761287368 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1761287368
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.813559480
Short name T16
Test name
Test status
Simulation time 241282891 ps
CPU time 3.19 seconds
Started Oct 03 11:46:52 AM UTC 24
Finished Oct 03 11:46:57 AM UTC 24
Peak memory 248212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813559480 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.813559480
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.2462183476
Short name T39
Test name
Test status
Simulation time 284854008 ps
CPU time 18.07 seconds
Started Oct 03 11:46:06 AM UTC 24
Finished Oct 03 11:46:25 AM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462183476 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2462183476
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1236276611
Short name T744
Test name
Test status
Simulation time 58389525339 ps
CPU time 3919.95 seconds
Started Oct 03 11:46:48 AM UTC 24
Finished Oct 03 12:52:52 PM UTC 24
Peak memory 395108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123627661
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.1236276611
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2957171577
Short name T24
Test name
Test status
Simulation time 521990571 ps
CPU time 10.88 seconds
Started Oct 03 11:46:47 AM UTC 24
Finished Oct 03 11:46:59 AM UTC 24
Peak memory 222512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957171577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2957171577
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.810007549
Short name T103
Test name
Test status
Simulation time 8366887040 ps
CPU time 234.03 seconds
Started Oct 03 11:46:09 AM UTC 24
Finished Oct 03 11:50:07 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810007549 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.810007549
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3386562531
Short name T54
Test name
Test status
Simulation time 55178893 ps
CPU time 6.94 seconds
Started Oct 03 11:46:26 AM UTC 24
Finished Oct 03 11:46:34 AM UTC 24
Peak memory 235768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3386562531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th
roughput_w_partial_write.3386562531
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.4089510251
Short name T460
Test name
Test status
Simulation time 2609833103 ps
CPU time 515.25 seconds
Started Oct 03 12:09:33 PM UTC 24
Finished Oct 03 12:18:15 PM UTC 24
Peak memory 370984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089510251 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during
_key_req.4089510251
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3038153755
Short name T379
Test name
Test status
Simulation time 71336003 ps
CPU time 1.03 seconds
Started Oct 03 12:10:36 PM UTC 24
Finished Oct 03 12:10:38 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038153755 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3038153755
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3117266139
Short name T372
Test name
Test status
Simulation time 10436760878 ps
CPU time 63.65 seconds
Started Oct 03 12:08:54 PM UTC 24
Finished Oct 03 12:10:00 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117266139 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3117266139
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.1679149672
Short name T487
Test name
Test status
Simulation time 44302279889 ps
CPU time 758.43 seconds
Started Oct 03 12:09:35 PM UTC 24
Finished Oct 03 12:22:23 PM UTC 24
Peak memory 379200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679149672 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.1679149672
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3407624885
Short name T371
Test name
Test status
Simulation time 300020412 ps
CPU time 5.5 seconds
Started Oct 03 12:09:28 PM UTC 24
Finished Oct 03 12:09:34 PM UTC 24
Peak memory 222516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407624885 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.3407624885
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.417994841
Short name T374
Test name
Test status
Simulation time 392645884 ps
CPU time 46.15 seconds
Started Oct 03 12:09:16 PM UTC 24
Finished Oct 03 12:10:03 PM UTC 24
Peak memory 317688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
17994841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max
_throughput.417994841
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3376125441
Short name T376
Test name
Test status
Simulation time 318793626 ps
CPU time 4.35 seconds
Started Oct 03 12:10:05 PM UTC 24
Finished Oct 03 12:10:11 PM UTC 24
Peak memory 222400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376125441 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3376125441
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3309038607
Short name T377
Test name
Test status
Simulation time 271974237 ps
CPU time 9.89 seconds
Started Oct 03 12:10:04 PM UTC 24
Finished Oct 03 12:10:15 PM UTC 24
Peak memory 222480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309038607 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.3309038607
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1423834332
Short name T534
Test name
Test status
Simulation time 6755858044 ps
CPU time 1132.97 seconds
Started Oct 03 12:08:54 PM UTC 24
Finished Oct 03 12:28:01 PM UTC 24
Peak memory 383228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423834332 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.1423834332
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1336249393
Short name T378
Test name
Test status
Simulation time 431447662 ps
CPU time 90.67 seconds
Started Oct 03 12:09:02 PM UTC 24
Finished Oct 03 12:10:35 PM UTC 24
Peak memory 376948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336249393 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.1336249393
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2964909590
Short name T449
Test name
Test status
Simulation time 23261469230 ps
CPU time 470.96 seconds
Started Oct 03 12:09:13 PM UTC 24
Finished Oct 03 12:17:10 PM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964909590 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc
ess_b2b.2964909590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.1251200666
Short name T375
Test name
Test status
Simulation time 29833638 ps
CPU time 1.17 seconds
Started Oct 03 12:10:02 PM UTC 24
Finished Oct 03 12:10:04 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251200666 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1251200666
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.2019655254
Short name T482
Test name
Test status
Simulation time 47795978367 ps
CPU time 687.21 seconds
Started Oct 03 12:10:00 PM UTC 24
Finished Oct 03 12:21:36 PM UTC 24
Peak memory 362812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019655254 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2019655254
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.295930359
Short name T366
Test name
Test status
Simulation time 205027488 ps
CPU time 17.98 seconds
Started Oct 03 12:08:52 PM UTC 24
Finished Oct 03 12:09:11 PM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295930359 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.295930359
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3960436571
Short name T930
Test name
Test status
Simulation time 61693904966 ps
CPU time 4533.2 seconds
Started Oct 03 12:10:17 PM UTC 24
Finished Oct 03 01:26:40 PM UTC 24
Peak memory 384840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396043657
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.3960436571
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3749586645
Short name T403
Test name
Test status
Simulation time 8220838433 ps
CPU time 275.45 seconds
Started Oct 03 12:08:57 PM UTC 24
Finished Oct 03 12:13:37 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749586645 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.3749586645
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3055574135
Short name T373
Test name
Test status
Simulation time 431573020 ps
CPU time 33.37 seconds
Started Oct 03 12:09:27 PM UTC 24
Finished Oct 03 12:10:01 PM UTC 24
Peak memory 311388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3055574135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t
hroughput_w_partial_write.3055574135
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3014602691
Short name T501
Test name
Test status
Simulation time 4466368982 ps
CPU time 716.72 seconds
Started Oct 03 12:11:41 PM UTC 24
Finished Oct 03 12:23:46 PM UTC 24
Peak memory 377084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014602691 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during
_key_req.3014602691
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1205053308
Short name T394
Test name
Test status
Simulation time 18084100 ps
CPU time 1.04 seconds
Started Oct 03 12:11:57 PM UTC 24
Finished Oct 03 12:11:59 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205053308 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1205053308
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.571538663
Short name T396
Test name
Test status
Simulation time 3706506711 ps
CPU time 87.41 seconds
Started Oct 03 12:10:53 PM UTC 24
Finished Oct 03 12:12:22 PM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571538663 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.571538663
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2382331033
Short name T610
Test name
Test status
Simulation time 7193283941 ps
CPU time 1417.5 seconds
Started Oct 03 12:11:42 PM UTC 24
Finished Oct 03 12:35:35 PM UTC 24
Peak memory 385344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382331033 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.2382331033
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.2251087510
Short name T387
Test name
Test status
Simulation time 423487008 ps
CPU time 4.61 seconds
Started Oct 03 12:11:36 PM UTC 24
Finished Oct 03 12:11:41 PM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251087510 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.2251087510
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3392834602
Short name T384
Test name
Test status
Simulation time 179293621 ps
CPU time 4.26 seconds
Started Oct 03 12:11:29 PM UTC 24
Finished Oct 03 12:11:35 PM UTC 24
Peak memory 229552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
392834602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma
x_throughput.3392834602
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.923438145
Short name T392
Test name
Test status
Simulation time 788827187 ps
CPU time 7.46 seconds
Started Oct 03 12:11:47 PM UTC 24
Finished Oct 03 12:11:56 PM UTC 24
Peak memory 222392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923438145 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.923438145
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2966783377
Short name T391
Test name
Test status
Simulation time 97747472 ps
CPU time 6.34 seconds
Started Oct 03 12:11:45 PM UTC 24
Finished Oct 03 12:11:53 PM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966783377 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.2966783377
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.737489886
Short name T556
Test name
Test status
Simulation time 13373836477 ps
CPU time 1140.28 seconds
Started Oct 03 12:10:44 PM UTC 24
Finished Oct 03 12:29:57 PM UTC 24
Peak memory 383276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737489886 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.737489886
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2944633349
Short name T382
Test name
Test status
Simulation time 221410024 ps
CPU time 3.35 seconds
Started Oct 03 12:11:11 PM UTC 24
Finished Oct 03 12:11:16 PM UTC 24
Peak memory 212208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944633349 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2944633349
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2116813422
Short name T465
Test name
Test status
Simulation time 20281704249 ps
CPU time 485.26 seconds
Started Oct 03 12:11:16 PM UTC 24
Finished Oct 03 12:19:28 PM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116813422 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc
ess_b2b.2116813422
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3008893103
Short name T390
Test name
Test status
Simulation time 41890169 ps
CPU time 1.08 seconds
Started Oct 03 12:11:44 PM UTC 24
Finished Oct 03 12:11:46 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008893103 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3008893103
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.2001731414
Short name T433
Test name
Test status
Simulation time 705018160 ps
CPU time 260.24 seconds
Started Oct 03 12:11:42 PM UTC 24
Finished Oct 03 12:16:06 PM UTC 24
Peak memory 362584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001731414 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2001731414
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.355252118
Short name T381
Test name
Test status
Simulation time 6049693720 ps
CPU time 11.88 seconds
Started Oct 03 12:10:39 PM UTC 24
Finished Oct 03 12:10:52 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355252118 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.355252118
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3507450009
Short name T893
Test name
Test status
Simulation time 11612316585 ps
CPU time 3503.46 seconds
Started Oct 03 12:11:56 PM UTC 24
Finished Oct 03 01:10:57 PM UTC 24
Peak memory 395100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350745000
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.3507450009
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2053605149
Short name T397
Test name
Test status
Simulation time 864914235 ps
CPU time 53.44 seconds
Started Oct 03 12:11:53 PM UTC 24
Finished Oct 03 12:12:48 PM UTC 24
Peak memory 311556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053605149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2053605149
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.643098580
Short name T434
Test name
Test status
Simulation time 2446853064 ps
CPU time 303 seconds
Started Oct 03 12:10:59 PM UTC 24
Finished Oct 03 12:16:07 PM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643098580 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.643098580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2101549918
Short name T388
Test name
Test status
Simulation time 662611323 ps
CPU time 9.66 seconds
Started Oct 03 12:11:32 PM UTC 24
Finished Oct 03 12:11:43 PM UTC 24
Peak memory 247916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2101549918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_t
hroughput_w_partial_write.2101549918
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3646260027
Short name T555
Test name
Test status
Simulation time 4652032544 ps
CPU time 965.67 seconds
Started Oct 03 12:13:36 PM UTC 24
Finished Oct 03 12:29:54 PM UTC 24
Peak memory 383208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646260027 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during
_key_req.3646260027
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2038246936
Short name T410
Test name
Test status
Simulation time 19729548 ps
CPU time 0.98 seconds
Started Oct 03 12:13:56 PM UTC 24
Finished Oct 03 12:13:58 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038246936 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2038246936
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.1536349067
Short name T406
Test name
Test status
Simulation time 3997162318 ps
CPU time 80.98 seconds
Started Oct 03 12:12:24 PM UTC 24
Finished Oct 03 12:13:47 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536349067 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.1536349067
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.2922712178
Short name T486
Test name
Test status
Simulation time 43392486361 ps
CPU time 509.73 seconds
Started Oct 03 12:13:36 PM UTC 24
Finished Oct 03 12:22:13 PM UTC 24
Peak memory 344224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922712178 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.2922712178
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2834565172
Short name T402
Test name
Test status
Simulation time 134059311 ps
CPU time 2.52 seconds
Started Oct 03 12:13:32 PM UTC 24
Finished Oct 03 12:13:36 PM UTC 24
Peak memory 212028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834565172 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.2834565172
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2682362682
Short name T416
Test name
Test status
Simulation time 526170016 ps
CPU time 112.04 seconds
Started Oct 03 12:13:03 PM UTC 24
Finished Oct 03 12:14:57 PM UTC 24
Peak memory 379084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
682362682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ma
x_throughput.2682362682
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.532648087
Short name T409
Test name
Test status
Simulation time 172974653 ps
CPU time 6.52 seconds
Started Oct 03 12:13:48 PM UTC 24
Finished Oct 03 12:13:55 PM UTC 24
Peak memory 222548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532648087 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.532648087
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.240587732
Short name T407
Test name
Test status
Simulation time 239368898 ps
CPU time 7.55 seconds
Started Oct 03 12:13:43 PM UTC 24
Finished Oct 03 12:13:51 PM UTC 24
Peak memory 222584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240587732 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.240587732
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2097683780
Short name T549
Test name
Test status
Simulation time 12948403834 ps
CPU time 1020.77 seconds
Started Oct 03 12:12:08 PM UTC 24
Finished Oct 03 12:29:21 PM UTC 24
Peak memory 383268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097683780 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.2097683780
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2287319200
Short name T400
Test name
Test status
Simulation time 342925910 ps
CPU time 21.92 seconds
Started Oct 03 12:12:49 PM UTC 24
Finished Oct 03 12:13:12 PM UTC 24
Peak memory 278644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287319200 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.2287319200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1124788790
Short name T477
Test name
Test status
Simulation time 5539470239 ps
CPU time 484.16 seconds
Started Oct 03 12:12:58 PM UTC 24
Finished Oct 03 12:21:09 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124788790 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc
ess_b2b.1124788790
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3454050546
Short name T405
Test name
Test status
Simulation time 29369783 ps
CPU time 1.08 seconds
Started Oct 03 12:13:40 PM UTC 24
Finished Oct 03 12:13:42 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454050546 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3454050546
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.43870094
Short name T521
Test name
Test status
Simulation time 27275232985 ps
CPU time 734.84 seconds
Started Oct 03 12:13:39 PM UTC 24
Finished Oct 03 12:26:02 PM UTC 24
Peak memory 383208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43870094 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.43870094
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.3407362787
Short name T395
Test name
Test status
Simulation time 162515251 ps
CPU time 5.93 seconds
Started Oct 03 12:12:00 PM UTC 24
Finished Oct 03 12:12:07 PM UTC 24
Peak memory 212164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407362787 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3407362787
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2771938522
Short name T912
Test name
Test status
Simulation time 51456222589 ps
CPU time 3803.55 seconds
Started Oct 03 12:13:54 PM UTC 24
Finished Oct 03 01:17:59 PM UTC 24
Peak memory 386784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277193852
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.2771938522
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2156240026
Short name T112
Test name
Test status
Simulation time 12613717997 ps
CPU time 233.82 seconds
Started Oct 03 12:13:52 PM UTC 24
Finished Oct 03 12:17:49 PM UTC 24
Peak memory 360708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156240026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2156240026
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2831972864
Short name T450
Test name
Test status
Simulation time 2501579175 ps
CPU time 276.09 seconds
Started Oct 03 12:12:37 PM UTC 24
Finished Oct 03 12:17:18 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831972864 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2831972864
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1328366942
Short name T401
Test name
Test status
Simulation time 157187102 ps
CPU time 16.85 seconds
Started Oct 03 12:13:13 PM UTC 24
Finished Oct 03 12:13:31 PM UTC 24
Peak memory 270460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1328366942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t
hroughput_w_partial_write.1328366942
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2251312289
Short name T567
Test name
Test status
Simulation time 1877941584 ps
CPU time 921.97 seconds
Started Oct 03 12:15:17 PM UTC 24
Finished Oct 03 12:30:51 PM UTC 24
Peak memory 381164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251312289 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during
_key_req.2251312289
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3099377536
Short name T428
Test name
Test status
Simulation time 36249326 ps
CPU time 1.04 seconds
Started Oct 03 12:15:46 PM UTC 24
Finished Oct 03 12:15:48 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099377536 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3099377536
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2807721894
Short name T422
Test name
Test status
Simulation time 8880466735 ps
CPU time 58.79 seconds
Started Oct 03 12:14:33 PM UTC 24
Finished Oct 03 12:15:34 PM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807721894 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.2807721894
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1217648785
Short name T481
Test name
Test status
Simulation time 43910709438 ps
CPU time 363.34 seconds
Started Oct 03 12:15:23 PM UTC 24
Finished Oct 03 12:21:31 PM UTC 24
Peak memory 377088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217648785 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.1217648785
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.3637449863
Short name T420
Test name
Test status
Simulation time 354253617 ps
CPU time 6.41 seconds
Started Oct 03 12:15:15 PM UTC 24
Finished Oct 03 12:15:22 PM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637449863 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.3637449863
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.3546805503
Short name T424
Test name
Test status
Simulation time 189507705 ps
CPU time 39.91 seconds
Started Oct 03 12:14:58 PM UTC 24
Finished Oct 03 12:15:39 PM UTC 24
Peak memory 311496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
546805503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma
x_throughput.3546805503
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.1635801625
Short name T86
Test name
Test status
Simulation time 67555513 ps
CPU time 3.81 seconds
Started Oct 03 12:15:41 PM UTC 24
Finished Oct 03 12:15:46 PM UTC 24
Peak memory 222580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635801625 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.1635801625
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.419373760
Short name T430
Test name
Test status
Simulation time 447513089 ps
CPU time 11.35 seconds
Started Oct 03 12:15:37 PM UTC 24
Finished Oct 03 12:15:50 PM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419373760 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.419373760
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.105689958
Short name T448
Test name
Test status
Simulation time 2709339944 ps
CPU time 158.82 seconds
Started Oct 03 12:14:26 PM UTC 24
Finished Oct 03 12:17:08 PM UTC 24
Peak memory 307492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105689958 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.105689958
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.966345345
Short name T418
Test name
Test status
Simulation time 225080907 ps
CPU time 30.38 seconds
Started Oct 03 12:14:43 PM UTC 24
Finished Oct 03 12:15:14 PM UTC 24
Peak memory 291008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966345345 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.966345345
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2628843119
Short name T455
Test name
Test status
Simulation time 4345418125 ps
CPU time 172.24 seconds
Started Oct 03 12:14:52 PM UTC 24
Finished Oct 03 12:17:47 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628843119 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acc
ess_b2b.2628843119
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2465548558
Short name T423
Test name
Test status
Simulation time 29094455 ps
CPU time 1.22 seconds
Started Oct 03 12:15:34 PM UTC 24
Finished Oct 03 12:15:37 PM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465548558 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2465548558
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3805595194
Short name T573
Test name
Test status
Simulation time 9867176251 ps
CPU time 965.44 seconds
Started Oct 03 12:15:26 PM UTC 24
Finished Oct 03 12:31:44 PM UTC 24
Peak memory 379112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805595194 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3805595194
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.2997884173
Short name T419
Test name
Test status
Simulation time 251710284 ps
CPU time 75.65 seconds
Started Oct 03 12:13:59 PM UTC 24
Finished Oct 03 12:15:17 PM UTC 24
Peak memory 370860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997884173 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2997884173
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.726607714
Short name T799
Test name
Test status
Simulation time 35379278150 ps
CPU time 2532.62 seconds
Started Oct 03 12:15:43 PM UTC 24
Finished Oct 03 12:58:25 PM UTC 24
Peak memory 385204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726607714
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.726607714
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.818280602
Short name T111
Test name
Test status
Simulation time 912908420 ps
CPU time 53.73 seconds
Started Oct 03 12:15:43 PM UTC 24
Finished Oct 03 12:16:38 PM UTC 24
Peak memory 317680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818280602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.818280602
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1411800612
Short name T447
Test name
Test status
Simulation time 1251467660 ps
CPU time 134.33 seconds
Started Oct 03 12:14:40 PM UTC 24
Finished Oct 03 12:16:56 PM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411800612 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1411800612
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2628768477
Short name T429
Test name
Test status
Simulation time 484586220 ps
CPU time 43.11 seconds
Started Oct 03 12:15:05 PM UTC 24
Finished Oct 03 12:15:50 PM UTC 24
Peak memory 319716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2628768477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_t
hroughput_w_partial_write.2628768477
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2089783725
Short name T499
Test name
Test status
Simulation time 2254044912 ps
CPU time 422.91 seconds
Started Oct 03 12:16:11 PM UTC 24
Finished Oct 03 12:23:19 PM UTC 24
Peak memory 377064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089783725 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during
_key_req.2089783725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2638390095
Short name T444
Test name
Test status
Simulation time 19688270 ps
CPU time 0.95 seconds
Started Oct 03 12:16:40 PM UTC 24
Finished Oct 03 12:16:42 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638390095 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2638390095
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3728225801
Short name T442
Test name
Test status
Simulation time 2209706299 ps
CPU time 46.22 seconds
Started Oct 03 12:15:50 PM UTC 24
Finished Oct 03 12:16:38 PM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728225801 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3728225801
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.894783085
Short name T523
Test name
Test status
Simulation time 15526701341 ps
CPU time 588.47 seconds
Started Oct 03 12:16:12 PM UTC 24
Finished Oct 03 12:26:08 PM UTC 24
Peak memory 385328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894783085 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.894783085
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2072889756
Short name T438
Test name
Test status
Simulation time 576105775 ps
CPU time 6.82 seconds
Started Oct 03 12:16:09 PM UTC 24
Finished Oct 03 12:16:17 PM UTC 24
Peak memory 222460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072889756 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.2072889756
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3038580028
Short name T437
Test name
Test status
Simulation time 148428876 ps
CPU time 3.69 seconds
Started Oct 03 12:16:06 PM UTC 24
Finished Oct 03 12:16:11 PM UTC 24
Peak memory 229480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
038580028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ma
x_throughput.3038580028
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3142811130
Short name T443
Test name
Test status
Simulation time 60687242 ps
CPU time 4.16 seconds
Started Oct 03 12:16:33 PM UTC 24
Finished Oct 03 12:16:39 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142811130 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.3142811130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.901764002
Short name T446
Test name
Test status
Simulation time 2296073479 ps
CPU time 16.8 seconds
Started Oct 03 12:16:31 PM UTC 24
Finished Oct 03 12:16:49 PM UTC 24
Peak memory 222460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901764002 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.901764002
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3348836831
Short name T670
Test name
Test status
Simulation time 49817380332 ps
CPU time 1638.26 seconds
Started Oct 03 12:15:49 PM UTC 24
Finished Oct 03 12:43:26 PM UTC 24
Peak memory 381080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348836831 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.3348836831
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2368936119
Short name T435
Test name
Test status
Simulation time 3209143854 ps
CPU time 9.6 seconds
Started Oct 03 12:15:57 PM UTC 24
Finished Oct 03 12:16:08 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368936119 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.2368936119
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1826148918
Short name T492
Test name
Test status
Simulation time 68589366106 ps
CPU time 394.25 seconds
Started Oct 03 12:16:04 PM UTC 24
Finished Oct 03 12:22:45 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826148918 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc
ess_b2b.1826148918
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1575642737
Short name T440
Test name
Test status
Simulation time 43726864 ps
CPU time 1.31 seconds
Started Oct 03 12:16:28 PM UTC 24
Finished Oct 03 12:16:31 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575642737 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1575642737
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.901705144
Short name T530
Test name
Test status
Simulation time 1598454593 ps
CPU time 616.66 seconds
Started Oct 03 12:16:17 PM UTC 24
Finished Oct 03 12:26:41 PM UTC 24
Peak memory 372840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901705144 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.901705144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3397677110
Short name T432
Test name
Test status
Simulation time 428511732 ps
CPU time 15.28 seconds
Started Oct 03 12:15:47 PM UTC 24
Finished Oct 03 12:16:03 PM UTC 24
Peak memory 212228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397677110 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3397677110
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1092559637
Short name T909
Test name
Test status
Simulation time 335887745107 ps
CPU time 3575.96 seconds
Started Oct 03 12:16:40 PM UTC 24
Finished Oct 03 01:16:55 PM UTC 24
Peak memory 390876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109255963
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.1092559637
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2179043756
Short name T478
Test name
Test status
Simulation time 11323455992 ps
CPU time 314.54 seconds
Started Oct 03 12:15:51 PM UTC 24
Finished Oct 03 12:21:11 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179043756 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.2179043756
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2150125294
Short name T441
Test name
Test status
Simulation time 88122146 ps
CPU time 23.05 seconds
Started Oct 03 12:16:09 PM UTC 24
Finished Oct 03 12:16:33 PM UTC 24
Peak memory 289012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2150125294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t
hroughput_w_partial_write.2150125294
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2059809935
Short name T497
Test name
Test status
Simulation time 4915110876 ps
CPU time 312.85 seconds
Started Oct 03 12:17:41 PM UTC 24
Finished Oct 03 12:22:59 PM UTC 24
Peak memory 352360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059809935 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during
_key_req.2059809935
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.785376427
Short name T461
Test name
Test status
Simulation time 16787456 ps
CPU time 1.18 seconds
Started Oct 03 12:18:15 PM UTC 24
Finished Oct 03 12:18:17 PM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785376427 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.785376427
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1419759408
Short name T459
Test name
Test status
Simulation time 11388409304 ps
CPU time 72.73 seconds
Started Oct 03 12:16:50 PM UTC 24
Finished Oct 03 12:18:05 PM UTC 24
Peak memory 212300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419759408 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.1419759408
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.44683019
Short name T514
Test name
Test status
Simulation time 995451786 ps
CPU time 447.23 seconds
Started Oct 03 12:17:44 PM UTC 24
Finished Oct 03 12:25:17 PM UTC 24
Peak memory 383148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44683019 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.44683019
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1344313639
Short name T453
Test name
Test status
Simulation time 2473613541 ps
CPU time 11.49 seconds
Started Oct 03 12:17:27 PM UTC 24
Finished Oct 03 12:17:40 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344313639 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.1344313639
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1881915490
Short name T458
Test name
Test status
Simulation time 195455596 ps
CPU time 43.78 seconds
Started Oct 03 12:17:19 PM UTC 24
Finished Oct 03 12:18:04 PM UTC 24
Peak memory 332016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
881915490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma
x_throughput.1881915490
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4058075535
Short name T87
Test name
Test status
Simulation time 192673291 ps
CPU time 10.05 seconds
Started Oct 03 12:18:02 PM UTC 24
Finished Oct 03 12:18:13 PM UTC 24
Peak memory 222528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058075535 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.4058075535
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3683896200
Short name T457
Test name
Test status
Simulation time 339389482 ps
CPU time 5.99 seconds
Started Oct 03 12:17:54 PM UTC 24
Finished Oct 03 12:18:01 PM UTC 24
Peak memory 222480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683896200 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.3683896200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.2697160345
Short name T571
Test name
Test status
Simulation time 2522726659 ps
CPU time 868.19 seconds
Started Oct 03 12:16:44 PM UTC 24
Finished Oct 03 12:31:23 PM UTC 24
Peak memory 381156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697160345 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.2697160345
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.162329550
Short name T451
Test name
Test status
Simulation time 950993919 ps
CPU time 9.14 seconds
Started Oct 03 12:17:10 PM UTC 24
Finished Oct 03 12:17:20 PM UTC 24
Peak memory 237664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162329550 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.162329550
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.4121391038
Short name T533
Test name
Test status
Simulation time 20676614974 ps
CPU time 633.5 seconds
Started Oct 03 12:17:11 PM UTC 24
Finished Oct 03 12:27:53 PM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121391038 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc
ess_b2b.4121391038
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1958501382
Short name T456
Test name
Test status
Simulation time 36246993 ps
CPU time 1.18 seconds
Started Oct 03 12:17:51 PM UTC 24
Finished Oct 03 12:17:53 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958501382 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1958501382
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.3058159193
Short name T724
Test name
Test status
Simulation time 16259962552 ps
CPU time 1882.11 seconds
Started Oct 03 12:17:48 PM UTC 24
Finished Oct 03 12:49:32 PM UTC 24
Peak memory 385280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058159193 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3058159193
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1403429436
Short name T454
Test name
Test status
Simulation time 367421448 ps
CPU time 57.5 seconds
Started Oct 03 12:16:43 PM UTC 24
Finished Oct 03 12:17:42 PM UTC 24
Peak memory 315712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403429436 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1403429436
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2953064762
Short name T795
Test name
Test status
Simulation time 32102870921 ps
CPU time 2365.18 seconds
Started Oct 03 12:18:05 PM UTC 24
Finished Oct 03 12:57:59 PM UTC 24
Peak memory 385292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295306476
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.2953064762
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4096385016
Short name T502
Test name
Test status
Simulation time 1138128319 ps
CPU time 340.33 seconds
Started Oct 03 12:18:05 PM UTC 24
Finished Oct 03 12:23:51 PM UTC 24
Peak memory 369036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096385016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4096385016
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.500488438
Short name T489
Test name
Test status
Simulation time 5869779753 ps
CPU time 332.68 seconds
Started Oct 03 12:16:57 PM UTC 24
Finished Oct 03 12:22:35 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500488438 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.500488438
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.442696924
Short name T452
Test name
Test status
Simulation time 179760538 ps
CPU time 3.79 seconds
Started Oct 03 12:17:21 PM UTC 24
Finished Oct 03 12:17:26 PM UTC 24
Peak memory 228948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
442696924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_th
roughput_w_partial_write.442696924
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3556076870
Short name T653
Test name
Test status
Simulation time 4007195855 ps
CPU time 1238.25 seconds
Started Oct 03 12:19:53 PM UTC 24
Finished Oct 03 12:40:47 PM UTC 24
Peak memory 381164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556076870 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during
_key_req.3556076870
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2747456214
Short name T479
Test name
Test status
Simulation time 40740262 ps
CPU time 1.05 seconds
Started Oct 03 12:21:10 PM UTC 24
Finished Oct 03 12:21:12 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747456214 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2747456214
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.328402800
Short name T463
Test name
Test status
Simulation time 1260201573 ps
CPU time 51.33 seconds
Started Oct 03 12:18:21 PM UTC 24
Finished Oct 03 12:19:14 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328402800 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.328402800
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.298088656
Short name T600
Test name
Test status
Simulation time 107645065061 ps
CPU time 845.37 seconds
Started Oct 03 12:20:01 PM UTC 24
Finished Oct 03 12:34:16 PM UTC 24
Peak memory 383160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298088656 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.298088656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3684747842
Short name T469
Test name
Test status
Simulation time 390748446 ps
CPU time 6.29 seconds
Started Oct 03 12:19:52 PM UTC 24
Finished Oct 03 12:20:00 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684747842 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.3684747842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2536166704
Short name T467
Test name
Test status
Simulation time 994172075 ps
CPU time 21.52 seconds
Started Oct 03 12:19:29 PM UTC 24
Finished Oct 03 12:19:52 PM UTC 24
Peak memory 262276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
536166704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ma
x_throughput.2536166704
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1188823755
Short name T475
Test name
Test status
Simulation time 254225720 ps
CPU time 8.64 seconds
Started Oct 03 12:20:57 PM UTC 24
Finished Oct 03 12:21:06 PM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188823755 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.1188823755
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3377984002
Short name T473
Test name
Test status
Simulation time 140616088 ps
CPU time 11.64 seconds
Started Oct 03 12:20:42 PM UTC 24
Finished Oct 03 12:20:55 PM UTC 24
Peak memory 222532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377984002 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.3377984002
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3758536941
Short name T559
Test name
Test status
Simulation time 2395643748 ps
CPU time 704.88 seconds
Started Oct 03 12:18:18 PM UTC 24
Finished Oct 03 12:30:12 PM UTC 24
Peak memory 379104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758536941 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3758536941
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.993380566
Short name T466
Test name
Test status
Simulation time 777190891 ps
CPU time 18.35 seconds
Started Oct 03 12:19:15 PM UTC 24
Finished Oct 03 12:19:34 PM UTC 24
Peak memory 212164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993380566 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.993380566
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1604851197
Short name T520
Test name
Test status
Simulation time 45803482836 ps
CPU time 396.61 seconds
Started Oct 03 12:19:19 PM UTC 24
Finished Oct 03 12:26:01 PM UTC 24
Peak memory 212228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604851197 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc
ess_b2b.1604851197
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.467965392
Short name T472
Test name
Test status
Simulation time 29514217 ps
CPU time 1.13 seconds
Started Oct 03 12:20:39 PM UTC 24
Finished Oct 03 12:20:41 PM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467965392 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.467965392
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.1626423596
Short name T476
Test name
Test status
Simulation time 1068772640 ps
CPU time 43.29 seconds
Started Oct 03 12:20:24 PM UTC 24
Finished Oct 03 12:21:09 PM UTC 24
Peak memory 290988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626423596 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1626423596
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.786794188
Short name T462
Test name
Test status
Simulation time 173238856 ps
CPU time 3.09 seconds
Started Oct 03 12:18:16 PM UTC 24
Finished Oct 03 12:18:20 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786794188 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.786794188
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2384150644
Short name T918
Test name
Test status
Simulation time 14889045261 ps
CPU time 3552.4 seconds
Started Oct 03 12:21:07 PM UTC 24
Finished Oct 03 01:20:58 PM UTC 24
Peak memory 388952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238415064
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.2384150644
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1247469240
Short name T113
Test name
Test status
Simulation time 869534455 ps
CPU time 11.08 seconds
Started Oct 03 12:21:01 PM UTC 24
Finished Oct 03 12:21:13 PM UTC 24
Peak memory 228756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247469240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1247469240
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.291460642
Short name T507
Test name
Test status
Simulation time 2797276451 ps
CPU time 345.25 seconds
Started Oct 03 12:18:41 PM UTC 24
Finished Oct 03 12:24:32 PM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291460642 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.291460642
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.977413403
Short name T470
Test name
Test status
Simulation time 108436676 ps
CPU time 45.76 seconds
Started Oct 03 12:19:35 PM UTC 24
Finished Oct 03 12:20:22 PM UTC 24
Peak memory 313600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
977413403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_th
roughput_w_partial_write.977413403
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.727773049
Short name T546
Test name
Test status
Simulation time 58354922878 ps
CPU time 431.96 seconds
Started Oct 03 12:21:57 PM UTC 24
Finished Oct 03 12:29:14 PM UTC 24
Peak memory 383212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727773049 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_
key_req.727773049
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2700110908
Short name T494
Test name
Test status
Simulation time 19021567 ps
CPU time 0.92 seconds
Started Oct 03 12:22:46 PM UTC 24
Finished Oct 03 12:22:48 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700110908 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.2700110908
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3153766580
Short name T483
Test name
Test status
Simulation time 882049123 ps
CPU time 31.72 seconds
Started Oct 03 12:21:13 PM UTC 24
Finished Oct 03 12:21:46 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153766580 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.3153766580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.2026638782
Short name T618
Test name
Test status
Simulation time 38213721110 ps
CPU time 834.35 seconds
Started Oct 03 12:22:14 PM UTC 24
Finished Oct 03 12:36:19 PM UTC 24
Peak memory 372992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026638782 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.2026638782
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2729378053
Short name T485
Test name
Test status
Simulation time 1956659734 ps
CPU time 5.91 seconds
Started Oct 03 12:21:48 PM UTC 24
Finished Oct 03 12:21:55 PM UTC 24
Peak memory 222536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729378053 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.2729378053
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.477484573
Short name T491
Test name
Test status
Simulation time 123133012 ps
CPU time 62.47 seconds
Started Oct 03 12:21:37 PM UTC 24
Finished Oct 03 12:22:41 PM UTC 24
Peak memory 346376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
77484573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_max
_throughput.477484573
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2195210857
Short name T493
Test name
Test status
Simulation time 90358251 ps
CPU time 4.18 seconds
Started Oct 03 12:22:40 PM UTC 24
Finished Oct 03 12:22:45 PM UTC 24
Peak memory 222592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195210857 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.2195210857
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1809327595
Short name T495
Test name
Test status
Simulation time 346089101 ps
CPU time 11.21 seconds
Started Oct 03 12:22:36 PM UTC 24
Finished Oct 03 12:22:49 PM UTC 24
Peak memory 222404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809327595 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.1809327595
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.819737537
Short name T628
Test name
Test status
Simulation time 4994315303 ps
CPU time 968.4 seconds
Started Oct 03 12:21:11 PM UTC 24
Finished Oct 03 12:37:32 PM UTC 24
Peak memory 381096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819737537 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.819737537
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.258053919
Short name T484
Test name
Test status
Simulation time 6167277697 ps
CPU time 31.36 seconds
Started Oct 03 12:21:15 PM UTC 24
Finished Oct 03 12:21:47 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258053919 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.258053919
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2070731428
Short name T599
Test name
Test status
Simulation time 50231889958 ps
CPU time 747.7 seconds
Started Oct 03 12:21:33 PM UTC 24
Finished Oct 03 12:34:11 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070731428 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acc
ess_b2b.2070731428
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2195467999
Short name T490
Test name
Test status
Simulation time 48994740 ps
CPU time 1.12 seconds
Started Oct 03 12:22:36 PM UTC 24
Finished Oct 03 12:22:39 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195467999 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2195467999
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.617053264
Short name T596
Test name
Test status
Simulation time 22570089111 ps
CPU time 681.55 seconds
Started Oct 03 12:22:24 PM UTC 24
Finished Oct 03 12:33:54 PM UTC 24
Peak memory 381168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617053264 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.617053264
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1421351244
Short name T496
Test name
Test status
Simulation time 108905240 ps
CPU time 97.11 seconds
Started Oct 03 12:21:10 PM UTC 24
Finished Oct 03 12:22:49 PM UTC 24
Peak memory 346284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421351244 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1421351244
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.2075302382
Short name T913
Test name
Test status
Simulation time 41820891785 ps
CPU time 3278.23 seconds
Started Oct 03 12:22:46 PM UTC 24
Finished Oct 03 01:18:01 PM UTC 24
Peak memory 387016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207530238
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.2075302382
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1903024841
Short name T114
Test name
Test status
Simulation time 2420005674 ps
CPU time 51.51 seconds
Started Oct 03 12:22:42 PM UTC 24
Finished Oct 03 12:23:35 PM UTC 24
Peak memory 276876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903024841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.1903024841
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1561505242
Short name T515
Test name
Test status
Simulation time 2439577741 ps
CPU time 256.87 seconds
Started Oct 03 12:21:13 PM UTC 24
Finished Oct 03 12:25:34 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561505242 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.1561505242
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1173225092
Short name T488
Test name
Test status
Simulation time 111054917 ps
CPU time 45.3 seconds
Started Oct 03 12:21:48 PM UTC 24
Finished Oct 03 12:22:35 PM UTC 24
Peak memory 309364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1173225092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t
hroughput_w_partial_write.1173225092
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2250905238
Short name T697
Test name
Test status
Simulation time 4447369408 ps
CPU time 1291.33 seconds
Started Oct 03 12:23:52 PM UTC 24
Finished Oct 03 12:45:38 PM UTC 24
Peak memory 383296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250905238 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during
_key_req.2250905238
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3385602149
Short name T512
Test name
Test status
Simulation time 14703912 ps
CPU time 1 seconds
Started Oct 03 12:24:58 PM UTC 24
Finished Oct 03 12:25:00 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385602149 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3385602149
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.832695751
Short name T510
Test name
Test status
Simulation time 53975117457 ps
CPU time 124.49 seconds
Started Oct 03 12:22:50 PM UTC 24
Finished Oct 03 12:24:57 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832695751 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.832695751
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.3918208644
Short name T741
Test name
Test status
Simulation time 14755419558 ps
CPU time 1660.71 seconds
Started Oct 03 12:23:59 PM UTC 24
Finished Oct 03 12:51:59 PM UTC 24
Peak memory 383212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918208644 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.3918208644
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.4193440322
Short name T503
Test name
Test status
Simulation time 929126633 ps
CPU time 8.62 seconds
Started Oct 03 12:23:47 PM UTC 24
Finished Oct 03 12:23:58 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193440322 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.4193440322
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.333876565
Short name T505
Test name
Test status
Simulation time 401283330 ps
CPU time 49.35 seconds
Started Oct 03 12:23:32 PM UTC 24
Finished Oct 03 12:24:23 PM UTC 24
Peak memory 317544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
33876565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max
_throughput.333876565
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.1532574158
Short name T508
Test name
Test status
Simulation time 71910709 ps
CPU time 6.22 seconds
Started Oct 03 12:24:33 PM UTC 24
Finished Oct 03 12:24:41 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532574158 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.1532574158
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.950699009
Short name T509
Test name
Test status
Simulation time 179331665 ps
CPU time 15.13 seconds
Started Oct 03 12:24:27 PM UTC 24
Finished Oct 03 12:24:43 PM UTC 24
Peak memory 222400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950699009 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.950699009
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1893424371
Short name T642
Test name
Test status
Simulation time 40104328407 ps
CPU time 964.82 seconds
Started Oct 03 12:22:49 PM UTC 24
Finished Oct 03 12:39:06 PM UTC 24
Peak memory 385336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893424371 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.1893424371
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3813491055
Short name T504
Test name
Test status
Simulation time 212591024 ps
CPU time 63.75 seconds
Started Oct 03 12:23:12 PM UTC 24
Finished Oct 03 12:24:17 PM UTC 24
Peak memory 364736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813491055 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.3813491055
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.522116083
Short name T550
Test name
Test status
Simulation time 40564739070 ps
CPU time 362.76 seconds
Started Oct 03 12:23:20 PM UTC 24
Finished Oct 03 12:29:28 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522116083 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acce
ss_b2b.522116083
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3949133199
Short name T506
Test name
Test status
Simulation time 33829669 ps
CPU time 1.18 seconds
Started Oct 03 12:24:24 PM UTC 24
Finished Oct 03 12:24:26 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949133199 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3949133199
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.3968891338
Short name T594
Test name
Test status
Simulation time 1435189418 ps
CPU time 564.8 seconds
Started Oct 03 12:24:18 PM UTC 24
Finished Oct 03 12:33:50 PM UTC 24
Peak memory 383168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968891338 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3968891338
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1622860127
Short name T498
Test name
Test status
Simulation time 1544427965 ps
CPU time 20.03 seconds
Started Oct 03 12:22:49 PM UTC 24
Finished Oct 03 12:23:10 PM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622860127 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1622860127
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.522718284
Short name T932
Test name
Test status
Simulation time 65700195003 ps
CPU time 3728.28 seconds
Started Oct 03 12:24:45 PM UTC 24
Finished Oct 03 01:27:35 PM UTC 24
Peak memory 395188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522718284
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.522718284
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3225665710
Short name T51
Test name
Test status
Simulation time 2231661185 ps
CPU time 130.21 seconds
Started Oct 03 12:24:41 PM UTC 24
Finished Oct 03 12:26:54 PM UTC 24
Peak memory 301508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225665710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3225665710
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.64111738
Short name T545
Test name
Test status
Simulation time 23400932282 ps
CPU time 365.63 seconds
Started Oct 03 12:23:01 PM UTC 24
Finished Oct 03 12:29:12 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64111738 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.64111738
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.298524110
Short name T511
Test name
Test status
Simulation time 298688706 ps
CPU time 79.35 seconds
Started Oct 03 12:23:36 PM UTC 24
Finished Oct 03 12:24:58 PM UTC 24
Peak memory 370776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
298524110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_th
roughput_w_partial_write.298524110
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3292756762
Short name T705
Test name
Test status
Simulation time 3122041608 ps
CPU time 1207.51 seconds
Started Oct 03 12:26:02 PM UTC 24
Finished Oct 03 12:46:23 PM UTC 24
Peak memory 383156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292756762 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during
_key_req.3292756762
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.275135686
Short name T529
Test name
Test status
Simulation time 20495971 ps
CPU time 1.03 seconds
Started Oct 03 12:26:31 PM UTC 24
Finished Oct 03 12:26:33 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275135686 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.275135686
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.1398068443
Short name T528
Test name
Test status
Simulation time 3615974078 ps
CPU time 73.98 seconds
Started Oct 03 12:25:14 PM UTC 24
Finished Oct 03 12:26:30 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398068443 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.1398068443
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.1199607947
Short name T578
Test name
Test status
Simulation time 1137554791 ps
CPU time 370.29 seconds
Started Oct 03 12:26:03 PM UTC 24
Finished Oct 03 12:32:19 PM UTC 24
Peak memory 350332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199607947 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.1199607947
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1230731335
Short name T524
Test name
Test status
Simulation time 1178125363 ps
CPU time 7.6 seconds
Started Oct 03 12:25:59 PM UTC 24
Finished Oct 03 12:26:08 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230731335 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.1230731335
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2393876759
Short name T519
Test name
Test status
Simulation time 260403116 ps
CPU time 5.12 seconds
Started Oct 03 12:25:52 PM UTC 24
Finished Oct 03 12:25:58 PM UTC 24
Peak memory 233736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
393876759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma
x_throughput.2393876759
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.49333974
Short name T526
Test name
Test status
Simulation time 193201651 ps
CPU time 4.75 seconds
Started Oct 03 12:26:12 PM UTC 24
Finished Oct 03 12:26:18 PM UTC 24
Peak memory 222396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49333974 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.49333974
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3639859246
Short name T527
Test name
Test status
Simulation time 6323635897 ps
CPU time 19.41 seconds
Started Oct 03 12:26:09 PM UTC 24
Finished Oct 03 12:26:29 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639859246 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.3639859246
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1217420372
Short name T700
Test name
Test status
Simulation time 15509162756 ps
CPU time 1256.27 seconds
Started Oct 03 12:25:01 PM UTC 24
Finished Oct 03 12:46:13 PM UTC 24
Peak memory 381100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217420372 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.1217420372
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2158982590
Short name T516
Test name
Test status
Simulation time 64811069 ps
CPU time 1.91 seconds
Started Oct 03 12:25:35 PM UTC 24
Finished Oct 03 12:25:39 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158982590 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.2158982590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2546392188
Short name T580
Test name
Test status
Simulation time 129762827404 ps
CPU time 398.16 seconds
Started Oct 03 12:25:40 PM UTC 24
Finished Oct 03 12:32:24 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546392188 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc
ess_b2b.2546392188
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.2515417316
Short name T525
Test name
Test status
Simulation time 30622596 ps
CPU time 1.32 seconds
Started Oct 03 12:26:09 PM UTC 24
Finished Oct 03 12:26:11 PM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515417316 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2515417316
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.4202575270
Short name T602
Test name
Test status
Simulation time 5608239379 ps
CPU time 484.16 seconds
Started Oct 03 12:26:09 PM UTC 24
Finished Oct 03 12:34:19 PM UTC 24
Peak memory 381088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202575270 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4202575270
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.115442653
Short name T513
Test name
Test status
Simulation time 1907377637 ps
CPU time 13.15 seconds
Started Oct 03 12:24:59 PM UTC 24
Finished Oct 03 12:25:13 PM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115442653 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.115442653
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1272624208
Short name T895
Test name
Test status
Simulation time 109611451900 ps
CPU time 2674.82 seconds
Started Oct 03 12:26:30 PM UTC 24
Finished Oct 03 01:11:35 PM UTC 24
Peak memory 393580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127262420
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.1272624208
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2794534534
Short name T566
Test name
Test status
Simulation time 399453342 ps
CPU time 259.28 seconds
Started Oct 03 12:26:19 PM UTC 24
Finished Oct 03 12:30:42 PM UTC 24
Peak memory 389424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794534534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2794534534
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.520660027
Short name T548
Test name
Test status
Simulation time 9165674696 ps
CPU time 238.58 seconds
Started Oct 03 12:25:17 PM UTC 24
Finished Oct 03 12:29:20 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520660027 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.520660027
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.309144934
Short name T522
Test name
Test status
Simulation time 126344218 ps
CPU time 10.25 seconds
Started Oct 03 12:25:56 PM UTC 24
Finished Oct 03 12:26:07 PM UTC 24
Peak memory 252224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
309144934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_th
roughput_w_partial_write.309144934
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2600305534
Short name T328
Test name
Test status
Simulation time 2998604713 ps
CPU time 1082.18 seconds
Started Oct 03 11:47:26 AM UTC 24
Finished Oct 03 12:05:41 PM UTC 24
Peak memory 381220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600305534 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_
key_req.2600305534
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2169056828
Short name T14
Test name
Test status
Simulation time 50723806 ps
CPU time 1.08 seconds
Started Oct 03 11:47:50 AM UTC 24
Finished Oct 03 11:47:52 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169056828 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2169056828
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.2853279176
Short name T158
Test name
Test status
Simulation time 721799431 ps
CPU time 56.84 seconds
Started Oct 03 11:46:58 AM UTC 24
Finished Oct 03 11:47:56 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853279176 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.2853279176
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1259773360
Short name T141
Test name
Test status
Simulation time 4153319539 ps
CPU time 237.3 seconds
Started Oct 03 11:47:26 AM UTC 24
Finished Oct 03 11:51:28 AM UTC 24
Peak memory 372972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259773360 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.1259773360
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.901793940
Short name T21
Test name
Test status
Simulation time 2026251267 ps
CPU time 7.78 seconds
Started Oct 03 11:47:17 AM UTC 24
Finished Oct 03 11:47:27 AM UTC 24
Peak memory 212240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901793940 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.901793940
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.123986018
Short name T70
Test name
Test status
Simulation time 91430190 ps
CPU time 33.3 seconds
Started Oct 03 11:47:14 AM UTC 24
Finished Oct 03 11:47:49 AM UTC 24
Peak memory 303368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
23986018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_
throughput.123986018
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1700720105
Short name T69
Test name
Test status
Simulation time 395550345 ps
CPU time 6.27 seconds
Started Oct 03 11:47:40 AM UTC 24
Finished Oct 03 11:47:47 AM UTC 24
Peak memory 222368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700720105 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1700720105
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1370809503
Short name T44
Test name
Test status
Simulation time 2353607132 ps
CPU time 18.17 seconds
Started Oct 03 11:47:37 AM UTC 24
Finished Oct 03 11:47:56 AM UTC 24
Peak memory 222512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370809503 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.1370809503
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2766866683
Short name T217
Test name
Test status
Simulation time 1940405912 ps
CPU time 410 seconds
Started Oct 03 11:46:58 AM UTC 24
Finished Oct 03 11:53:53 AM UTC 24
Peak memory 342188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766866683 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.2766866683
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.322896884
Short name T63
Test name
Test status
Simulation time 332904699 ps
CPU time 8.28 seconds
Started Oct 03 11:47:02 AM UTC 24
Finished Oct 03 11:47:11 AM UTC 24
Peak memory 237668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322896884 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.322896884
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1625566595
Short name T149
Test name
Test status
Simulation time 149560230203 ps
CPU time 350.15 seconds
Started Oct 03 11:47:12 AM UTC 24
Finished Oct 03 11:53:07 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625566595 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce
ss_b2b.1625566595
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.229707853
Short name T67
Test name
Test status
Simulation time 117191821 ps
CPU time 1.23 seconds
Started Oct 03 11:47:37 AM UTC 24
Finished Oct 03 11:47:39 AM UTC 24
Peak memory 211052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229707853 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.229707853
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1184873311
Short name T135
Test name
Test status
Simulation time 7676011993 ps
CPU time 622.93 seconds
Started Oct 03 11:47:27 AM UTC 24
Finished Oct 03 11:57:58 AM UTC 24
Peak memory 385348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184873311 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1184873311
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3700397997
Short name T33
Test name
Test status
Simulation time 230602676 ps
CPU time 2.71 seconds
Started Oct 03 11:47:48 AM UTC 24
Finished Oct 03 11:47:52 AM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700397997 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3700397997
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.2918112493
Short name T64
Test name
Test status
Simulation time 80851876 ps
CPU time 16.4 seconds
Started Oct 03 11:46:55 AM UTC 24
Finished Oct 03 11:47:13 AM UTC 24
Peak memory 268480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918112493 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2918112493
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2535215491
Short name T568
Test name
Test status
Simulation time 65188688270 ps
CPU time 2562.26 seconds
Started Oct 03 11:47:43 AM UTC 24
Finished Oct 03 12:30:55 PM UTC 24
Peak memory 385200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253521549
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.2535215491
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2057881823
Short name T57
Test name
Test status
Simulation time 1492125987 ps
CPU time 154.9 seconds
Started Oct 03 11:47:40 AM UTC 24
Finished Oct 03 11:50:18 AM UTC 24
Peak memory 368852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057881823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2057881823
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1875887352
Short name T183
Test name
Test status
Simulation time 3953223385 ps
CPU time 217.39 seconds
Started Oct 03 11:47:00 AM UTC 24
Finished Oct 03 11:50:41 AM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875887352 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.1875887352
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1025599498
Short name T66
Test name
Test status
Simulation time 87230391 ps
CPU time 18.9 seconds
Started Oct 03 11:47:16 AM UTC 24
Finished Oct 03 11:47:36 AM UTC 24
Peak memory 280760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1025599498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th
roughput_w_partial_write.1025599498
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.953222955
Short name T737
Test name
Test status
Simulation time 12544867974 ps
CPU time 1347.45 seconds
Started Oct 03 12:28:37 PM UTC 24
Finished Oct 03 12:51:20 PM UTC 24
Peak memory 385180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953222955 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_
key_req.953222955
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3466770424
Short name T547
Test name
Test status
Simulation time 18451982 ps
CPU time 0.99 seconds
Started Oct 03 12:29:13 PM UTC 24
Finished Oct 03 12:29:15 PM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466770424 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3466770424
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1817836654
Short name T537
Test name
Test status
Simulation time 28753761549 ps
CPU time 106.04 seconds
Started Oct 03 12:26:48 PM UTC 24
Finished Oct 03 12:28:36 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817836654 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.1817836654
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3616493291
Short name T603
Test name
Test status
Simulation time 3246618156 ps
CPU time 362.61 seconds
Started Oct 03 12:28:37 PM UTC 24
Finished Oct 03 12:34:44 PM UTC 24
Peak memory 370840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616493291 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.3616493291
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.857662605
Short name T539
Test name
Test status
Simulation time 2086799043 ps
CPU time 9.25 seconds
Started Oct 03 12:28:32 PM UTC 24
Finished Oct 03 12:28:42 PM UTC 24
Peak memory 222476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857662605 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.857662605
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.715330470
Short name T535
Test name
Test status
Simulation time 128393255 ps
CPU time 15.08 seconds
Started Oct 03 12:28:02 PM UTC 24
Finished Oct 03 12:28:19 PM UTC 24
Peak memory 262272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7
15330470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_max
_throughput.715330470
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3837320176
Short name T543
Test name
Test status
Simulation time 395397194 ps
CPU time 5 seconds
Started Oct 03 12:28:55 PM UTC 24
Finished Oct 03 12:29:02 PM UTC 24
Peak memory 222520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837320176 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.3837320176
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3721190054
Short name T544
Test name
Test status
Simulation time 1803701543 ps
CPU time 9.42 seconds
Started Oct 03 12:28:51 PM UTC 24
Finished Oct 03 12:29:02 PM UTC 24
Peak memory 222476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721190054 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.3721190054
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2456969259
Short name T683
Test name
Test status
Simulation time 71465458433 ps
CPU time 1061.57 seconds
Started Oct 03 12:26:42 PM UTC 24
Finished Oct 03 12:44:35 PM UTC 24
Peak memory 381172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456969259 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2456969259
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2370419175
Short name T542
Test name
Test status
Simulation time 208300370 ps
CPU time 117.58 seconds
Started Oct 03 12:26:55 PM UTC 24
Finished Oct 03 12:28:55 PM UTC 24
Peak memory 376948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370419175 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.2370419175
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1318002034
Short name T624
Test name
Test status
Simulation time 75217090780 ps
CPU time 541 seconds
Started Oct 03 12:27:53 PM UTC 24
Finished Oct 03 12:37:02 PM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318002034 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acc
ess_b2b.1318002034
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1176712323
Short name T541
Test name
Test status
Simulation time 35568006 ps
CPU time 1.23 seconds
Started Oct 03 12:28:48 PM UTC 24
Finished Oct 03 12:28:50 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176712323 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1176712323
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.3771542094
Short name T625
Test name
Test status
Simulation time 89864110664 ps
CPU time 500.5 seconds
Started Oct 03 12:28:43 PM UTC 24
Finished Oct 03 12:37:10 PM UTC 24
Peak memory 360616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771542094 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3771542094
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.971696589
Short name T532
Test name
Test status
Simulation time 1456051547 ps
CPU time 12.66 seconds
Started Oct 03 12:26:34 PM UTC 24
Finished Oct 03 12:26:48 PM UTC 24
Peak memory 212220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971696589 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.971696589
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1815800428
Short name T921
Test name
Test status
Simulation time 40818088307 ps
CPU time 3150.86 seconds
Started Oct 03 12:29:03 PM UTC 24
Finished Oct 03 01:22:08 PM UTC 24
Peak memory 386592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181580042
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.1815800428
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.647028727
Short name T115
Test name
Test status
Simulation time 1301469198 ps
CPU time 51.59 seconds
Started Oct 03 12:29:03 PM UTC 24
Finished Oct 03 12:29:56 PM UTC 24
Peak memory 278300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647028727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.647028727
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3916542025
Short name T584
Test name
Test status
Simulation time 2932226466 ps
CPU time 335.14 seconds
Started Oct 03 12:26:49 PM UTC 24
Finished Oct 03 12:32:29 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916542025 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.3916542025
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2489674525
Short name T536
Test name
Test status
Simulation time 72773355 ps
CPU time 10.07 seconds
Started Oct 03 12:28:20 PM UTC 24
Finished Oct 03 12:28:31 PM UTC 24
Peak memory 250044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2489674525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_t
hroughput_w_partial_write.2489674525
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.909619909
Short name T708
Test name
Test status
Simulation time 6306298686 ps
CPU time 1004.43 seconds
Started Oct 03 12:29:47 PM UTC 24
Finished Oct 03 12:46:44 PM UTC 24
Peak memory 385312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909619909 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during_
key_req.909619909
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3890155451
Short name T563
Test name
Test status
Simulation time 43636206 ps
CPU time 1.1 seconds
Started Oct 03 12:30:19 PM UTC 24
Finished Oct 03 12:30:21 PM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890155451 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3890155451
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.884037374
Short name T564
Test name
Test status
Simulation time 3386554145 ps
CPU time 61.51 seconds
Started Oct 03 12:29:20 PM UTC 24
Finished Oct 03 12:30:23 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884037374 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.884037374
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1445006838
Short name T612
Test name
Test status
Simulation time 48008896612 ps
CPU time 340.54 seconds
Started Oct 03 12:29:55 PM UTC 24
Finished Oct 03 12:35:40 PM UTC 24
Peak memory 370872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445006838 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.1445006838
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.598946683
Short name T554
Test name
Test status
Simulation time 571416846 ps
CPU time 3.19 seconds
Started Oct 03 12:29:42 PM UTC 24
Finished Oct 03 12:29:46 PM UTC 24
Peak memory 222532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598946683 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.598946683
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1867965911
Short name T553
Test name
Test status
Simulation time 224199051 ps
CPU time 5.15 seconds
Started Oct 03 12:29:35 PM UTC 24
Finished Oct 03 12:29:41 PM UTC 24
Peak memory 245868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
867965911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma
x_throughput.1867965911
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1006201781
Short name T561
Test name
Test status
Simulation time 104333453 ps
CPU time 4.21 seconds
Started Oct 03 12:30:12 PM UTC 24
Finished Oct 03 12:30:17 PM UTC 24
Peak memory 222464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006201781 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1006201781
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1716781884
Short name T560
Test name
Test status
Simulation time 4703366326 ps
CPU time 10.58 seconds
Started Oct 03 12:30:01 PM UTC 24
Finished Oct 03 12:30:13 PM UTC 24
Peak memory 222604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716781884 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.1716781884
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2450709927
Short name T690
Test name
Test status
Simulation time 6634019632 ps
CPU time 928.1 seconds
Started Oct 03 12:29:16 PM UTC 24
Finished Oct 03 12:44:56 PM UTC 24
Peak memory 383148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450709927 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.2450709927
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1713976589
Short name T552
Test name
Test status
Simulation time 796267925 ps
CPU time 8.32 seconds
Started Oct 03 12:29:26 PM UTC 24
Finished Oct 03 12:29:35 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713976589 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1713976589
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1392783098
Short name T604
Test name
Test status
Simulation time 20728185155 ps
CPU time 316.97 seconds
Started Oct 03 12:29:29 PM UTC 24
Finished Oct 03 12:34:51 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392783098 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc
ess_b2b.1392783098
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2120761794
Short name T557
Test name
Test status
Simulation time 29747045 ps
CPU time 1.1 seconds
Started Oct 03 12:29:58 PM UTC 24
Finished Oct 03 12:30:00 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120761794 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2120761794
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.795561400
Short name T562
Test name
Test status
Simulation time 409306917 ps
CPU time 20.84 seconds
Started Oct 03 12:29:57 PM UTC 24
Finished Oct 03 12:30:19 PM UTC 24
Peak memory 270432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795561400 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.795561400
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.119449720
Short name T551
Test name
Test status
Simulation time 5223712117 ps
CPU time 17.62 seconds
Started Oct 03 12:29:15 PM UTC 24
Finished Oct 03 12:29:34 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119449720 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.119449720
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.408379782
Short name T937
Test name
Test status
Simulation time 40906636513 ps
CPU time 3933.91 seconds
Started Oct 03 12:30:13 PM UTC 24
Finished Oct 03 01:36:29 PM UTC 24
Peak memory 389144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408379782
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.408379782
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1895891198
Short name T608
Test name
Test status
Simulation time 2021415154 ps
CPU time 304.13 seconds
Started Oct 03 12:30:12 PM UTC 24
Finished Oct 03 12:35:21 PM UTC 24
Peak memory 370884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895891198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1895891198
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1419759739
Short name T579
Test name
Test status
Simulation time 6525321964 ps
CPU time 176.96 seconds
Started Oct 03 12:29:22 PM UTC 24
Finished Oct 03 12:32:23 PM UTC 24
Peak memory 212300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419759739 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.1419759739
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3204576909
Short name T558
Test name
Test status
Simulation time 229863331 ps
CPU time 33.83 seconds
Started Oct 03 12:29:36 PM UTC 24
Finished Oct 03 12:30:11 PM UTC 24
Peak memory 286948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3204576909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t
hroughput_w_partial_write.3204576909
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3078311987
Short name T641
Test name
Test status
Simulation time 5376736594 ps
CPU time 448.27 seconds
Started Oct 03 12:31:23 PM UTC 24
Finished Oct 03 12:38:58 PM UTC 24
Peak memory 383212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078311987 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during
_key_req.3078311987
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2186520340
Short name T581
Test name
Test status
Simulation time 15839386 ps
CPU time 1.06 seconds
Started Oct 03 12:32:23 PM UTC 24
Finished Oct 03 12:32:25 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186520340 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2186520340
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1198745465
Short name T570
Test name
Test status
Simulation time 32904108132 ps
CPU time 52.28 seconds
Started Oct 03 12:30:24 PM UTC 24
Finished Oct 03 12:31:18 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198745465 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.1198745465
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2421089720
Short name T585
Test name
Test status
Simulation time 1572826118 ps
CPU time 55.57 seconds
Started Oct 03 12:31:33 PM UTC 24
Finished Oct 03 12:32:31 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421089720 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.2421089720
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3876514490
Short name T572
Test name
Test status
Simulation time 1522297912 ps
CPU time 11.8 seconds
Started Oct 03 12:31:19 PM UTC 24
Finished Oct 03 12:31:32 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876514490 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.3876514490
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.962030358
Short name T574
Test name
Test status
Simulation time 92119812 ps
CPU time 57.8 seconds
Started Oct 03 12:30:56 PM UTC 24
Finished Oct 03 12:31:55 PM UTC 24
Peak memory 303236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9
62030358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_max
_throughput.962030358
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1527716847
Short name T577
Test name
Test status
Simulation time 168578034 ps
CPU time 6.75 seconds
Started Oct 03 12:32:08 PM UTC 24
Finished Oct 03 12:32:16 PM UTC 24
Peak memory 222520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527716847 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.1527716847
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.4049866776
Short name T576
Test name
Test status
Simulation time 923617151 ps
CPU time 7.46 seconds
Started Oct 03 12:31:59 PM UTC 24
Finished Oct 03 12:32:07 PM UTC 24
Peak memory 222596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049866776 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.4049866776
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2728122209
Short name T772
Test name
Test status
Simulation time 47688219334 ps
CPU time 1475.86 seconds
Started Oct 03 12:30:22 PM UTC 24
Finished Oct 03 12:55:14 PM UTC 24
Peak memory 383288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728122209 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.2728122209
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2312520027
Short name T569
Test name
Test status
Simulation time 965070961 ps
CPU time 16.21 seconds
Started Oct 03 12:30:43 PM UTC 24
Finished Oct 03 12:31:01 PM UTC 24
Peak memory 212152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312520027 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.2312520027
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3056597853
Short name T644
Test name
Test status
Simulation time 17825495302 ps
CPU time 532.68 seconds
Started Oct 03 12:30:51 PM UTC 24
Finished Oct 03 12:39:51 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056597853 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acc
ess_b2b.3056597853
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1478284160
Short name T575
Test name
Test status
Simulation time 54134346 ps
CPU time 1.16 seconds
Started Oct 03 12:31:56 PM UTC 24
Finished Oct 03 12:31:58 PM UTC 24
Peak memory 211496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478284160 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1478284160
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2159957858
Short name T672
Test name
Test status
Simulation time 82548834526 ps
CPU time 709.06 seconds
Started Oct 03 12:31:45 PM UTC 24
Finished Oct 03 12:43:43 PM UTC 24
Peak memory 385184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159957858 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2159957858
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.1966486120
Short name T565
Test name
Test status
Simulation time 2924800374 ps
CPU time 19.53 seconds
Started Oct 03 12:30:20 PM UTC 24
Finished Oct 03 12:30:40 PM UTC 24
Peak memory 212300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966486120 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1966486120
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.725640782
Short name T621
Test name
Test status
Simulation time 1370955505 ps
CPU time 265.39 seconds
Started Oct 03 12:32:17 PM UTC 24
Finished Oct 03 12:36:47 PM UTC 24
Peak memory 381120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725640782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.725640782
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3139848554
Short name T619
Test name
Test status
Simulation time 3254035196 ps
CPU time 348.06 seconds
Started Oct 03 12:30:41 PM UTC 24
Finished Oct 03 12:36:34 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139848554 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.3139848554
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2642526350
Short name T588
Test name
Test status
Simulation time 183845059 ps
CPU time 110.06 seconds
Started Oct 03 12:31:02 PM UTC 24
Finished Oct 03 12:32:54 PM UTC 24
Peak memory 379068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2642526350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t
hroughput_w_partial_write.2642526350
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3082406169
Short name T707
Test name
Test status
Simulation time 2443157370 ps
CPU time 809.64 seconds
Started Oct 03 12:33:04 PM UTC 24
Finished Oct 03 12:46:43 PM UTC 24
Peak memory 381112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082406169 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during
_key_req.3082406169
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1635448914
Short name T598
Test name
Test status
Simulation time 14657301 ps
CPU time 0.96 seconds
Started Oct 03 12:33:58 PM UTC 24
Finished Oct 03 12:34:00 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635448914 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1635448914
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.1844702393
Short name T591
Test name
Test status
Simulation time 7711391292 ps
CPU time 64.33 seconds
Started Oct 03 12:32:27 PM UTC 24
Finished Oct 03 12:33:33 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844702393 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.1844702393
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3949904681
Short name T656
Test name
Test status
Simulation time 15861430212 ps
CPU time 475.41 seconds
Started Oct 03 12:33:05 PM UTC 24
Finished Oct 03 12:41:07 PM UTC 24
Peak memory 379136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949904681 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3949904681
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1560059044
Short name T590
Test name
Test status
Simulation time 1594726496 ps
CPU time 7.07 seconds
Started Oct 03 12:32:56 PM UTC 24
Finished Oct 03 12:33:04 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560059044 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.1560059044
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3056653220
Short name T587
Test name
Test status
Simulation time 311499738 ps
CPU time 12.12 seconds
Started Oct 03 12:32:37 PM UTC 24
Finished Oct 03 12:32:51 PM UTC 24
Peak memory 268552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
056653220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma
x_throughput.3056653220
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1501575300
Short name T597
Test name
Test status
Simulation time 472739834 ps
CPU time 5.23 seconds
Started Oct 03 12:33:51 PM UTC 24
Finished Oct 03 12:33:57 PM UTC 24
Peak memory 222460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501575300 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.1501575300
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.389880840
Short name T595
Test name
Test status
Simulation time 333239449 ps
CPU time 9.43 seconds
Started Oct 03 12:33:42 PM UTC 24
Finished Oct 03 12:33:53 PM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389880840 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.389880840
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2395389514
Short name T687
Test name
Test status
Simulation time 10991762691 ps
CPU time 732.02 seconds
Started Oct 03 12:32:27 PM UTC 24
Finished Oct 03 12:44:48 PM UTC 24
Peak memory 383268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395389514 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.2395389514
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2534073406
Short name T586
Test name
Test status
Simulation time 195948551 ps
CPU time 5.23 seconds
Started Oct 03 12:32:30 PM UTC 24
Finished Oct 03 12:32:36 PM UTC 24
Peak memory 212208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534073406 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.2534073406
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3894080657
Short name T663
Test name
Test status
Simulation time 21382181538 ps
CPU time 585.29 seconds
Started Oct 03 12:32:32 PM UTC 24
Finished Oct 03 12:42:25 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894080657 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc
ess_b2b.3894080657
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2325471102
Short name T593
Test name
Test status
Simulation time 53517460 ps
CPU time 1.51 seconds
Started Oct 03 12:33:39 PM UTC 24
Finished Oct 03 12:33:42 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325471102 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2325471102
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.557682312
Short name T680
Test name
Test status
Simulation time 57819993816 ps
CPU time 646.74 seconds
Started Oct 03 12:33:34 PM UTC 24
Finished Oct 03 12:44:29 PM UTC 24
Peak memory 383280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557682312 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.557682312
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.2725149264
Short name T583
Test name
Test status
Simulation time 28994886 ps
CPU time 1.23 seconds
Started Oct 03 12:32:25 PM UTC 24
Finished Oct 03 12:32:27 PM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725149264 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2725149264
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2129662954
Short name T788
Test name
Test status
Simulation time 29085912320 ps
CPU time 1412.15 seconds
Started Oct 03 12:33:55 PM UTC 24
Finished Oct 03 12:57:43 PM UTC 24
Peak memory 385332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212966295
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.2129662954
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.599214440
Short name T658
Test name
Test status
Simulation time 1049919158 ps
CPU time 436.28 seconds
Started Oct 03 12:33:54 PM UTC 24
Finished Oct 03 12:41:16 PM UTC 24
Peak memory 366860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599214440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.599214440
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.61432740
Short name T622
Test name
Test status
Simulation time 2725704434 ps
CPU time 255.21 seconds
Started Oct 03 12:32:28 PM UTC 24
Finished Oct 03 12:36:47 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61432740 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.61432740
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1198275163
Short name T592
Test name
Test status
Simulation time 125539287 ps
CPU time 45.23 seconds
Started Oct 03 12:32:52 PM UTC 24
Finished Oct 03 12:33:38 PM UTC 24
Peak memory 344180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1198275163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_t
hroughput_w_partial_write.1198275163
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.4000119837
Short name T825
Test name
Test status
Simulation time 21490634093 ps
CPU time 1516.71 seconds
Started Oct 03 12:35:14 PM UTC 24
Finished Oct 03 01:00:47 PM UTC 24
Peak memory 383292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000119837 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during
_key_req.4000119837
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3443169993
Short name T616
Test name
Test status
Simulation time 11362132 ps
CPU time 0.98 seconds
Started Oct 03 12:36:00 PM UTC 24
Finished Oct 03 12:36:02 PM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443169993 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3443169993
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1742553484
Short name T605
Test name
Test status
Simulation time 2013600601 ps
CPU time 43.82 seconds
Started Oct 03 12:34:17 PM UTC 24
Finished Oct 03 12:35:03 PM UTC 24
Peak memory 212232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742553484 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1742553484
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3700792375
Short name T786
Test name
Test status
Simulation time 54907283326 ps
CPU time 1315.91 seconds
Started Oct 03 12:35:22 PM UTC 24
Finished Oct 03 12:57:32 PM UTC 24
Peak memory 385208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700792375 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.3700792375
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3835573068
Short name T607
Test name
Test status
Simulation time 1047944172 ps
CPU time 7.45 seconds
Started Oct 03 12:35:05 PM UTC 24
Finished Oct 03 12:35:14 PM UTC 24
Peak memory 222520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835573068 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.3835573068
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.520531143
Short name T615
Test name
Test status
Simulation time 1139105903 ps
CPU time 65.63 seconds
Started Oct 03 12:34:51 PM UTC 24
Finished Oct 03 12:35:58 PM UTC 24
Peak memory 354568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5
20531143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_max
_throughput.520531143
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2877328842
Short name T613
Test name
Test status
Simulation time 157728880 ps
CPU time 6.43 seconds
Started Oct 03 12:35:41 PM UTC 24
Finished Oct 03 12:35:49 PM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877328842 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.2877328842
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3789094767
Short name T614
Test name
Test status
Simulation time 1686456605 ps
CPU time 11.82 seconds
Started Oct 03 12:35:39 PM UTC 24
Finished Oct 03 12:35:52 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789094767 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.3789094767
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1586592503
Short name T802
Test name
Test status
Simulation time 14559196975 ps
CPU time 1440.51 seconds
Started Oct 03 12:34:11 PM UTC 24
Finished Oct 03 12:58:29 PM UTC 24
Peak memory 385384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586592503 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.1586592503
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1416600646
Short name T606
Test name
Test status
Simulation time 562849539 ps
CPU time 43.54 seconds
Started Oct 03 12:34:20 PM UTC 24
Finished Oct 03 12:35:05 PM UTC 24
Peak memory 319652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416600646 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.1416600646
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2541532605
Short name T638
Test name
Test status
Simulation time 78468925749 ps
CPU time 223.86 seconds
Started Oct 03 12:34:45 PM UTC 24
Finished Oct 03 12:38:32 PM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541532605 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc
ess_b2b.2541532605
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1353546396
Short name T611
Test name
Test status
Simulation time 95054770 ps
CPU time 1.18 seconds
Started Oct 03 12:35:36 PM UTC 24
Finished Oct 03 12:35:38 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353546396 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1353546396
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2451432078
Short name T654
Test name
Test status
Simulation time 13274644662 ps
CPU time 311.75 seconds
Started Oct 03 12:35:35 PM UTC 24
Finished Oct 03 12:40:51 PM UTC 24
Peak memory 383152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451432078 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2451432078
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.866206684
Short name T601
Test name
Test status
Simulation time 439451149 ps
CPU time 14.76 seconds
Started Oct 03 12:34:01 PM UTC 24
Finished Oct 03 12:34:17 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866206684 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.866206684
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2025409566
Short name T889
Test name
Test status
Simulation time 336763379187 ps
CPU time 1962.91 seconds
Started Oct 03 12:35:52 PM UTC 24
Finished Oct 03 01:08:58 PM UTC 24
Peak memory 385260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202540956
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.2025409566
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1103722624
Short name T620
Test name
Test status
Simulation time 1223633260 ps
CPU time 43.79 seconds
Started Oct 03 12:35:49 PM UTC 24
Finished Oct 03 12:36:35 PM UTC 24
Peak memory 305308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103722624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1103722624
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.213816441
Short name T655
Test name
Test status
Simulation time 7530058153 ps
CPU time 394.35 seconds
Started Oct 03 12:34:17 PM UTC 24
Finished Oct 03 12:40:58 PM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213816441 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.213816441
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1485042011
Short name T609
Test name
Test status
Simulation time 92204176 ps
CPU time 28.28 seconds
Started Oct 03 12:35:04 PM UTC 24
Finished Oct 03 12:35:34 PM UTC 24
Peak memory 290924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1485042011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t
hroughput_w_partial_write.1485042011
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3920578629
Short name T635
Test name
Test status
Simulation time 899598794 ps
CPU time 42.4 seconds
Started Oct 03 12:37:10 PM UTC 24
Finished Oct 03 12:37:54 PM UTC 24
Peak memory 301288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920578629 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during
_key_req.3920578629
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1675776659
Short name T634
Test name
Test status
Simulation time 14735883 ps
CPU time 1 seconds
Started Oct 03 12:37:51 PM UTC 24
Finished Oct 03 12:37:53 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675776659 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1675776659
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.2613727931
Short name T627
Test name
Test status
Simulation time 6517340828 ps
CPU time 66.99 seconds
Started Oct 03 12:36:20 PM UTC 24
Finished Oct 03 12:37:29 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613727931 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.2613727931
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.120890483
Short name T640
Test name
Test status
Simulation time 2395042259 ps
CPU time 92.6 seconds
Started Oct 03 12:37:17 PM UTC 24
Finished Oct 03 12:38:51 PM UTC 24
Peak memory 297216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120890483 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.120890483
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3944447200
Short name T626
Test name
Test status
Simulation time 788533741 ps
CPU time 12.14 seconds
Started Oct 03 12:37:02 PM UTC 24
Finished Oct 03 12:37:16 PM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944447200 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.3944447200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3734236523
Short name T631
Test name
Test status
Simulation time 112469004 ps
CPU time 45.93 seconds
Started Oct 03 12:36:48 PM UTC 24
Finished Oct 03 12:37:35 PM UTC 24
Peak memory 315660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
734236523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma
x_throughput.3734236523
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.595784121
Short name T632
Test name
Test status
Simulation time 68125991 ps
CPU time 4.46 seconds
Started Oct 03 12:37:36 PM UTC 24
Finished Oct 03 12:37:42 PM UTC 24
Peak memory 222448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595784121 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.595784121
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2801004118
Short name T633
Test name
Test status
Simulation time 1647003066 ps
CPU time 14.23 seconds
Started Oct 03 12:37:34 PM UTC 24
Finished Oct 03 12:37:50 PM UTC 24
Peak memory 222528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801004118 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.2801004118
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.733227631
Short name T623
Test name
Test status
Simulation time 344440557 ps
CPU time 29.67 seconds
Started Oct 03 12:36:16 PM UTC 24
Finished Oct 03 12:36:47 PM UTC 24
Peak memory 272552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733227631 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.733227631
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3936374818
Short name T637
Test name
Test status
Simulation time 806117680 ps
CPU time 111.02 seconds
Started Oct 03 12:36:35 PM UTC 24
Finished Oct 03 12:38:29 PM UTC 24
Peak memory 377020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936374818 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.3936374818
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.11765144
Short name T676
Test name
Test status
Simulation time 16020446630 ps
CPU time 442.48 seconds
Started Oct 03 12:36:48 PM UTC 24
Finished Oct 03 12:44:16 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11765144 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acces
s_b2b.11765144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1965514183
Short name T630
Test name
Test status
Simulation time 89518342 ps
CPU time 1.13 seconds
Started Oct 03 12:37:33 PM UTC 24
Finished Oct 03 12:37:35 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965514183 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1965514183
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.562108086
Short name T754
Test name
Test status
Simulation time 41452102580 ps
CPU time 940.67 seconds
Started Oct 03 12:37:30 PM UTC 24
Finished Oct 03 12:53:22 PM UTC 24
Peak memory 383212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562108086 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.562108086
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.4274398168
Short name T617
Test name
Test status
Simulation time 1040576629 ps
CPU time 10.86 seconds
Started Oct 03 12:36:03 PM UTC 24
Finished Oct 03 12:36:15 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274398168 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.4274398168
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.511120569
Short name T939
Test name
Test status
Simulation time 13009898286 ps
CPU time 3879.5 seconds
Started Oct 03 12:37:43 PM UTC 24
Finished Oct 03 01:43:06 PM UTC 24
Peak memory 386908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511120569
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.511120569
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4163222490
Short name T728
Test name
Test status
Simulation time 1340762211 ps
CPU time 721.67 seconds
Started Oct 03 12:37:36 PM UTC 24
Finished Oct 03 12:49:47 PM UTC 24
Peak memory 379044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163222490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4163222490
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.679272525
Short name T668
Test name
Test status
Simulation time 3820789718 ps
CPU time 399.34 seconds
Started Oct 03 12:36:35 PM UTC 24
Finished Oct 03 12:43:20 PM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679272525 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.679272525
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.286807048
Short name T629
Test name
Test status
Simulation time 706733960 ps
CPU time 43.74 seconds
Started Oct 03 12:36:48 PM UTC 24
Finished Oct 03 12:37:33 PM UTC 24
Peak memory 327872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
286807048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_th
roughput_w_partial_write.286807048
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2153626685
Short name T840
Test name
Test status
Simulation time 14530279423 ps
CPU time 1438.9 seconds
Started Oct 03 12:39:12 PM UTC 24
Finished Oct 03 01:03:27 PM UTC 24
Peak memory 383276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153626685 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during
_key_req.2153626685
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1848515119
Short name T652
Test name
Test status
Simulation time 35304563 ps
CPU time 1 seconds
Started Oct 03 12:40:35 PM UTC 24
Finished Oct 03 12:40:37 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848515119 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1848515119
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.3426737782
Short name T639
Test name
Test status
Simulation time 6113588548 ps
CPU time 23.36 seconds
Started Oct 03 12:38:20 PM UTC 24
Finished Oct 03 12:38:45 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426737782 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.3426737782
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1448184281
Short name T675
Test name
Test status
Simulation time 5667132400 ps
CPU time 259.24 seconds
Started Oct 03 12:39:53 PM UTC 24
Finished Oct 03 12:44:16 PM UTC 24
Peak memory 346296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448184281 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.1448184281
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2099246583
Short name T643
Test name
Test status
Simulation time 237969634 ps
CPU time 3.09 seconds
Started Oct 03 12:39:07 PM UTC 24
Finished Oct 03 12:39:12 PM UTC 24
Peak memory 226624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099246583 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.2099246583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.367353352
Short name T648
Test name
Test status
Simulation time 128140844 ps
CPU time 76.09 seconds
Started Oct 03 12:38:52 PM UTC 24
Finished Oct 03 12:40:11 PM UTC 24
Peak memory 358732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
67353352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max
_throughput.367353352
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.665768930
Short name T649
Test name
Test status
Simulation time 59963168 ps
CPU time 4.25 seconds
Started Oct 03 12:40:11 PM UTC 24
Finished Oct 03 12:40:17 PM UTC 24
Peak memory 222392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665768930 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.665768930
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1404038129
Short name T650
Test name
Test status
Simulation time 4085431403 ps
CPU time 14.73 seconds
Started Oct 03 12:40:05 PM UTC 24
Finished Oct 03 12:40:21 PM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404038129 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.1404038129
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.989337930
Short name T782
Test name
Test status
Simulation time 31625007981 ps
CPU time 1119.42 seconds
Started Oct 03 12:37:55 PM UTC 24
Finished Oct 03 12:56:48 PM UTC 24
Peak memory 368808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989337930 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.989337930
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3159991527
Short name T645
Test name
Test status
Simulation time 641348448 ps
CPU time 85.21 seconds
Started Oct 03 12:38:33 PM UTC 24
Finished Oct 03 12:40:01 PM UTC 24
Peak memory 323876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159991527 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.3159991527
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1658752385
Short name T698
Test name
Test status
Simulation time 45687604362 ps
CPU time 431.34 seconds
Started Oct 03 12:38:46 PM UTC 24
Finished Oct 03 12:46:03 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658752385 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acc
ess_b2b.1658752385
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.2733646055
Short name T647
Test name
Test status
Simulation time 78720323 ps
CPU time 1.17 seconds
Started Oct 03 12:40:02 PM UTC 24
Finished Oct 03 12:40:04 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733646055 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2733646055
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.4031031997
Short name T751
Test name
Test status
Simulation time 12752698330 ps
CPU time 780.47 seconds
Started Oct 03 12:40:02 PM UTC 24
Finished Oct 03 12:53:12 PM UTC 24
Peak memory 385244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031031997 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.4031031997
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.4222451957
Short name T636
Test name
Test status
Simulation time 853102652 ps
CPU time 24.2 seconds
Started Oct 03 12:37:54 PM UTC 24
Finished Oct 03 12:38:19 PM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222451957 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.4222451957
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3946080762
Short name T940
Test name
Test status
Simulation time 112402606735 ps
CPU time 4166.17 seconds
Started Oct 03 12:40:22 PM UTC 24
Finished Oct 03 01:50:39 PM UTC 24
Peak memory 386980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394608076
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.3946080762
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3655172878
Short name T52
Test name
Test status
Simulation time 2403848084 ps
CPU time 202.67 seconds
Started Oct 03 12:40:17 PM UTC 24
Finished Oct 03 12:43:43 PM UTC 24
Peak memory 385224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655172878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3655172878
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3740306583
Short name T671
Test name
Test status
Simulation time 3188361578 ps
CPU time 294.35 seconds
Started Oct 03 12:38:29 PM UTC 24
Finished Oct 03 12:43:28 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740306583 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.3740306583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.202702070
Short name T646
Test name
Test status
Simulation time 422629108 ps
CPU time 60.01 seconds
Started Oct 03 12:38:59 PM UTC 24
Finished Oct 03 12:40:01 PM UTC 24
Peak memory 311484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
202702070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_th
roughput_w_partial_write.202702070
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.838661195
Short name T727
Test name
Test status
Simulation time 2101923774 ps
CPU time 463.33 seconds
Started Oct 03 12:41:51 PM UTC 24
Finished Oct 03 12:49:41 PM UTC 24
Peak memory 342136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838661195 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_
key_req.838661195
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1855713982
Short name T669
Test name
Test status
Simulation time 22170143 ps
CPU time 0.97 seconds
Started Oct 03 12:43:22 PM UTC 24
Finished Oct 03 12:43:24 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855713982 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1855713982
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1982431727
Short name T659
Test name
Test status
Simulation time 2104529852 ps
CPU time 52.72 seconds
Started Oct 03 12:40:52 PM UTC 24
Finished Oct 03 12:41:47 PM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982431727 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.1982431727
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3916943863
Short name T817
Test name
Test status
Simulation time 61156429901 ps
CPU time 1098.91 seconds
Started Oct 03 12:41:56 PM UTC 24
Finished Oct 03 01:00:28 PM UTC 24
Peak memory 371012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916943863 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.3916943863
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.427504583
Short name T661
Test name
Test status
Simulation time 446115836 ps
CPU time 6.37 seconds
Started Oct 03 12:41:47 PM UTC 24
Finished Oct 03 12:41:55 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427504583 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.427504583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.4094168728
Short name T667
Test name
Test status
Simulation time 131166642 ps
CPU time 94.77 seconds
Started Oct 03 12:41:17 PM UTC 24
Finished Oct 03 12:42:53 PM UTC 24
Peak memory 354508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
094168728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ma
x_throughput.4094168728
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2823335167
Short name T666
Test name
Test status
Simulation time 192660920 ps
CPU time 4.23 seconds
Started Oct 03 12:42:39 PM UTC 24
Finished Oct 03 12:42:45 PM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823335167 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.2823335167
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.45157815
Short name T665
Test name
Test status
Simulation time 331489499 ps
CPU time 8.15 seconds
Started Oct 03 12:42:29 PM UTC 24
Finished Oct 03 12:42:38 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45157815 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.45157815
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3518325758
Short name T742
Test name
Test status
Simulation time 15330944697 ps
CPU time 665.38 seconds
Started Oct 03 12:40:48 PM UTC 24
Finished Oct 03 12:52:02 PM UTC 24
Peak memory 385272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518325758 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.3518325758
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3757107946
Short name T657
Test name
Test status
Simulation time 164464976 ps
CPU time 6.32 seconds
Started Oct 03 12:41:07 PM UTC 24
Finished Oct 03 12:41:15 PM UTC 24
Peak memory 239804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757107946 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3757107946
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3503094539
Short name T726
Test name
Test status
Simulation time 28679893721 ps
CPU time 497.53 seconds
Started Oct 03 12:41:16 PM UTC 24
Finished Oct 03 12:49:40 PM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503094539 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc
ess_b2b.3503094539
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3599693799
Short name T664
Test name
Test status
Simulation time 28376762 ps
CPU time 1 seconds
Started Oct 03 12:42:26 PM UTC 24
Finished Oct 03 12:42:28 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599693799 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3599693799
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2965519423
Short name T709
Test name
Test status
Simulation time 24248485950 ps
CPU time 300.04 seconds
Started Oct 03 12:41:57 PM UTC 24
Finished Oct 03 12:47:01 PM UTC 24
Peak memory 354468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965519423 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2965519423
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2332612466
Short name T662
Test name
Test status
Simulation time 2196172636 ps
CPU time 76 seconds
Started Oct 03 12:40:38 PM UTC 24
Finished Oct 03 12:41:56 PM UTC 24
Peak memory 364728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332612466 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2332612466
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2927724828
Short name T922
Test name
Test status
Simulation time 14520132500 ps
CPU time 2347.69 seconds
Started Oct 03 12:42:55 PM UTC 24
Finished Oct 03 01:22:30 PM UTC 24
Peak memory 385292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292772482
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.2927724828
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2042636624
Short name T783
Test name
Test status
Simulation time 2198258389 ps
CPU time 837.19 seconds
Started Oct 03 12:42:45 PM UTC 24
Finished Oct 03 12:56:53 PM UTC 24
Peak memory 389580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042636624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2042636624
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1670715935
Short name T673
Test name
Test status
Simulation time 7719312132 ps
CPU time 167.16 seconds
Started Oct 03 12:40:58 PM UTC 24
Finished Oct 03 12:43:49 PM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670715935 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.1670715935
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.340687978
Short name T660
Test name
Test status
Simulation time 169667247 ps
CPU time 15.25 seconds
Started Oct 03 12:41:34 PM UTC 24
Finished Oct 03 12:41:51 PM UTC 24
Peak memory 284856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
340687978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_th
roughput_w_partial_write.340687978
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2242429130
Short name T756
Test name
Test status
Simulation time 7559950366 ps
CPU time 542.64 seconds
Started Oct 03 12:44:19 PM UTC 24
Finished Oct 03 12:53:29 PM UTC 24
Peak memory 385280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242429130 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during
_key_req.2242429130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3418578547
Short name T688
Test name
Test status
Simulation time 13168632 ps
CPU time 0.9 seconds
Started Oct 03 12:44:46 PM UTC 24
Finished Oct 03 12:44:48 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418578547 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3418578547
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.1238236713
Short name T679
Test name
Test status
Simulation time 18312017617 ps
CPU time 58.4 seconds
Started Oct 03 12:43:29 PM UTC 24
Finished Oct 03 12:44:29 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238236713 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.1238236713
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1136955085
Short name T926
Test name
Test status
Simulation time 21957706051 ps
CPU time 2396.22 seconds
Started Oct 03 12:44:21 PM UTC 24
Finished Oct 03 01:24:44 PM UTC 24
Peak memory 383232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136955085 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.1136955085
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3002319508
Short name T681
Test name
Test status
Simulation time 483514287 ps
CPU time 10.15 seconds
Started Oct 03 12:44:18 PM UTC 24
Finished Oct 03 12:44:30 PM UTC 24
Peak memory 222440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002319508 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.3002319508
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.386768352
Short name T677
Test name
Test status
Simulation time 69402338 ps
CPU time 11.89 seconds
Started Oct 03 12:44:05 PM UTC 24
Finished Oct 03 12:44:18 PM UTC 24
Peak memory 270604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
86768352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_max
_throughput.386768352
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1179324737
Short name T684
Test name
Test status
Simulation time 185625854 ps
CPU time 3.51 seconds
Started Oct 03 12:44:34 PM UTC 24
Finished Oct 03 12:44:39 PM UTC 24
Peak memory 222648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179324737 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.1179324737
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.588466942
Short name T686
Test name
Test status
Simulation time 467822397 ps
CPU time 13.43 seconds
Started Oct 03 12:44:31 PM UTC 24
Finished Oct 03 12:44:45 PM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588466942 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.588466942
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1694007218
Short name T931
Test name
Test status
Simulation time 22290510347 ps
CPU time 2605.43 seconds
Started Oct 03 12:43:27 PM UTC 24
Finished Oct 03 01:27:24 PM UTC 24
Peak memory 385412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694007218 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1694007218
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3041950797
Short name T692
Test name
Test status
Simulation time 470533241 ps
CPU time 78.35 seconds
Started Oct 03 12:43:44 PM UTC 24
Finished Oct 03 12:45:05 PM UTC 24
Peak memory 329828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041950797 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.3041950797
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2506554807
Short name T774
Test name
Test status
Simulation time 280482938738 ps
CPU time 718.45 seconds
Started Oct 03 12:43:50 PM UTC 24
Finished Oct 03 12:55:58 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506554807 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc
ess_b2b.2506554807
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1042744518
Short name T682
Test name
Test status
Simulation time 85408797 ps
CPU time 1.21 seconds
Started Oct 03 12:44:31 PM UTC 24
Finished Oct 03 12:44:33 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042744518 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1042744518
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1999246184
Short name T732
Test name
Test status
Simulation time 711667662 ps
CPU time 363.08 seconds
Started Oct 03 12:44:30 PM UTC 24
Finished Oct 03 12:50:37 PM UTC 24
Peak memory 379068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999246184 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1999246184
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.362395705
Short name T674
Test name
Test status
Simulation time 99389124 ps
CPU time 37.29 seconds
Started Oct 03 12:43:25 PM UTC 24
Finished Oct 03 12:44:04 PM UTC 24
Peak memory 307360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362395705 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.362395705
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2874314300
Short name T915
Test name
Test status
Simulation time 8304383302 ps
CPU time 2040.09 seconds
Started Oct 03 12:44:39 PM UTC 24
Finished Oct 03 01:19:04 PM UTC 24
Peak memory 383240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287431430
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.2874314300
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1542739630
Short name T685
Test name
Test status
Simulation time 246773068 ps
CPU time 7.83 seconds
Started Oct 03 12:44:36 PM UTC 24
Finished Oct 03 12:44:45 PM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542739630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1542739630
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.3952320473
Short name T715
Test name
Test status
Simulation time 2283030310 ps
CPU time 242.5 seconds
Started Oct 03 12:43:43 PM UTC 24
Finished Oct 03 12:47:50 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952320473 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.3952320473
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2368168066
Short name T678
Test name
Test status
Simulation time 125276209 ps
CPU time 1.44 seconds
Started Oct 03 12:44:17 PM UTC 24
Finished Oct 03 12:44:20 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2368168066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t
hroughput_w_partial_write.2368168066
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2279932622
Short name T738
Test name
Test status
Simulation time 8942377010 ps
CPU time 372.94 seconds
Started Oct 03 12:45:26 PM UTC 24
Finished Oct 03 12:51:44 PM UTC 24
Peak memory 381112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279932622 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during
_key_req.2279932622
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1929242029
Short name T703
Test name
Test status
Simulation time 41363851 ps
CPU time 1.1 seconds
Started Oct 03 12:46:18 PM UTC 24
Finished Oct 03 12:46:20 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929242029 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1929242029
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.3578693577
Short name T696
Test name
Test status
Simulation time 2583840096 ps
CPU time 37.68 seconds
Started Oct 03 12:44:50 PM UTC 24
Finished Oct 03 12:45:29 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578693577 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.3578693577
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.1282807593
Short name T763
Test name
Test status
Simulation time 7572988326 ps
CPU time 524.77 seconds
Started Oct 03 12:45:30 PM UTC 24
Finished Oct 03 12:54:21 PM UTC 24
Peak memory 385284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282807593 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.1282807593
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2865297840
Short name T695
Test name
Test status
Simulation time 404429805 ps
CPU time 6.8 seconds
Started Oct 03 12:45:17 PM UTC 24
Finished Oct 03 12:45:25 PM UTC 24
Peak memory 212220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865297840 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2865297840
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1440518668
Short name T693
Test name
Test status
Simulation time 185172059 ps
CPU time 4.56 seconds
Started Oct 03 12:45:05 PM UTC 24
Finished Oct 03 12:45:11 PM UTC 24
Peak memory 231684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
440518668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ma
x_throughput.1440518668
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3737961856
Short name T704
Test name
Test status
Simulation time 397131842 ps
CPU time 7.69 seconds
Started Oct 03 12:46:14 PM UTC 24
Finished Oct 03 12:46:23 PM UTC 24
Peak memory 222440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737961856 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.3737961856
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1521583093
Short name T702
Test name
Test status
Simulation time 433829827 ps
CPU time 7.38 seconds
Started Oct 03 12:46:08 PM UTC 24
Finished Oct 03 12:46:16 PM UTC 24
Peak memory 222460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521583093 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.1521583093
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1698264539
Short name T873
Test name
Test status
Simulation time 12144570332 ps
CPU time 1354.48 seconds
Started Oct 03 12:44:49 PM UTC 24
Finished Oct 03 01:07:39 PM UTC 24
Peak memory 383200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698264539 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.1698264539
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1375415433
Short name T691
Test name
Test status
Simulation time 918966447 ps
CPU time 7.02 seconds
Started Oct 03 12:44:56 PM UTC 24
Finished Oct 03 12:45:04 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375415433 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1375415433
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.3116208768
Short name T768
Test name
Test status
Simulation time 76075674681 ps
CPU time 567.47 seconds
Started Oct 03 12:45:05 PM UTC 24
Finished Oct 03 12:54:40 PM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116208768 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acc
ess_b2b.3116208768
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3029523808
Short name T699
Test name
Test status
Simulation time 25362604 ps
CPU time 1.23 seconds
Started Oct 03 12:46:04 PM UTC 24
Finished Oct 03 12:46:07 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029523808 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3029523808
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.3766049521
Short name T798
Test name
Test status
Simulation time 18572461832 ps
CPU time 740.13 seconds
Started Oct 03 12:45:38 PM UTC 24
Finished Oct 03 12:58:08 PM UTC 24
Peak memory 379188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766049521 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3766049521
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1582383243
Short name T689
Test name
Test status
Simulation time 224126668 ps
CPU time 1.25 seconds
Started Oct 03 12:44:47 PM UTC 24
Finished Oct 03 12:44:49 PM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582383243 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1582383243
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.164546559
Short name T885
Test name
Test status
Simulation time 8090132563 ps
CPU time 1299.23 seconds
Started Oct 03 12:46:17 PM UTC 24
Finished Oct 03 01:08:12 PM UTC 24
Peak memory 383232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164546559
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.164546559
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4222997510
Short name T713
Test name
Test status
Simulation time 1326507741 ps
CPU time 83.98 seconds
Started Oct 03 12:46:15 PM UTC 24
Finished Oct 03 12:47:41 PM UTC 24
Peak memory 301240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222997510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.4222997510
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.4045208063
Short name T722
Test name
Test status
Simulation time 1639290626 ps
CPU time 197.6 seconds
Started Oct 03 12:44:50 PM UTC 24
Finished Oct 03 12:48:11 PM UTC 24
Peak memory 212300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045208063 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.4045208063
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.3749453814
Short name T694
Test name
Test status
Simulation time 98003600 ps
CPU time 2.92 seconds
Started Oct 03 12:45:12 PM UTC 24
Finished Oct 03 12:45:16 PM UTC 24
Peak memory 228660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3749453814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_t
hroughput_w_partial_write.3749453814
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1969338952
Short name T41
Test name
Test status
Simulation time 1082477863 ps
CPU time 282.29 seconds
Started Oct 03 11:48:13 AM UTC 24
Finished Oct 03 11:53:00 AM UTC 24
Peak memory 379068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969338952 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_
key_req.1969338952
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2091887263
Short name T165
Test name
Test status
Simulation time 45605190 ps
CPU time 1.04 seconds
Started Oct 03 11:48:34 AM UTC 24
Finished Oct 03 11:48:36 AM UTC 24
Peak memory 211164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091887263 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2091887263
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.3870793822
Short name T167
Test name
Test status
Simulation time 4270529251 ps
CPU time 40.77 seconds
Started Oct 03 11:47:56 AM UTC 24
Finished Oct 03 11:48:39 AM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870793822 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.3870793822
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1228540211
Short name T28
Test name
Test status
Simulation time 688862859 ps
CPU time 169.89 seconds
Started Oct 03 11:48:21 AM UTC 24
Finished Oct 03 11:51:14 AM UTC 24
Peak memory 372932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228540211 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.1228540211
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3572973397
Short name T22
Test name
Test status
Simulation time 2076288031 ps
CPU time 12.68 seconds
Started Oct 03 11:48:07 AM UTC 24
Finished Oct 03 11:48:21 AM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572973397 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.3572973397
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1106433013
Short name T161
Test name
Test status
Simulation time 138022309 ps
CPU time 89.79 seconds
Started Oct 03 11:48:03 AM UTC 24
Finished Oct 03 11:49:35 AM UTC 24
Peak memory 379080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
106433013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max
_throughput.1106433013
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2731670854
Short name T47
Test name
Test status
Simulation time 239526061 ps
CPU time 4.24 seconds
Started Oct 03 11:48:28 AM UTC 24
Finished Oct 03 11:48:33 AM UTC 24
Peak memory 222552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731670854 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.2731670854
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3536162171
Short name T166
Test name
Test status
Simulation time 279063103 ps
CPU time 10.6 seconds
Started Oct 03 11:48:26 AM UTC 24
Finished Oct 03 11:48:38 AM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536162171 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.3536162171
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2618399669
Short name T261
Test name
Test status
Simulation time 10168388145 ps
CPU time 704.78 seconds
Started Oct 03 11:47:53 AM UTC 24
Finished Oct 03 11:59:47 AM UTC 24
Peak memory 383276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618399669 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.2618399669
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.787421186
Short name T162
Test name
Test status
Simulation time 518499077 ps
CPU time 13.17 seconds
Started Oct 03 11:47:58 AM UTC 24
Finished Oct 03 11:48:12 AM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787421186 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.787421186
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.318886737
Short name T206
Test name
Test status
Simulation time 3973518029 ps
CPU time 306.53 seconds
Started Oct 03 11:47:59 AM UTC 24
Finished Oct 03 11:53:10 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318886737 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acces
s_b2b.318886737
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2594236019
Short name T164
Test name
Test status
Simulation time 28400557 ps
CPU time 1.13 seconds
Started Oct 03 11:48:25 AM UTC 24
Finished Oct 03 11:48:27 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594236019 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2594236019
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1434817778
Short name T134
Test name
Test status
Simulation time 39642889555 ps
CPU time 491.09 seconds
Started Oct 03 11:48:22 AM UTC 24
Finished Oct 03 11:56:40 AM UTC 24
Peak memory 383356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434817778 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1434817778
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1219853860
Short name T34
Test name
Test status
Simulation time 569840315 ps
CPU time 3.2 seconds
Started Oct 03 11:48:34 AM UTC 24
Finished Oct 03 11:48:38 AM UTC 24
Peak memory 248228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219853860 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1219853860
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.1438877451
Short name T163
Test name
Test status
Simulation time 183905488 ps
CPU time 8.7 seconds
Started Oct 03 11:47:53 AM UTC 24
Finished Oct 03 11:48:03 AM UTC 24
Peak memory 243880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438877451 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1438877451
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1978095496
Short name T824
Test name
Test status
Simulation time 234836673554 ps
CPU time 4290.99 seconds
Started Oct 03 11:48:29 AM UTC 24
Finished Oct 03 01:00:46 PM UTC 24
Peak memory 386896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197809549
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.1978095496
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2646488998
Short name T194
Test name
Test status
Simulation time 6024583710 ps
CPU time 232.21 seconds
Started Oct 03 11:47:58 AM UTC 24
Finished Oct 03 11:51:53 AM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646488998 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.2646488998
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1479756945
Short name T169
Test name
Test status
Simulation time 555146794 ps
CPU time 63.54 seconds
Started Oct 03 11:48:04 AM UTC 24
Finished Oct 03 11:49:10 AM UTC 24
Peak memory 342272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1479756945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th
roughput_w_partial_write.1479756945
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1874086873
Short name T901
Test name
Test status
Simulation time 16531201663 ps
CPU time 1551.63 seconds
Started Oct 03 12:47:35 PM UTC 24
Finished Oct 03 01:13:44 PM UTC 24
Peak memory 383164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874086873 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during
_key_req.1874086873
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.2470097791
Short name T721
Test name
Test status
Simulation time 29390627 ps
CPU time 0.87 seconds
Started Oct 03 12:48:06 PM UTC 24
Finished Oct 03 12:48:08 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470097791 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.2470097791
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.108693098
Short name T719
Test name
Test status
Simulation time 7237600949 ps
CPU time 97.64 seconds
Started Oct 03 12:46:25 PM UTC 24
Finished Oct 03 12:48:05 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108693098 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.108693098
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3357553771
Short name T925
Test name
Test status
Simulation time 47001886757 ps
CPU time 2197.26 seconds
Started Oct 03 12:47:42 PM UTC 24
Finished Oct 03 01:24:44 PM UTC 24
Peak memory 385280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357553771 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.3357553771
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.937419979
Short name T714
Test name
Test status
Simulation time 2656897613 ps
CPU time 8.93 seconds
Started Oct 03 12:47:32 PM UTC 24
Finished Oct 03 12:47:42 PM UTC 24
Peak memory 222608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937419979 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.937419979
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.245402403
Short name T716
Test name
Test status
Simulation time 382499637 ps
CPU time 47.98 seconds
Started Oct 03 12:47:02 PM UTC 24
Finished Oct 03 12:47:52 PM UTC 24
Peak memory 317688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
45402403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max
_throughput.245402403
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3335743626
Short name T718
Test name
Test status
Simulation time 819496440 ps
CPU time 7.45 seconds
Started Oct 03 12:47:54 PM UTC 24
Finished Oct 03 12:48:03 PM UTC 24
Peak memory 222644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335743626 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.3335743626
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.1998111036
Short name T720
Test name
Test status
Simulation time 3176966237 ps
CPU time 11.91 seconds
Started Oct 03 12:47:53 PM UTC 24
Finished Oct 03 12:48:06 PM UTC 24
Peak memory 222612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998111036 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.1998111036
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1650994097
Short name T740
Test name
Test status
Simulation time 6950447764 ps
CPU time 327.3 seconds
Started Oct 03 12:46:24 PM UTC 24
Finished Oct 03 12:51:55 PM UTC 24
Peak memory 375012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650994097 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1650994097
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1709763442
Short name T710
Test name
Test status
Simulation time 3064832951 ps
CPU time 24.35 seconds
Started Oct 03 12:46:44 PM UTC 24
Finished Oct 03 12:47:10 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709763442 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.1709763442
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1015836884
Short name T746
Test name
Test status
Simulation time 24056304618 ps
CPU time 367.79 seconds
Started Oct 03 12:46:45 PM UTC 24
Finished Oct 03 12:52:58 PM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015836884 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc
ess_b2b.1015836884
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2197900199
Short name T717
Test name
Test status
Simulation time 28849353 ps
CPU time 1.21 seconds
Started Oct 03 12:47:51 PM UTC 24
Finished Oct 03 12:47:53 PM UTC 24
Peak memory 211496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197900199 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2197900199
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2939268180
Short name T855
Test name
Test status
Simulation time 3756916257 ps
CPU time 1064.7 seconds
Started Oct 03 12:47:43 PM UTC 24
Finished Oct 03 01:05:40 PM UTC 24
Peak memory 383224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939268180 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2939268180
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.2195860547
Short name T706
Test name
Test status
Simulation time 2248017650 ps
CPU time 15.2 seconds
Started Oct 03 12:46:21 PM UTC 24
Finished Oct 03 12:46:38 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195860547 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2195860547
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.95003685
Short name T865
Test name
Test status
Simulation time 18915185359 ps
CPU time 1095.43 seconds
Started Oct 03 12:48:05 PM UTC 24
Finished Oct 03 01:06:34 PM UTC 24
Peak memory 393384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95003685
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.95003685
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2472264178
Short name T745
Test name
Test status
Simulation time 1687845609 ps
CPU time 288.17 seconds
Started Oct 03 12:48:03 PM UTC 24
Finished Oct 03 12:52:55 PM UTC 24
Peak memory 372924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472264178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2472264178
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4150781738
Short name T760
Test name
Test status
Simulation time 6944687965 ps
CPU time 410.74 seconds
Started Oct 03 12:46:39 PM UTC 24
Finished Oct 03 12:53:35 PM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150781738 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.4150781738
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1471593704
Short name T711
Test name
Test status
Simulation time 359215438 ps
CPU time 18.34 seconds
Started Oct 03 12:47:11 PM UTC 24
Finished Oct 03 12:47:31 PM UTC 24
Peak memory 262332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1471593704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_t
hroughput_w_partial_write.1471593704
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2988364655
Short name T810
Test name
Test status
Simulation time 3481250720 ps
CPU time 548.95 seconds
Started Oct 03 12:50:09 PM UTC 24
Finished Oct 03 12:59:25 PM UTC 24
Peak memory 377128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988364655 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during
_key_req.2988364655
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.808176890
Short name T739
Test name
Test status
Simulation time 11484357 ps
CPU time 1.04 seconds
Started Oct 03 12:51:45 PM UTC 24
Finished Oct 03 12:51:47 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808176890 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.808176890
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1654609650
Short name T725
Test name
Test status
Simulation time 2683181211 ps
CPU time 60.26 seconds
Started Oct 03 12:48:30 PM UTC 24
Finished Oct 03 12:49:32 PM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654609650 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.1654609650
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2664331266
Short name T816
Test name
Test status
Simulation time 14135829036 ps
CPU time 563.51 seconds
Started Oct 03 12:50:38 PM UTC 24
Finished Oct 03 01:00:08 PM UTC 24
Peak memory 383236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664331266 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.2664331266
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2613640246
Short name T730
Test name
Test status
Simulation time 710671735 ps
CPU time 13.2 seconds
Started Oct 03 12:49:54 PM UTC 24
Finished Oct 03 12:50:09 PM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613640246 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.2613640246
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2596226074
Short name T733
Test name
Test status
Simulation time 126594092 ps
CPU time 72.57 seconds
Started Oct 03 12:49:42 PM UTC 24
Finished Oct 03 12:50:56 PM UTC 24
Peak memory 358600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
596226074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma
x_throughput.2596226074
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.1983316888
Short name T736
Test name
Test status
Simulation time 103109767 ps
CPU time 4.35 seconds
Started Oct 03 12:51:08 PM UTC 24
Finished Oct 03 12:51:14 PM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983316888 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.1983316888
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.3002203149
Short name T735
Test name
Test status
Simulation time 352784378 ps
CPU time 6.04 seconds
Started Oct 03 12:51:00 PM UTC 24
Finished Oct 03 12:51:07 PM UTC 24
Peak memory 222604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002203149 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.3002203149
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2676498763
Short name T903
Test name
Test status
Simulation time 24488329497 ps
CPU time 1628.97 seconds
Started Oct 03 12:48:12 PM UTC 24
Finished Oct 03 01:15:39 PM UTC 24
Peak memory 385256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676498763 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2676498763
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1998022659
Short name T731
Test name
Test status
Simulation time 599704393 ps
CPU time 61.1 seconds
Started Oct 03 12:49:34 PM UTC 24
Finished Oct 03 12:50:36 PM UTC 24
Peak memory 360680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998022659 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.1998022659
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1510832358
Short name T814
Test name
Test status
Simulation time 175804060038 ps
CPU time 599.92 seconds
Started Oct 03 12:49:41 PM UTC 24
Finished Oct 03 12:59:48 PM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510832358 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc
ess_b2b.1510832358
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4117216860
Short name T734
Test name
Test status
Simulation time 32988010 ps
CPU time 1.05 seconds
Started Oct 03 12:50:57 PM UTC 24
Finished Oct 03 12:50:59 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117216860 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4117216860
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1713646425
Short name T794
Test name
Test status
Simulation time 4214331924 ps
CPU time 430.71 seconds
Started Oct 03 12:50:39 PM UTC 24
Finished Oct 03 12:57:55 PM UTC 24
Peak memory 360624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713646425 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1713646425
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2820157083
Short name T723
Test name
Test status
Simulation time 2174011571 ps
CPU time 18 seconds
Started Oct 03 12:48:10 PM UTC 24
Finished Oct 03 12:48:29 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820157083 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2820157083
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2733007413
Short name T941
Test name
Test status
Simulation time 11563004718 ps
CPU time 4513.78 seconds
Started Oct 03 12:51:21 PM UTC 24
Finished Oct 03 02:07:26 PM UTC 24
Peak memory 395092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273300741
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.2733007413
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2506698361
Short name T821
Test name
Test status
Simulation time 7394436633 ps
CPU time 559.66 seconds
Started Oct 03 12:51:14 PM UTC 24
Finished Oct 03 01:00:41 PM UTC 24
Peak memory 375092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506698361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2506698361
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3997042097
Short name T743
Test name
Test status
Simulation time 1395729778 ps
CPU time 173.74 seconds
Started Oct 03 12:49:34 PM UTC 24
Finished Oct 03 12:52:30 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997042097 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.3997042097
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3244906450
Short name T729
Test name
Test status
Simulation time 54952765 ps
CPU time 4.25 seconds
Started Oct 03 12:49:48 PM UTC 24
Finished Oct 03 12:49:53 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3244906450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t
hroughput_w_partial_write.3244906450
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3174460076
Short name T836
Test name
Test status
Simulation time 6042208908 ps
CPU time 556.01 seconds
Started Oct 03 12:53:03 PM UTC 24
Finished Oct 03 01:02:27 PM UTC 24
Peak memory 362652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174460076 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during
_key_req.3174460076
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3296345148
Short name T759
Test name
Test status
Simulation time 12483332 ps
CPU time 0.98 seconds
Started Oct 03 12:53:31 PM UTC 24
Finished Oct 03 12:53:33 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296345148 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3296345148
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3760564368
Short name T747
Test name
Test status
Simulation time 18686653679 ps
CPU time 57.84 seconds
Started Oct 03 12:52:00 PM UTC 24
Finished Oct 03 12:53:00 PM UTC 24
Peak memory 212220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760564368 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.3760564368
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.1739409328
Short name T876
Test name
Test status
Simulation time 7677499827 ps
CPU time 863.05 seconds
Started Oct 03 12:53:13 PM UTC 24
Finished Oct 03 01:07:46 PM UTC 24
Peak memory 383232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739409328 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.1739409328
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3029241421
Short name T749
Test name
Test status
Simulation time 2367890072 ps
CPU time 10.22 seconds
Started Oct 03 12:53:00 PM UTC 24
Finished Oct 03 12:53:12 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029241421 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.3029241421
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2817115215
Short name T764
Test name
Test status
Simulation time 218222617 ps
CPU time 83.33 seconds
Started Oct 03 12:52:57 PM UTC 24
Finished Oct 03 12:54:22 PM UTC 24
Peak memory 346240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
817115215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma
x_throughput.2817115215
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.645815971
Short name T757
Test name
Test status
Simulation time 553477379 ps
CPU time 5.32 seconds
Started Oct 03 12:53:23 PM UTC 24
Finished Oct 03 12:53:30 PM UTC 24
Peak memory 222588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645815971 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.645815971
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1359523557
Short name T758
Test name
Test status
Simulation time 595791590 ps
CPU time 15.2 seconds
Started Oct 03 12:53:16 PM UTC 24
Finished Oct 03 12:53:32 PM UTC 24
Peak memory 222452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359523557 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.1359523557
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3598298544
Short name T897
Test name
Test status
Simulation time 14510045328 ps
CPU time 1210.25 seconds
Started Oct 03 12:51:56 PM UTC 24
Finished Oct 03 01:12:20 PM UTC 24
Peak memory 385212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598298544 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.3598298544
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3000842001
Short name T755
Test name
Test status
Simulation time 768106458 ps
CPU time 52.14 seconds
Started Oct 03 12:52:31 PM UTC 24
Finished Oct 03 12:53:25 PM UTC 24
Peak memory 350324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000842001 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.3000842001
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1025047610
Short name T797
Test name
Test status
Simulation time 3547840663 ps
CPU time 305.58 seconds
Started Oct 03 12:52:53 PM UTC 24
Finished Oct 03 12:58:03 PM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025047610 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acc
ess_b2b.1025047610
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.606592714
Short name T752
Test name
Test status
Simulation time 31655148 ps
CPU time 1.26 seconds
Started Oct 03 12:53:13 PM UTC 24
Finished Oct 03 12:53:15 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606592714 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.606592714
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.4228382296
Short name T898
Test name
Test status
Simulation time 12451392121 ps
CPU time 1159.43 seconds
Started Oct 03 12:53:13 PM UTC 24
Finished Oct 03 01:12:45 PM UTC 24
Peak memory 385208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228382296 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.4228382296
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2646781556
Short name T750
Test name
Test status
Simulation time 1087795599 ps
CPU time 81.79 seconds
Started Oct 03 12:51:48 PM UTC 24
Finished Oct 03 12:53:12 PM UTC 24
Peak memory 352488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646781556 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2646781556
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.251302981
Short name T938
Test name
Test status
Simulation time 71101751510 ps
CPU time 2626.46 seconds
Started Oct 03 12:53:26 PM UTC 24
Finished Oct 03 01:37:44 PM UTC 24
Peak memory 386916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251302981
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.251302981
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3783272972
Short name T765
Test name
Test status
Simulation time 2447012044 ps
CPU time 63.68 seconds
Started Oct 03 12:53:23 PM UTC 24
Finished Oct 03 12:54:29 PM UTC 24
Peak memory 303364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783272972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3783272972
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.119399230
Short name T778
Test name
Test status
Simulation time 1826961547 ps
CPU time 246.01 seconds
Started Oct 03 12:52:03 PM UTC 24
Finished Oct 03 12:56:13 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119399230 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.119399230
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3051553034
Short name T748
Test name
Test status
Simulation time 47085656 ps
CPU time 2.44 seconds
Started Oct 03 12:52:59 PM UTC 24
Finished Oct 03 12:53:02 PM UTC 24
Peak memory 222512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3051553034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t
hroughput_w_partial_write.3051553034
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3494276254
Short name T843
Test name
Test status
Simulation time 15013144641 ps
CPU time 533.38 seconds
Started Oct 03 12:54:36 PM UTC 24
Finished Oct 03 01:03:36 PM UTC 24
Peak memory 375012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494276254 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during
_key_req.3494276254
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1403023294
Short name T777
Test name
Test status
Simulation time 27243283 ps
CPU time 0.92 seconds
Started Oct 03 12:56:00 PM UTC 24
Finished Oct 03 12:56:02 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403023294 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1403023294
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3864021788
Short name T769
Test name
Test status
Simulation time 15514623468 ps
CPU time 69.62 seconds
Started Oct 03 12:53:35 PM UTC 24
Finished Oct 03 12:54:46 PM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864021788 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.3864021788
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2296905872
Short name T883
Test name
Test status
Simulation time 2517069798 ps
CPU time 790.3 seconds
Started Oct 03 12:54:39 PM UTC 24
Finished Oct 03 01:07:59 PM UTC 24
Peak memory 375036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296905872 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.2296905872
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4116098528
Short name T766
Test name
Test status
Simulation time 183653352 ps
CPU time 3.93 seconds
Started Oct 03 12:54:30 PM UTC 24
Finished Oct 03 12:54:35 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116098528 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.4116098528
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.4040955988
Short name T767
Test name
Test status
Simulation time 77351115 ps
CPU time 14.72 seconds
Started Oct 03 12:54:23 PM UTC 24
Finished Oct 03 12:54:38 PM UTC 24
Peak memory 278724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
040955988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma
x_throughput.4040955988
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1517500704
Short name T773
Test name
Test status
Simulation time 303581714 ps
CPU time 6.98 seconds
Started Oct 03 12:55:06 PM UTC 24
Finished Oct 03 12:55:14 PM UTC 24
Peak memory 222464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517500704 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.1517500704
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3547695830
Short name T771
Test name
Test status
Simulation time 454656555 ps
CPU time 13.96 seconds
Started Oct 03 12:54:50 PM UTC 24
Finished Oct 03 12:55:05 PM UTC 24
Peak memory 222404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547695830 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3547695830
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3283367473
Short name T899
Test name
Test status
Simulation time 79548880223 ps
CPU time 1141.09 seconds
Started Oct 03 12:53:33 PM UTC 24
Finished Oct 03 01:12:48 PM UTC 24
Peak memory 385200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283367473 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.3283367473
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.907615594
Short name T762
Test name
Test status
Simulation time 1853444885 ps
CPU time 26.33 seconds
Started Oct 03 12:53:43 PM UTC 24
Finished Oct 03 12:54:11 PM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907615594 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.907615594
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.875957200
Short name T785
Test name
Test status
Simulation time 2218486834 ps
CPU time 181.91 seconds
Started Oct 03 12:54:12 PM UTC 24
Finished Oct 03 12:57:17 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875957200 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acce
ss_b2b.875957200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3662902610
Short name T770
Test name
Test status
Simulation time 110893086 ps
CPU time 1.18 seconds
Started Oct 03 12:54:47 PM UTC 24
Finished Oct 03 12:54:49 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662902610 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3662902610
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3439373323
Short name T914
Test name
Test status
Simulation time 7833489057 ps
CPU time 1420.25 seconds
Started Oct 03 12:54:41 PM UTC 24
Finished Oct 03 01:18:37 PM UTC 24
Peak memory 375040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439373323 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3439373323
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3150158829
Short name T761
Test name
Test status
Simulation time 560425378 ps
CPU time 9.77 seconds
Started Oct 03 12:53:31 PM UTC 24
Finished Oct 03 12:53:42 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150158829 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3150158829
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1953819051
Short name T936
Test name
Test status
Simulation time 24819086558 ps
CPU time 2327.51 seconds
Started Oct 03 12:55:15 PM UTC 24
Finished Oct 03 01:34:32 PM UTC 24
Peak memory 383376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195381905
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.1953819051
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.173163681
Short name T775
Test name
Test status
Simulation time 1033098114 ps
CPU time 41.85 seconds
Started Oct 03 12:55:14 PM UTC 24
Finished Oct 03 12:55:58 PM UTC 24
Peak memory 299252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173163681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.173163681
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3449457811
Short name T839
Test name
Test status
Simulation time 21067298646 ps
CPU time 582.03 seconds
Started Oct 03 12:53:36 PM UTC 24
Finished Oct 03 01:03:26 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449457811 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.3449457811
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.620081972
Short name T776
Test name
Test status
Simulation time 142712763 ps
CPU time 96.53 seconds
Started Oct 03 12:54:23 PM UTC 24
Finished Oct 03 12:56:01 PM UTC 24
Peak memory 368888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
620081972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_th
roughput_w_partial_write.620081972
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1286687203
Short name T809
Test name
Test status
Simulation time 1279947700 ps
CPU time 146.25 seconds
Started Oct 03 12:56:54 PM UTC 24
Finished Oct 03 12:59:23 PM UTC 24
Peak memory 362744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286687203 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during
_key_req.1286687203
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2854441055
Short name T792
Test name
Test status
Simulation time 42326947 ps
CPU time 1.07 seconds
Started Oct 03 12:57:50 PM UTC 24
Finished Oct 03 12:57:52 PM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854441055 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2854441055
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.3824672366
Short name T780
Test name
Test status
Simulation time 7415992129 ps
CPU time 37.85 seconds
Started Oct 03 12:56:03 PM UTC 24
Finished Oct 03 12:56:42 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824672366 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.3824672366
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.3763295423
Short name T902
Test name
Test status
Simulation time 11805969055 ps
CPU time 1062.67 seconds
Started Oct 03 12:56:59 PM UTC 24
Finished Oct 03 01:14:54 PM UTC 24
Peak memory 383208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763295423 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.3763295423
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3474101400
Short name T784
Test name
Test status
Simulation time 352214791 ps
CPU time 7.38 seconds
Started Oct 03 12:56:50 PM UTC 24
Finished Oct 03 12:56:58 PM UTC 24
Peak memory 212236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474101400 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.3474101400
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1201244372
Short name T801
Test name
Test status
Simulation time 539548627 ps
CPU time 102.79 seconds
Started Oct 03 12:56:43 PM UTC 24
Finished Oct 03 12:58:28 PM UTC 24
Peak memory 381168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
201244372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ma
x_throughput.1201244372
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3687275520
Short name T791
Test name
Test status
Simulation time 453834240 ps
CPU time 3.26 seconds
Started Oct 03 12:57:44 PM UTC 24
Finished Oct 03 12:57:49 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687275520 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.3687275520
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2356461436
Short name T789
Test name
Test status
Simulation time 188393878 ps
CPU time 6.59 seconds
Started Oct 03 12:57:36 PM UTC 24
Finished Oct 03 12:57:44 PM UTC 24
Peak memory 212220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356461436 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.2356461436
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4266407464
Short name T880
Test name
Test status
Simulation time 45692747370 ps
CPU time 700.52 seconds
Started Oct 03 12:56:03 PM UTC 24
Finished Oct 03 01:07:51 PM UTC 24
Peak memory 383208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266407464 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.4266407464
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3730657538
Short name T781
Test name
Test status
Simulation time 3976669587 ps
CPU time 28.92 seconds
Started Oct 03 12:56:14 PM UTC 24
Finished Oct 03 12:56:44 PM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730657538 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.3730657538
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.2239308743
Short name T815
Test name
Test status
Simulation time 12688607985 ps
CPU time 224.76 seconds
Started Oct 03 12:56:16 PM UTC 24
Finished Oct 03 01:00:05 PM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239308743 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc
ess_b2b.2239308743
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.2136103776
Short name T787
Test name
Test status
Simulation time 30316413 ps
CPU time 1.11 seconds
Started Oct 03 12:57:33 PM UTC 24
Finished Oct 03 12:57:35 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136103776 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2136103776
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.35844360
Short name T879
Test name
Test status
Simulation time 1825054248 ps
CPU time 624.35 seconds
Started Oct 03 12:57:19 PM UTC 24
Finished Oct 03 01:07:50 PM UTC 24
Peak memory 374880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35844360 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.35844360
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.3702988367
Short name T779
Test name
Test status
Simulation time 333786222 ps
CPU time 14.33 seconds
Started Oct 03 12:56:00 PM UTC 24
Finished Oct 03 12:56:16 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702988367 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3702988367
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3262493699
Short name T943
Test name
Test status
Simulation time 80834141375 ps
CPU time 5774.15 seconds
Started Oct 03 12:57:46 PM UTC 24
Finished Oct 03 02:35:06 PM UTC 24
Peak memory 386828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326249369
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.3262493699
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3501367988
Short name T793
Test name
Test status
Simulation time 841971503 ps
CPU time 8.12 seconds
Started Oct 03 12:57:46 PM UTC 24
Finished Oct 03 12:57:55 PM UTC 24
Peak memory 222544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501367988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3501367988
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1255041951
Short name T830
Test name
Test status
Simulation time 2729403787 ps
CPU time 306.65 seconds
Started Oct 03 12:56:04 PM UTC 24
Finished Oct 03 01:01:15 PM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255041951 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1255041951
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3235397136
Short name T790
Test name
Test status
Simulation time 274195238 ps
CPU time 57.17 seconds
Started Oct 03 12:56:46 PM UTC 24
Finished Oct 03 12:57:44 PM UTC 24
Peak memory 366836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3235397136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t
hroughput_w_partial_write.3235397136
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3847764697
Short name T870
Test name
Test status
Simulation time 3138449538 ps
CPU time 527.29 seconds
Started Oct 03 12:58:30 PM UTC 24
Finished Oct 03 01:07:24 PM UTC 24
Peak memory 379128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847764697 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during
_key_req.3847764697
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.4029783360
Short name T811
Test name
Test status
Simulation time 10573043 ps
CPU time 1.04 seconds
Started Oct 03 12:59:24 PM UTC 24
Finished Oct 03 12:59:26 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029783360 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.4029783360
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2212495891
Short name T813
Test name
Test status
Simulation time 3639176528 ps
CPU time 104.17 seconds
Started Oct 03 12:57:56 PM UTC 24
Finished Oct 03 12:59:43 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212495891 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.2212495891
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3373873911
Short name T927
Test name
Test status
Simulation time 8083681872 ps
CPU time 1568.86 seconds
Started Oct 03 12:58:30 PM UTC 24
Finished Oct 03 01:24:58 PM UTC 24
Peak memory 383160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373873911 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3373873911
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1650289115
Short name T803
Test name
Test status
Simulation time 705159971 ps
CPU time 8.55 seconds
Started Oct 03 12:58:28 PM UTC 24
Finished Oct 03 12:58:38 PM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650289115 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.1650289115
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.126422225
Short name T812
Test name
Test status
Simulation time 648531594 ps
CPU time 79.36 seconds
Started Oct 03 12:58:09 PM UTC 24
Finished Oct 03 12:59:30 PM UTC 24
Peak memory 379084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
26422225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_max
_throughput.126422225
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2656096343
Short name T808
Test name
Test status
Simulation time 84711482 ps
CPU time 4.15 seconds
Started Oct 03 12:58:54 PM UTC 24
Finished Oct 03 12:58:59 PM UTC 24
Peak memory 222516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656096343 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.2656096343
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.326464796
Short name T807
Test name
Test status
Simulation time 377779382 ps
CPU time 6.81 seconds
Started Oct 03 12:58:46 PM UTC 24
Finished Oct 03 12:58:53 PM UTC 24
Peak memory 222472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326464796 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.326464796
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.386326699
Short name T875
Test name
Test status
Simulation time 26395915734 ps
CPU time 582.29 seconds
Started Oct 03 12:57:56 PM UTC 24
Finished Oct 03 01:07:46 PM UTC 24
Peak memory 385320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386326699 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.386326699
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2642449782
Short name T800
Test name
Test status
Simulation time 1003804486 ps
CPU time 23.73 seconds
Started Oct 03 12:58:03 PM UTC 24
Finished Oct 03 12:58:28 PM UTC 24
Peak memory 212208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642449782 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.2642449782
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.294160627
Short name T867
Test name
Test status
Simulation time 216481429863 ps
CPU time 521.97 seconds
Started Oct 03 12:58:04 PM UTC 24
Finished Oct 03 01:06:53 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294160627 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acce
ss_b2b.294160627
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2920307916
Short name T805
Test name
Test status
Simulation time 50452693 ps
CPU time 1.18 seconds
Started Oct 03 12:58:42 PM UTC 24
Finished Oct 03 12:58:44 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920307916 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2920307916
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3320942656
Short name T905
Test name
Test status
Simulation time 6739138580 ps
CPU time 1037.29 seconds
Started Oct 03 12:58:39 PM UTC 24
Finished Oct 03 01:16:09 PM UTC 24
Peak memory 381172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320942656 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3320942656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.1688729252
Short name T804
Test name
Test status
Simulation time 1064881255 ps
CPU time 46.83 seconds
Started Oct 03 12:57:53 PM UTC 24
Finished Oct 03 12:58:41 PM UTC 24
Peak memory 327912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688729252 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1688729252
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2356293395
Short name T904
Test name
Test status
Simulation time 12860141834 ps
CPU time 1007.02 seconds
Started Oct 03 12:59:00 PM UTC 24
Finished Oct 03 01:15:59 PM UTC 24
Peak memory 385272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235629339
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.2356293395
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.400957069
Short name T868
Test name
Test status
Simulation time 4063051483 ps
CPU time 487.79 seconds
Started Oct 03 12:58:55 PM UTC 24
Finished Oct 03 01:07:09 PM UTC 24
Peak memory 364848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400957069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.400957069
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2517751239
Short name T834
Test name
Test status
Simulation time 7620179361 ps
CPU time 248.22 seconds
Started Oct 03 12:57:59 PM UTC 24
Finished Oct 03 01:02:12 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517751239 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.2517751239
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2481844173
Short name T806
Test name
Test status
Simulation time 338626473 ps
CPU time 25.8 seconds
Started Oct 03 12:58:25 PM UTC 24
Finished Oct 03 12:58:53 PM UTC 24
Peak memory 303284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2481844173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t
hroughput_w_partial_write.2481844173
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3161178521
Short name T906
Test name
Test status
Simulation time 14109103026 ps
CPU time 939.81 seconds
Started Oct 03 01:00:37 PM UTC 24
Finished Oct 03 01:16:30 PM UTC 24
Peak memory 385276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161178521 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during
_key_req.3161178521
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3099531648
Short name T828
Test name
Test status
Simulation time 16919805 ps
CPU time 0.95 seconds
Started Oct 03 01:01:00 PM UTC 24
Finished Oct 03 01:01:02 PM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099531648 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.3099531648
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3257377325
Short name T819
Test name
Test status
Simulation time 10273030096 ps
CPU time 63.23 seconds
Started Oct 03 12:59:31 PM UTC 24
Finished Oct 03 01:00:36 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257377325 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.3257377325
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1986279337
Short name T923
Test name
Test status
Simulation time 62352266186 ps
CPU time 1363.79 seconds
Started Oct 03 01:00:39 PM UTC 24
Finished Oct 03 01:23:39 PM UTC 24
Peak memory 383212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986279337 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.1986279337
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.4021948081
Short name T822
Test name
Test status
Simulation time 355401355 ps
CPU time 5.79 seconds
Started Oct 03 01:00:34 PM UTC 24
Finished Oct 03 01:00:41 PM UTC 24
Peak memory 212148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021948081 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.4021948081
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3871193371
Short name T833
Test name
Test status
Simulation time 146481422 ps
CPU time 117.53 seconds
Started Oct 03 01:00:09 PM UTC 24
Finished Oct 03 01:02:09 PM UTC 24
Peak memory 379080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
871193371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ma
x_throughput.3871193371
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.721579050
Short name T826
Test name
Test status
Simulation time 189860017 ps
CPU time 8.45 seconds
Started Oct 03 01:00:47 PM UTC 24
Finished Oct 03 01:00:57 PM UTC 24
Peak memory 222480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721579050 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.721579050
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3674440450
Short name T827
Test name
Test status
Simulation time 1987215141 ps
CPU time 12.92 seconds
Started Oct 03 01:00:45 PM UTC 24
Finished Oct 03 01:00:59 PM UTC 24
Peak memory 222532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674440450 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.3674440450
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3193366061
Short name T907
Test name
Test status
Simulation time 55110462263 ps
CPU time 1013.3 seconds
Started Oct 03 12:59:28 PM UTC 24
Finished Oct 03 01:16:33 PM UTC 24
Peak memory 379056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193366061 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.3193366061
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1481257344
Short name T820
Test name
Test status
Simulation time 1093164455 ps
CPU time 47.69 seconds
Started Oct 03 12:59:49 PM UTC 24
Finished Oct 03 01:00:39 PM UTC 24
Peak memory 323772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481257344 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.1481257344
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3876822522
Short name T849
Test name
Test status
Simulation time 17209102578 ps
CPU time 255.53 seconds
Started Oct 03 01:00:06 PM UTC 24
Finished Oct 03 01:04:25 PM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876822522 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc
ess_b2b.3876822522
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.615029390
Short name T823
Test name
Test status
Simulation time 31290621 ps
CPU time 1.25 seconds
Started Oct 03 01:00:42 PM UTC 24
Finished Oct 03 01:00:44 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615029390 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.615029390
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.1123793522
Short name T890
Test name
Test status
Simulation time 9019406207 ps
CPU time 537.63 seconds
Started Oct 03 01:00:42 PM UTC 24
Finished Oct 03 01:09:46 PM UTC 24
Peak memory 385216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123793522 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1123793522
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2155669212
Short name T829
Test name
Test status
Simulation time 539973922 ps
CPU time 96.73 seconds
Started Oct 03 12:59:26 PM UTC 24
Finished Oct 03 01:01:04 PM UTC 24
Peak memory 340072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155669212 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2155669212
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.533005127
Short name T942
Test name
Test status
Simulation time 235190256824 ps
CPU time 4136.86 seconds
Started Oct 03 01:00:58 PM UTC 24
Finished Oct 03 02:10:42 PM UTC 24
Peak memory 397136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533005127
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.533005127
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1888755058
Short name T832
Test name
Test status
Simulation time 4254942893 ps
CPU time 77.96 seconds
Started Oct 03 01:00:48 PM UTC 24
Finished Oct 03 01:02:08 PM UTC 24
Peak memory 323888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888755058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1888755058
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2575377164
Short name T857
Test name
Test status
Simulation time 17760411044 ps
CPU time 367.1 seconds
Started Oct 03 12:59:43 PM UTC 24
Finished Oct 03 01:05:56 PM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575377164 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.2575377164
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.4104973083
Short name T818
Test name
Test status
Simulation time 45467706 ps
CPU time 2.76 seconds
Started Oct 03 01:00:29 PM UTC 24
Finished Oct 03 01:00:33 PM UTC 24
Peak memory 222576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4104973083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t
hroughput_w_partial_write.4104973083
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.4217235606
Short name T900
Test name
Test status
Simulation time 11054995492 ps
CPU time 606.36 seconds
Started Oct 03 01:02:37 PM UTC 24
Finished Oct 03 01:12:52 PM UTC 24
Peak memory 362812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217235606 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during
_key_req.4217235606
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3994477317
Short name T846
Test name
Test status
Simulation time 18779999 ps
CPU time 0.89 seconds
Started Oct 03 01:03:41 PM UTC 24
Finished Oct 03 01:03:43 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994477317 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3994477317
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.1487086308
Short name T837
Test name
Test status
Simulation time 13901501624 ps
CPU time 79.19 seconds
Started Oct 03 01:01:16 PM UTC 24
Finished Oct 03 01:02:37 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487086308 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.1487086308
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.3283253240
Short name T888
Test name
Test status
Simulation time 4687757122 ps
CPU time 347.37 seconds
Started Oct 03 01:02:42 PM UTC 24
Finished Oct 03 01:08:34 PM UTC 24
Peak memory 374948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283253240 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.3283253240
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.860256839
Short name T838
Test name
Test status
Simulation time 728349567 ps
CPU time 11.2 seconds
Started Oct 03 01:02:28 PM UTC 24
Finished Oct 03 01:02:41 PM UTC 24
Peak memory 212236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860256839 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.860256839
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2199738340
Short name T835
Test name
Test status
Simulation time 335553591 ps
CPU time 1.76 seconds
Started Oct 03 01:02:13 PM UTC 24
Finished Oct 03 01:02:16 PM UTC 24
Peak memory 221296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
199738340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ma
x_throughput.2199738340
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1620350915
Short name T845
Test name
Test status
Simulation time 340056954 ps
CPU time 10.02 seconds
Started Oct 03 01:03:30 PM UTC 24
Finished Oct 03 01:03:41 PM UTC 24
Peak memory 222548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620350915 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.1620350915
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.542936683
Short name T844
Test name
Test status
Simulation time 1035394045 ps
CPU time 10.83 seconds
Started Oct 03 01:03:27 PM UTC 24
Finished Oct 03 01:03:39 PM UTC 24
Peak memory 222396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542936683 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.542936683
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2260157694
Short name T847
Test name
Test status
Simulation time 1365396782 ps
CPU time 114.31 seconds
Started Oct 03 01:02:09 PM UTC 24
Finished Oct 03 01:04:06 PM UTC 24
Peak memory 368828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260157694 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2260157694
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2809985735
Short name T864
Test name
Test status
Simulation time 13705296626 ps
CPU time 255.05 seconds
Started Oct 03 01:02:09 PM UTC 24
Finished Oct 03 01:06:29 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809985735 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc
ess_b2b.2809985735
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.861276968
Short name T842
Test name
Test status
Simulation time 39779333 ps
CPU time 1.34 seconds
Started Oct 03 01:03:26 PM UTC 24
Finished Oct 03 01:03:29 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861276968 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.861276968
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2135763245
Short name T924
Test name
Test status
Simulation time 4314815185 ps
CPU time 1292.2 seconds
Started Oct 03 01:02:51 PM UTC 24
Finished Oct 03 01:24:39 PM UTC 24
Peak memory 383204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135763245 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2135763245
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.38251957
Short name T831
Test name
Test status
Simulation time 3017936017 ps
CPU time 19.28 seconds
Started Oct 03 01:01:03 PM UTC 24
Finished Oct 03 01:01:24 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38251957 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.38251957
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1937391258
Short name T917
Test name
Test status
Simulation time 18707719887 ps
CPU time 991.44 seconds
Started Oct 03 01:03:37 PM UTC 24
Finished Oct 03 01:20:20 PM UTC 24
Peak memory 385324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193739125
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.1937391258
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3562500879
Short name T886
Test name
Test status
Simulation time 1434706899 ps
CPU time 283.22 seconds
Started Oct 03 01:03:30 PM UTC 24
Finished Oct 03 01:08:18 PM UTC 24
Peak memory 342320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562500879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3562500879
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2552632267
Short name T856
Test name
Test status
Simulation time 2136763175 ps
CPU time 255.05 seconds
Started Oct 03 01:01:25 PM UTC 24
Finished Oct 03 01:05:44 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552632267 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.2552632267
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.524641125
Short name T848
Test name
Test status
Simulation time 305047476 ps
CPU time 108.21 seconds
Started Oct 03 01:02:17 PM UTC 24
Finished Oct 03 01:04:08 PM UTC 24
Peak memory 379072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
524641125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_th
roughput_w_partial_write.524641125
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1447392282
Short name T891
Test name
Test status
Simulation time 3860199822 ps
CPU time 276.68 seconds
Started Oct 03 01:05:22 PM UTC 24
Finished Oct 03 01:10:03 PM UTC 24
Peak memory 366756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447392282 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during
_key_req.1447392282
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1625241282
Short name T863
Test name
Test status
Simulation time 11790253 ps
CPU time 0.95 seconds
Started Oct 03 01:06:25 PM UTC 24
Finished Oct 03 01:06:27 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625241282 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1625241282
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1946391994
Short name T851
Test name
Test status
Simulation time 538480259 ps
CPU time 37.68 seconds
Started Oct 03 01:04:08 PM UTC 24
Finished Oct 03 01:04:47 PM UTC 24
Peak memory 212232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946391994 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1946391994
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1758094694
Short name T919
Test name
Test status
Simulation time 8994264385 ps
CPU time 931.84 seconds
Started Oct 03 01:05:41 PM UTC 24
Finished Oct 03 01:21:25 PM UTC 24
Peak memory 379136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758094694 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1758094694
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2650940418
Short name T854
Test name
Test status
Simulation time 1428181520 ps
CPU time 8.68 seconds
Started Oct 03 01:05:11 PM UTC 24
Finished Oct 03 01:05:21 PM UTC 24
Peak memory 212220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650940418 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2650940418
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2626008625
Short name T852
Test name
Test status
Simulation time 179453384 ps
CPU time 4.51 seconds
Started Oct 03 01:04:48 PM UTC 24
Finished Oct 03 01:04:54 PM UTC 24
Peak memory 231624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
626008625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ma
x_throughput.2626008625
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3259795670
Short name T860
Test name
Test status
Simulation time 177276841 ps
CPU time 6.89 seconds
Started Oct 03 01:06:01 PM UTC 24
Finished Oct 03 01:06:09 PM UTC 24
Peak memory 222396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259795670 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.3259795670
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2286827460
Short name T861
Test name
Test status
Simulation time 531349478 ps
CPU time 10.86 seconds
Started Oct 03 01:05:57 PM UTC 24
Finished Oct 03 01:06:09 PM UTC 24
Peak memory 222408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286827460 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.2286827460
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.393030296
Short name T916
Test name
Test status
Simulation time 9811815917 ps
CPU time 934.34 seconds
Started Oct 03 01:03:44 PM UTC 24
Finished Oct 03 01:19:30 PM UTC 24
Peak memory 370952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393030296 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.393030296
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3517205411
Short name T850
Test name
Test status
Simulation time 869946184 ps
CPU time 9.54 seconds
Started Oct 03 01:04:26 PM UTC 24
Finished Oct 03 01:04:37 PM UTC 24
Peak memory 212152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517205411 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.3517205411
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1285918792
Short name T892
Test name
Test status
Simulation time 17513118105 ps
CPU time 360.72 seconds
Started Oct 03 01:04:39 PM UTC 24
Finished Oct 03 01:10:45 PM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285918792 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc
ess_b2b.1285918792
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2156730163
Short name T859
Test name
Test status
Simulation time 50848152 ps
CPU time 1.22 seconds
Started Oct 03 01:05:57 PM UTC 24
Finished Oct 03 01:06:00 PM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156730163 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2156730163
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.908243604
Short name T908
Test name
Test status
Simulation time 4221736264 ps
CPU time 658.84 seconds
Started Oct 03 01:05:46 PM UTC 24
Finished Oct 03 01:16:53 PM UTC 24
Peak memory 374964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908243604 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.908243604
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.52352063
Short name T853
Test name
Test status
Simulation time 5534697356 ps
CPU time 84.71 seconds
Started Oct 03 01:03:42 PM UTC 24
Finished Oct 03 01:05:09 PM UTC 24
Peak memory 354556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52352063 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.52352063
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.789774656
Short name T934
Test name
Test status
Simulation time 7989361483 ps
CPU time 1352.04 seconds
Started Oct 03 01:06:10 PM UTC 24
Finished Oct 03 01:28:59 PM UTC 24
Peak memory 393400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789774656
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.789774656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3283593192
Short name T862
Test name
Test status
Simulation time 1309072367 ps
CPU time 12.4 seconds
Started Oct 03 01:06:10 PM UTC 24
Finished Oct 03 01:06:24 PM UTC 24
Peak memory 229536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283593192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3283593192
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2216176010
Short name T871
Test name
Test status
Simulation time 22327046570 ps
CPU time 196.44 seconds
Started Oct 03 01:04:09 PM UTC 24
Finished Oct 03 01:07:29 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216176010 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.2216176010
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.479014812
Short name T858
Test name
Test status
Simulation time 524925457 ps
CPU time 60.58 seconds
Started Oct 03 01:04:54 PM UTC 24
Finished Oct 03 01:05:57 PM UTC 24
Peak memory 342108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
479014812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_th
roughput_w_partial_write.479014812
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1642687384
Short name T933
Test name
Test status
Simulation time 14214962294 ps
CPU time 1209.97 seconds
Started Oct 03 01:07:40 PM UTC 24
Finished Oct 03 01:28:05 PM UTC 24
Peak memory 385348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642687384 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during
_key_req.1642687384
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3960991852
Short name T881
Test name
Test status
Simulation time 39078245 ps
CPU time 0.95 seconds
Started Oct 03 01:07:52 PM UTC 24
Finished Oct 03 01:07:54 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960991852 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.3960991852
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.1914381463
Short name T878
Test name
Test status
Simulation time 21710465173 ps
CPU time 72.35 seconds
Started Oct 03 01:06:35 PM UTC 24
Finished Oct 03 01:07:49 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914381463 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.1914381463
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1792469959
Short name T920
Test name
Test status
Simulation time 80521201178 ps
CPU time 843.6 seconds
Started Oct 03 01:07:40 PM UTC 24
Finished Oct 03 01:21:54 PM UTC 24
Peak memory 377016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792469959 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1792469959
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2874528977
Short name T874
Test name
Test status
Simulation time 1569376361 ps
CPU time 11.29 seconds
Started Oct 03 01:07:30 PM UTC 24
Finished Oct 03 01:07:43 PM UTC 24
Peak memory 212412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874528977 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.2874528977
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2446541273
Short name T887
Test name
Test status
Simulation time 748920860 ps
CPU time 76.46 seconds
Started Oct 03 01:07:15 PM UTC 24
Finished Oct 03 01:08:33 PM UTC 24
Peak memory 375048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
446541273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma
x_throughput.2446541273
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4097988798
Short name T882
Test name
Test status
Simulation time 1350721477 ps
CPU time 4.68 seconds
Started Oct 03 01:07:51 PM UTC 24
Finished Oct 03 01:07:56 PM UTC 24
Peak memory 222548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097988798 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.4097988798
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.999565529
Short name T884
Test name
Test status
Simulation time 2599357422 ps
CPU time 17.04 seconds
Started Oct 03 01:07:47 PM UTC 24
Finished Oct 03 01:08:05 PM UTC 24
Peak memory 222588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999565529 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.999565529
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1693414901
Short name T928
Test name
Test status
Simulation time 16756012036 ps
CPU time 1149.28 seconds
Started Oct 03 01:06:30 PM UTC 24
Finished Oct 03 01:25:54 PM UTC 24
Peak memory 372972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693414901 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.1693414901
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.867508252
Short name T869
Test name
Test status
Simulation time 969233027 ps
CPU time 18.64 seconds
Started Oct 03 01:06:54 PM UTC 24
Finished Oct 03 01:07:14 PM UTC 24
Peak memory 264448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867508252 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.867508252
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3267487142
Short name T910
Test name
Test status
Simulation time 17953119340 ps
CPU time 627.27 seconds
Started Oct 03 01:07:10 PM UTC 24
Finished Oct 03 01:17:46 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267487142 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc
ess_b2b.3267487142
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.551604246
Short name T877
Test name
Test status
Simulation time 35371901 ps
CPU time 1.2 seconds
Started Oct 03 01:07:47 PM UTC 24
Finished Oct 03 01:07:49 PM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551604246 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.551604246
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.1390979741
Short name T911
Test name
Test status
Simulation time 34766320903 ps
CPU time 595.84 seconds
Started Oct 03 01:07:43 PM UTC 24
Finished Oct 03 01:17:47 PM UTC 24
Peak memory 370980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390979741 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1390979741
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.3781692512
Short name T866
Test name
Test status
Simulation time 3555328144 ps
CPU time 19.62 seconds
Started Oct 03 01:06:28 PM UTC 24
Finished Oct 03 01:06:49 PM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781692512 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3781692512
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3565348818
Short name T929
Test name
Test status
Simulation time 22210906714 ps
CPU time 1091.16 seconds
Started Oct 03 01:07:52 PM UTC 24
Finished Oct 03 01:26:18 PM UTC 24
Peak memory 385196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356534881
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.3565348818
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2542538513
Short name T896
Test name
Test status
Simulation time 3591626097 ps
CPU time 237.53 seconds
Started Oct 03 01:07:51 PM UTC 24
Finished Oct 03 01:11:52 PM UTC 24
Peak memory 383232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542538513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.2542538513
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.4189326072
Short name T894
Test name
Test status
Simulation time 10003337726 ps
CPU time 267.03 seconds
Started Oct 03 01:06:51 PM UTC 24
Finished Oct 03 01:11:22 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189326072 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.4189326072
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.236749400
Short name T872
Test name
Test status
Simulation time 336589375 ps
CPU time 12.08 seconds
Started Oct 03 01:07:25 PM UTC 24
Finished Oct 03 01:07:38 PM UTC 24
Peak memory 274616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
236749400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_th
roughput_w_partial_write.236749400
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1153274612
Short name T295
Test name
Test status
Simulation time 5785640754 ps
CPU time 835.49 seconds
Started Oct 03 11:48:56 AM UTC 24
Finished Oct 03 12:03:02 PM UTC 24
Peak memory 383292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153274612 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_
key_req.1153274612
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.4108045188
Short name T173
Test name
Test status
Simulation time 42224198 ps
CPU time 1.01 seconds
Started Oct 03 11:49:40 AM UTC 24
Finished Oct 03 11:49:42 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108045188 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.4108045188
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2486585035
Short name T172
Test name
Test status
Simulation time 1102960418 ps
CPU time 52.85 seconds
Started Oct 03 11:48:39 AM UTC 24
Finished Oct 03 11:49:34 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486585035 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2486585035
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.658861467
Short name T142
Test name
Test status
Simulation time 8805323674 ps
CPU time 606.99 seconds
Started Oct 03 11:49:07 AM UTC 24
Finished Oct 03 11:59:21 AM UTC 24
Peak memory 374940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658861467 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.658861467
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.956339529
Short name T160
Test name
Test status
Simulation time 683604198 ps
CPU time 6.04 seconds
Started Oct 03 11:48:48 AM UTC 24
Finished Oct 03 11:48:55 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956339529 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.956339529
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.235396656
Short name T170
Test name
Test status
Simulation time 182898900 ps
CPU time 34.97 seconds
Started Oct 03 11:48:44 AM UTC 24
Finished Oct 03 11:49:20 AM UTC 24
Peak memory 303348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
35396656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max_
throughput.235396656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1955659565
Short name T85
Test name
Test status
Simulation time 709366205 ps
CPU time 3.42 seconds
Started Oct 03 11:49:35 AM UTC 24
Finished Oct 03 11:49:39 AM UTC 24
Peak memory 222528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955659565 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1955659565
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3937690888
Short name T56
Test name
Test status
Simulation time 925870718 ps
CPU time 11.8 seconds
Started Oct 03 11:49:24 AM UTC 24
Finished Oct 03 11:49:37 AM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937690888 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.3937690888
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2496493902
Short name T211
Test name
Test status
Simulation time 2486259147 ps
CPU time 294.38 seconds
Started Oct 03 11:48:39 AM UTC 24
Finished Oct 03 11:53:38 AM UTC 24
Peak memory 375092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496493902 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.2496493902
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2561088983
Short name T151
Test name
Test status
Simulation time 57192766 ps
CPU time 2.97 seconds
Started Oct 03 11:48:43 AM UTC 24
Finished Oct 03 11:48:47 AM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561088983 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.2561088983
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3304647811
Short name T171
Test name
Test status
Simulation time 74810532 ps
CPU time 1.23 seconds
Started Oct 03 11:49:21 AM UTC 24
Finished Oct 03 11:49:23 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304647811 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3304647811
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2848696383
Short name T138
Test name
Test status
Simulation time 31241737686 ps
CPU time 1037.92 seconds
Started Oct 03 11:49:11 AM UTC 24
Finished Oct 03 12:06:41 PM UTC 24
Peak memory 379136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848696383 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2848696383
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3434175401
Short name T168
Test name
Test status
Simulation time 181839008 ps
CPU time 4.41 seconds
Started Oct 03 11:48:37 AM UTC 24
Finished Oct 03 11:48:43 AM UTC 24
Peak memory 223448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434175401 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3434175401
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1555702800
Short name T329
Test name
Test status
Simulation time 10433592948 ps
CPU time 953.41 seconds
Started Oct 03 11:49:38 AM UTC 24
Finished Oct 03 12:05:43 PM UTC 24
Peak memory 393492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155570280
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.1555702800
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.782095234
Short name T18
Test name
Test status
Simulation time 586347341 ps
CPU time 54.31 seconds
Started Oct 03 11:49:36 AM UTC 24
Finished Oct 03 11:50:32 AM UTC 24
Peak memory 266484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782095234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.782095234
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.4076499589
Short name T208
Test name
Test status
Simulation time 2765900228 ps
CPU time 278.38 seconds
Started Oct 03 11:48:40 AM UTC 24
Finished Oct 03 11:53:22 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076499589 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.4076499589
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3088087664
Short name T174
Test name
Test status
Simulation time 433443427 ps
CPU time 56.31 seconds
Started Oct 03 11:48:48 AM UTC 24
Finished Oct 03 11:49:46 AM UTC 24
Peak memory 319720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3088087664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th
roughput_w_partial_write.3088087664
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3754813750
Short name T427
Test name
Test status
Simulation time 9114862628 ps
CPU time 1515.48 seconds
Started Oct 03 11:50:12 AM UTC 24
Finished Oct 03 12:15:45 PM UTC 24
Peak memory 381160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754813750 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_
key_req.3754813750
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.4243182415
Short name T181
Test name
Test status
Simulation time 17831061 ps
CPU time 0.98 seconds
Started Oct 03 11:50:33 AM UTC 24
Finished Oct 03 11:50:35 AM UTC 24
Peak memory 211396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243182415 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.4243182415
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.2970040883
Short name T177
Test name
Test status
Simulation time 1061936274 ps
CPU time 23.47 seconds
Started Oct 03 11:49:50 AM UTC 24
Finished Oct 03 11:50:15 AM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970040883 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.2970040883
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.2693648718
Short name T146
Test name
Test status
Simulation time 8389579202 ps
CPU time 853.02 seconds
Started Oct 03 11:50:15 AM UTC 24
Finished Oct 03 12:04:38 PM UTC 24
Peak memory 375152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693648718 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.2693648718
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2588381791
Short name T178
Test name
Test status
Simulation time 2267538848 ps
CPU time 9.74 seconds
Started Oct 03 11:50:09 AM UTC 24
Finished Oct 03 11:50:20 AM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588381791 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2588381791
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.2029865892
Short name T185
Test name
Test status
Simulation time 111406598 ps
CPU time 51.06 seconds
Started Oct 03 11:50:03 AM UTC 24
Finished Oct 03 11:50:56 AM UTC 24
Peak memory 329928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
029865892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max
_throughput.2029865892
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.4098245114
Short name T45
Test name
Test status
Simulation time 849027624 ps
CPU time 8.6 seconds
Started Oct 03 11:50:22 AM UTC 24
Finished Oct 03 11:50:31 AM UTC 24
Peak memory 222404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098245114 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.4098245114
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.640771448
Short name T182
Test name
Test status
Simulation time 1701757981 ps
CPU time 14.95 seconds
Started Oct 03 11:50:22 AM UTC 24
Finished Oct 03 11:50:38 AM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640771448 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.640771448
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2569357947
Short name T276
Test name
Test status
Simulation time 2771336138 ps
CPU time 684.09 seconds
Started Oct 03 11:49:47 AM UTC 24
Finished Oct 03 12:01:20 PM UTC 24
Peak memory 381224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569357947 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.2569357947
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3282166666
Short name T176
Test name
Test status
Simulation time 81641821 ps
CPU time 11.55 seconds
Started Oct 03 11:49:56 AM UTC 24
Finished Oct 03 11:50:08 AM UTC 24
Peak memory 247924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282166666 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.3282166666
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1920240350
Short name T220
Test name
Test status
Simulation time 20832062101 ps
CPU time 310.73 seconds
Started Oct 03 11:49:57 AM UTC 24
Finished Oct 03 11:55:12 AM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920240350 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce
ss_b2b.1920240350
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3981416200
Short name T180
Test name
Test status
Simulation time 76243438 ps
CPU time 1.19 seconds
Started Oct 03 11:50:20 AM UTC 24
Finished Oct 03 11:50:23 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981416200 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3981416200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1419586600
Short name T175
Test name
Test status
Simulation time 531178022 ps
CPU time 9.85 seconds
Started Oct 03 11:49:43 AM UTC 24
Finished Oct 03 11:49:55 AM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419586600 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1419586600
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1609015887
Short name T500
Test name
Test status
Simulation time 8932445606 ps
CPU time 1958.24 seconds
Started Oct 03 11:50:32 AM UTC 24
Finished Oct 03 12:23:31 PM UTC 24
Peak memory 381180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160901588
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.1609015887
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4109433028
Short name T59
Test name
Test status
Simulation time 727963558 ps
CPU time 95.55 seconds
Started Oct 03 11:50:24 AM UTC 24
Finished Oct 03 11:52:01 AM UTC 24
Peak memory 325816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109433028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.4109433028
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1334071729
Short name T226
Test name
Test status
Simulation time 12633130325 ps
CPU time 365.67 seconds
Started Oct 03 11:49:53 AM UTC 24
Finished Oct 03 11:56:04 AM UTC 24
Peak memory 212400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334071729 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1334071729
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1377563586
Short name T179
Test name
Test status
Simulation time 149324604 ps
CPU time 11.5 seconds
Started Oct 03 11:50:08 AM UTC 24
Finished Oct 03 11:50:20 AM UTC 24
Peak memory 262392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1377563586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th
roughput_w_partial_write.1377563586
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1022115713
Short name T42
Test name
Test status
Simulation time 976800908 ps
CPU time 275.56 seconds
Started Oct 03 11:51:06 AM UTC 24
Finished Oct 03 11:55:46 AM UTC 24
Peak memory 383168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022115713 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_
key_req.1022115713
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.18712438
Short name T192
Test name
Test status
Simulation time 17034666 ps
CPU time 1.04 seconds
Started Oct 03 11:51:28 AM UTC 24
Finished Oct 03 11:51:30 AM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18712438 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.18712438
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.1905276736
Short name T191
Test name
Test status
Simulation time 733651445 ps
CPU time 46.78 seconds
Started Oct 03 11:50:41 AM UTC 24
Finished Oct 03 11:51:29 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905276736 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.1905276736
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2833209702
Short name T140
Test name
Test status
Simulation time 6323052548 ps
CPU time 628.82 seconds
Started Oct 03 11:51:06 AM UTC 24
Finished Oct 03 12:01:43 PM UTC 24
Peak memory 377156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833209702 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2833209702
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4283991603
Short name T188
Test name
Test status
Simulation time 143337378 ps
CPU time 3.71 seconds
Started Oct 03 11:51:02 AM UTC 24
Finished Oct 03 11:51:07 AM UTC 24
Peak memory 222588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283991603 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.4283991603
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1691170998
Short name T197
Test name
Test status
Simulation time 119744106 ps
CPU time 77.5 seconds
Started Oct 03 11:50:58 AM UTC 24
Finished Oct 03 11:52:17 AM UTC 24
Peak memory 348284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
691170998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max
_throughput.1691170998
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3487377091
Short name T58
Test name
Test status
Simulation time 62228857 ps
CPU time 3.97 seconds
Started Oct 03 11:51:21 AM UTC 24
Finished Oct 03 11:51:26 AM UTC 24
Peak memory 222448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487377091 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.3487377091
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2718041520
Short name T190
Test name
Test status
Simulation time 280977253 ps
CPU time 7.79 seconds
Started Oct 03 11:51:18 AM UTC 24
Finished Oct 03 11:51:26 AM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718041520 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.2718041520
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2876003252
Short name T289
Test name
Test status
Simulation time 3617164667 ps
CPU time 697.26 seconds
Started Oct 03 11:50:38 AM UTC 24
Finished Oct 03 12:02:23 PM UTC 24
Peak memory 376992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876003252 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.2876003252
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3518346058
Short name T186
Test name
Test status
Simulation time 280176778 ps
CPU time 7.03 seconds
Started Oct 03 11:50:48 AM UTC 24
Finished Oct 03 11:50:56 AM UTC 24
Peak memory 229476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518346058 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.3518346058
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.251114452
Short name T244
Test name
Test status
Simulation time 6010760137 ps
CPU time 437.68 seconds
Started Oct 03 11:50:56 AM UTC 24
Finished Oct 03 11:58:20 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251114452 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acces
s_b2b.251114452
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1842198195
Short name T189
Test name
Test status
Simulation time 126587445 ps
CPU time 1.27 seconds
Started Oct 03 11:51:15 AM UTC 24
Finished Oct 03 11:51:17 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842198195 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1842198195
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.18614040
Short name T399
Test name
Test status
Simulation time 12927488163 ps
CPU time 1300.12 seconds
Started Oct 03 11:51:07 AM UTC 24
Finished Oct 03 12:13:02 PM UTC 24
Peak memory 385260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18614040 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.18614040
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.3789455401
Short name T184
Test name
Test status
Simulation time 305163013 ps
CPU time 6.9 seconds
Started Oct 03 11:50:36 AM UTC 24
Finished Oct 03 11:50:44 AM UTC 24
Peak memory 212148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789455401 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3789455401
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2228512236
Short name T531
Test name
Test status
Simulation time 24203526142 ps
CPU time 2095.45 seconds
Started Oct 03 11:51:28 AM UTC 24
Finished Oct 03 12:26:47 PM UTC 24
Peak memory 385260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222851223
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.2228512236
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1907828694
Short name T49
Test name
Test status
Simulation time 12612415983 ps
CPU time 198.29 seconds
Started Oct 03 11:51:27 AM UTC 24
Finished Oct 03 11:54:49 AM UTC 24
Peak memory 372948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907828694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1907828694
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3582800175
Short name T224
Test name
Test status
Simulation time 11137818629 ps
CPU time 301.56 seconds
Started Oct 03 11:50:45 AM UTC 24
Finished Oct 03 11:55:51 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582800175 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.3582800175
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761126317
Short name T187
Test name
Test status
Simulation time 84137730 ps
CPU time 2.91 seconds
Started Oct 03 11:51:02 AM UTC 24
Finished Oct 03 11:51:06 AM UTC 24
Peak memory 224588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1761126317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th
roughput_w_partial_write.1761126317
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3469985004
Short name T273
Test name
Test status
Simulation time 2657722285 ps
CPU time 522.1 seconds
Started Oct 03 11:52:02 AM UTC 24
Finished Oct 03 12:00:51 PM UTC 24
Peak memory 372972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469985004 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_
key_req.3469985004
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3540403151
Short name T201
Test name
Test status
Simulation time 25510497 ps
CPU time 1.03 seconds
Started Oct 03 11:52:28 AM UTC 24
Finished Oct 03 11:52:31 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540403151 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3540403151
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3652737212
Short name T199
Test name
Test status
Simulation time 3167301048 ps
CPU time 53.26 seconds
Started Oct 03 11:51:31 AM UTC 24
Finished Oct 03 11:52:26 AM UTC 24
Peak memory 212400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652737212 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.3652737212
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.2353766171
Short name T318
Test name
Test status
Simulation time 88260558708 ps
CPU time 998.27 seconds
Started Oct 03 11:52:06 AM UTC 24
Finished Oct 03 12:08:57 PM UTC 24
Peak memory 385344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353766171 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.2353766171
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4225934797
Short name T120
Test name
Test status
Simulation time 156206084 ps
CPU time 3.65 seconds
Started Oct 03 11:52:01 AM UTC 24
Finished Oct 03 11:52:06 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225934797 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.4225934797
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1761922380
Short name T200
Test name
Test status
Simulation time 132921659 ps
CPU time 35.19 seconds
Started Oct 03 11:51:51 AM UTC 24
Finished Oct 03 11:52:28 AM UTC 24
Peak memory 297164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
761922380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max
_throughput.1761922380
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.566216590
Short name T48
Test name
Test status
Simulation time 118780282 ps
CPU time 4.79 seconds
Started Oct 03 11:52:18 AM UTC 24
Finished Oct 03 11:52:24 AM UTC 24
Peak memory 222528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566216590 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.566216590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3226780935
Short name T202
Test name
Test status
Simulation time 1901092004 ps
CPU time 12.92 seconds
Started Oct 03 11:52:18 AM UTC 24
Finished Oct 03 11:52:32 AM UTC 24
Peak memory 222584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226780935 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3226780935
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2008564611
Short name T296
Test name
Test status
Simulation time 11403712654 ps
CPU time 684.13 seconds
Started Oct 03 11:51:30 AM UTC 24
Finished Oct 03 12:03:02 PM UTC 24
Peak memory 374944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008564611 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.2008564611
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2932251075
Short name T196
Test name
Test status
Simulation time 4157855790 ps
CPU time 27.82 seconds
Started Oct 03 11:51:44 AM UTC 24
Finished Oct 03 11:52:13 AM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932251075 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.2932251075
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3894154882
Short name T250
Test name
Test status
Simulation time 4629406695 ps
CPU time 408.87 seconds
Started Oct 03 11:51:47 AM UTC 24
Finished Oct 03 11:58:42 AM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894154882 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce
ss_b2b.3894154882
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3020297794
Short name T198
Test name
Test status
Simulation time 27047858 ps
CPU time 1.12 seconds
Started Oct 03 11:52:15 AM UTC 24
Finished Oct 03 11:52:17 AM UTC 24
Peak memory 211048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020297794 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3020297794
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.248732971
Short name T157
Test name
Test status
Simulation time 1163999478 ps
CPU time 596.51 seconds
Started Oct 03 11:52:10 AM UTC 24
Finished Oct 03 12:02:14 PM UTC 24
Peak memory 383160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248732971 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.248732971
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.4291558850
Short name T193
Test name
Test status
Simulation time 994396714 ps
CPU time 15.01 seconds
Started Oct 03 11:51:29 AM UTC 24
Finished Oct 03 11:51:46 AM UTC 24
Peak memory 212228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291558850 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.4291558850
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3865048599
Short name T796
Test name
Test status
Simulation time 25075396369 ps
CPU time 3891.59 seconds
Started Oct 03 11:52:27 AM UTC 24
Finished Oct 03 12:58:02 PM UTC 24
Peak memory 387056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386504859
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.3865048599
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2973308115
Short name T61
Test name
Test status
Simulation time 8867921507 ps
CPU time 373.83 seconds
Started Oct 03 11:52:25 AM UTC 24
Finished Oct 03 11:58:44 AM UTC 24
Peak memory 385276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973308115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2973308115
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3771938519
Short name T222
Test name
Test status
Simulation time 1999430127 ps
CPU time 212.31 seconds
Started Oct 03 11:51:44 AM UTC 24
Finished Oct 03 11:55:20 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771938519 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.3771938519
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1231261998
Short name T204
Test name
Test status
Simulation time 118520599 ps
CPU time 53.78 seconds
Started Oct 03 11:51:54 AM UTC 24
Finished Oct 03 11:52:50 AM UTC 24
Peak memory 330048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1231261998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th
roughput_w_partial_write.1231261998
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.476748604
Short name T341
Test name
Test status
Simulation time 2309482964 ps
CPU time 784.78 seconds
Started Oct 03 11:53:20 AM UTC 24
Finished Oct 03 12:06:34 PM UTC 24
Peak memory 377000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476748604 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_k
ey_req.476748604
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.530617792
Short name T216
Test name
Test status
Simulation time 67915643 ps
CPU time 0.91 seconds
Started Oct 03 11:53:48 AM UTC 24
Finished Oct 03 11:53:50 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530617792 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.530617792
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.1023936477
Short name T209
Test name
Test status
Simulation time 3272994645 ps
CPU time 55.59 seconds
Started Oct 03 11:52:35 AM UTC 24
Finished Oct 03 11:53:32 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023936477 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.1023936477
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2169208751
Short name T137
Test name
Test status
Simulation time 20607801091 ps
CPU time 646.03 seconds
Started Oct 03 11:53:23 AM UTC 24
Finished Oct 03 12:04:18 PM UTC 24
Peak memory 362668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169208751 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.2169208751
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2603267916
Short name T207
Test name
Test status
Simulation time 1791842042 ps
CPU time 7.62 seconds
Started Oct 03 11:53:11 AM UTC 24
Finished Oct 03 11:53:19 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603267916 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2603267916
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3734274682
Short name T213
Test name
Test status
Simulation time 109349636 ps
CPU time 44.63 seconds
Started Oct 03 11:53:00 AM UTC 24
Finished Oct 03 11:53:47 AM UTC 24
Peak memory 311496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
734274682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max
_throughput.3734274682
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2551996597
Short name T214
Test name
Test status
Simulation time 204330990 ps
CPU time 4.78 seconds
Started Oct 03 11:53:41 AM UTC 24
Finished Oct 03 11:53:47 AM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551996597 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.2551996597
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.576083219
Short name T215
Test name
Test status
Simulation time 891972824 ps
CPU time 7.62 seconds
Started Oct 03 11:53:39 AM UTC 24
Finished Oct 03 11:53:48 AM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576083219 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.576083219
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1961363276
Short name T246
Test name
Test status
Simulation time 11271064558 ps
CPU time 350.92 seconds
Started Oct 03 11:52:33 AM UTC 24
Finished Oct 03 11:58:28 AM UTC 24
Peak memory 383276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961363276 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.1961363276
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.615687815
Short name T205
Test name
Test status
Simulation time 530337078 ps
CPU time 2.85 seconds
Started Oct 03 11:52:50 AM UTC 24
Finished Oct 03 11:52:54 AM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615687815 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.615687815
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.566699960
Short name T245
Test name
Test status
Simulation time 51722438339 ps
CPU time 325.75 seconds
Started Oct 03 11:52:55 AM UTC 24
Finished Oct 03 11:58:26 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566699960 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acces
s_b2b.566699960
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3203957465
Short name T212
Test name
Test status
Simulation time 29328064 ps
CPU time 1.27 seconds
Started Oct 03 11:53:38 AM UTC 24
Finished Oct 03 11:53:40 AM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203957465 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3203957465
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.3986409785
Short name T136
Test name
Test status
Simulation time 1346600970 ps
CPU time 510.66 seconds
Started Oct 03 11:53:33 AM UTC 24
Finished Oct 03 12:02:10 PM UTC 24
Peak memory 360640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986409785 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3986409785
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3017557908
Short name T203
Test name
Test status
Simulation time 55613090 ps
CPU time 6.16 seconds
Started Oct 03 11:52:31 AM UTC 24
Finished Oct 03 11:52:39 AM UTC 24
Peak memory 231584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017557908 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3017557908
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2218611495
Short name T841
Test name
Test status
Simulation time 40417309676 ps
CPU time 4134.49 seconds
Started Oct 03 11:53:48 AM UTC 24
Finished Oct 03 01:03:28 PM UTC 24
Peak memory 395092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221861149
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.2218611495
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1427905841
Short name T60
Test name
Test status
Simulation time 6798277622 ps
CPU time 272.76 seconds
Started Oct 03 11:53:47 AM UTC 24
Finished Oct 03 11:58:24 AM UTC 24
Peak memory 348420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427905841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1427905841
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1192438096
Short name T249
Test name
Test status
Simulation time 7284791816 ps
CPU time 353.8 seconds
Started Oct 03 11:52:39 AM UTC 24
Finished Oct 03 11:58:38 AM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192438096 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.1192438096
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4294161244
Short name T210
Test name
Test status
Simulation time 111095576 ps
CPU time 27.3 seconds
Started Oct 03 11:53:09 AM UTC 24
Finished Oct 03 11:53:37 AM UTC 24
Peak memory 317688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4294161244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th
roughput_w_partial_write.4294161244
Directory /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest
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