| T548 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.520660027 |
|
|
Oct 03 12:25:17 PM UTC 24 |
Oct 03 12:29:20 PM UTC 24 |
9165674696 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2097683780 |
|
|
Oct 03 12:12:08 PM UTC 24 |
Oct 03 12:29:21 PM UTC 24 |
12948403834 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.522116083 |
|
|
Oct 03 12:23:20 PM UTC 24 |
Oct 03 12:29:28 PM UTC 24 |
40564739070 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.119449720 |
|
|
Oct 03 12:29:15 PM UTC 24 |
Oct 03 12:29:34 PM UTC 24 |
5223712117 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1713976589 |
|
|
Oct 03 12:29:26 PM UTC 24 |
Oct 03 12:29:35 PM UTC 24 |
796267925 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1867965911 |
|
|
Oct 03 12:29:35 PM UTC 24 |
Oct 03 12:29:41 PM UTC 24 |
224199051 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.598946683 |
|
|
Oct 03 12:29:42 PM UTC 24 |
Oct 03 12:29:46 PM UTC 24 |
571416846 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3646260027 |
|
|
Oct 03 12:13:36 PM UTC 24 |
Oct 03 12:29:54 PM UTC 24 |
4652032544 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.647028727 |
|
|
Oct 03 12:29:03 PM UTC 24 |
Oct 03 12:29:56 PM UTC 24 |
1301469198 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.737489886 |
|
|
Oct 03 12:10:44 PM UTC 24 |
Oct 03 12:29:57 PM UTC 24 |
13373836477 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2120761794 |
|
|
Oct 03 12:29:58 PM UTC 24 |
Oct 03 12:30:00 PM UTC 24 |
29747045 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3204576909 |
|
|
Oct 03 12:29:36 PM UTC 24 |
Oct 03 12:30:11 PM UTC 24 |
229863331 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3758536941 |
|
|
Oct 03 12:18:18 PM UTC 24 |
Oct 03 12:30:12 PM UTC 24 |
2395643748 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1716781884 |
|
|
Oct 03 12:30:01 PM UTC 24 |
Oct 03 12:30:13 PM UTC 24 |
4703366326 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1006201781 |
|
|
Oct 03 12:30:12 PM UTC 24 |
Oct 03 12:30:17 PM UTC 24 |
104333453 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.795561400 |
|
|
Oct 03 12:29:57 PM UTC 24 |
Oct 03 12:30:19 PM UTC 24 |
409306917 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3890155451 |
|
|
Oct 03 12:30:19 PM UTC 24 |
Oct 03 12:30:21 PM UTC 24 |
43636206 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.884037374 |
|
|
Oct 03 12:29:20 PM UTC 24 |
Oct 03 12:30:23 PM UTC 24 |
3386554145 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.1966486120 |
|
|
Oct 03 12:30:20 PM UTC 24 |
Oct 03 12:30:40 PM UTC 24 |
2924800374 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2794534534 |
|
|
Oct 03 12:26:19 PM UTC 24 |
Oct 03 12:30:42 PM UTC 24 |
399453342 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2251312289 |
|
|
Oct 03 12:15:17 PM UTC 24 |
Oct 03 12:30:51 PM UTC 24 |
1877941584 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2535215491 |
|
|
Oct 03 11:47:43 AM UTC 24 |
Oct 03 12:30:55 PM UTC 24 |
65188688270 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2312520027 |
|
|
Oct 03 12:30:43 PM UTC 24 |
Oct 03 12:31:01 PM UTC 24 |
965070961 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1198745465 |
|
|
Oct 03 12:30:24 PM UTC 24 |
Oct 03 12:31:18 PM UTC 24 |
32904108132 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.2697160345 |
|
|
Oct 03 12:16:44 PM UTC 24 |
Oct 03 12:31:23 PM UTC 24 |
2522726659 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3876514490 |
|
|
Oct 03 12:31:19 PM UTC 24 |
Oct 03 12:31:32 PM UTC 24 |
1522297912 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3805595194 |
|
|
Oct 03 12:15:26 PM UTC 24 |
Oct 03 12:31:44 PM UTC 24 |
9867176251 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.962030358 |
|
|
Oct 03 12:30:56 PM UTC 24 |
Oct 03 12:31:55 PM UTC 24 |
92119812 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1478284160 |
|
|
Oct 03 12:31:56 PM UTC 24 |
Oct 03 12:31:58 PM UTC 24 |
54134346 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.4049866776 |
|
|
Oct 03 12:31:59 PM UTC 24 |
Oct 03 12:32:07 PM UTC 24 |
923617151 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1527716847 |
|
|
Oct 03 12:32:08 PM UTC 24 |
Oct 03 12:32:16 PM UTC 24 |
168578034 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.1199607947 |
|
|
Oct 03 12:26:03 PM UTC 24 |
Oct 03 12:32:19 PM UTC 24 |
1137554791 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1419759739 |
|
|
Oct 03 12:29:22 PM UTC 24 |
Oct 03 12:32:23 PM UTC 24 |
6525321964 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2546392188 |
|
|
Oct 03 12:25:40 PM UTC 24 |
Oct 03 12:32:24 PM UTC 24 |
129762827404 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2186520340 |
|
|
Oct 03 12:32:23 PM UTC 24 |
Oct 03 12:32:25 PM UTC 24 |
15839386 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3878152919 |
|
|
Oct 03 12:06:11 PM UTC 24 |
Oct 03 12:32:26 PM UTC 24 |
10766408573 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.2725149264 |
|
|
Oct 03 12:32:25 PM UTC 24 |
Oct 03 12:32:27 PM UTC 24 |
28994886 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3916542025 |
|
|
Oct 03 12:26:49 PM UTC 24 |
Oct 03 12:32:29 PM UTC 24 |
2932226466 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2421089720 |
|
|
Oct 03 12:31:33 PM UTC 24 |
Oct 03 12:32:31 PM UTC 24 |
1572826118 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2534073406 |
|
|
Oct 03 12:32:30 PM UTC 24 |
Oct 03 12:32:36 PM UTC 24 |
195948551 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3056653220 |
|
|
Oct 03 12:32:37 PM UTC 24 |
Oct 03 12:32:51 PM UTC 24 |
311499738 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2642526350 |
|
|
Oct 03 12:31:02 PM UTC 24 |
Oct 03 12:32:54 PM UTC 24 |
183845059 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.522715244 |
|
|
Oct 03 12:08:14 PM UTC 24 |
Oct 03 12:33:03 PM UTC 24 |
13045576301 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1560059044 |
|
|
Oct 03 12:32:56 PM UTC 24 |
Oct 03 12:33:04 PM UTC 24 |
1594726496 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.1844702393 |
|
|
Oct 03 12:32:27 PM UTC 24 |
Oct 03 12:33:33 PM UTC 24 |
7711391292 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1198275163 |
|
|
Oct 03 12:32:52 PM UTC 24 |
Oct 03 12:33:38 PM UTC 24 |
125539287 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2325471102 |
|
|
Oct 03 12:33:39 PM UTC 24 |
Oct 03 12:33:42 PM UTC 24 |
53517460 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.3968891338 |
|
|
Oct 03 12:24:18 PM UTC 24 |
Oct 03 12:33:50 PM UTC 24 |
1435189418 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.389880840 |
|
|
Oct 03 12:33:42 PM UTC 24 |
Oct 03 12:33:53 PM UTC 24 |
333239449 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.617053264 |
|
|
Oct 03 12:22:24 PM UTC 24 |
Oct 03 12:33:54 PM UTC 24 |
22570089111 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1501575300 |
|
|
Oct 03 12:33:51 PM UTC 24 |
Oct 03 12:33:57 PM UTC 24 |
472739834 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1635448914 |
|
|
Oct 03 12:33:58 PM UTC 24 |
Oct 03 12:34:00 PM UTC 24 |
14657301 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2070731428 |
|
|
Oct 03 12:21:33 PM UTC 24 |
Oct 03 12:34:11 PM UTC 24 |
50231889958 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.298088656 |
|
|
Oct 03 12:20:01 PM UTC 24 |
Oct 03 12:34:16 PM UTC 24 |
107645065061 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.866206684 |
|
|
Oct 03 12:34:01 PM UTC 24 |
Oct 03 12:34:17 PM UTC 24 |
439451149 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.4202575270 |
|
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Oct 03 12:26:09 PM UTC 24 |
Oct 03 12:34:19 PM UTC 24 |
5608239379 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3616493291 |
|
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Oct 03 12:28:37 PM UTC 24 |
Oct 03 12:34:44 PM UTC 24 |
3246618156 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1392783098 |
|
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Oct 03 12:29:29 PM UTC 24 |
Oct 03 12:34:51 PM UTC 24 |
20728185155 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1742553484 |
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Oct 03 12:34:17 PM UTC 24 |
Oct 03 12:35:03 PM UTC 24 |
2013600601 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1416600646 |
|
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Oct 03 12:34:20 PM UTC 24 |
Oct 03 12:35:05 PM UTC 24 |
562849539 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3835573068 |
|
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Oct 03 12:35:05 PM UTC 24 |
Oct 03 12:35:14 PM UTC 24 |
1047944172 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1895891198 |
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Oct 03 12:30:12 PM UTC 24 |
Oct 03 12:35:21 PM UTC 24 |
2021415154 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1485042011 |
|
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Oct 03 12:35:04 PM UTC 24 |
Oct 03 12:35:34 PM UTC 24 |
92204176 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2382331033 |
|
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Oct 03 12:11:42 PM UTC 24 |
Oct 03 12:35:35 PM UTC 24 |
7193283941 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1353546396 |
|
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Oct 03 12:35:36 PM UTC 24 |
Oct 03 12:35:38 PM UTC 24 |
95054770 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1445006838 |
|
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Oct 03 12:29:55 PM UTC 24 |
Oct 03 12:35:40 PM UTC 24 |
48008896612 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2877328842 |
|
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Oct 03 12:35:41 PM UTC 24 |
Oct 03 12:35:49 PM UTC 24 |
157728880 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3789094767 |
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Oct 03 12:35:39 PM UTC 24 |
Oct 03 12:35:52 PM UTC 24 |
1686456605 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.520531143 |
|
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Oct 03 12:34:51 PM UTC 24 |
Oct 03 12:35:58 PM UTC 24 |
1139105903 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3443169993 |
|
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Oct 03 12:36:00 PM UTC 24 |
Oct 03 12:36:02 PM UTC 24 |
11362132 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.4274398168 |
|
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Oct 03 12:36:03 PM UTC 24 |
Oct 03 12:36:15 PM UTC 24 |
1040576629 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.2026638782 |
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Oct 03 12:22:14 PM UTC 24 |
Oct 03 12:36:19 PM UTC 24 |
38213721110 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3139848554 |
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Oct 03 12:30:41 PM UTC 24 |
Oct 03 12:36:34 PM UTC 24 |
3254035196 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1103722624 |
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Oct 03 12:35:49 PM UTC 24 |
Oct 03 12:36:35 PM UTC 24 |
1223633260 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.725640782 |
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Oct 03 12:32:17 PM UTC 24 |
Oct 03 12:36:47 PM UTC 24 |
1370955505 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.61432740 |
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Oct 03 12:32:28 PM UTC 24 |
Oct 03 12:36:47 PM UTC 24 |
2725704434 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.733227631 |
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Oct 03 12:36:16 PM UTC 24 |
Oct 03 12:36:47 PM UTC 24 |
344440557 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1318002034 |
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Oct 03 12:27:53 PM UTC 24 |
Oct 03 12:37:02 PM UTC 24 |
75217090780 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.3771542094 |
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Oct 03 12:28:43 PM UTC 24 |
Oct 03 12:37:10 PM UTC 24 |
89864110664 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3944447200 |
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Oct 03 12:37:02 PM UTC 24 |
Oct 03 12:37:16 PM UTC 24 |
788533741 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.2613727931 |
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Oct 03 12:36:20 PM UTC 24 |
Oct 03 12:37:29 PM UTC 24 |
6517340828 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.819737537 |
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Oct 03 12:21:11 PM UTC 24 |
Oct 03 12:37:32 PM UTC 24 |
4994315303 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.286807048 |
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Oct 03 12:36:48 PM UTC 24 |
Oct 03 12:37:33 PM UTC 24 |
706733960 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1965514183 |
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Oct 03 12:37:33 PM UTC 24 |
Oct 03 12:37:35 PM UTC 24 |
89518342 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3734236523 |
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Oct 03 12:36:48 PM UTC 24 |
Oct 03 12:37:35 PM UTC 24 |
112469004 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.595784121 |
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Oct 03 12:37:36 PM UTC 24 |
Oct 03 12:37:42 PM UTC 24 |
68125991 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2801004118 |
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Oct 03 12:37:34 PM UTC 24 |
Oct 03 12:37:50 PM UTC 24 |
1647003066 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1675776659 |
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Oct 03 12:37:51 PM UTC 24 |
Oct 03 12:37:53 PM UTC 24 |
14735883 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3920578629 |
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Oct 03 12:37:10 PM UTC 24 |
Oct 03 12:37:54 PM UTC 24 |
899598794 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.4222451957 |
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Oct 03 12:37:54 PM UTC 24 |
Oct 03 12:38:19 PM UTC 24 |
853102652 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3936374818 |
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Oct 03 12:36:35 PM UTC 24 |
Oct 03 12:38:29 PM UTC 24 |
806117680 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2541532605 |
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Oct 03 12:34:45 PM UTC 24 |
Oct 03 12:38:32 PM UTC 24 |
78468925749 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.3426737782 |
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Oct 03 12:38:20 PM UTC 24 |
Oct 03 12:38:45 PM UTC 24 |
6113588548 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.120890483 |
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Oct 03 12:37:17 PM UTC 24 |
Oct 03 12:38:51 PM UTC 24 |
2395042259 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3078311987 |
|
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Oct 03 12:31:23 PM UTC 24 |
Oct 03 12:38:58 PM UTC 24 |
5376736594 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1893424371 |
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Oct 03 12:22:49 PM UTC 24 |
Oct 03 12:39:06 PM UTC 24 |
40104328407 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2099246583 |
|
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Oct 03 12:39:07 PM UTC 24 |
Oct 03 12:39:12 PM UTC 24 |
237969634 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3056597853 |
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Oct 03 12:30:51 PM UTC 24 |
Oct 03 12:39:51 PM UTC 24 |
17825495302 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3159991527 |
|
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Oct 03 12:38:33 PM UTC 24 |
Oct 03 12:40:01 PM UTC 24 |
641348448 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.202702070 |
|
|
Oct 03 12:38:59 PM UTC 24 |
Oct 03 12:40:01 PM UTC 24 |
422629108 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.2733646055 |
|
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Oct 03 12:40:02 PM UTC 24 |
Oct 03 12:40:04 PM UTC 24 |
78720323 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.367353352 |
|
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Oct 03 12:38:52 PM UTC 24 |
Oct 03 12:40:11 PM UTC 24 |
128140844 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.665768930 |
|
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Oct 03 12:40:11 PM UTC 24 |
Oct 03 12:40:17 PM UTC 24 |
59963168 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1404038129 |
|
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Oct 03 12:40:05 PM UTC 24 |
Oct 03 12:40:21 PM UTC 24 |
4085431403 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2518199716 |
|
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Oct 03 11:56:06 AM UTC 24 |
Oct 03 12:40:34 PM UTC 24 |
44413945700 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1848515119 |
|
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Oct 03 12:40:35 PM UTC 24 |
Oct 03 12:40:37 PM UTC 24 |
35304563 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3556076870 |
|
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Oct 03 12:19:53 PM UTC 24 |
Oct 03 12:40:47 PM UTC 24 |
4007195855 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.2451432078 |
|
|
Oct 03 12:35:35 PM UTC 24 |
Oct 03 12:40:51 PM UTC 24 |
13274644662 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.213816441 |
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Oct 03 12:34:17 PM UTC 24 |
Oct 03 12:40:58 PM UTC 24 |
7530058153 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3949904681 |
|
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Oct 03 12:33:05 PM UTC 24 |
Oct 03 12:41:07 PM UTC 24 |
15861430212 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3757107946 |
|
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Oct 03 12:41:07 PM UTC 24 |
Oct 03 12:41:15 PM UTC 24 |
164464976 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.599214440 |
|
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Oct 03 12:33:54 PM UTC 24 |
Oct 03 12:41:16 PM UTC 24 |
1049919158 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1982431727 |
|
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Oct 03 12:40:52 PM UTC 24 |
Oct 03 12:41:47 PM UTC 24 |
2104529852 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.340687978 |
|
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Oct 03 12:41:34 PM UTC 24 |
Oct 03 12:41:51 PM UTC 24 |
169667247 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.427504583 |
|
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Oct 03 12:41:47 PM UTC 24 |
Oct 03 12:41:55 PM UTC 24 |
446115836 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2332612466 |
|
|
Oct 03 12:40:38 PM UTC 24 |
Oct 03 12:41:56 PM UTC 24 |
2196172636 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3894080657 |
|
|
Oct 03 12:32:32 PM UTC 24 |
Oct 03 12:42:25 PM UTC 24 |
21382181538 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3599693799 |
|
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Oct 03 12:42:26 PM UTC 24 |
Oct 03 12:42:28 PM UTC 24 |
28376762 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.45157815 |
|
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Oct 03 12:42:29 PM UTC 24 |
Oct 03 12:42:38 PM UTC 24 |
331489499 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2823335167 |
|
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Oct 03 12:42:39 PM UTC 24 |
Oct 03 12:42:45 PM UTC 24 |
192660920 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.4094168728 |
|
|
Oct 03 12:41:17 PM UTC 24 |
Oct 03 12:42:53 PM UTC 24 |
131166642 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.679272525 |
|
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Oct 03 12:36:35 PM UTC 24 |
Oct 03 12:43:20 PM UTC 24 |
3820789718 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1855713982 |
|
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Oct 03 12:43:22 PM UTC 24 |
Oct 03 12:43:24 PM UTC 24 |
22170143 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3348836831 |
|
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Oct 03 12:15:49 PM UTC 24 |
Oct 03 12:43:26 PM UTC 24 |
49817380332 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3740306583 |
|
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Oct 03 12:38:29 PM UTC 24 |
Oct 03 12:43:28 PM UTC 24 |
3188361578 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2159957858 |
|
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Oct 03 12:31:45 PM UTC 24 |
Oct 03 12:43:43 PM UTC 24 |
82548834526 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3655172878 |
|
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Oct 03 12:40:17 PM UTC 24 |
Oct 03 12:43:43 PM UTC 24 |
2403848084 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1670715935 |
|
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Oct 03 12:40:58 PM UTC 24 |
Oct 03 12:43:49 PM UTC 24 |
7719312132 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.362395705 |
|
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Oct 03 12:43:25 PM UTC 24 |
Oct 03 12:44:04 PM UTC 24 |
99389124 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1448184281 |
|
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Oct 03 12:39:53 PM UTC 24 |
Oct 03 12:44:16 PM UTC 24 |
5667132400 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.11765144 |
|
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Oct 03 12:36:48 PM UTC 24 |
Oct 03 12:44:16 PM UTC 24 |
16020446630 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.386768352 |
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Oct 03 12:44:05 PM UTC 24 |
Oct 03 12:44:18 PM UTC 24 |
69402338 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2368168066 |
|
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Oct 03 12:44:17 PM UTC 24 |
Oct 03 12:44:20 PM UTC 24 |
125276209 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.1238236713 |
|
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Oct 03 12:43:29 PM UTC 24 |
Oct 03 12:44:29 PM UTC 24 |
18312017617 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.557682312 |
|
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Oct 03 12:33:34 PM UTC 24 |
Oct 03 12:44:29 PM UTC 24 |
57819993816 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3002319508 |
|
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Oct 03 12:44:18 PM UTC 24 |
Oct 03 12:44:30 PM UTC 24 |
483514287 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1042744518 |
|
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Oct 03 12:44:31 PM UTC 24 |
Oct 03 12:44:33 PM UTC 24 |
85408797 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2456969259 |
|
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Oct 03 12:26:42 PM UTC 24 |
Oct 03 12:44:35 PM UTC 24 |
71465458433 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1179324737 |
|
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Oct 03 12:44:34 PM UTC 24 |
Oct 03 12:44:39 PM UTC 24 |
185625854 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1542739630 |
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Oct 03 12:44:36 PM UTC 24 |
Oct 03 12:44:45 PM UTC 24 |
246773068 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.588466942 |
|
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Oct 03 12:44:31 PM UTC 24 |
Oct 03 12:44:45 PM UTC 24 |
467822397 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2395389514 |
|
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Oct 03 12:32:27 PM UTC 24 |
Oct 03 12:44:48 PM UTC 24 |
10991762691 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3418578547 |
|
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Oct 03 12:44:46 PM UTC 24 |
Oct 03 12:44:48 PM UTC 24 |
13168632 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1582383243 |
|
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Oct 03 12:44:47 PM UTC 24 |
Oct 03 12:44:49 PM UTC 24 |
224126668 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2450709927 |
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Oct 03 12:29:16 PM UTC 24 |
Oct 03 12:44:56 PM UTC 24 |
6634019632 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1375415433 |
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Oct 03 12:44:56 PM UTC 24 |
Oct 03 12:45:04 PM UTC 24 |
918966447 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3041950797 |
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Oct 03 12:43:44 PM UTC 24 |
Oct 03 12:45:05 PM UTC 24 |
470533241 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1440518668 |
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Oct 03 12:45:05 PM UTC 24 |
Oct 03 12:45:11 PM UTC 24 |
185172059 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.3749453814 |
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Oct 03 12:45:12 PM UTC 24 |
Oct 03 12:45:16 PM UTC 24 |
98003600 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2865297840 |
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Oct 03 12:45:17 PM UTC 24 |
Oct 03 12:45:25 PM UTC 24 |
404429805 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.3578693577 |
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Oct 03 12:44:50 PM UTC 24 |
Oct 03 12:45:29 PM UTC 24 |
2583840096 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2250905238 |
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Oct 03 12:23:52 PM UTC 24 |
Oct 03 12:45:38 PM UTC 24 |
4447369408 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1658752385 |
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Oct 03 12:38:46 PM UTC 24 |
Oct 03 12:46:03 PM UTC 24 |
45687604362 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3029523808 |
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Oct 03 12:46:04 PM UTC 24 |
Oct 03 12:46:07 PM UTC 24 |
25362604 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1217420372 |
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Oct 03 12:25:01 PM UTC 24 |
Oct 03 12:46:13 PM UTC 24 |
15509162756 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.176531272 |
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Oct 03 12:05:34 PM UTC 24 |
Oct 03 12:46:14 PM UTC 24 |
33931820870 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1521583093 |
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Oct 03 12:46:08 PM UTC 24 |
Oct 03 12:46:16 PM UTC 24 |
433829827 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1929242029 |
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Oct 03 12:46:18 PM UTC 24 |
Oct 03 12:46:20 PM UTC 24 |
41363851 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3737961856 |
|
|
Oct 03 12:46:14 PM UTC 24 |
Oct 03 12:46:23 PM UTC 24 |
397131842 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3292756762 |
|
|
Oct 03 12:26:02 PM UTC 24 |
Oct 03 12:46:23 PM UTC 24 |
3122041608 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.2195860547 |
|
|
Oct 03 12:46:21 PM UTC 24 |
Oct 03 12:46:38 PM UTC 24 |
2248017650 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3082406169 |
|
|
Oct 03 12:33:04 PM UTC 24 |
Oct 03 12:46:43 PM UTC 24 |
2443157370 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.909619909 |
|
|
Oct 03 12:29:47 PM UTC 24 |
Oct 03 12:46:44 PM UTC 24 |
6306298686 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.2965519423 |
|
|
Oct 03 12:41:57 PM UTC 24 |
Oct 03 12:47:01 PM UTC 24 |
24248485950 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1709763442 |
|
|
Oct 03 12:46:44 PM UTC 24 |
Oct 03 12:47:10 PM UTC 24 |
3064832951 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1471593704 |
|
|
Oct 03 12:47:11 PM UTC 24 |
Oct 03 12:47:31 PM UTC 24 |
359215438 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.544702130 |
|
|
Oct 03 11:46:01 AM UTC 24 |
Oct 03 12:47:34 PM UTC 24 |
37052313696 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4222997510 |
|
|
Oct 03 12:46:15 PM UTC 24 |
Oct 03 12:47:41 PM UTC 24 |
1326507741 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.937419979 |
|
|
Oct 03 12:47:32 PM UTC 24 |
Oct 03 12:47:42 PM UTC 24 |
2656897613 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.3952320473 |
|
|
Oct 03 12:43:43 PM UTC 24 |
Oct 03 12:47:50 PM UTC 24 |
2283030310 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.245402403 |
|
|
Oct 03 12:47:02 PM UTC 24 |
Oct 03 12:47:52 PM UTC 24 |
382499637 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2197900199 |
|
|
Oct 03 12:47:51 PM UTC 24 |
Oct 03 12:47:53 PM UTC 24 |
28849353 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3335743626 |
|
|
Oct 03 12:47:54 PM UTC 24 |
Oct 03 12:48:03 PM UTC 24 |
819496440 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.108693098 |
|
|
Oct 03 12:46:25 PM UTC 24 |
Oct 03 12:48:05 PM UTC 24 |
7237600949 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.1998111036 |
|
|
Oct 03 12:47:53 PM UTC 24 |
Oct 03 12:48:06 PM UTC 24 |
3176966237 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.2470097791 |
|
|
Oct 03 12:48:06 PM UTC 24 |
Oct 03 12:48:08 PM UTC 24 |
29390627 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.4045208063 |
|
|
Oct 03 12:44:50 PM UTC 24 |
Oct 03 12:48:11 PM UTC 24 |
1639290626 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2820157083 |
|
|
Oct 03 12:48:10 PM UTC 24 |
Oct 03 12:48:29 PM UTC 24 |
2174011571 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.3058159193 |
|
|
Oct 03 12:17:48 PM UTC 24 |
Oct 03 12:49:32 PM UTC 24 |
16259962552 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1654609650 |
|
|
Oct 03 12:48:30 PM UTC 24 |
Oct 03 12:49:32 PM UTC 24 |
2683181211 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3503094539 |
|
|
Oct 03 12:41:16 PM UTC 24 |
Oct 03 12:49:40 PM UTC 24 |
28679893721 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.838661195 |
|
|
Oct 03 12:41:51 PM UTC 24 |
Oct 03 12:49:41 PM UTC 24 |
2101923774 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4163222490 |
|
|
Oct 03 12:37:36 PM UTC 24 |
Oct 03 12:49:47 PM UTC 24 |
1340762211 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3244906450 |
|
|
Oct 03 12:49:48 PM UTC 24 |
Oct 03 12:49:53 PM UTC 24 |
54952765 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2613640246 |
|
|
Oct 03 12:49:54 PM UTC 24 |
Oct 03 12:50:09 PM UTC 24 |
710671735 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1998022659 |
|
|
Oct 03 12:49:34 PM UTC 24 |
Oct 03 12:50:36 PM UTC 24 |
599704393 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1999246184 |
|
|
Oct 03 12:44:30 PM UTC 24 |
Oct 03 12:50:37 PM UTC 24 |
711667662 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2596226074 |
|
|
Oct 03 12:49:42 PM UTC 24 |
Oct 03 12:50:56 PM UTC 24 |
126594092 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4117216860 |
|
|
Oct 03 12:50:57 PM UTC 24 |
Oct 03 12:50:59 PM UTC 24 |
32988010 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.3002203149 |
|
|
Oct 03 12:51:00 PM UTC 24 |
Oct 03 12:51:07 PM UTC 24 |
352784378 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.1983316888 |
|
|
Oct 03 12:51:08 PM UTC 24 |
Oct 03 12:51:14 PM UTC 24 |
103109767 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.953222955 |
|
|
Oct 03 12:28:37 PM UTC 24 |
Oct 03 12:51:20 PM UTC 24 |
12544867974 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2279932622 |
|
|
Oct 03 12:45:26 PM UTC 24 |
Oct 03 12:51:44 PM UTC 24 |
8942377010 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.808176890 |
|
|
Oct 03 12:51:45 PM UTC 24 |
Oct 03 12:51:47 PM UTC 24 |
11484357 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1650994097 |
|
|
Oct 03 12:46:24 PM UTC 24 |
Oct 03 12:51:55 PM UTC 24 |
6950447764 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.3918208644 |
|
|
Oct 03 12:23:59 PM UTC 24 |
Oct 03 12:51:59 PM UTC 24 |
14755419558 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3518325758 |
|
|
Oct 03 12:40:48 PM UTC 24 |
Oct 03 12:52:02 PM UTC 24 |
15330944697 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3997042097 |
|
|
Oct 03 12:49:34 PM UTC 24 |
Oct 03 12:52:30 PM UTC 24 |
1395729778 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1236276611 |
|
|
Oct 03 11:46:48 AM UTC 24 |
Oct 03 12:52:52 PM UTC 24 |
58389525339 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2472264178 |
|
|
Oct 03 12:48:03 PM UTC 24 |
Oct 03 12:52:55 PM UTC 24 |
1687845609 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1015836884 |
|
|
Oct 03 12:46:45 PM UTC 24 |
Oct 03 12:52:58 PM UTC 24 |
24056304618 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3760564368 |
|
|
Oct 03 12:52:00 PM UTC 24 |
Oct 03 12:53:00 PM UTC 24 |
18686653679 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3051553034 |
|
|
Oct 03 12:52:59 PM UTC 24 |
Oct 03 12:53:02 PM UTC 24 |
47085656 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3029241421 |
|
|
Oct 03 12:53:00 PM UTC 24 |
Oct 03 12:53:12 PM UTC 24 |
2367890072 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.2646781556 |
|
|
Oct 03 12:51:48 PM UTC 24 |
Oct 03 12:53:12 PM UTC 24 |
1087795599 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.4031031997 |
|
|
Oct 03 12:40:02 PM UTC 24 |
Oct 03 12:53:12 PM UTC 24 |
12752698330 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.606592714 |
|
|
Oct 03 12:53:13 PM UTC 24 |
Oct 03 12:53:15 PM UTC 24 |
31655148 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3245980457 |
|
|
Oct 03 12:03:17 PM UTC 24 |
Oct 03 12:53:22 PM UTC 24 |
16674777790 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.562108086 |
|
|
Oct 03 12:37:30 PM UTC 24 |
Oct 03 12:53:22 PM UTC 24 |
41452102580 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3000842001 |
|
|
Oct 03 12:52:31 PM UTC 24 |
Oct 03 12:53:25 PM UTC 24 |
768106458 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2242429130 |
|
|
Oct 03 12:44:19 PM UTC 24 |
Oct 03 12:53:29 PM UTC 24 |
7559950366 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.645815971 |
|
|
Oct 03 12:53:23 PM UTC 24 |
Oct 03 12:53:30 PM UTC 24 |
553477379 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1359523557 |
|
|
Oct 03 12:53:16 PM UTC 24 |
Oct 03 12:53:32 PM UTC 24 |
595791590 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3296345148 |
|
|
Oct 03 12:53:31 PM UTC 24 |
Oct 03 12:53:33 PM UTC 24 |
12483332 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4150781738 |
|
|
Oct 03 12:46:39 PM UTC 24 |
Oct 03 12:53:35 PM UTC 24 |
6944687965 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3150158829 |
|
|
Oct 03 12:53:31 PM UTC 24 |
Oct 03 12:53:42 PM UTC 24 |
560425378 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.907615594 |
|
|
Oct 03 12:53:43 PM UTC 24 |
Oct 03 12:54:11 PM UTC 24 |
1853444885 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.1282807593 |
|
|
Oct 03 12:45:30 PM UTC 24 |
Oct 03 12:54:21 PM UTC 24 |
7572988326 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2817115215 |
|
|
Oct 03 12:52:57 PM UTC 24 |
Oct 03 12:54:22 PM UTC 24 |
218222617 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3783272972 |
|
|
Oct 03 12:53:23 PM UTC 24 |
Oct 03 12:54:29 PM UTC 24 |
2447012044 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4116098528 |
|
|
Oct 03 12:54:30 PM UTC 24 |
Oct 03 12:54:35 PM UTC 24 |
183653352 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.4040955988 |
|
|
Oct 03 12:54:23 PM UTC 24 |
Oct 03 12:54:38 PM UTC 24 |
77351115 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.3116208768 |
|
|
Oct 03 12:45:05 PM UTC 24 |
Oct 03 12:54:40 PM UTC 24 |
76075674681 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3864021788 |
|
|
Oct 03 12:53:35 PM UTC 24 |
Oct 03 12:54:46 PM UTC 24 |
15514623468 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3662902610 |
|
|
Oct 03 12:54:47 PM UTC 24 |
Oct 03 12:54:49 PM UTC 24 |
110893086 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3547695830 |
|
|
Oct 03 12:54:50 PM UTC 24 |
Oct 03 12:55:05 PM UTC 24 |
454656555 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2728122209 |
|
|
Oct 03 12:30:22 PM UTC 24 |
Oct 03 12:55:14 PM UTC 24 |
47688219334 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1517500704 |
|
|
Oct 03 12:55:06 PM UTC 24 |
Oct 03 12:55:14 PM UTC 24 |
303581714 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2506554807 |
|
|
Oct 03 12:43:50 PM UTC 24 |
Oct 03 12:55:58 PM UTC 24 |
280482938738 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.173163681 |
|
|
Oct 03 12:55:14 PM UTC 24 |
Oct 03 12:55:58 PM UTC 24 |
1033098114 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.620081972 |
|
|
Oct 03 12:54:23 PM UTC 24 |
Oct 03 12:56:01 PM UTC 24 |
142712763 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1403023294 |
|
|
Oct 03 12:56:00 PM UTC 24 |
Oct 03 12:56:02 PM UTC 24 |
27243283 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.119399230 |
|
|
Oct 03 12:52:03 PM UTC 24 |
Oct 03 12:56:13 PM UTC 24 |
1826961547 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.3702988367 |
|
|
Oct 03 12:56:00 PM UTC 24 |
Oct 03 12:56:16 PM UTC 24 |
333786222 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.3824672366 |
|
|
Oct 03 12:56:03 PM UTC 24 |
Oct 03 12:56:42 PM UTC 24 |
7415992129 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3730657538 |
|
|
Oct 03 12:56:14 PM UTC 24 |
Oct 03 12:56:44 PM UTC 24 |
3976669587 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.989337930 |
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Oct 03 12:37:55 PM UTC 24 |
Oct 03 12:56:48 PM UTC 24 |
31625007981 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2042636624 |
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Oct 03 12:42:45 PM UTC 24 |
Oct 03 12:56:53 PM UTC 24 |
2198258389 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3474101400 |
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Oct 03 12:56:50 PM UTC 24 |
Oct 03 12:56:58 PM UTC 24 |
352214791 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.875957200 |
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Oct 03 12:54:12 PM UTC 24 |
Oct 03 12:57:17 PM UTC 24 |
2218486834 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3700792375 |
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Oct 03 12:35:22 PM UTC 24 |
Oct 03 12:57:32 PM UTC 24 |
54907283326 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.2136103776 |
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Oct 03 12:57:33 PM UTC 24 |
Oct 03 12:57:35 PM UTC 24 |
30316413 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2129662954 |
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Oct 03 12:33:55 PM UTC 24 |
Oct 03 12:57:43 PM UTC 24 |
29085912320 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2356461436 |
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Oct 03 12:57:36 PM UTC 24 |
Oct 03 12:57:44 PM UTC 24 |
188393878 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3235397136 |
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Oct 03 12:56:46 PM UTC 24 |
Oct 03 12:57:44 PM UTC 24 |
274195238 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3687275520 |
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Oct 03 12:57:44 PM UTC 24 |
Oct 03 12:57:49 PM UTC 24 |
453834240 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2854441055 |
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Oct 03 12:57:50 PM UTC 24 |
Oct 03 12:57:52 PM UTC 24 |
42326947 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3501367988 |
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Oct 03 12:57:46 PM UTC 24 |
Oct 03 12:57:55 PM UTC 24 |
841971503 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1713646425 |
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Oct 03 12:50:39 PM UTC 24 |
Oct 03 12:57:55 PM UTC 24 |
4214331924 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2953064762 |
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Oct 03 12:18:05 PM UTC 24 |
Oct 03 12:57:59 PM UTC 24 |
32102870921 ps |