| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3865048599 |
|
|
Oct 03 11:52:27 AM UTC 24 |
Oct 03 12:58:02 PM UTC 24 |
25075396369 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1025047610 |
|
|
Oct 03 12:52:53 PM UTC 24 |
Oct 03 12:58:03 PM UTC 24 |
3547840663 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.3766049521 |
|
|
Oct 03 12:45:38 PM UTC 24 |
Oct 03 12:58:08 PM UTC 24 |
18572461832 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.726607714 |
|
|
Oct 03 12:15:43 PM UTC 24 |
Oct 03 12:58:25 PM UTC 24 |
35379278150 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2642449782 |
|
|
Oct 03 12:58:03 PM UTC 24 |
Oct 03 12:58:28 PM UTC 24 |
1003804486 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1201244372 |
|
|
Oct 03 12:56:43 PM UTC 24 |
Oct 03 12:58:28 PM UTC 24 |
539548627 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1586592503 |
|
|
Oct 03 12:34:11 PM UTC 24 |
Oct 03 12:58:29 PM UTC 24 |
14559196975 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1650289115 |
|
|
Oct 03 12:58:28 PM UTC 24 |
Oct 03 12:58:38 PM UTC 24 |
705159971 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.1688729252 |
|
|
Oct 03 12:57:53 PM UTC 24 |
Oct 03 12:58:41 PM UTC 24 |
1064881255 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2920307916 |
|
|
Oct 03 12:58:42 PM UTC 24 |
Oct 03 12:58:44 PM UTC 24 |
50452693 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2481844173 |
|
|
Oct 03 12:58:25 PM UTC 24 |
Oct 03 12:58:53 PM UTC 24 |
338626473 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.326464796 |
|
|
Oct 03 12:58:46 PM UTC 24 |
Oct 03 12:58:53 PM UTC 24 |
377779382 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2656096343 |
|
|
Oct 03 12:58:54 PM UTC 24 |
Oct 03 12:58:59 PM UTC 24 |
84711482 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1286687203 |
|
|
Oct 03 12:56:54 PM UTC 24 |
Oct 03 12:59:23 PM UTC 24 |
1279947700 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2988364655 |
|
|
Oct 03 12:50:09 PM UTC 24 |
Oct 03 12:59:25 PM UTC 24 |
3481250720 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.4029783360 |
|
|
Oct 03 12:59:24 PM UTC 24 |
Oct 03 12:59:26 PM UTC 24 |
10573043 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.126422225 |
|
|
Oct 03 12:58:09 PM UTC 24 |
Oct 03 12:59:30 PM UTC 24 |
648531594 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2212495891 |
|
|
Oct 03 12:57:56 PM UTC 24 |
Oct 03 12:59:43 PM UTC 24 |
3639176528 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1510832358 |
|
|
Oct 03 12:49:41 PM UTC 24 |
Oct 03 12:59:48 PM UTC 24 |
175804060038 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.2239308743 |
|
|
Oct 03 12:56:16 PM UTC 24 |
Oct 03 01:00:05 PM UTC 24 |
12688607985 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.2664331266 |
|
|
Oct 03 12:50:38 PM UTC 24 |
Oct 03 01:00:08 PM UTC 24 |
14135829036 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3916943863 |
|
|
Oct 03 12:41:56 PM UTC 24 |
Oct 03 01:00:28 PM UTC 24 |
61156429901 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.4104973083 |
|
|
Oct 03 01:00:29 PM UTC 24 |
Oct 03 01:00:33 PM UTC 24 |
45467706 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3257377325 |
|
|
Oct 03 12:59:31 PM UTC 24 |
Oct 03 01:00:36 PM UTC 24 |
10273030096 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1481257344 |
|
|
Oct 03 12:59:49 PM UTC 24 |
Oct 03 01:00:39 PM UTC 24 |
1093164455 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2506698361 |
|
|
Oct 03 12:51:14 PM UTC 24 |
Oct 03 01:00:41 PM UTC 24 |
7394436633 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.4021948081 |
|
|
Oct 03 01:00:34 PM UTC 24 |
Oct 03 01:00:41 PM UTC 24 |
355401355 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.615029390 |
|
|
Oct 03 01:00:42 PM UTC 24 |
Oct 03 01:00:44 PM UTC 24 |
31290621 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1978095496 |
|
|
Oct 03 11:48:29 AM UTC 24 |
Oct 03 01:00:46 PM UTC 24 |
234836673554 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.4000119837 |
|
|
Oct 03 12:35:14 PM UTC 24 |
Oct 03 01:00:47 PM UTC 24 |
21490634093 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.721579050 |
|
|
Oct 03 01:00:47 PM UTC 24 |
Oct 03 01:00:57 PM UTC 24 |
189860017 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3674440450 |
|
|
Oct 03 01:00:45 PM UTC 24 |
Oct 03 01:00:59 PM UTC 24 |
1987215141 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3099531648 |
|
|
Oct 03 01:01:00 PM UTC 24 |
Oct 03 01:01:02 PM UTC 24 |
16919805 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2155669212 |
|
|
Oct 03 12:59:26 PM UTC 24 |
Oct 03 01:01:04 PM UTC 24 |
539973922 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1255041951 |
|
|
Oct 03 12:56:04 PM UTC 24 |
Oct 03 01:01:15 PM UTC 24 |
2729403787 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.38251957 |
|
|
Oct 03 01:01:03 PM UTC 24 |
Oct 03 01:01:24 PM UTC 24 |
3017936017 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1888755058 |
|
|
Oct 03 01:00:48 PM UTC 24 |
Oct 03 01:02:08 PM UTC 24 |
4254942893 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3871193371 |
|
|
Oct 03 01:00:09 PM UTC 24 |
Oct 03 01:02:09 PM UTC 24 |
146481422 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2517751239 |
|
|
Oct 03 12:57:59 PM UTC 24 |
Oct 03 01:02:12 PM UTC 24 |
7620179361 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2199738340 |
|
|
Oct 03 01:02:13 PM UTC 24 |
Oct 03 01:02:16 PM UTC 24 |
335553591 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3174460076 |
|
|
Oct 03 12:53:03 PM UTC 24 |
Oct 03 01:02:27 PM UTC 24 |
6042208908 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.1487086308 |
|
|
Oct 03 01:01:16 PM UTC 24 |
Oct 03 01:02:37 PM UTC 24 |
13901501624 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.860256839 |
|
|
Oct 03 01:02:28 PM UTC 24 |
Oct 03 01:02:41 PM UTC 24 |
728349567 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3449457811 |
|
|
Oct 03 12:53:36 PM UTC 24 |
Oct 03 01:03:26 PM UTC 24 |
21067298646 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2153626685 |
|
|
Oct 03 12:39:12 PM UTC 24 |
Oct 03 01:03:27 PM UTC 24 |
14530279423 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2218611495 |
|
|
Oct 03 11:53:48 AM UTC 24 |
Oct 03 01:03:28 PM UTC 24 |
40417309676 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.861276968 |
|
|
Oct 03 01:03:26 PM UTC 24 |
Oct 03 01:03:29 PM UTC 24 |
39779333 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3494276254 |
|
|
Oct 03 12:54:36 PM UTC 24 |
Oct 03 01:03:36 PM UTC 24 |
15013144641 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.542936683 |
|
|
Oct 03 01:03:27 PM UTC 24 |
Oct 03 01:03:39 PM UTC 24 |
1035394045 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1620350915 |
|
|
Oct 03 01:03:30 PM UTC 24 |
Oct 03 01:03:41 PM UTC 24 |
340056954 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3994477317 |
|
|
Oct 03 01:03:41 PM UTC 24 |
Oct 03 01:03:43 PM UTC 24 |
18779999 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2260157694 |
|
|
Oct 03 01:02:09 PM UTC 24 |
Oct 03 01:04:06 PM UTC 24 |
1365396782 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.524641125 |
|
|
Oct 03 01:02:17 PM UTC 24 |
Oct 03 01:04:08 PM UTC 24 |
305047476 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3876822522 |
|
|
Oct 03 01:00:06 PM UTC 24 |
Oct 03 01:04:25 PM UTC 24 |
17209102578 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3517205411 |
|
|
Oct 03 01:04:26 PM UTC 24 |
Oct 03 01:04:37 PM UTC 24 |
869946184 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1946391994 |
|
|
Oct 03 01:04:08 PM UTC 24 |
Oct 03 01:04:47 PM UTC 24 |
538480259 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2626008625 |
|
|
Oct 03 01:04:48 PM UTC 24 |
Oct 03 01:04:54 PM UTC 24 |
179453384 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.52352063 |
|
|
Oct 03 01:03:42 PM UTC 24 |
Oct 03 01:05:09 PM UTC 24 |
5534697356 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2650940418 |
|
|
Oct 03 01:05:11 PM UTC 24 |
Oct 03 01:05:21 PM UTC 24 |
1428181520 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2939268180 |
|
|
Oct 03 12:47:43 PM UTC 24 |
Oct 03 01:05:40 PM UTC 24 |
3756916257 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2552632267 |
|
|
Oct 03 01:01:25 PM UTC 24 |
Oct 03 01:05:44 PM UTC 24 |
2136763175 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2575377164 |
|
|
Oct 03 12:59:43 PM UTC 24 |
Oct 03 01:05:56 PM UTC 24 |
17760411044 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.479014812 |
|
|
Oct 03 01:04:54 PM UTC 24 |
Oct 03 01:05:57 PM UTC 24 |
524925457 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2156730163 |
|
|
Oct 03 01:05:57 PM UTC 24 |
Oct 03 01:06:00 PM UTC 24 |
50848152 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3259795670 |
|
|
Oct 03 01:06:01 PM UTC 24 |
Oct 03 01:06:09 PM UTC 24 |
177276841 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2286827460 |
|
|
Oct 03 01:05:57 PM UTC 24 |
Oct 03 01:06:09 PM UTC 24 |
531349478 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3283593192 |
|
|
Oct 03 01:06:10 PM UTC 24 |
Oct 03 01:06:24 PM UTC 24 |
1309072367 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1625241282 |
|
|
Oct 03 01:06:25 PM UTC 24 |
Oct 03 01:06:27 PM UTC 24 |
11790253 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2809985735 |
|
|
Oct 03 01:02:09 PM UTC 24 |
Oct 03 01:06:29 PM UTC 24 |
13705296626 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.95003685 |
|
|
Oct 03 12:48:05 PM UTC 24 |
Oct 03 01:06:34 PM UTC 24 |
18915185359 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.3781692512 |
|
|
Oct 03 01:06:28 PM UTC 24 |
Oct 03 01:06:49 PM UTC 24 |
3555328144 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.294160627 |
|
|
Oct 03 12:58:04 PM UTC 24 |
Oct 03 01:06:53 PM UTC 24 |
216481429863 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.400957069 |
|
|
Oct 03 12:58:55 PM UTC 24 |
Oct 03 01:07:09 PM UTC 24 |
4063051483 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.867508252 |
|
|
Oct 03 01:06:54 PM UTC 24 |
Oct 03 01:07:14 PM UTC 24 |
969233027 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3847764697 |
|
|
Oct 03 12:58:30 PM UTC 24 |
Oct 03 01:07:24 PM UTC 24 |
3138449538 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2216176010 |
|
|
Oct 03 01:04:09 PM UTC 24 |
Oct 03 01:07:29 PM UTC 24 |
22327046570 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.236749400 |
|
|
Oct 03 01:07:25 PM UTC 24 |
Oct 03 01:07:38 PM UTC 24 |
336589375 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1698264539 |
|
|
Oct 03 12:44:49 PM UTC 24 |
Oct 03 01:07:39 PM UTC 24 |
12144570332 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2874528977 |
|
|
Oct 03 01:07:30 PM UTC 24 |
Oct 03 01:07:43 PM UTC 24 |
1569376361 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.386326699 |
|
|
Oct 03 12:57:56 PM UTC 24 |
Oct 03 01:07:46 PM UTC 24 |
26395915734 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.1739409328 |
|
|
Oct 03 12:53:13 PM UTC 24 |
Oct 03 01:07:46 PM UTC 24 |
7677499827 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.551604246 |
|
|
Oct 03 01:07:47 PM UTC 24 |
Oct 03 01:07:49 PM UTC 24 |
35371901 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.1914381463 |
|
|
Oct 03 01:06:35 PM UTC 24 |
Oct 03 01:07:49 PM UTC 24 |
21710465173 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.35844360 |
|
|
Oct 03 12:57:19 PM UTC 24 |
Oct 03 01:07:50 PM UTC 24 |
1825054248 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4266407464 |
|
|
Oct 03 12:56:03 PM UTC 24 |
Oct 03 01:07:51 PM UTC 24 |
45692747370 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3960991852 |
|
|
Oct 03 01:07:52 PM UTC 24 |
Oct 03 01:07:54 PM UTC 24 |
39078245 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4097988798 |
|
|
Oct 03 01:07:51 PM UTC 24 |
Oct 03 01:07:56 PM UTC 24 |
1350721477 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2296905872 |
|
|
Oct 03 12:54:39 PM UTC 24 |
Oct 03 01:07:59 PM UTC 24 |
2517069798 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.999565529 |
|
|
Oct 03 01:07:47 PM UTC 24 |
Oct 03 01:08:05 PM UTC 24 |
2599357422 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.164546559 |
|
|
Oct 03 12:46:17 PM UTC 24 |
Oct 03 01:08:12 PM UTC 24 |
8090132563 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3562500879 |
|
|
Oct 03 01:03:30 PM UTC 24 |
Oct 03 01:08:18 PM UTC 24 |
1434706899 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2446541273 |
|
|
Oct 03 01:07:15 PM UTC 24 |
Oct 03 01:08:33 PM UTC 24 |
748920860 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.3283253240 |
|
|
Oct 03 01:02:42 PM UTC 24 |
Oct 03 01:08:34 PM UTC 24 |
4687757122 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2025409566 |
|
|
Oct 03 12:35:52 PM UTC 24 |
Oct 03 01:08:58 PM UTC 24 |
336763379187 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.1123793522 |
|
|
Oct 03 01:00:42 PM UTC 24 |
Oct 03 01:09:46 PM UTC 24 |
9019406207 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1447392282 |
|
|
Oct 03 01:05:22 PM UTC 24 |
Oct 03 01:10:03 PM UTC 24 |
3860199822 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1285918792 |
|
|
Oct 03 01:04:39 PM UTC 24 |
Oct 03 01:10:45 PM UTC 24 |
17513118105 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3507450009 |
|
|
Oct 03 12:11:56 PM UTC 24 |
Oct 03 01:10:57 PM UTC 24 |
11612316585 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.4189326072 |
|
|
Oct 03 01:06:51 PM UTC 24 |
Oct 03 01:11:22 PM UTC 24 |
10003337726 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1272624208 |
|
|
Oct 03 12:26:30 PM UTC 24 |
Oct 03 01:11:35 PM UTC 24 |
109611451900 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2542538513 |
|
|
Oct 03 01:07:51 PM UTC 24 |
Oct 03 01:11:52 PM UTC 24 |
3591626097 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3598298544 |
|
|
Oct 03 12:51:56 PM UTC 24 |
Oct 03 01:12:20 PM UTC 24 |
14510045328 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.4228382296 |
|
|
Oct 03 12:53:13 PM UTC 24 |
Oct 03 01:12:45 PM UTC 24 |
12451392121 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3283367473 |
|
|
Oct 03 12:53:33 PM UTC 24 |
Oct 03 01:12:48 PM UTC 24 |
79548880223 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.4217235606 |
|
|
Oct 03 01:02:37 PM UTC 24 |
Oct 03 01:12:52 PM UTC 24 |
11054995492 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1874086873 |
|
|
Oct 03 12:47:35 PM UTC 24 |
Oct 03 01:13:44 PM UTC 24 |
16531201663 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.3763295423 |
|
|
Oct 03 12:56:59 PM UTC 24 |
Oct 03 01:14:54 PM UTC 24 |
11805969055 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2676498763 |
|
|
Oct 03 12:48:12 PM UTC 24 |
Oct 03 01:15:39 PM UTC 24 |
24488329497 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2356293395 |
|
|
Oct 03 12:59:00 PM UTC 24 |
Oct 03 01:15:59 PM UTC 24 |
12860141834 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3320942656 |
|
|
Oct 03 12:58:39 PM UTC 24 |
Oct 03 01:16:09 PM UTC 24 |
6739138580 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3161178521 |
|
|
Oct 03 01:00:37 PM UTC 24 |
Oct 03 01:16:30 PM UTC 24 |
14109103026 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3193366061 |
|
|
Oct 03 12:59:28 PM UTC 24 |
Oct 03 01:16:33 PM UTC 24 |
55110462263 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.908243604 |
|
|
Oct 03 01:05:46 PM UTC 24 |
Oct 03 01:16:53 PM UTC 24 |
4221736264 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1092559637 |
|
|
Oct 03 12:16:40 PM UTC 24 |
Oct 03 01:16:55 PM UTC 24 |
335887745107 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3267487142 |
|
|
Oct 03 01:07:10 PM UTC 24 |
Oct 03 01:17:46 PM UTC 24 |
17953119340 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.1390979741 |
|
|
Oct 03 01:07:43 PM UTC 24 |
Oct 03 01:17:47 PM UTC 24 |
34766320903 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2771938522 |
|
|
Oct 03 12:13:54 PM UTC 24 |
Oct 03 01:17:59 PM UTC 24 |
51456222589 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.2075302382 |
|
|
Oct 03 12:22:46 PM UTC 24 |
Oct 03 01:18:01 PM UTC 24 |
41820891785 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3439373323 |
|
|
Oct 03 12:54:41 PM UTC 24 |
Oct 03 01:18:37 PM UTC 24 |
7833489057 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2874314300 |
|
|
Oct 03 12:44:39 PM UTC 24 |
Oct 03 01:19:04 PM UTC 24 |
8304383302 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.393030296 |
|
|
Oct 03 01:03:44 PM UTC 24 |
Oct 03 01:19:30 PM UTC 24 |
9811815917 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1937391258 |
|
|
Oct 03 01:03:37 PM UTC 24 |
Oct 03 01:20:20 PM UTC 24 |
18707719887 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2384150644 |
|
|
Oct 03 12:21:07 PM UTC 24 |
Oct 03 01:20:58 PM UTC 24 |
14889045261 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1758094694 |
|
|
Oct 03 01:05:41 PM UTC 24 |
Oct 03 01:21:25 PM UTC 24 |
8994264385 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1792469959 |
|
|
Oct 03 01:07:40 PM UTC 24 |
Oct 03 01:21:54 PM UTC 24 |
80521201178 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1815800428 |
|
|
Oct 03 12:29:03 PM UTC 24 |
Oct 03 01:22:08 PM UTC 24 |
40818088307 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2927724828 |
|
|
Oct 03 12:42:55 PM UTC 24 |
Oct 03 01:22:30 PM UTC 24 |
14520132500 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1986279337 |
|
|
Oct 03 01:00:39 PM UTC 24 |
Oct 03 01:23:39 PM UTC 24 |
62352266186 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2135763245 |
|
|
Oct 03 01:02:51 PM UTC 24 |
Oct 03 01:24:39 PM UTC 24 |
4314815185 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3357553771 |
|
|
Oct 03 12:47:42 PM UTC 24 |
Oct 03 01:24:44 PM UTC 24 |
47001886757 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1136955085 |
|
|
Oct 03 12:44:21 PM UTC 24 |
Oct 03 01:24:44 PM UTC 24 |
21957706051 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3373873911 |
|
|
Oct 03 12:58:30 PM UTC 24 |
Oct 03 01:24:58 PM UTC 24 |
8083681872 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1693414901 |
|
|
Oct 03 01:06:30 PM UTC 24 |
Oct 03 01:25:54 PM UTC 24 |
16756012036 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3565348818 |
|
|
Oct 03 01:07:52 PM UTC 24 |
Oct 03 01:26:18 PM UTC 24 |
22210906714 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3960436571 |
|
|
Oct 03 12:10:17 PM UTC 24 |
Oct 03 01:26:40 PM UTC 24 |
61693904966 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1694007218 |
|
|
Oct 03 12:43:27 PM UTC 24 |
Oct 03 01:27:24 PM UTC 24 |
22290510347 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.522718284 |
|
|
Oct 03 12:24:45 PM UTC 24 |
Oct 03 01:27:35 PM UTC 24 |
65700195003 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1642687384 |
|
|
Oct 03 01:07:40 PM UTC 24 |
Oct 03 01:28:05 PM UTC 24 |
14214962294 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.789774656 |
|
|
Oct 03 01:06:10 PM UTC 24 |
Oct 03 01:28:59 PM UTC 24 |
7989361483 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3891831094 |
|
|
Oct 03 12:04:49 PM UTC 24 |
Oct 03 01:31:11 PM UTC 24 |
50601991522 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1953819051 |
|
|
Oct 03 12:55:15 PM UTC 24 |
Oct 03 01:34:32 PM UTC 24 |
24819086558 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.408379782 |
|
|
Oct 03 12:30:13 PM UTC 24 |
Oct 03 01:36:29 PM UTC 24 |
40906636513 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.251302981 |
|
|
Oct 03 12:53:26 PM UTC 24 |
Oct 03 01:37:44 PM UTC 24 |
71101751510 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.511120569 |
|
|
Oct 03 12:37:43 PM UTC 24 |
Oct 03 01:43:06 PM UTC 24 |
13009898286 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3946080762 |
|
|
Oct 03 12:40:22 PM UTC 24 |
Oct 03 01:50:39 PM UTC 24 |
112402606735 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2733007413 |
|
|
Oct 03 12:51:21 PM UTC 24 |
Oct 03 02:07:26 PM UTC 24 |
11563004718 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.533005127 |
|
|
Oct 03 01:00:58 PM UTC 24 |
Oct 03 02:10:42 PM UTC 24 |
235190256824 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3262493699 |
|
|
Oct 03 12:57:46 PM UTC 24 |
Oct 03 02:35:06 PM UTC 24 |
80834141375 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3957909019 |
|
|
Oct 03 11:36:34 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
161137553 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3786140641 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
44950155 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.822888358 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
63622378 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3120701293 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
77645345 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2722381984 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
34278533 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.770542569 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
16824937 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.698911521 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
22189020 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1297196979 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
333021978 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.596126278 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:24 AM UTC 24 |
31180840 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.610265315 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:25 AM UTC 24 |
86258648 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.330674654 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:25 AM UTC 24 |
107486687 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.212967472 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:25 AM UTC 24 |
211728669 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2748312931 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:26 AM UTC 24 |
32293476 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3429450253 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:26 AM UTC 24 |
475999956 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1583683193 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:26 AM UTC 24 |
218004318 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.210021249 |
|
|
Oct 03 11:36:24 AM UTC 24 |
Oct 03 11:36:26 AM UTC 24 |
12688065 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2462304129 |
|
|
Oct 03 11:36:24 AM UTC 24 |
Oct 03 11:36:26 AM UTC 24 |
30605395 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2703286602 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:26 AM UTC 24 |
23775122 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3982725571 |
|
|
Oct 03 11:36:22 AM UTC 24 |
Oct 03 11:36:27 AM UTC 24 |
2757063444 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.653455718 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:27 AM UTC 24 |
26778472 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2873613649 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:27 AM UTC 24 |
16243081 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4055932902 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:27 AM UTC 24 |
127201329 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1661213618 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:27 AM UTC 24 |
92413860 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4212714207 |
|
|
Oct 03 11:36:30 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
815989649 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4265853934 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:28 AM UTC 24 |
240388511 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2458612137 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:28 AM UTC 24 |
196986906 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.465310454 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:28 AM UTC 24 |
65382100 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2963262062 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:28 AM UTC 24 |
1036354788 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1827247995 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:28 AM UTC 24 |
133945036 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.268234598 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
18328004 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.875814571 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
21223922 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1424929300 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
57610527 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2681501945 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
18913974 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3085116258 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
27594935 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1030485303 |
|
|
Oct 03 11:36:28 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
18483491 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2944053480 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
256707222 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3798421326 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:29 AM UTC 24 |
48340760 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1803230796 |
|
|
Oct 03 11:36:28 AM UTC 24 |
Oct 03 11:36:30 AM UTC 24 |
49699708 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2608769040 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:30 AM UTC 24 |
410422833 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3850808679 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:30 AM UTC 24 |
538453612 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3194885415 |
|
|
Oct 03 11:36:28 AM UTC 24 |
Oct 03 11:36:30 AM UTC 24 |
100985620 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2033274963 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
11695974 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.365121232 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
123169616 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3410483004 |
|
|
Oct 03 11:36:28 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
291917797 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1469011187 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
21820810 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2272108232 |
|
|
Oct 03 11:36:28 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
270572022 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4240018551 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
31419710 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2497484819 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
74462460 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.514188604 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:31 AM UTC 24 |
425186045 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3051635421 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
97161942 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4163112949 |
|
|
Oct 03 11:36:25 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
2896098115 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3804938642 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
117157376 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4121357870 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
116229850 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3900474988 |
|
|
Oct 03 11:36:30 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
13904653 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.474455258 |
|
|
Oct 03 11:36:30 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
32146478 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3010899086 |
|
|
Oct 03 11:36:30 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
175351214 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2597754811 |
|
|
Oct 03 11:36:27 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
1548549810 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1835256321 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
474457932 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3709687362 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:32 AM UTC 24 |
79155185 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1110993157 |
|
|
Oct 03 11:36:31 AM UTC 24 |
Oct 03 11:36:33 AM UTC 24 |
22749581 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2886940286 |
|
|
Oct 03 11:36:31 AM UTC 24 |
Oct 03 11:36:33 AM UTC 24 |
33472102 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4045806331 |
|
|
Oct 03 11:36:30 AM UTC 24 |
Oct 03 11:36:33 AM UTC 24 |
193731377 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3546514612 |
|
|
Oct 03 11:36:28 AM UTC 24 |
Oct 03 11:36:33 AM UTC 24 |
97885104 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1645759025 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
1162537250 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2711988385 |
|
|
Oct 03 11:36:30 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
59787743 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2143411843 |
|
|
Oct 03 11:36:29 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
2058995765 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3602386837 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
59069563 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1886787010 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
28421456 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3953949579 |
|
|
Oct 03 11:36:31 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
377833720 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1186475926 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:34 AM UTC 24 |
92946780 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3359116759 |
|
|
Oct 03 11:36:31 AM UTC 24 |
Oct 03 11:36:35 AM UTC 24 |
1099604846 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.459561571 |
|
|
Oct 03 11:36:34 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
346943742 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4108858981 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
44110431 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.690995652 |
|
|
Oct 03 11:36:33 AM UTC 24 |
Oct 03 11:36:35 AM UTC 24 |
28295792 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.123009340 |
|
|
Oct 03 11:36:33 AM UTC 24 |
Oct 03 11:36:35 AM UTC 24 |
102561893 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2133666748 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
3911282518 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2500787814 |
|
|
Oct 03 11:36:34 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
69129171 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.357160726 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
291403209 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3323939552 |
|
|
Oct 03 11:36:33 AM UTC 24 |
Oct 03 11:36:36 AM UTC 24 |
41192504 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3510425818 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:37 AM UTC 24 |
17033143 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.733295358 |
|
|
Oct 03 11:36:34 AM UTC 24 |
Oct 03 11:36:37 AM UTC 24 |
33495314 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4285989484 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:37 AM UTC 24 |
63645083 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1704999227 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:37 AM UTC 24 |
16973056 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3605044 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:37 AM UTC 24 |
191686730 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1065542002 |
|
|
Oct 03 11:36:31 AM UTC 24 |
Oct 03 11:36:37 AM UTC 24 |
157160250 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3212243467 |
|
|
Oct 03 11:36:34 AM UTC 24 |
Oct 03 11:36:37 AM UTC 24 |
223553552 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3640392754 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:38 AM UTC 24 |
528674916 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3693165361 |
|
|
Oct 03 11:36:32 AM UTC 24 |
Oct 03 11:36:38 AM UTC 24 |
2705794437 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3873878242 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:38 AM UTC 24 |
88220687 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.515740083 |
|
|
Oct 03 11:36:34 AM UTC 24 |
Oct 03 11:36:38 AM UTC 24 |
131861371 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4016159670 |
|
|
Oct 03 11:36:34 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
1040383461 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4237366668 |
|
|
Oct 03 11:36:37 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
27595558 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3213285665 |
|
|
Oct 03 11:36:37 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
26266474 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.429932592 |
|
|
Oct 03 11:36:37 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
29326840 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4069426529 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
73880408 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.593312653 |
|
|
Oct 03 11:36:37 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
31676955 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3381383381 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
41586652 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.635414736 |
|
|
Oct 03 11:36:37 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
65301158 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2026571531 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:39 AM UTC 24 |
294790970 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3340295742 |
|
|
Oct 03 11:36:35 AM UTC 24 |
Oct 03 11:36:40 AM UTC 24 |
1567881594 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2286972112 |
|
|
Oct 03 11:36:36 AM UTC 24 |
Oct 03 11:36:40 AM UTC 24 |
226430515 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3377816189 |
|
|
Oct 03 11:36:38 AM UTC 24 |
Oct 03 11:36:40 AM UTC 24 |
42871935 ps |