| T312 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1928964030 |
|
|
Oct 09 09:11:50 AM UTC 24 |
Oct 09 09:11:57 AM UTC 24 |
71514771 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2876354121 |
|
|
Oct 09 09:05:54 AM UTC 24 |
Oct 09 09:11:59 AM UTC 24 |
23277338392 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1545028208 |
|
|
Oct 09 09:11:58 AM UTC 24 |
Oct 09 09:12:01 AM UTC 24 |
16153879 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3546112829 |
|
|
Oct 09 09:11:48 AM UTC 24 |
Oct 09 09:12:03 AM UTC 24 |
636978427 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3177399972 |
|
|
Oct 09 09:11:58 AM UTC 24 |
Oct 09 09:12:06 AM UTC 24 |
156426923 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2286634391 |
|
|
Oct 09 09:10:58 AM UTC 24 |
Oct 09 09:12:11 AM UTC 24 |
446440586 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3296937217 |
|
|
Oct 09 09:12:07 AM UTC 24 |
Oct 09 09:12:20 AM UTC 24 |
316212164 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.4137576708 |
|
|
Oct 09 09:11:03 AM UTC 24 |
Oct 09 09:12:34 AM UTC 24 |
908039993 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.13948966 |
|
|
Oct 09 09:04:53 AM UTC 24 |
Oct 09 09:12:40 AM UTC 24 |
17993498622 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.436544054 |
|
|
Oct 09 09:07:16 AM UTC 24 |
Oct 09 09:12:41 AM UTC 24 |
14506736689 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.376764308 |
|
|
Oct 09 09:12:21 AM UTC 24 |
Oct 09 09:12:55 AM UTC 24 |
100866228 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1790457138 |
|
|
Oct 09 09:12:41 AM UTC 24 |
Oct 09 09:13:00 AM UTC 24 |
8964859612 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3789607531 |
|
|
Oct 09 09:04:45 AM UTC 24 |
Oct 09 09:13:04 AM UTC 24 |
1576140182 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.4123920055 |
|
|
Oct 09 09:13:04 AM UTC 24 |
Oct 09 09:13:07 AM UTC 24 |
52511869 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.3120011006 |
|
|
Oct 09 09:12:01 AM UTC 24 |
Oct 09 09:13:08 AM UTC 24 |
1404831930 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.2587876474 |
|
|
Oct 09 09:07:48 AM UTC 24 |
Oct 09 09:13:14 AM UTC 24 |
3666587751 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2165323669 |
|
|
Oct 09 09:13:09 AM UTC 24 |
Oct 09 09:13:15 AM UTC 24 |
405149594 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_readback_err.1987422302 |
|
|
Oct 09 09:13:15 AM UTC 24 |
Oct 09 09:13:17 AM UTC 24 |
184289047 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1255967404 |
|
|
Oct 09 09:13:08 AM UTC 24 |
Oct 09 09:13:21 AM UTC 24 |
352182207 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.172071838 |
|
|
Oct 09 09:13:22 AM UTC 24 |
Oct 09 09:13:24 AM UTC 24 |
12081008 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3697998953 |
|
|
Oct 09 09:09:50 AM UTC 24 |
Oct 09 09:13:24 AM UTC 24 |
3357048820 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2275044305 |
|
|
Oct 09 09:12:35 AM UTC 24 |
Oct 09 09:13:35 AM UTC 24 |
525430611 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.178110635 |
|
|
Oct 09 09:09:02 AM UTC 24 |
Oct 09 09:13:42 AM UTC 24 |
3551332906 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3539810114 |
|
|
Oct 09 09:13:16 AM UTC 24 |
Oct 09 09:13:56 AM UTC 24 |
2176564916 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3518915459 |
|
|
Oct 09 08:54:05 AM UTC 24 |
Oct 09 09:14:19 AM UTC 24 |
8415216340 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3396372333 |
|
|
Oct 09 08:56:32 AM UTC 24 |
Oct 09 09:14:21 AM UTC 24 |
15546566370 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3156500872 |
|
|
Oct 09 09:14:19 AM UTC 24 |
Oct 09 09:14:22 AM UTC 24 |
173082797 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2403105963 |
|
|
Oct 09 09:08:44 AM UTC 24 |
Oct 09 09:14:27 AM UTC 24 |
3550733903 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3415515638 |
|
|
Oct 09 09:03:36 AM UTC 24 |
Oct 09 09:14:29 AM UTC 24 |
5802440726 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2839785944 |
|
|
Oct 09 09:14:22 AM UTC 24 |
Oct 09 09:14:35 AM UTC 24 |
1149864940 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2084336851 |
|
|
Oct 09 09:14:36 AM UTC 24 |
Oct 09 09:14:39 AM UTC 24 |
219805162 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2980983478 |
|
|
Oct 09 08:52:45 AM UTC 24 |
Oct 09 09:14:41 AM UTC 24 |
11249008102 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1122743157 |
|
|
Oct 09 09:14:40 AM UTC 24 |
Oct 09 09:14:47 AM UTC 24 |
1324821974 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.1794709960 |
|
|
Oct 09 09:13:36 AM UTC 24 |
Oct 09 09:14:48 AM UTC 24 |
2589209268 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2163417311 |
|
|
Oct 09 09:14:42 AM UTC 24 |
Oct 09 09:14:50 AM UTC 24 |
966076092 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_readback_err.429763863 |
|
|
Oct 09 09:14:49 AM UTC 24 |
Oct 09 09:14:52 AM UTC 24 |
121551185 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2833743090 |
|
|
Oct 09 09:14:52 AM UTC 24 |
Oct 09 09:14:54 AM UTC 24 |
15346406 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2987001729 |
|
|
Oct 09 09:13:49 AM UTC 24 |
Oct 09 09:15:15 AM UTC 24 |
2841377318 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.528583800 |
|
|
Oct 09 09:13:00 AM UTC 24 |
Oct 09 09:15:22 AM UTC 24 |
12163660168 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.642569315 |
|
|
Oct 09 09:14:21 AM UTC 24 |
Oct 09 09:15:30 AM UTC 24 |
270388831 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.683412810 |
|
|
Oct 09 09:12:04 AM UTC 24 |
Oct 09 09:15:45 AM UTC 24 |
1636358706 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.1125794896 |
|
|
Oct 09 09:14:55 AM UTC 24 |
Oct 09 09:15:53 AM UTC 24 |
901289256 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3793754161 |
|
|
Oct 09 09:15:46 AM UTC 24 |
Oct 09 09:15:55 AM UTC 24 |
294213908 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.901925931 |
|
|
Oct 09 09:14:30 AM UTC 24 |
Oct 09 09:16:07 AM UTC 24 |
2641891993 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2207238938 |
|
|
Oct 09 09:15:23 AM UTC 24 |
Oct 09 09:16:15 AM UTC 24 |
2737217039 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.285419101 |
|
|
Oct 09 09:16:16 AM UTC 24 |
Oct 09 09:16:23 AM UTC 24 |
2717251604 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3832317697 |
|
|
Oct 09 09:01:44 AM UTC 24 |
Oct 09 09:16:23 AM UTC 24 |
5648056405 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1976066019 |
|
|
Oct 09 08:58:40 AM UTC 24 |
Oct 09 09:16:23 AM UTC 24 |
12694163674 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.963358950 |
|
|
Oct 09 09:16:24 AM UTC 24 |
Oct 09 09:16:27 AM UTC 24 |
28721081 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3054539346 |
|
|
Oct 09 09:16:27 AM UTC 24 |
Oct 09 09:16:36 AM UTC 24 |
276995631 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2937378851 |
|
|
Oct 09 09:16:37 AM UTC 24 |
Oct 09 09:16:45 AM UTC 24 |
90645794 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2948636739 |
|
|
Oct 09 09:16:46 AM UTC 24 |
Oct 09 09:16:48 AM UTC 24 |
30452663 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.4017891162 |
|
|
Oct 09 09:02:51 AM UTC 24 |
Oct 09 09:16:50 AM UTC 24 |
2382244934 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4001679644 |
|
|
Oct 09 09:14:49 AM UTC 24 |
Oct 09 09:17:06 AM UTC 24 |
1988589786 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.74694538 |
|
|
Oct 09 09:12:42 AM UTC 24 |
Oct 09 09:17:06 AM UTC 24 |
1059113990 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1946987331 |
|
|
Oct 09 09:15:56 AM UTC 24 |
Oct 09 09:17:08 AM UTC 24 |
216106846 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2782409158 |
|
|
Oct 09 09:17:06 AM UTC 24 |
Oct 09 09:17:08 AM UTC 24 |
16829203 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.888028736 |
|
|
Oct 09 09:10:49 AM UTC 24 |
Oct 09 09:17:16 AM UTC 24 |
21042011521 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.3108238201 |
|
|
Oct 09 09:11:28 AM UTC 24 |
Oct 09 09:17:24 AM UTC 24 |
1776251734 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2642101043 |
|
|
Oct 09 09:05:31 AM UTC 24 |
Oct 09 09:17:26 AM UTC 24 |
42760464875 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1565228721 |
|
|
Oct 09 09:10:55 AM UTC 24 |
Oct 09 09:17:35 AM UTC 24 |
13663485848 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1268511511 |
|
|
Oct 09 09:17:25 AM UTC 24 |
Oct 09 09:17:43 AM UTC 24 |
90576026 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1655988113 |
|
|
Oct 09 09:16:08 AM UTC 24 |
Oct 09 09:17:46 AM UTC 24 |
418814150 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3952806476 |
|
|
Oct 09 09:17:46 AM UTC 24 |
Oct 09 09:17:54 AM UTC 24 |
684221574 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3749903384 |
|
|
Oct 09 09:00:40 AM UTC 24 |
Oct 09 09:17:57 AM UTC 24 |
11102988155 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3129407825 |
|
|
Oct 09 09:17:35 AM UTC 24 |
Oct 09 09:18:12 AM UTC 24 |
101466361 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2995319602 |
|
|
Oct 09 09:17:10 AM UTC 24 |
Oct 09 09:18:24 AM UTC 24 |
1069158027 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1148089080 |
|
|
Oct 09 09:18:25 AM UTC 24 |
Oct 09 09:18:27 AM UTC 24 |
31427805 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3086553308 |
|
|
Oct 09 08:57:19 AM UTC 24 |
Oct 09 09:18:28 AM UTC 24 |
5826808861 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2870258808 |
|
|
Oct 09 09:12:56 AM UTC 24 |
Oct 09 09:18:37 AM UTC 24 |
9149557565 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3530897482 |
|
|
Oct 09 09:18:29 AM UTC 24 |
Oct 09 09:18:39 AM UTC 24 |
1994741108 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_readback_err.845502099 |
|
|
Oct 09 09:18:38 AM UTC 24 |
Oct 09 09:18:41 AM UTC 24 |
37644997 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.659545357 |
|
|
Oct 09 09:18:28 AM UTC 24 |
Oct 09 09:18:42 AM UTC 24 |
3378727231 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.679668066 |
|
|
Oct 09 09:18:43 AM UTC 24 |
Oct 09 09:18:45 AM UTC 24 |
21362716 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.346991248 |
|
|
Oct 09 09:17:44 AM UTC 24 |
Oct 09 09:18:46 AM UTC 24 |
257762575 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.268588509 |
|
|
Oct 09 09:17:07 AM UTC 24 |
Oct 09 09:18:52 AM UTC 24 |
129125905 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.928563587 |
|
|
Oct 09 09:13:43 AM UTC 24 |
Oct 09 09:18:55 AM UTC 24 |
5759720944 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3064477967 |
|
|
Oct 09 09:06:27 AM UTC 24 |
Oct 09 09:19:02 AM UTC 24 |
3735686673 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2646378763 |
|
|
Oct 09 09:18:46 AM UTC 24 |
Oct 09 09:19:06 AM UTC 24 |
243856129 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1362648654 |
|
|
Oct 09 09:16:18 AM UTC 24 |
Oct 09 09:19:08 AM UTC 24 |
458092255 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3144820091 |
|
|
Oct 09 09:13:26 AM UTC 24 |
Oct 09 09:19:08 AM UTC 24 |
3683490963 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1981104413 |
|
|
Oct 09 09:19:07 AM UTC 24 |
Oct 09 09:19:09 AM UTC 24 |
380732533 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.74139984 |
|
|
Oct 09 09:19:08 AM UTC 24 |
Oct 09 09:19:13 AM UTC 24 |
207349414 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3269834487 |
|
|
Oct 09 09:12:11 AM UTC 24 |
Oct 09 09:19:26 AM UTC 24 |
9508053621 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2987075401 |
|
|
Oct 09 09:19:08 AM UTC 24 |
Oct 09 09:19:28 AM UTC 24 |
1810054432 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.125668827 |
|
|
Oct 09 09:19:27 AM UTC 24 |
Oct 09 09:19:30 AM UTC 24 |
31926015 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.323754055 |
|
|
Oct 09 09:13:56 AM UTC 24 |
Oct 09 09:19:31 AM UTC 24 |
43774959107 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_readback_err.1383143360 |
|
|
Oct 09 09:19:32 AM UTC 24 |
Oct 09 09:19:35 AM UTC 24 |
30010656 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3484258001 |
|
|
Oct 09 09:19:31 AM UTC 24 |
Oct 09 09:19:37 AM UTC 24 |
88659464 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.727073128 |
|
|
Oct 09 09:19:29 AM UTC 24 |
Oct 09 09:19:38 AM UTC 24 |
960119751 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.86417321 |
|
|
Oct 09 09:19:39 AM UTC 24 |
Oct 09 09:19:41 AM UTC 24 |
11857592 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1317031934 |
|
|
Oct 09 08:49:46 AM UTC 24 |
Oct 09 09:19:48 AM UTC 24 |
56182305705 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2898758009 |
|
|
Oct 09 09:18:40 AM UTC 24 |
Oct 09 09:19:51 AM UTC 24 |
7805857475 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.58306364 |
|
|
Oct 09 09:19:42 AM UTC 24 |
Oct 09 09:19:52 AM UTC 24 |
358567436 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3175809474 |
|
|
Oct 09 09:18:57 AM UTC 24 |
Oct 09 09:20:01 AM UTC 24 |
508102166 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.2200881283 |
|
|
Oct 09 09:09:34 AM UTC 24 |
Oct 09 09:20:02 AM UTC 24 |
13245660004 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2325292991 |
|
|
Oct 09 09:20:02 AM UTC 24 |
Oct 09 09:20:08 AM UTC 24 |
212892420 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2117091092 |
|
|
Oct 09 09:19:52 AM UTC 24 |
Oct 09 09:20:16 AM UTC 24 |
3866788594 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.363418800 |
|
|
Oct 09 09:06:34 AM UTC 24 |
Oct 09 09:20:16 AM UTC 24 |
69616892991 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3347738809 |
|
|
Oct 09 09:18:52 AM UTC 24 |
Oct 09 09:20:19 AM UTC 24 |
8618455798 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2409535956 |
|
|
Oct 09 09:01:26 AM UTC 24 |
Oct 09 09:20:20 AM UTC 24 |
6556640990 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3085414729 |
|
|
Oct 09 09:20:17 AM UTC 24 |
Oct 09 09:20:22 AM UTC 24 |
154382891 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.418725205 |
|
|
Oct 09 09:20:23 AM UTC 24 |
Oct 09 09:20:25 AM UTC 24 |
150146389 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.630551901 |
|
|
Oct 09 09:20:26 AM UTC 24 |
Oct 09 09:20:35 AM UTC 24 |
1245850270 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3878352115 |
|
|
Oct 09 09:11:10 AM UTC 24 |
Oct 09 09:20:38 AM UTC 24 |
3011060788 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.987261497 |
|
|
Oct 09 08:52:47 AM UTC 24 |
Oct 09 09:20:40 AM UTC 24 |
60950450843 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_readback_err.2587586028 |
|
|
Oct 09 09:20:39 AM UTC 24 |
Oct 09 09:20:42 AM UTC 24 |
83715575 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3472452882 |
|
|
Oct 09 09:20:06 AM UTC 24 |
Oct 09 09:20:43 AM UTC 24 |
351183169 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.407601813 |
|
|
Oct 09 09:20:36 AM UTC 24 |
Oct 09 09:20:44 AM UTC 24 |
151051234 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2899070897 |
|
|
Oct 09 09:15:32 AM UTC 24 |
Oct 09 09:20:44 AM UTC 24 |
6907450466 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2717997679 |
|
|
Oct 09 09:20:44 AM UTC 24 |
Oct 09 09:20:47 AM UTC 24 |
54450935 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2986551755 |
|
|
Oct 09 08:56:31 AM UTC 24 |
Oct 09 09:21:01 AM UTC 24 |
3642458682 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2671157346 |
|
|
Oct 09 09:20:09 AM UTC 24 |
Oct 09 09:21:33 AM UTC 24 |
182145961 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3318117925 |
|
|
Oct 09 09:09:35 AM UTC 24 |
Oct 09 09:21:37 AM UTC 24 |
29427469098 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1979504386 |
|
|
Oct 09 09:20:20 AM UTC 24 |
Oct 09 09:21:47 AM UTC 24 |
16339413367 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.2341137520 |
|
|
Oct 09 09:20:46 AM UTC 24 |
Oct 09 09:21:48 AM UTC 24 |
3077026278 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2136231121 |
|
|
Oct 09 09:15:53 AM UTC 24 |
Oct 09 09:21:50 AM UTC 24 |
17535145356 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.4177242258 |
|
|
Oct 09 09:21:51 AM UTC 24 |
Oct 09 09:21:54 AM UTC 24 |
121957050 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2088967610 |
|
|
Oct 09 09:21:49 AM UTC 24 |
Oct 09 09:21:59 AM UTC 24 |
269199176 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.763595942 |
|
|
Oct 09 09:11:55 AM UTC 24 |
Oct 09 09:22:02 AM UTC 24 |
26788735212 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3387532579 |
|
|
Oct 09 09:20:48 AM UTC 24 |
Oct 09 09:22:02 AM UTC 24 |
29026144194 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3921730012 |
|
|
Oct 09 09:22:03 AM UTC 24 |
Oct 09 09:22:05 AM UTC 24 |
136397928 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4013892293 |
|
|
Oct 09 09:21:34 AM UTC 24 |
Oct 09 09:22:08 AM UTC 24 |
1933964001 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_readback_err.2928001539 |
|
|
Oct 09 09:22:09 AM UTC 24 |
Oct 09 09:22:11 AM UTC 24 |
189887734 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.475743085 |
|
|
Oct 09 09:22:03 AM UTC 24 |
Oct 09 09:22:16 AM UTC 24 |
1774422860 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1865579903 |
|
|
Oct 09 09:22:06 AM UTC 24 |
Oct 09 09:22:17 AM UTC 24 |
339230732 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2334911724 |
|
|
Oct 09 09:14:23 AM UTC 24 |
Oct 09 09:22:18 AM UTC 24 |
2307300445 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4040446595 |
|
|
Oct 09 09:22:18 AM UTC 24 |
Oct 09 09:22:20 AM UTC 24 |
41039086 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.47130437 |
|
|
Oct 09 09:22:19 AM UTC 24 |
Oct 09 09:22:26 AM UTC 24 |
722596712 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1000263304 |
|
|
Oct 09 09:21:47 AM UTC 24 |
Oct 09 09:22:36 AM UTC 24 |
393320134 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2600242900 |
|
|
Oct 09 09:12:00 AM UTC 24 |
Oct 09 09:22:36 AM UTC 24 |
6166487573 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.555188831 |
|
|
Oct 09 09:20:46 AM UTC 24 |
Oct 09 09:22:39 AM UTC 24 |
1907789094 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.3059226189 |
|
|
Oct 09 09:22:37 AM UTC 24 |
Oct 09 09:22:49 AM UTC 24 |
253144074 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1833830118 |
|
|
Oct 09 09:00:41 AM UTC 24 |
Oct 09 09:23:07 AM UTC 24 |
37642019922 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.211043656 |
|
|
Oct 09 09:18:47 AM UTC 24 |
Oct 09 09:23:17 AM UTC 24 |
3657670843 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1535148010 |
|
|
Oct 09 09:23:13 AM UTC 24 |
Oct 09 09:23:25 AM UTC 24 |
1676075659 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.563377028 |
|
|
Oct 09 09:17:17 AM UTC 24 |
Oct 09 09:23:37 AM UTC 24 |
3795909199 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.101426426 |
|
|
Oct 09 09:18:53 AM UTC 24 |
Oct 09 09:23:46 AM UTC 24 |
2833486628 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3528332325 |
|
|
Oct 09 09:17:27 AM UTC 24 |
Oct 09 09:23:48 AM UTC 24 |
12835672500 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.4147168290 |
|
|
Oct 09 09:23:47 AM UTC 24 |
Oct 09 09:23:49 AM UTC 24 |
43021376 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1919485146 |
|
|
Oct 09 08:59:25 AM UTC 24 |
Oct 09 09:23:50 AM UTC 24 |
72158583317 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_readback_err.767133333 |
|
|
Oct 09 09:23:51 AM UTC 24 |
Oct 09 09:23:53 AM UTC 24 |
29212102 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.1979557157 |
|
|
Oct 09 09:23:51 AM UTC 24 |
Oct 09 09:23:56 AM UTC 24 |
96027268 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2904666026 |
|
|
Oct 09 09:23:50 AM UTC 24 |
Oct 09 09:24:09 AM UTC 24 |
4753738851 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4287339121 |
|
|
Oct 09 09:24:09 AM UTC 24 |
Oct 09 09:24:11 AM UTC 24 |
46150597 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2379628520 |
|
|
Oct 09 09:22:50 AM UTC 24 |
Oct 09 09:24:11 AM UTC 24 |
139304625 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2336486646 |
|
|
Oct 09 09:22:27 AM UTC 24 |
Oct 09 09:24:24 AM UTC 24 |
16695200693 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1762206453 |
|
|
Oct 09 09:23:12 AM UTC 24 |
Oct 09 09:24:25 AM UTC 24 |
136886288 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3401981713 |
|
|
Oct 09 09:24:12 AM UTC 24 |
Oct 09 09:24:31 AM UTC 24 |
2293545919 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.613700332 |
|
|
Oct 09 09:14:27 AM UTC 24 |
Oct 09 09:24:35 AM UTC 24 |
6751377310 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3325653766 |
|
|
Oct 09 08:51:42 AM UTC 24 |
Oct 09 09:24:48 AM UTC 24 |
60318398389 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.37847493 |
|
|
Oct 09 09:19:53 AM UTC 24 |
Oct 09 09:24:59 AM UTC 24 |
3849588046 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.45026245 |
|
|
Oct 09 09:23:54 AM UTC 24 |
Oct 09 09:25:11 AM UTC 24 |
2693990411 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2983218468 |
|
|
Oct 09 09:25:13 AM UTC 24 |
Oct 09 09:25:18 AM UTC 24 |
253687605 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.544905426 |
|
|
Oct 09 09:24:48 AM UTC 24 |
Oct 09 09:25:26 AM UTC 24 |
96773170 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1764034076 |
|
|
Oct 09 09:24:25 AM UTC 24 |
Oct 09 09:25:30 AM UTC 24 |
23243942546 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4049441558 |
|
|
Oct 09 09:19:36 AM UTC 24 |
Oct 09 09:25:31 AM UTC 24 |
2303965915 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1824110943 |
|
|
Oct 09 09:25:32 AM UTC 24 |
Oct 09 09:25:34 AM UTC 24 |
118906411 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.821866482 |
|
|
Oct 09 09:21:02 AM UTC 24 |
Oct 09 09:25:36 AM UTC 24 |
2594636510 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1855575344 |
|
|
Oct 09 09:25:36 AM UTC 24 |
Oct 09 09:25:42 AM UTC 24 |
109446299 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3158202568 |
|
|
Oct 09 09:25:43 AM UTC 24 |
Oct 09 09:25:46 AM UTC 24 |
47961319 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1372970216 |
|
|
Oct 09 09:25:35 AM UTC 24 |
Oct 09 09:25:52 AM UTC 24 |
1677395007 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1996003818 |
|
|
Oct 09 09:25:00 AM UTC 24 |
Oct 09 09:26:20 AM UTC 24 |
558232573 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4007909257 |
|
|
Oct 09 09:24:32 AM UTC 24 |
Oct 09 09:26:20 AM UTC 24 |
1933056162 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3521210016 |
|
|
Oct 09 09:26:21 AM UTC 24 |
Oct 09 09:26:23 AM UTC 24 |
15846886 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3162197377 |
|
|
Oct 09 09:22:40 AM UTC 24 |
Oct 09 09:26:38 AM UTC 24 |
12203091397 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.4045288151 |
|
|
Oct 09 09:19:11 AM UTC 24 |
Oct 09 09:26:40 AM UTC 24 |
32966824346 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1187417820 |
|
|
Oct 09 09:26:21 AM UTC 24 |
Oct 09 09:26:49 AM UTC 24 |
1977284205 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.854245781 |
|
|
Oct 09 09:16:24 AM UTC 24 |
Oct 09 09:26:49 AM UTC 24 |
4459365394 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.4134238187 |
|
|
Oct 09 09:20:17 AM UTC 24 |
Oct 09 09:26:49 AM UTC 24 |
9865945156 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1087592613 |
|
|
Oct 09 09:26:50 AM UTC 24 |
Oct 09 09:27:14 AM UTC 24 |
400269559 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3140241811 |
|
|
Oct 09 09:27:15 AM UTC 24 |
Oct 09 09:27:21 AM UTC 24 |
187490559 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1414773699 |
|
|
Oct 09 09:20:03 AM UTC 24 |
Oct 09 09:27:22 AM UTC 24 |
17644526013 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2767083406 |
|
|
Oct 09 09:26:50 AM UTC 24 |
Oct 09 09:27:30 AM UTC 24 |
426365106 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3164920638 |
|
|
Oct 09 09:01:27 AM UTC 24 |
Oct 09 09:27:31 AM UTC 24 |
34047247724 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3234340652 |
|
|
Oct 09 09:27:32 AM UTC 24 |
Oct 09 09:27:35 AM UTC 24 |
85032808 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1423035360 |
|
|
Oct 09 09:17:55 AM UTC 24 |
Oct 09 09:27:35 AM UTC 24 |
1415951006 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2436638802 |
|
|
Oct 09 09:19:03 AM UTC 24 |
Oct 09 09:27:38 AM UTC 24 |
32548384331 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2921336478 |
|
|
Oct 09 09:27:39 AM UTC 24 |
Oct 09 09:27:41 AM UTC 24 |
32423882 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.49659654 |
|
|
Oct 09 09:27:35 AM UTC 24 |
Oct 09 09:27:42 AM UTC 24 |
727579874 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4245123314 |
|
|
Oct 09 09:11:56 AM UTC 24 |
Oct 09 09:27:49 AM UTC 24 |
4359967167 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.4054964759 |
|
|
Oct 09 09:27:35 AM UTC 24 |
Oct 09 09:27:51 AM UTC 24 |
8732803289 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1797509091 |
|
|
Oct 09 09:27:50 AM UTC 24 |
Oct 09 09:27:52 AM UTC 24 |
23495569 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.3792983790 |
|
|
Oct 09 09:27:52 AM UTC 24 |
Oct 09 09:27:55 AM UTC 24 |
161024870 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1281904747 |
|
|
Oct 09 09:26:39 AM UTC 24 |
Oct 09 09:28:08 AM UTC 24 |
11554818568 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1951502359 |
|
|
Oct 09 09:22:37 AM UTC 24 |
Oct 09 09:28:24 AM UTC 24 |
6176257558 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1534523682 |
|
|
Oct 09 09:21:38 AM UTC 24 |
Oct 09 09:28:29 AM UTC 24 |
4640544571 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.4126424281 |
|
|
Oct 09 09:27:56 AM UTC 24 |
Oct 09 09:28:31 AM UTC 24 |
642361563 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.123899643 |
|
|
Oct 09 09:28:32 AM UTC 24 |
Oct 09 09:28:38 AM UTC 24 |
81714284 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2511877462 |
|
|
Oct 09 09:28:25 AM UTC 24 |
Oct 09 09:28:40 AM UTC 24 |
2527637429 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2198668936 |
|
|
Oct 09 09:27:14 AM UTC 24 |
Oct 09 09:28:42 AM UTC 24 |
1823058937 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2930445698 |
|
|
Oct 09 09:24:26 AM UTC 24 |
Oct 09 09:28:48 AM UTC 24 |
1974414760 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3968116235 |
|
|
Oct 09 09:28:41 AM UTC 24 |
Oct 09 09:28:49 AM UTC 24 |
336012504 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.231948658 |
|
|
Oct 09 09:28:39 AM UTC 24 |
Oct 09 09:28:52 AM UTC 24 |
518770501 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1197526685 |
|
|
Oct 09 09:28:53 AM UTC 24 |
Oct 09 09:28:55 AM UTC 24 |
27547186 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1381306505 |
|
|
Oct 09 09:28:56 AM UTC 24 |
Oct 09 09:29:09 AM UTC 24 |
3431568592 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3213877 |
|
|
Oct 09 09:29:10 AM UTC 24 |
Oct 09 09:29:15 AM UTC 24 |
229049189 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_readback_err.1721215955 |
|
|
Oct 09 09:29:16 AM UTC 24 |
Oct 09 09:29:19 AM UTC 24 |
32011460 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3474389689 |
|
|
Oct 09 09:27:43 AM UTC 24 |
Oct 09 09:30:29 AM UTC 24 |
1404670706 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.73002916 |
|
|
Oct 09 09:15:16 AM UTC 24 |
Oct 09 09:30:57 AM UTC 24 |
18723488211 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2505765458 |
|
|
Oct 09 09:30:58 AM UTC 24 |
Oct 09 09:31:00 AM UTC 24 |
16259094 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2428114567 |
|
|
Oct 09 09:29:19 AM UTC 24 |
Oct 09 09:31:02 AM UTC 24 |
2609114654 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2061424290 |
|
|
Oct 09 09:26:41 AM UTC 24 |
Oct 09 09:31:07 AM UTC 24 |
8572661561 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4175991936 |
|
|
Oct 09 09:16:49 AM UTC 24 |
Oct 09 09:31:12 AM UTC 24 |
2998049314 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.262315080 |
|
|
Oct 09 09:31:01 AM UTC 24 |
Oct 09 09:31:17 AM UTC 24 |
2738073369 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2994940485 |
|
|
Oct 09 09:31:19 AM UTC 24 |
Oct 09 09:31:38 AM UTC 24 |
2745762348 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4181334842 |
|
|
Oct 09 09:22:13 AM UTC 24 |
Oct 09 09:31:43 AM UTC 24 |
1954626246 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1378346301 |
|
|
Oct 09 09:24:36 AM UTC 24 |
Oct 09 09:31:51 AM UTC 24 |
5493535544 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.491995936 |
|
|
Oct 09 09:04:54 AM UTC 24 |
Oct 09 09:31:52 AM UTC 24 |
4243297115 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2623953447 |
|
|
Oct 09 09:31:53 AM UTC 24 |
Oct 09 09:32:03 AM UTC 24 |
1656723762 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.2355738799 |
|
|
Oct 09 09:22:02 AM UTC 24 |
Oct 09 09:32:15 AM UTC 24 |
1830242628 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.3657361573 |
|
|
Oct 09 09:17:59 AM UTC 24 |
Oct 09 09:32:16 AM UTC 24 |
6419947158 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1648573589 |
|
|
Oct 09 09:31:52 AM UTC 24 |
Oct 09 09:32:20 AM UTC 24 |
344860469 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3220445332 |
|
|
Oct 09 09:32:21 AM UTC 24 |
Oct 09 09:32:23 AM UTC 24 |
43010873 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.996003482 |
|
|
Oct 09 09:31:44 AM UTC 24 |
Oct 09 09:32:26 AM UTC 24 |
101996971 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.1191826373 |
|
|
Oct 09 09:31:08 AM UTC 24 |
Oct 09 09:32:27 AM UTC 24 |
12739798467 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_readback_err.681999691 |
|
|
Oct 09 09:32:28 AM UTC 24 |
Oct 09 09:32:31 AM UTC 24 |
108297178 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2364388652 |
|
|
Oct 09 09:32:26 AM UTC 24 |
Oct 09 09:32:31 AM UTC 24 |
240320499 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3434545870 |
|
|
Oct 09 09:32:24 AM UTC 24 |
Oct 09 09:32:33 AM UTC 24 |
234344688 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1712157014 |
|
|
Oct 09 09:32:35 AM UTC 24 |
Oct 09 09:32:37 AM UTC 24 |
32891866 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3146451659 |
|
|
Oct 09 09:26:50 AM UTC 24 |
Oct 09 09:32:45 AM UTC 24 |
29342185098 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1773349025 |
|
|
Oct 09 09:20:19 AM UTC 24 |
Oct 09 09:32:46 AM UTC 24 |
8520401512 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2985878915 |
|
|
Oct 09 09:32:47 AM UTC 24 |
Oct 09 09:32:50 AM UTC 24 |
63978927 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.722147954 |
|
|
Oct 09 09:27:23 AM UTC 24 |
Oct 09 09:32:55 AM UTC 24 |
9636831282 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2249827162 |
|
|
Oct 09 09:32:57 AM UTC 24 |
Oct 09 09:33:07 AM UTC 24 |
157748553 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.326022000 |
|
|
Oct 09 09:25:28 AM UTC 24 |
Oct 09 09:33:29 AM UTC 24 |
5546174356 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3579504432 |
|
|
Oct 09 09:28:09 AM UTC 24 |
Oct 09 09:33:34 AM UTC 24 |
6031260877 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2976284648 |
|
|
Oct 09 09:19:09 AM UTC 24 |
Oct 09 09:33:37 AM UTC 24 |
3761216821 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3051706368 |
|
|
Oct 09 09:33:35 AM UTC 24 |
Oct 09 09:33:43 AM UTC 24 |
2529139686 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.950079579 |
|
|
Oct 09 09:11:12 AM UTC 24 |
Oct 09 09:33:43 AM UTC 24 |
44895267728 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1755917758 |
|
|
Oct 09 09:33:30 AM UTC 24 |
Oct 09 09:33:44 AM UTC 24 |
297280860 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3605401728 |
|
|
Oct 09 09:06:49 AM UTC 24 |
Oct 09 09:33:47 AM UTC 24 |
86649394148 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.211011033 |
|
|
Oct 09 09:33:45 AM UTC 24 |
Oct 09 09:33:48 AM UTC 24 |
44150601 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.4063379032 |
|
|
Oct 09 09:33:48 AM UTC 24 |
Oct 09 09:33:56 AM UTC 24 |
977582353 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.4129796500 |
|
|
Oct 09 09:33:49 AM UTC 24 |
Oct 09 09:33:57 AM UTC 24 |
167185955 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_readback_err.1103407066 |
|
|
Oct 09 09:33:57 AM UTC 24 |
Oct 09 09:33:59 AM UTC 24 |
33576862 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.2753822789 |
|
|
Oct 09 09:32:47 AM UTC 24 |
Oct 09 09:34:02 AM UTC 24 |
13365952190 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.4244537985 |
|
|
Oct 09 09:34:03 AM UTC 24 |
Oct 09 09:34:05 AM UTC 24 |
44322803 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.926041343 |
|
|
Oct 09 09:33:58 AM UTC 24 |
Oct 09 09:34:09 AM UTC 24 |
422888363 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.2213387049 |
|
|
Oct 09 09:34:06 AM UTC 24 |
Oct 09 09:34:10 AM UTC 24 |
62896382 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3959384418 |
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|
Oct 09 09:33:08 AM UTC 24 |
Oct 09 09:34:31 AM UTC 24 |
562151325 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1056526720 |
|
|
Oct 09 09:21:55 AM UTC 24 |
Oct 09 09:34:35 AM UTC 24 |
14976891373 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.431692795 |
|
|
Oct 09 09:34:32 AM UTC 24 |
Oct 09 09:34:36 AM UTC 24 |
95204478 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3355829415 |
|
|
Oct 09 09:22:21 AM UTC 24 |
Oct 09 09:34:51 AM UTC 24 |
40676871592 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1219130842 |
|
|
Oct 09 09:05:15 AM UTC 24 |
Oct 09 09:34:56 AM UTC 24 |
138093419501 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2186969434 |
|
|
Oct 09 09:34:57 AM UTC 24 |
Oct 09 09:35:08 AM UTC 24 |
5509712811 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.2819240650 |
|
|
Oct 09 09:22:00 AM UTC 24 |
Oct 09 09:35:08 AM UTC 24 |
5282325672 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3207233700 |
|
|
Oct 09 09:34:11 AM UTC 24 |
Oct 09 09:35:11 AM UTC 24 |
6299432607 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2016001156 |
|
|
Oct 09 09:34:37 AM UTC 24 |
Oct 09 09:35:23 AM UTC 24 |
120698903 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.3221354395 |
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|
Oct 09 09:16:24 AM UTC 24 |
Oct 09 09:35:26 AM UTC 24 |
2680194829 ps |