| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 98.63 | 99.48 | 96.05 | 99.72 | 100.00 | 97.29 | 99.12 | 98.72 |
| T83 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2586299687 | Oct 09 10:08:49 AM UTC 24 | Oct 09 10:08:51 AM UTC 24 | 35316593 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3224393114 | Oct 09 10:08:48 AM UTC 24 | Oct 09 10:08:53 AM UTC 24 | 1678354022 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3470276286 | Oct 09 10:08:52 AM UTC 24 | Oct 09 10:08:54 AM UTC 24 | 14605279 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.80495773 | Oct 09 10:08:52 AM UTC 24 | Oct 09 10:08:54 AM UTC 24 | 88434874 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2431723707 | Oct 09 10:08:48 AM UTC 24 | Oct 09 10:08:55 AM UTC 24 | 771406413 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1301066301 | Oct 09 10:08:48 AM UTC 24 | Oct 09 10:08:55 AM UTC 24 | 255072663 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3505954476 | Oct 09 10:08:52 AM UTC 24 | Oct 09 10:08:56 AM UTC 24 | 749430901 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2186408393 | Oct 09 10:08:54 AM UTC 24 | Oct 09 10:08:56 AM UTC 24 | 30091403 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3145133267 | Oct 09 10:08:54 AM UTC 24 | Oct 09 10:08:56 AM UTC 24 | 92368076 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1537635487 | Oct 09 10:08:52 AM UTC 24 | Oct 09 10:08:57 AM UTC 24 | 76356418 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.150229233 | Oct 09 10:08:55 AM UTC 24 | Oct 09 10:08:59 AM UTC 24 | 180821543 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.842040611 | Oct 09 10:08:57 AM UTC 24 | Oct 09 10:08:59 AM UTC 24 | 12415252 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4246585402 | Oct 09 10:08:57 AM UTC 24 | Oct 09 10:08:59 AM UTC 24 | 34884279 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2054520055 | Oct 09 10:08:57 AM UTC 24 | Oct 09 10:09:00 AM UTC 24 | 127710264 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2679807247 | Oct 09 10:08:57 AM UTC 24 | Oct 09 10:09:01 AM UTC 24 | 106116310 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2844233109 | Oct 09 10:09:00 AM UTC 24 | Oct 09 10:09:02 AM UTC 24 | 47346056 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2979816837 | Oct 09 10:09:00 AM UTC 24 | Oct 09 10:09:02 AM UTC 24 | 22692881 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.758702918 | Oct 09 10:08:57 AM UTC 24 | Oct 09 10:09:02 AM UTC 24 | 663690960 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.899897518 | Oct 09 10:09:00 AM UTC 24 | Oct 09 10:09:03 AM UTC 24 | 1133967317 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4116020240 | Oct 09 10:08:57 AM UTC 24 | Oct 09 10:09:03 AM UTC 24 | 1601775564 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2882855980 | Oct 09 10:08:58 AM UTC 24 | Oct 09 10:09:04 AM UTC 24 | 214339333 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3146535365 | Oct 09 10:09:01 AM UTC 24 | Oct 09 10:09:05 AM UTC 24 | 834308031 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1619213585 | Oct 09 10:08:58 AM UTC 24 | Oct 09 10:09:05 AM UTC 24 | 1754644043 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3169597383 | Oct 09 10:09:01 AM UTC 24 | Oct 09 10:09:05 AM UTC 24 | 146616744 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1860425736 | Oct 09 10:09:04 AM UTC 24 | Oct 09 10:09:06 AM UTC 24 | 12559845 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4020193820 | Oct 09 10:09:02 AM UTC 24 | Oct 09 10:09:06 AM UTC 24 | 437139954 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4166468318 | Oct 09 10:09:04 AM UTC 24 | Oct 09 10:09:06 AM UTC 24 | 51198966 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2513092557 | Oct 09 10:09:04 AM UTC 24 | Oct 09 10:09:07 AM UTC 24 | 53980252 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1011855424 | Oct 09 10:09:02 AM UTC 24 | Oct 09 10:09:08 AM UTC 24 | 141889607 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3011743904 | Oct 09 10:09:06 AM UTC 24 | Oct 09 10:09:08 AM UTC 24 | 39844733 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2883673169 | Oct 09 10:09:06 AM UTC 24 | Oct 09 10:09:08 AM UTC 24 | 32010739 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3531150138 | Oct 09 10:09:05 AM UTC 24 | Oct 09 10:09:09 AM UTC 24 | 399175625 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2944545956 | Oct 09 10:09:06 AM UTC 24 | Oct 09 10:09:09 AM UTC 24 | 74315208 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2572465263 | Oct 09 10:09:06 AM UTC 24 | Oct 09 10:09:10 AM UTC 24 | 71134825 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1356721754 | Oct 09 10:09:09 AM UTC 24 | Oct 09 10:09:11 AM UTC 24 | 20050125 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2132839680 | Oct 09 10:09:10 AM UTC 24 | Oct 09 10:09:12 AM UTC 24 | 26251956 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1943800288 | Oct 09 10:09:06 AM UTC 24 | Oct 09 10:09:12 AM UTC 24 | 122446302 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1416279409 | Oct 09 10:09:10 AM UTC 24 | Oct 09 10:09:13 AM UTC 24 | 80466298 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1439300645 | Oct 09 10:09:07 AM UTC 24 | Oct 09 10:09:13 AM UTC 24 | 1802583098 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2447440868 | Oct 09 10:09:09 AM UTC 24 | Oct 09 10:09:14 AM UTC 24 | 199480869 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.189716602 | Oct 09 10:09:12 AM UTC 24 | Oct 09 10:09:14 AM UTC 24 | 60384908 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1114899077 | Oct 09 10:09:12 AM UTC 24 | Oct 09 10:09:14 AM UTC 24 | 54991760 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3108259479 | Oct 09 10:09:11 AM UTC 24 | Oct 09 10:09:15 AM UTC 24 | 860524744 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3445105138 | Oct 09 10:09:11 AM UTC 24 | Oct 09 10:09:15 AM UTC 24 | 307631692 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.249248726 | Oct 09 10:09:11 AM UTC 24 | Oct 09 10:09:16 AM UTC 24 | 217860970 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1952976628 | Oct 09 10:09:08 AM UTC 24 | Oct 09 10:09:17 AM UTC 24 | 293215706 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3526589100 | Oct 09 10:09:14 AM UTC 24 | Oct 09 10:09:17 AM UTC 24 | 115356138 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2439233452 | Oct 09 10:09:14 AM UTC 24 | Oct 09 10:09:18 AM UTC 24 | 209476813 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1019198960 | Oct 09 10:09:14 AM UTC 24 | Oct 09 10:09:18 AM UTC 24 | 397621175 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2058264933 | Oct 09 10:09:15 AM UTC 24 | Oct 09 10:09:20 AM UTC 24 | 36013990 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.376629611 | Oct 09 10:09:15 AM UTC 24 | Oct 09 10:09:20 AM UTC 24 | 22136743 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.143118171 | Oct 09 10:09:18 AM UTC 24 | Oct 09 10:09:21 AM UTC 24 | 55228584 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3017595652 | Oct 09 10:09:18 AM UTC 24 | Oct 09 10:09:22 AM UTC 24 | 199791601 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3345406147 | Oct 09 10:09:20 AM UTC 24 | Oct 09 10:09:22 AM UTC 24 | 39239512 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1474239918 | Oct 09 10:09:15 AM UTC 24 | Oct 09 10:09:22 AM UTC 24 | 323082285 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3630975198 | Oct 09 10:09:20 AM UTC 24 | Oct 09 10:09:22 AM UTC 24 | 41096525 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1704322004 | Oct 09 10:09:16 AM UTC 24 | Oct 09 10:09:22 AM UTC 24 | 21851932 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.35605519 | Oct 09 10:09:20 AM UTC 24 | Oct 09 10:09:23 AM UTC 24 | 118274273 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3929060035 | Oct 09 10:09:22 AM UTC 24 | Oct 09 10:09:24 AM UTC 24 | 18736783 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2888834899 | Oct 09 10:09:16 AM UTC 24 | Oct 09 10:09:25 AM UTC 24 | 455307032 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.657452291 | Oct 09 10:09:20 AM UTC 24 | Oct 09 10:09:26 AM UTC 24 | 2566631784 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.401782892 | Oct 09 10:09:23 AM UTC 24 | Oct 09 10:09:26 AM UTC 24 | 75476698 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4103738831 | Oct 09 10:09:24 AM UTC 24 | Oct 09 10:09:27 AM UTC 24 | 18025457 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1592328343 | Oct 09 10:09:24 AM UTC 24 | Oct 09 10:09:27 AM UTC 24 | 35404746 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3227799461 | Oct 09 10:09:20 AM UTC 24 | Oct 09 10:09:27 AM UTC 24 | 464559757 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4114318858 | Oct 09 10:09:20 AM UTC 24 | Oct 09 10:09:28 AM UTC 24 | 3816231618 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2171148523 | Oct 09 10:09:23 AM UTC 24 | Oct 09 10:09:30 AM UTC 24 | 5239510459 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3187124066 | Oct 09 10:09:24 AM UTC 24 | Oct 09 10:09:30 AM UTC 24 | 469590602 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1884937141 | Oct 09 10:09:28 AM UTC 24 | Oct 09 10:09:30 AM UTC 24 | 12909030 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1751355562 | Oct 09 10:09:28 AM UTC 24 | Oct 09 10:09:30 AM UTC 24 | 55676885 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3536188705 | Oct 09 10:09:27 AM UTC 24 | Oct 09 10:09:30 AM UTC 24 | 304674598 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2347808683 | Oct 09 10:09:23 AM UTC 24 | Oct 09 10:09:31 AM UTC 24 | 244752488 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.776951989 | Oct 09 10:09:28 AM UTC 24 | Oct 09 10:09:31 AM UTC 24 | 158498147 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.384260280 | Oct 09 10:09:27 AM UTC 24 | Oct 09 10:09:34 AM UTC 24 | 158300017 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.196656149 | Oct 09 10:09:27 AM UTC 24 | Oct 09 10:09:34 AM UTC 24 | 6467077334 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1867469380 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 529891097 ps |
| CPU time | 11.86 seconds |
| Started | Oct 09 08:49:45 AM UTC 24 |
| Finished | Oct 09 08:49:58 AM UTC 24 |
| Peak memory | 222928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867469380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1867469380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.692194487 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1728162617 ps |
| CPU time | 49.35 seconds |
| Started | Oct 09 08:50:01 AM UTC 24 |
| Finished | Oct 09 08:50:52 AM UTC 24 |
| Peak memory | 222988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692194487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.692194487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3458200118 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 866506123 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 08:49:43 AM UTC 24 |
| Finished | Oct 09 08:49:49 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458200118 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.3458200118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.715622790 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 26450729360 ps |
| CPU time | 560.55 seconds |
| Started | Oct 09 08:49:56 AM UTC 24 |
| Finished | Oct 09 08:59:23 AM UTC 24 |
| Peak memory | 369084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715622790 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.715622790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.560671007 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 883167527 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 08:53:13 AM UTC 24 |
| Finished | Oct 09 08:53:18 AM UTC 24 |
| Peak memory | 248396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560671007 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.560671007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2482128323 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2868353381 ps |
| CPU time | 4.15 seconds |
| Started | Oct 09 10:08:45 AM UTC 24 |
| Finished | Oct 09 10:08:51 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24821 28323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in tg_err.2482128323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1091018111 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 11046255942 ps |
| CPU time | 319.49 seconds |
| Started | Oct 09 08:50:11 AM UTC 24 |
| Finished | Oct 09 08:55:35 AM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091018111 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce ss_b2b.1091018111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_readback_err.471986454 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 117165767 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 08:50:01 AM UTC 24 |
| Finished | Oct 09 08:50:03 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471986454 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_readback_err.471986454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.950510568 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 824314569 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 10:08:11 AM UTC 24 |
| Finished | Oct 09 10:08:16 AM UTC 24 |
| Peak memory | 213576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95 0510568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pas sthru_mem_tl_intg_err.950510568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2839901996 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 45759852 ps |
| CPU time | 4.3 seconds |
| Started | Oct 09 08:49:58 AM UTC 24 |
| Finished | Oct 09 08:50:04 AM UTC 24 |
| Peak memory | 223032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839901996 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.2839901996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1344511603 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 203442151535 ps |
| CPU time | 1025.26 seconds |
| Started | Oct 09 08:54:27 AM UTC 24 |
| Finished | Oct 09 09:11:44 AM UTC 24 |
| Peak memory | 379404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344511603 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1344511603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4005205333 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 49109573 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 08:49:44 AM UTC 24 |
| Finished | Oct 09 08:49:46 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005205333 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.4005205333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2636185169 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1246422906 ps |
| CPU time | 365.5 seconds |
| Started | Oct 09 08:59:04 AM UTC 24 |
| Finished | Oct 09 09:05:15 AM UTC 24 |
| Peak memory | 377288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636185169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2636185169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1474239918 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 323082285 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 10:09:15 AM UTC 24 |
| Finished | Oct 09 10:09:22 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14742 39918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i ntg_err.1474239918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2220186186 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6342354139 ps |
| CPU time | 182.76 seconds |
| Started | Oct 09 09:08:21 AM UTC 24 |
| Finished | Oct 09 09:11:26 AM UTC 24 |
| Peak memory | 383568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220186186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2220186186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1976066019 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 12694163674 ps |
| CPU time | 1051.49 seconds |
| Started | Oct 09 08:58:40 AM UTC 24 |
| Finished | Oct 09 09:16:23 AM UTC 24 |
| Peak memory | 383480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976066019 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1976066019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1001987648 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 43856763 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 08:49:45 AM UTC 24 |
| Finished | Oct 09 08:49:47 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001987648 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1001987648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3445105138 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 307631692 ps |
| CPU time | 3.42 seconds |
| Started | Oct 09 10:09:11 AM UTC 24 |
| Finished | Oct 09 10:09:15 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34451 05138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i ntg_err.3445105138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.874711855 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 140558289 ps |
| CPU time | 121.69 seconds |
| Started | Oct 09 08:49:43 AM UTC 24 |
| Finished | Oct 09 08:51:47 AM UTC 24 |
| Peak memory | 379324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 74711855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max_ throughput.874711855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4020193820 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 437139954 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 10:09:02 AM UTC 24 |
| Finished | Oct 09 10:09:06 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40201 93820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_i ntg_err.4020193820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2344947325 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 65399995164 ps |
| CPU time | 459.32 seconds |
| Started | Oct 09 08:49:42 AM UTC 24 |
| Finished | Oct 09 08:57:28 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344947325 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce ss_b2b.2344947325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1714920693 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 10992888692 ps |
| CPU time | 474.92 seconds |
| Started | Oct 09 08:49:45 AM UTC 24 |
| Finished | Oct 09 08:57:45 AM UTC 24 |
| Peak memory | 383492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171492069 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.1714920693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1939170632 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 46202634 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:08:10 AM UTC 24 |
| Finished | Oct 09 10:08:12 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19391706 32 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alia sing.1939170632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.195996836 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 213640965 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 10:08:10 AM UTC 24 |
| Finished | Oct 09 10:08:13 AM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19599683 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_b ash.195996836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3108216818 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 42956274 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:08:07 AM UTC 24 |
| Finished | Oct 09 10:08:09 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31082168 18 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_r eset.3108216818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.96899992 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 106769172 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:08:10 AM UTC 24 |
| Finished | Oct 09 10:08:13 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=96899992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.96899992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2922901823 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 14043572 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:08:07 AM UTC 24 |
| Finished | Oct 09 10:08:09 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922901823 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2922901823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3812903925 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2015918719 ps |
| CPU time | 5.59 seconds |
| Started | Oct 09 10:08:02 AM UTC 24 |
| Finished | Oct 09 10:08:09 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 12903925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pa ssthru_mem_tl_intg_err.3812903925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1096348038 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 74834018 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:08:10 AM UTC 24 |
| Finished | Oct 09 10:08:12 AM UTC 24 |
| Peak memory | 212624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1096348038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c trl_same_csr_outstanding.1096348038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1629534077 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 65250458 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 10:08:05 AM UTC 24 |
| Finished | Oct 09 10:08:09 AM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629534077 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.1629534077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3132494921 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 115589484 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 10:08:07 AM UTC 24 |
| Finished | Oct 09 10:08:10 AM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31324 94921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_in tg_err.3132494921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.715918399 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 51172071 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:08:17 AM UTC 24 |
| Finished | Oct 09 10:08:19 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71591839 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alias ing.715918399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.393970708 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 649345246 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 10:08:17 AM UTC 24 |
| Finished | Oct 09 10:08:21 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39397070 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_b ash.393970708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1838406076 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 27360828 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 10:08:14 AM UTC 24 |
| Finished | Oct 09 10:08:16 AM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18384060 76 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r eset.1838406076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1344829726 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 109982454 ps |
| CPU time | 3.3 seconds |
| Started | Oct 09 10:08:18 AM UTC 24 |
| Finished | Oct 09 10:08:23 AM UTC 24 |
| Peak memory | 226328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1344829726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1344829726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1849754605 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 66990512 ps |
| CPU time | 1 seconds |
| Started | Oct 09 10:08:15 AM UTC 24 |
| Finished | Oct 09 10:08:17 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849754605 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.1849754605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2313004315 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 198038125 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:08:18 AM UTC 24 |
| Finished | Oct 09 10:08:21 AM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2313004315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c trl_same_csr_outstanding.2313004315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1356455355 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 137956249 ps |
| CPU time | 7.01 seconds |
| Started | Oct 09 10:08:14 AM UTC 24 |
| Finished | Oct 09 10:08:22 AM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356455355 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.1356455355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4207395235 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 345193792 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 10:08:14 AM UTC 24 |
| Finished | Oct 09 10:08:18 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42073 95235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_in tg_err.4207395235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3169597383 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 146616744 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:09:01 AM UTC 24 |
| Finished | Oct 09 10:09:05 AM UTC 24 |
| Peak memory | 224296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3169597383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3169597383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2844233109 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 47346056 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 10:09:00 AM UTC 24 |
| Finished | Oct 09 10:09:02 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844233109 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2844233109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1619213585 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 1754644043 ps |
| CPU time | 5.54 seconds |
| Started | Oct 09 10:08:58 AM UTC 24 |
| Finished | Oct 09 10:09:05 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 19213585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p assthru_mem_tl_intg_err.1619213585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2979816837 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 22692881 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:09:00 AM UTC 24 |
| Finished | Oct 09 10:09:02 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2979816837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ ctrl_same_csr_outstanding.2979816837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2882855980 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 214339333 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 10:08:58 AM UTC 24 |
| Finished | Oct 09 10:09:04 AM UTC 24 |
| Peak memory | 213732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882855980 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.2882855980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.899897518 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1133967317 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 10:09:00 AM UTC 24 |
| Finished | Oct 09 10:09:03 AM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89989 7518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_in tg_err.899897518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2513092557 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 53980252 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 10:09:04 AM UTC 24 |
| Finished | Oct 09 10:09:07 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2513092557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2513092557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1860425736 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 12559845 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 10:09:04 AM UTC 24 |
| Finished | Oct 09 10:09:06 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860425736 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.1860425736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3146535365 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 834308031 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 10:09:01 AM UTC 24 |
| Finished | Oct 09 10:09:05 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 46535365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p assthru_mem_tl_intg_err.3146535365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4166468318 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 51198966 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:09:04 AM UTC 24 |
| Finished | Oct 09 10:09:06 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4166468318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ ctrl_same_csr_outstanding.4166468318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1011855424 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 141889607 ps |
| CPU time | 4.68 seconds |
| Started | Oct 09 10:09:02 AM UTC 24 |
| Finished | Oct 09 10:09:08 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011855424 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.1011855424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2572465263 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 71134825 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 10:09:06 AM UTC 24 |
| Finished | Oct 09 10:09:10 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2572465263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2572465263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3011743904 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 39844733 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 10:09:06 AM UTC 24 |
| Finished | Oct 09 10:09:08 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011743904 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.3011743904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3531150138 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 399175625 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 10:09:05 AM UTC 24 |
| Finished | Oct 09 10:09:09 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 31150138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p assthru_mem_tl_intg_err.3531150138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2883673169 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 32010739 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 10:09:06 AM UTC 24 |
| Finished | Oct 09 10:09:08 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2883673169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ ctrl_same_csr_outstanding.2883673169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1943800288 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 122446302 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 10:09:06 AM UTC 24 |
| Finished | Oct 09 10:09:12 AM UTC 24 |
| Peak memory | 224240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943800288 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.1943800288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2944545956 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 74315208 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 10:09:06 AM UTC 24 |
| Finished | Oct 09 10:09:09 AM UTC 24 |
| Peak memory | 222788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29445 45956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i ntg_err.2944545956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1416279409 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 80466298 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 10:09:10 AM UTC 24 |
| Finished | Oct 09 10:09:13 AM UTC 24 |
| Peak memory | 224152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1416279409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1416279409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1356721754 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 20050125 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:09:09 AM UTC 24 |
| Finished | Oct 09 10:09:11 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356721754 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.1356721754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1439300645 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 1802583098 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 10:09:07 AM UTC 24 |
| Finished | Oct 09 10:09:13 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14 39300645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p assthru_mem_tl_intg_err.1439300645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2132839680 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 26251956 ps |
| CPU time | 1 seconds |
| Started | Oct 09 10:09:10 AM UTC 24 |
| Finished | Oct 09 10:09:12 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2132839680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ ctrl_same_csr_outstanding.2132839680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1952976628 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 293215706 ps |
| CPU time | 7.66 seconds |
| Started | Oct 09 10:09:08 AM UTC 24 |
| Finished | Oct 09 10:09:17 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952976628 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.1952976628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2447440868 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 199480869 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 10:09:09 AM UTC 24 |
| Finished | Oct 09 10:09:14 AM UTC 24 |
| Peak memory | 223800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24474 40868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i ntg_err.2447440868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3526589100 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 115356138 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 10:09:14 AM UTC 24 |
| Finished | Oct 09 10:09:17 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3526589100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3526589100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.189716602 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 60384908 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 10:09:12 AM UTC 24 |
| Finished | Oct 09 10:09:14 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189716602 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.189716602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3108259479 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 860524744 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 10:09:11 AM UTC 24 |
| Finished | Oct 09 10:09:15 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 08259479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_p assthru_mem_tl_intg_err.3108259479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1114899077 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 54991760 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:09:12 AM UTC 24 |
| Finished | Oct 09 10:09:14 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1114899077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ ctrl_same_csr_outstanding.1114899077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.249248726 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 217860970 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 10:09:11 AM UTC 24 |
| Finished | Oct 09 10:09:16 AM UTC 24 |
| Peak memory | 213728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249248726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.249248726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2058264933 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 36013990 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:09:15 AM UTC 24 |
| Finished | Oct 09 10:09:20 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058264933 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.2058264933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1019198960 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 397621175 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 10:09:14 AM UTC 24 |
| Finished | Oct 09 10:09:18 AM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10 19198960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p assthru_mem_tl_intg_err.1019198960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.376629611 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 22136743 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:09:15 AM UTC 24 |
| Finished | Oct 09 10:09:20 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=376629611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_c trl_same_csr_outstanding.376629611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2439233452 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 209476813 ps |
| CPU time | 3.05 seconds |
| Started | Oct 09 10:09:14 AM UTC 24 |
| Finished | Oct 09 10:09:18 AM UTC 24 |
| Peak memory | 213744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439233452 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.2439233452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.35605519 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 118274273 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 10:09:20 AM UTC 24 |
| Finished | Oct 09 10:09:23 AM UTC 24 |
| Peak memory | 222844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=35605519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.35605519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.143118171 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 55228584 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 10:09:18 AM UTC 24 |
| Finished | Oct 09 10:09:21 AM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143118171 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.143118171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2888834899 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 455307032 ps |
| CPU time | 5.94 seconds |
| Started | Oct 09 10:09:16 AM UTC 24 |
| Finished | Oct 09 10:09:25 AM UTC 24 |
| Peak memory | 214128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28 88834899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p assthru_mem_tl_intg_err.2888834899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3345406147 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 39239512 ps |
| CPU time | 1 seconds |
| Started | Oct 09 10:09:20 AM UTC 24 |
| Finished | Oct 09 10:09:22 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3345406147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ ctrl_same_csr_outstanding.3345406147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1704322004 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 21851932 ps |
| CPU time | 2.91 seconds |
| Started | Oct 09 10:09:16 AM UTC 24 |
| Finished | Oct 09 10:09:22 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704322004 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.1704322004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3017595652 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 199791601 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 10:09:18 AM UTC 24 |
| Finished | Oct 09 10:09:22 AM UTC 24 |
| Peak memory | 213732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30175 95652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i ntg_err.3017595652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.401782892 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 75476698 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 10:09:23 AM UTC 24 |
| Finished | Oct 09 10:09:26 AM UTC 24 |
| Peak memory | 222780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=401782892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.401782892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3630975198 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 41096525 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 10:09:20 AM UTC 24 |
| Finished | Oct 09 10:09:22 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630975198 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.3630975198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.657452291 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2566631784 ps |
| CPU time | 4.55 seconds |
| Started | Oct 09 10:09:20 AM UTC 24 |
| Finished | Oct 09 10:09:26 AM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65 7452291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_pa ssthru_mem_tl_intg_err.657452291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3929060035 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 18736783 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:09:22 AM UTC 24 |
| Finished | Oct 09 10:09:24 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3929060035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ ctrl_same_csr_outstanding.3929060035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3227799461 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 464559757 ps |
| CPU time | 5.96 seconds |
| Started | Oct 09 10:09:20 AM UTC 24 |
| Finished | Oct 09 10:09:27 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227799461 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.3227799461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4114318858 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3816231618 ps |
| CPU time | 7.02 seconds |
| Started | Oct 09 10:09:20 AM UTC 24 |
| Finished | Oct 09 10:09:28 AM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41143 18858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.4114318858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4103738831 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 18025457 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:09:24 AM UTC 24 |
| Finished | Oct 09 10:09:27 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103738831 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.4103738831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2171148523 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 5239510459 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 10:09:23 AM UTC 24 |
| Finished | Oct 09 10:09:30 AM UTC 24 |
| Peak memory | 214260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 71148523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p assthru_mem_tl_intg_err.2171148523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1592328343 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 35404746 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:09:24 AM UTC 24 |
| Finished | Oct 09 10:09:27 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1592328343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ ctrl_same_csr_outstanding.1592328343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2347808683 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 244752488 ps |
| CPU time | 6.35 seconds |
| Started | Oct 09 10:09:23 AM UTC 24 |
| Finished | Oct 09 10:09:31 AM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347808683 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.2347808683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3187124066 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 469590602 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 10:09:24 AM UTC 24 |
| Finished | Oct 09 10:09:30 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31871 24066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i ntg_err.3187124066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.776951989 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 158498147 ps |
| CPU time | 1.71 seconds |
| Started | Oct 09 10:09:28 AM UTC 24 |
| Finished | Oct 09 10:09:31 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=776951989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.776951989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1884937141 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 12909030 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 10:09:28 AM UTC 24 |
| Finished | Oct 09 10:09:30 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884937141 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.1884937141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.196656149 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 6467077334 ps |
| CPU time | 6.07 seconds |
| Started | Oct 09 10:09:27 AM UTC 24 |
| Finished | Oct 09 10:09:34 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 6656149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_pa ssthru_mem_tl_intg_err.196656149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1751355562 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 55676885 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:09:28 AM UTC 24 |
| Finished | Oct 09 10:09:30 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1751355562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ ctrl_same_csr_outstanding.1751355562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.384260280 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 158300017 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 10:09:27 AM UTC 24 |
| Finished | Oct 09 10:09:34 AM UTC 24 |
| Peak memory | 214064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384260280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.384260280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3536188705 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 304674598 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 10:09:27 AM UTC 24 |
| Finished | Oct 09 10:09:30 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35361 88705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_i ntg_err.3536188705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3484141471 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 23379588 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 10:08:26 AM UTC 24 |
| Finished | Oct 09 10:08:28 AM UTC 24 |
| Peak memory | 212688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34841414 71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alia sing.3484141471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2258063268 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 177967515 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 10:08:24 AM UTC 24 |
| Finished | Oct 09 10:08:27 AM UTC 24 |
| Peak memory | 214012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22580632 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_ bash.2258063268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1217318119 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 30218583 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:08:23 AM UTC 24 |
| Finished | Oct 09 10:08:25 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12173181 19 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r eset.1217318119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4278183688 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 81730478 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 10:08:27 AM UTC 24 |
| Finished | Oct 09 10:08:29 AM UTC 24 |
| Peak memory | 222572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4278183688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.4278183688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2060084308 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 14691782 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:08:23 AM UTC 24 |
| Finished | Oct 09 10:08:25 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060084308 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.2060084308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.763174854 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1200158300 ps |
| CPU time | 5.67 seconds |
| Started | Oct 09 10:08:20 AM UTC 24 |
| Finished | Oct 09 10:08:27 AM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76 3174854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pas sthru_mem_tl_intg_err.763174854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.101503659 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 85981988 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:08:26 AM UTC 24 |
| Finished | Oct 09 10:08:29 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=101503659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ct rl_same_csr_outstanding.101503659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4201398332 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 277405406 ps |
| CPU time | 3.19 seconds |
| Started | Oct 09 10:08:22 AM UTC 24 |
| Finished | Oct 09 10:08:26 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201398332 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.4201398332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.550301026 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 667426115 ps |
| CPU time | 4.6 seconds |
| Started | Oct 09 10:08:23 AM UTC 24 |
| Finished | Oct 09 10:08:29 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55030 1026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_int g_err.550301026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2807541101 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 164444420 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 10:08:34 AM UTC 24 |
| Finished | Oct 09 10:08:36 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28075411 01 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia sing.2807541101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2112069199 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 31697825 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 10:08:30 AM UTC 24 |
| Finished | Oct 09 10:08:33 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21120691 99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_ bash.2112069199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3288727201 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 17780677 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:08:30 AM UTC 24 |
| Finished | Oct 09 10:08:32 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32887272 01 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_r eset.3288727201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3905019272 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 105720736 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 10:08:35 AM UTC 24 |
| Finished | Oct 09 10:08:38 AM UTC 24 |
| Peak memory | 222844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3905019272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3905019272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2698213332 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 12993780 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:08:30 AM UTC 24 |
| Finished | Oct 09 10:08:32 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698213332 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.2698213332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4023047691 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 461503636 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 10:08:29 AM UTC 24 |
| Finished | Oct 09 10:08:35 AM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 23047691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pa ssthru_mem_tl_intg_err.4023047691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2741024508 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 27804565 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:08:34 AM UTC 24 |
| Finished | Oct 09 10:08:36 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2741024508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c trl_same_csr_outstanding.2741024508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3101740761 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 44374655 ps |
| CPU time | 5.37 seconds |
| Started | Oct 09 10:08:29 AM UTC 24 |
| Finished | Oct 09 10:08:35 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101740761 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.3101740761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1072363266 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 649610532 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 10:08:29 AM UTC 24 |
| Finished | Oct 09 10:08:33 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10723 63266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in tg_err.1072363266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2268629614 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 97171314 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:08:39 AM UTC 24 |
| Finished | Oct 09 10:08:41 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22686296 14 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia sing.2268629614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1329885459 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 585599235 ps |
| CPU time | 3.13 seconds |
| Started | Oct 09 10:08:36 AM UTC 24 |
| Finished | Oct 09 10:08:41 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13298854 59 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_ bash.1329885459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.293860826 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 14119066 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:08:36 AM UTC 24 |
| Finished | Oct 09 10:08:38 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29386082 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_re set.293860826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4246721731 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 44915335 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 10:08:40 AM UTC 24 |
| Finished | Oct 09 10:08:43 AM UTC 24 |
| Peak memory | 226016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4246721731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.4246721731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1931739886 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 53890216 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:08:36 AM UTC 24 |
| Finished | Oct 09 10:08:38 AM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931739886 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.1931739886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2902694878 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 801756717 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 10:08:35 AM UTC 24 |
| Finished | Oct 09 10:08:40 AM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 02694878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pa ssthru_mem_tl_intg_err.2902694878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4216351449 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 26131723 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 10:08:40 AM UTC 24 |
| Finished | Oct 09 10:08:42 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4216351449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c trl_same_csr_outstanding.4216351449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.925230834 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 138953834 ps |
| CPU time | 6.68 seconds |
| Started | Oct 09 10:08:35 AM UTC 24 |
| Finished | Oct 09 10:08:43 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925230834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.925230834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3401790416 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2155575532 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 10:08:36 AM UTC 24 |
| Finished | Oct 09 10:08:41 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34017 90416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in tg_err.3401790416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3461747974 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 70180705 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 10:08:44 AM UTC 24 |
| Finished | Oct 09 10:08:47 AM UTC 24 |
| Peak memory | 224228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3461747974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3461747974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.488981571 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 31322018 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 10:08:43 AM UTC 24 |
| Finished | Oct 09 10:08:45 AM UTC 24 |
| Peak memory | 212624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488981571 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.488981571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1156870175 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 209156180 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:08:41 AM UTC 24 |
| Finished | Oct 09 10:08:45 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 56870175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa ssthru_mem_tl_intg_err.1156870175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.51859761 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 16497330 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:08:43 AM UTC 24 |
| Finished | Oct 09 10:08:45 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=51859761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctr l_same_csr_outstanding.51859761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3763310842 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 83180383 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 10:08:41 AM UTC 24 |
| Finished | Oct 09 10:08:47 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763310842 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3763310842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2264263536 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 50313885 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 10:08:48 AM UTC 24 |
| Finished | Oct 09 10:08:51 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2264263536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2264263536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1455974462 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 38223163 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 10:08:45 AM UTC 24 |
| Finished | Oct 09 10:08:47 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455974462 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.1455974462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2753726162 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 948488304 ps |
| CPU time | 5.24 seconds |
| Started | Oct 09 10:08:44 AM UTC 24 |
| Finished | Oct 09 10:08:50 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 53726162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa ssthru_mem_tl_intg_err.2753726162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1065592493 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 45596157 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:08:47 AM UTC 24 |
| Finished | Oct 09 10:08:49 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1065592493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c trl_same_csr_outstanding.1065592493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3528765459 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 479617193 ps |
| CPU time | 3.81 seconds |
| Started | Oct 09 10:08:45 AM UTC 24 |
| Finished | Oct 09 10:08:50 AM UTC 24 |
| Peak memory | 213744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528765459 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3528765459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.80495773 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 88434874 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:08:52 AM UTC 24 |
| Finished | Oct 09 10:08:54 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=80495773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.80495773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2586299687 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 35316593 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 10:08:49 AM UTC 24 |
| Finished | Oct 09 10:08:51 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586299687 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2586299687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2431723707 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 771406413 ps |
| CPU time | 6 seconds |
| Started | Oct 09 10:08:48 AM UTC 24 |
| Finished | Oct 09 10:08:55 AM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24 31723707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pa ssthru_mem_tl_intg_err.2431723707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3470276286 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 14605279 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 10:08:52 AM UTC 24 |
| Finished | Oct 09 10:08:54 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3470276286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_c trl_same_csr_outstanding.3470276286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1301066301 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 255072663 ps |
| CPU time | 6.18 seconds |
| Started | Oct 09 10:08:48 AM UTC 24 |
| Finished | Oct 09 10:08:55 AM UTC 24 |
| Peak memory | 213728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301066301 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.1301066301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3224393114 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1678354022 ps |
| CPU time | 3.39 seconds |
| Started | Oct 09 10:08:48 AM UTC 24 |
| Finished | Oct 09 10:08:53 AM UTC 24 |
| Peak memory | 224248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32243 93114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in tg_err.3224393114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.150229233 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 180821543 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 10:08:55 AM UTC 24 |
| Finished | Oct 09 10:08:59 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=150229233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.150229233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2186408393 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 30091403 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:08:54 AM UTC 24 |
| Finished | Oct 09 10:08:56 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186408393 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.2186408393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3505954476 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 749430901 ps |
| CPU time | 3.1 seconds |
| Started | Oct 09 10:08:52 AM UTC 24 |
| Finished | Oct 09 10:08:56 AM UTC 24 |
| Peak memory | 213640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 05954476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa ssthru_mem_tl_intg_err.3505954476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3145133267 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 92368076 ps |
| CPU time | 1 seconds |
| Started | Oct 09 10:08:54 AM UTC 24 |
| Finished | Oct 09 10:08:56 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3145133267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c trl_same_csr_outstanding.3145133267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1537635487 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 76356418 ps |
| CPU time | 3.83 seconds |
| Started | Oct 09 10:08:52 AM UTC 24 |
| Finished | Oct 09 10:08:57 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537635487 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1537635487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1539318587 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 413497656 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 10:08:53 AM UTC 24 |
| Finished | Oct 09 10:08:56 AM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15393 18587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in tg_err.1539318587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2679807247 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 106116310 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 10:08:57 AM UTC 24 |
| Finished | Oct 09 10:09:01 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2679807247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2679807247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.842040611 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 12415252 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 10:08:57 AM UTC 24 |
| Finished | Oct 09 10:08:59 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842040611 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.842040611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4116020240 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1601775564 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 10:08:57 AM UTC 24 |
| Finished | Oct 09 10:09:03 AM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 16020240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pa ssthru_mem_tl_intg_err.4116020240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4246585402 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 34884279 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 10:08:57 AM UTC 24 |
| Finished | Oct 09 10:08:59 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4246585402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c trl_same_csr_outstanding.4246585402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2054520055 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 127710264 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 10:08:57 AM UTC 24 |
| Finished | Oct 09 10:09:00 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054520055 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.2054520055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.758702918 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 663690960 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 10:08:57 AM UTC 24 |
| Finished | Oct 09 10:09:02 AM UTC 24 |
| Peak memory | 224300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75870 2918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_int g_err.758702918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.3498642437 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2889206001 ps |
| CPU time | 649 seconds |
| Started | Oct 09 08:49:43 AM UTC 24 |
| Finished | Oct 09 09:00:40 AM UTC 24 |
| Peak memory | 383412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498642437 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_ key_req.3498642437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.479458874 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6013500936 ps |
| CPU time | 62.02 seconds |
| Started | Oct 09 08:49:42 AM UTC 24 |
| Finished | Oct 09 08:50:46 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479458874 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.479458874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2314024083 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 50064568227 ps |
| CPU time | 1264.85 seconds |
| Started | Oct 09 08:49:43 AM UTC 24 |
| Finished | Oct 09 09:11:02 AM UTC 24 |
| Peak memory | 383500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314024083 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2314024083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2772309959 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 64604709 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 08:49:44 AM UTC 24 |
| Finished | Oct 09 08:49:49 AM UTC 24 |
| Peak memory | 222756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772309959 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.2772309959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3195824413 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 683252798 ps |
| CPU time | 11.64 seconds |
| Started | Oct 09 08:49:44 AM UTC 24 |
| Finished | Oct 09 08:49:56 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195824413 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.3195824413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3166053246 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 7092391939 ps |
| CPU time | 694.64 seconds |
| Started | Oct 09 08:49:42 AM UTC 24 |
| Finished | Oct 09 09:01:25 AM UTC 24 |
| Peak memory | 381376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166053246 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.3166053246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2226555042 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 383793624 ps |
| CPU time | 65.27 seconds |
| Started | Oct 09 08:49:42 AM UTC 24 |
| Finished | Oct 09 08:50:49 AM UTC 24 |
| Peak memory | 366984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226555042 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.2226555042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_readback_err.2263485710 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 105796858 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 08:49:45 AM UTC 24 |
| Finished | Oct 09 08:49:47 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263485710 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_readback_err.2263485710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.3695752139 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 6201310818 ps |
| CPU time | 693.31 seconds |
| Started | Oct 09 08:49:43 AM UTC 24 |
| Finished | Oct 09 09:01:25 AM UTC 24 |
| Peak memory | 377540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695752139 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3695752139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.544014536 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 204064285 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 08:49:45 AM UTC 24 |
| Finished | Oct 09 08:49:50 AM UTC 24 |
| Peak memory | 248520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544014536 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.544014536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.4068182845 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3476218089 ps |
| CPU time | 22.34 seconds |
| Started | Oct 09 08:49:42 AM UTC 24 |
| Finished | Oct 09 08:50:05 AM UTC 24 |
| Peak memory | 212592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068182845 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.4068182845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2912633314 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3347833175 ps |
| CPU time | 306.15 seconds |
| Started | Oct 09 08:49:42 AM UTC 24 |
| Finished | Oct 09 08:54:52 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912633314 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.2912633314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2220767628 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 202271051 ps |
| CPU time | 66.78 seconds |
| Started | Oct 09 08:49:43 AM UTC 24 |
| Finished | Oct 09 08:50:52 AM UTC 24 |
| Peak memory | 350216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2220767628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th roughput_w_partial_write.2220767628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1461779571 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3038926994 ps |
| CPU time | 651.35 seconds |
| Started | Oct 09 08:49:51 AM UTC 24 |
| Finished | Oct 09 09:00:50 AM UTC 24 |
| Peak memory | 375224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461779571 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_ key_req.1461779571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.739005842 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 30749203 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 08:50:04 AM UTC 24 |
| Finished | Oct 09 08:50:06 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739005842 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.739005842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.338723861 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 16475511161 ps |
| CPU time | 62.64 seconds |
| Started | Oct 09 08:49:46 AM UTC 24 |
| Finished | Oct 09 08:50:51 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338723861 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.338723861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.2402257933 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 12487648653 ps |
| CPU time | 965.22 seconds |
| Started | Oct 09 08:49:52 AM UTC 24 |
| Finished | Oct 09 09:06:08 AM UTC 24 |
| Peak memory | 383484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402257933 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.2402257933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1345177711 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1148906126 ps |
| CPU time | 10.61 seconds |
| Started | Oct 09 08:49:51 AM UTC 24 |
| Finished | Oct 09 08:50:03 AM UTC 24 |
| Peak memory | 212592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345177711 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.1345177711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3758713741 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 574113293 ps |
| CPU time | 90.39 seconds |
| Started | Oct 09 08:49:49 AM UTC 24 |
| Finished | Oct 09 08:51:21 AM UTC 24 |
| Peak memory | 381396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 758713741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max _throughput.3758713741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4167033068 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5009307935 ps |
| CPU time | 13.9 seconds |
| Started | Oct 09 08:49:58 AM UTC 24 |
| Finished | Oct 09 08:50:13 AM UTC 24 |
| Peak memory | 222912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167033068 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.4167033068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1317031934 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 56182305705 ps |
| CPU time | 1782.61 seconds |
| Started | Oct 09 08:49:46 AM UTC 24 |
| Finished | Oct 09 09:19:48 AM UTC 24 |
| Peak memory | 385468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317031934 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.1317031934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3787747513 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 236384624 ps |
| CPU time | 20.01 seconds |
| Started | Oct 09 08:49:47 AM UTC 24 |
| Finished | Oct 09 08:50:09 AM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787747513 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.3787747513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1176650529 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 26809010108 ps |
| CPU time | 385.74 seconds |
| Started | Oct 09 08:49:48 AM UTC 24 |
| Finished | Oct 09 08:56:19 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176650529 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce ss_b2b.1176650529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.4275257224 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 32067099 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 08:49:57 AM UTC 24 |
| Finished | Oct 09 08:49:59 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275257224 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.4275257224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1302539117 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 784440609 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 08:50:04 AM UTC 24 |
| Finished | Oct 09 08:50:09 AM UTC 24 |
| Peak memory | 248400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302539117 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1302539117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.681943585 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 722326622 ps |
| CPU time | 12.98 seconds |
| Started | Oct 09 08:49:45 AM UTC 24 |
| Finished | Oct 09 08:49:59 AM UTC 24 |
| Peak memory | 212652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681943585 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.681943585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2510534855 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 450510921999 ps |
| CPU time | 6689.79 seconds |
| Started | Oct 09 08:50:01 AM UTC 24 |
| Finished | Oct 09 10:42:44 AM UTC 24 |
| Peak memory | 387100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251053485 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.2510534855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2239552264 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1961918760 ps |
| CPU time | 252.81 seconds |
| Started | Oct 09 08:49:47 AM UTC 24 |
| Finished | Oct 09 08:54:04 AM UTC 24 |
| Peak memory | 212600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239552264 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2239552264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.4178410685 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 103582366 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 08:49:50 AM UTC 24 |
| Finished | Oct 09 08:49:55 AM UTC 24 |
| Peak memory | 229656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4178410685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th roughput_w_partial_write.4178410685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.519966988 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2286427895 ps |
| CPU time | 221.38 seconds |
| Started | Oct 09 09:02:49 AM UTC 24 |
| Finished | Oct 09 09:06:34 AM UTC 24 |
| Peak memory | 369360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519966988 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during_ key_req.519966988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1983711007 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 14833085 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 09:03:18 AM UTC 24 |
| Finished | Oct 09 09:03:20 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983711007 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1983711007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.243260019 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 7536138593 ps |
| CPU time | 53.8 seconds |
| Started | Oct 09 09:01:59 AM UTC 24 |
| Finished | Oct 09 09:02:54 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243260019 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.243260019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.4017891162 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2382244934 ps |
| CPU time | 829.82 seconds |
| Started | Oct 09 09:02:51 AM UTC 24 |
| Finished | Oct 09 09:16:50 AM UTC 24 |
| Peak memory | 375304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017891162 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.4017891162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.180158246 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 421386090 ps |
| CPU time | 8.53 seconds |
| Started | Oct 09 09:02:49 AM UTC 24 |
| Finished | Oct 09 09:02:58 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180158246 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.180158246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3866816591 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 118818734 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 09:02:32 AM UTC 24 |
| Finished | Oct 09 09:02:35 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 866816591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma x_throughput.3866816591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.234191611 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 67926615 ps |
| CPU time | 6.79 seconds |
| Started | Oct 09 09:02:59 AM UTC 24 |
| Finished | Oct 09 09:03:07 AM UTC 24 |
| Peak memory | 223032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234191611 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.234191611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2667872049 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2286044892 ps |
| CPU time | 16.33 seconds |
| Started | Oct 09 09:02:58 AM UTC 24 |
| Finished | Oct 09 09:03:17 AM UTC 24 |
| Peak memory | 223152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667872049 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.2667872049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2307556932 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 54679754225 ps |
| CPU time | 529.97 seconds |
| Started | Oct 09 09:01:54 AM UTC 24 |
| Finished | Oct 09 09:10:50 AM UTC 24 |
| Peak memory | 381372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307556932 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2307556932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.2239235865 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 248870289 ps |
| CPU time | 108.17 seconds |
| Started | Oct 09 09:02:15 AM UTC 24 |
| Finished | Oct 09 09:04:06 AM UTC 24 |
| Peak memory | 369088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239235865 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.2239235865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3216824505 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 36543177532 ps |
| CPU time | 357.06 seconds |
| Started | Oct 09 09:02:29 AM UTC 24 |
| Finished | Oct 09 09:08:32 AM UTC 24 |
| Peak memory | 212548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216824505 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc ess_b2b.3216824505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3926393620 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 85623946 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 09:02:55 AM UTC 24 |
| Finished | Oct 09 09:02:58 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926393620 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3926393620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_readback_err.2188572485 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 33578224 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 09:03:09 AM UTC 24 |
| Finished | Oct 09 09:03:11 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188572485 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_readback_err.2188572485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.882633667 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1441030663 ps |
| CPU time | 428.04 seconds |
| Started | Oct 09 09:02:52 AM UTC 24 |
| Finished | Oct 09 09:10:05 AM UTC 24 |
| Peak memory | 385604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882633667 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.882633667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.4289633849 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3682890963 ps |
| CPU time | 106.19 seconds |
| Started | Oct 09 09:01:52 AM UTC 24 |
| Finished | Oct 09 09:03:40 AM UTC 24 |
| Peak memory | 375316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289633849 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.4289633849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2650985909 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 4210874851 ps |
| CPU time | 78.17 seconds |
| Started | Oct 09 09:03:14 AM UTC 24 |
| Finished | Oct 09 09:04:34 AM UTC 24 |
| Peak memory | 334504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265098590 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.2650985909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.781458157 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 24534093707 ps |
| CPU time | 107.18 seconds |
| Started | Oct 09 09:03:12 AM UTC 24 |
| Finished | Oct 09 09:05:01 AM UTC 24 |
| Peak memory | 293592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781458157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.781458157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.85225778 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4496271550 ps |
| CPU time | 263.11 seconds |
| Started | Oct 09 09:02:06 AM UTC 24 |
| Finished | Oct 09 09:06:33 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85225778 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.85225778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3290291698 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 65043553 ps |
| CPU time | 11.03 seconds |
| Started | Oct 09 09:02:36 AM UTC 24 |
| Finished | Oct 09 09:02:48 AM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3290291698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t hroughput_w_partial_write.3290291698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3789607531 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1576140182 ps |
| CPU time | 492.06 seconds |
| Started | Oct 09 09:04:45 AM UTC 24 |
| Finished | Oct 09 09:13:04 AM UTC 24 |
| Peak memory | 383620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789607531 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during _key_req.3789607531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3868911106 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 33902527 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 09:05:18 AM UTC 24 |
| Finished | Oct 09 09:05:20 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868911106 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3868911106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2235818963 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2430261850 ps |
| CPU time | 49.34 seconds |
| Started | Oct 09 09:03:40 AM UTC 24 |
| Finished | Oct 09 09:04:31 AM UTC 24 |
| Peak memory | 212844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235818963 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.2235818963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.13948966 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 17993498622 ps |
| CPU time | 462.01 seconds |
| Started | Oct 09 09:04:53 AM UTC 24 |
| Finished | Oct 09 09:12:40 AM UTC 24 |
| Peak memory | 379388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13948966 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.13948966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.4017493840 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 522893389 ps |
| CPU time | 7.48 seconds |
| Started | Oct 09 09:04:35 AM UTC 24 |
| Finished | Oct 09 09:04:44 AM UTC 24 |
| Peak memory | 222804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017493840 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.4017493840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1071597411 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 429597077 ps |
| CPU time | 101.71 seconds |
| Started | Oct 09 09:04:32 AM UTC 24 |
| Finished | Oct 09 09:06:16 AM UTC 24 |
| Peak memory | 375376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 071597411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ma x_throughput.1071597411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3670593924 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1355212273 ps |
| CPU time | 7.96 seconds |
| Started | Oct 09 09:05:02 AM UTC 24 |
| Finished | Oct 09 09:05:11 AM UTC 24 |
| Peak memory | 222832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670593924 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.3670593924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2787641697 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1383716724 ps |
| CPU time | 14.85 seconds |
| Started | Oct 09 09:05:00 AM UTC 24 |
| Finished | Oct 09 09:05:16 AM UTC 24 |
| Peak memory | 212572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787641697 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.2787641697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3415515638 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5802440726 ps |
| CPU time | 645.56 seconds |
| Started | Oct 09 09:03:36 AM UTC 24 |
| Finished | Oct 09 09:14:29 AM UTC 24 |
| Peak memory | 385468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415515638 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.3415515638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.890803073 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 248396241 ps |
| CPU time | 7.02 seconds |
| Started | Oct 09 09:04:07 AM UTC 24 |
| Finished | Oct 09 09:04:15 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890803073 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.890803073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.4001712528 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 52401368132 ps |
| CPU time | 282.97 seconds |
| Started | Oct 09 09:04:16 AM UTC 24 |
| Finished | Oct 09 09:09:03 AM UTC 24 |
| Peak memory | 212788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001712528 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc ess_b2b.4001712528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1389189725 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 78554153 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 09:04:57 AM UTC 24 |
| Finished | Oct 09 09:04:59 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389189725 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1389189725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_readback_err.4148923456 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 145126924 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 09:05:12 AM UTC 24 |
| Finished | Oct 09 09:05:15 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148923456 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_readback_err.4148923456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.491995936 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4243297115 ps |
| CPU time | 1600.92 seconds |
| Started | Oct 09 09:04:54 AM UTC 24 |
| Finished | Oct 09 09:31:52 AM UTC 24 |
| Peak memory | 381456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491995936 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.491995936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.2659948192 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3943780610 ps |
| CPU time | 88.34 seconds |
| Started | Oct 09 09:03:21 AM UTC 24 |
| Finished | Oct 09 09:04:52 AM UTC 24 |
| Peak memory | 377284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659948192 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2659948192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1219130842 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 138093419501 ps |
| CPU time | 1761.35 seconds |
| Started | Oct 09 09:05:15 AM UTC 24 |
| Finished | Oct 09 09:34:56 AM UTC 24 |
| Peak memory | 385472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121913084 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.1219130842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3014772089 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 9030239676 ps |
| CPU time | 225.66 seconds |
| Started | Oct 09 09:03:43 AM UTC 24 |
| Finished | Oct 09 09:07:32 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014772089 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.3014772089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1370034540 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 145167314 ps |
| CPU time | 78.44 seconds |
| Started | Oct 09 09:04:33 AM UTC 24 |
| Finished | Oct 09 09:05:53 AM UTC 24 |
| Peak memory | 367064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1370034540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t hroughput_w_partial_write.1370034540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3064477967 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3735686673 ps |
| CPU time | 745.72 seconds |
| Started | Oct 09 09:06:27 AM UTC 24 |
| Finished | Oct 09 09:19:02 AM UTC 24 |
| Peak memory | 377600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064477967 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during _key_req.3064477967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3325772363 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 38219758 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 09:06:47 AM UTC 24 |
| Finished | Oct 09 09:06:49 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325772363 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3325772363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.2663835791 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1890582037 ps |
| CPU time | 51.89 seconds |
| Started | Oct 09 09:05:49 AM UTC 24 |
| Finished | Oct 09 09:06:43 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663835791 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.2663835791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.420416680 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2260549256 ps |
| CPU time | 42.84 seconds |
| Started | Oct 09 09:06:29 AM UTC 24 |
| Finished | Oct 09 09:07:13 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420416680 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.420416680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.898918973 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 6452772997 ps |
| CPU time | 7.91 seconds |
| Started | Oct 09 09:06:17 AM UTC 24 |
| Finished | Oct 09 09:06:26 AM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898918973 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.898918973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3313613562 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 106006317 ps |
| CPU time | 31.2 seconds |
| Started | Oct 09 09:06:09 AM UTC 24 |
| Finished | Oct 09 09:06:42 AM UTC 24 |
| Peak memory | 311684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 313613562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma x_throughput.3313613562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3175681103 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 205417549 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 09:06:42 AM UTC 24 |
| Finished | Oct 09 09:06:47 AM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175681103 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.3175681103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.237654365 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 335555741 ps |
| CPU time | 6.84 seconds |
| Started | Oct 09 09:06:38 AM UTC 24 |
| Finished | Oct 09 09:06:46 AM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237654365 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.237654365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2642101043 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 42760464875 ps |
| CPU time | 706.81 seconds |
| Started | Oct 09 09:05:31 AM UTC 24 |
| Finished | Oct 09 09:17:26 AM UTC 24 |
| Peak memory | 369172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642101043 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.2642101043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.4262161840 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 165123286 ps |
| CPU time | 34.66 seconds |
| Started | Oct 09 09:06:05 AM UTC 24 |
| Finished | Oct 09 09:06:41 AM UTC 24 |
| Peak memory | 315764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262161840 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.4262161840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.73933840 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 19339475361 ps |
| CPU time | 283.63 seconds |
| Started | Oct 09 09:06:06 AM UTC 24 |
| Finished | Oct 09 09:10:54 AM UTC 24 |
| Peak memory | 212592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73933840 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acces s_b2b.73933840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2093417482 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 89431754 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 09:06:35 AM UTC 24 |
| Finished | Oct 09 09:06:37 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093417482 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2093417482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_readback_err.2292541532 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 98714793 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 09:06:42 AM UTC 24 |
| Finished | Oct 09 09:06:45 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292541532 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_readback_err.2292541532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.363418800 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 69616892991 ps |
| CPU time | 813.05 seconds |
| Started | Oct 09 09:06:34 AM UTC 24 |
| Finished | Oct 09 09:20:16 AM UTC 24 |
| Peak memory | 383452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363418800 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.363418800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.3306672495 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 259076323 ps |
| CPU time | 8.11 seconds |
| Started | Oct 09 09:05:21 AM UTC 24 |
| Finished | Oct 09 09:05:30 AM UTC 24 |
| Peak memory | 235988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306672495 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3306672495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.105750790 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 62397145295 ps |
| CPU time | 4604 seconds |
| Started | Oct 09 09:06:45 AM UTC 24 |
| Finished | Oct 09 10:24:17 AM UTC 24 |
| Peak memory | 395272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105750790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.105750790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2215531823 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6453753882 ps |
| CPU time | 134.36 seconds |
| Started | Oct 09 09:06:43 AM UTC 24 |
| Finished | Oct 09 09:09:00 AM UTC 24 |
| Peak memory | 332356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215531823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2215531823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2876354121 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 23277338392 ps |
| CPU time | 359.42 seconds |
| Started | Oct 09 09:05:54 AM UTC 24 |
| Finished | Oct 09 09:11:59 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876354121 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.2876354121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2561964725 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 183453298 ps |
| CPU time | 87.59 seconds |
| Started | Oct 09 09:06:17 AM UTC 24 |
| Finished | Oct 09 09:07:47 AM UTC 24 |
| Peak memory | 379344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2561964725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t hroughput_w_partial_write.2561964725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.26632733 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1629150907 ps |
| CPU time | 103.7 seconds |
| Started | Oct 09 09:07:48 AM UTC 24 |
| Finished | Oct 09 09:09:34 AM UTC 24 |
| Peak memory | 309880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26632733 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_k ey_req.26632733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1636036326 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 36448774 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 09:08:33 AM UTC 24 |
| Finished | Oct 09 09:08:35 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636036326 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1636036326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.4100449135 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 10424340857 ps |
| CPU time | 100.78 seconds |
| Started | Oct 09 09:06:50 AM UTC 24 |
| Finished | Oct 09 09:08:33 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100449135 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.4100449135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.2587876474 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3666587751 ps |
| CPU time | 321.68 seconds |
| Started | Oct 09 09:07:48 AM UTC 24 |
| Finished | Oct 09 09:13:14 AM UTC 24 |
| Peak memory | 375232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587876474 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.2587876474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2981674684 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 459416331 ps |
| CPU time | 9.07 seconds |
| Started | Oct 09 09:07:41 AM UTC 24 |
| Finished | Oct 09 09:07:51 AM UTC 24 |
| Peak memory | 224816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981674684 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.2981674684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2624464345 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 228179304 ps |
| CPU time | 83.26 seconds |
| Started | Oct 09 09:07:18 AM UTC 24 |
| Finished | Oct 09 09:08:43 AM UTC 24 |
| Peak memory | 379536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 624464345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ma x_throughput.2624464345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1032796144 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 100787779 ps |
| CPU time | 4.6 seconds |
| Started | Oct 09 09:08:14 AM UTC 24 |
| Finished | Oct 09 09:08:20 AM UTC 24 |
| Peak memory | 222840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032796144 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.1032796144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1708851860 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5975703821 ps |
| CPU time | 15.27 seconds |
| Started | Oct 09 09:08:02 AM UTC 24 |
| Finished | Oct 09 09:08:19 AM UTC 24 |
| Peak memory | 222912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708851860 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.1708851860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3605401728 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 86649394148 ps |
| CPU time | 1601.03 seconds |
| Started | Oct 09 09:06:49 AM UTC 24 |
| Finished | Oct 09 09:33:47 AM UTC 24 |
| Peak memory | 385548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605401728 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.3605401728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.423440959 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 274996018 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 09:07:14 AM UTC 24 |
| Finished | Oct 09 09:07:18 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423440959 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.423440959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.436544054 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 14506736689 ps |
| CPU time | 320.18 seconds |
| Started | Oct 09 09:07:16 AM UTC 24 |
| Finished | Oct 09 09:12:41 AM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436544054 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acce ss_b2b.436544054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.157850880 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 29927253 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 09:07:59 AM UTC 24 |
| Finished | Oct 09 09:08:01 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157850880 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.157850880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_readback_err.2953706890 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 94072317 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 09:08:19 AM UTC 24 |
| Finished | Oct 09 09:08:22 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953706890 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_readback_err.2953706890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.1840678601 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1083945538 ps |
| CPU time | 20.09 seconds |
| Started | Oct 09 09:07:52 AM UTC 24 |
| Finished | Oct 09 09:08:13 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840678601 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1840678601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2439842169 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 185587725 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 09:06:48 AM UTC 24 |
| Finished | Oct 09 09:06:54 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439842169 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2439842169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3965902177 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 226843005793 ps |
| CPU time | 3926.45 seconds |
| Started | Oct 09 09:08:23 AM UTC 24 |
| Finished | Oct 09 10:14:29 AM UTC 24 |
| Peak memory | 387084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396590217 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.3965902177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2775228154 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 9480314951 ps |
| CPU time | 246.06 seconds |
| Started | Oct 09 09:06:55 AM UTC 24 |
| Finished | Oct 09 09:11:05 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775228154 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2775228154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2939676602 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2428874564 ps |
| CPU time | 114.55 seconds |
| Started | Oct 09 09:07:32 AM UTC 24 |
| Finished | Oct 09 09:09:30 AM UTC 24 |
| Peak memory | 379392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2939676602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t hroughput_w_partial_write.2939676602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2583463775 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4584787914 ps |
| CPU time | 142.2 seconds |
| Started | Oct 09 09:09:30 AM UTC 24 |
| Finished | Oct 09 09:11:55 AM UTC 24 |
| Peak memory | 348616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583463775 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during _key_req.2583463775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2882450624 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 12410018 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 09:10:06 AM UTC 24 |
| Finished | Oct 09 09:10:08 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882450624 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.2882450624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.2875753931 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1377707062 ps |
| CPU time | 27.38 seconds |
| Started | Oct 09 09:08:42 AM UTC 24 |
| Finished | Oct 09 09:09:11 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875753931 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.2875753931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.2200881283 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 13245660004 ps |
| CPU time | 619.5 seconds |
| Started | Oct 09 09:09:34 AM UTC 24 |
| Finished | Oct 09 09:20:02 AM UTC 24 |
| Peak memory | 375232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200881283 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.2200881283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1799437164 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 713392001 ps |
| CPU time | 8.66 seconds |
| Started | Oct 09 09:09:25 AM UTC 24 |
| Finished | Oct 09 09:09:35 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799437164 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.1799437164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3380420292 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 356986190 ps |
| CPU time | 37.43 seconds |
| Started | Oct 09 09:09:04 AM UTC 24 |
| Finished | Oct 09 09:09:43 AM UTC 24 |
| Peak memory | 303500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 380420292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma x_throughput.3380420292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2486168895 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 351850220 ps |
| CPU time | 4.28 seconds |
| Started | Oct 09 09:09:44 AM UTC 24 |
| Finished | Oct 09 09:09:49 AM UTC 24 |
| Peak memory | 222788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486168895 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2486168895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4160389534 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 453489047 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 09:09:41 AM UTC 24 |
| Finished | Oct 09 09:09:49 AM UTC 24 |
| Peak memory | 222728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160389534 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.4160389534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3382585670 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 16180501883 ps |
| CPU time | 1691.95 seconds |
| Started | Oct 09 09:08:36 AM UTC 24 |
| Finished | Oct 09 09:37:07 AM UTC 24 |
| Peak memory | 383508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382585670 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.3382585670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.4117128851 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 313386067 ps |
| CPU time | 47.02 seconds |
| Started | Oct 09 09:08:47 AM UTC 24 |
| Finished | Oct 09 09:09:36 AM UTC 24 |
| Peak memory | 321996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117128851 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.4117128851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.178110635 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3551332906 ps |
| CPU time | 276.07 seconds |
| Started | Oct 09 09:09:02 AM UTC 24 |
| Finished | Oct 09 09:13:42 AM UTC 24 |
| Peak memory | 212872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178110635 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acce ss_b2b.178110635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2608704881 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 33080659 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 09:09:37 AM UTC 24 |
| Finished | Oct 09 09:09:40 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608704881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2608704881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_readback_err.4213836320 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 135304829 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 09:09:50 AM UTC 24 |
| Finished | Oct 09 09:09:52 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213836320 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_readback_err.4213836320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3318117925 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 29427469098 ps |
| CPU time | 713.16 seconds |
| Started | Oct 09 09:09:35 AM UTC 24 |
| Finished | Oct 09 09:21:37 AM UTC 24 |
| Peak memory | 375236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318117925 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3318117925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.1159863495 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 158764343 ps |
| CPU time | 11.57 seconds |
| Started | Oct 09 09:08:34 AM UTC 24 |
| Finished | Oct 09 09:08:47 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159863495 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1159863495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3202707676 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 152873876191 ps |
| CPU time | 4967.17 seconds |
| Started | Oct 09 09:09:53 AM UTC 24 |
| Finished | Oct 09 10:33:35 AM UTC 24 |
| Peak memory | 395244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320270767 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.3202707676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3697998953 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3357048820 ps |
| CPU time | 211.15 seconds |
| Started | Oct 09 09:09:50 AM UTC 24 |
| Finished | Oct 09 09:13:24 AM UTC 24 |
| Peak memory | 333988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697998953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3697998953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2403105963 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3550733903 ps |
| CPU time | 337.8 seconds |
| Started | Oct 09 09:08:44 AM UTC 24 |
| Finished | Oct 09 09:14:27 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403105963 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.2403105963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1222002769 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 77297218 ps |
| CPU time | 10.56 seconds |
| Started | Oct 09 09:09:12 AM UTC 24 |
| Finished | Oct 09 09:09:24 AM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1222002769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_t hroughput_w_partial_write.1222002769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3878352115 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3011060788 ps |
| CPU time | 561.14 seconds |
| Started | Oct 09 09:11:10 AM UTC 24 |
| Finished | Oct 09 09:20:38 AM UTC 24 |
| Peak memory | 379336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878352115 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during _key_req.3878352115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1545028208 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 16153879 ps |
| CPU time | 1 seconds |
| Started | Oct 09 09:11:58 AM UTC 24 |
| Finished | Oct 09 09:12:01 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545028208 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1545028208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.3311791748 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2298620684 ps |
| CPU time | 67.01 seconds |
| Started | Oct 09 09:10:47 AM UTC 24 |
| Finished | Oct 09 09:11:57 AM UTC 24 |
| Peak memory | 212580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311791748 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.3311791748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.950079579 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 44895267728 ps |
| CPU time | 1335.8 seconds |
| Started | Oct 09 09:11:12 AM UTC 24 |
| Finished | Oct 09 09:33:43 AM UTC 24 |
| Peak memory | 385524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950079579 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.950079579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2759602515 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 549004349 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 09:11:06 AM UTC 24 |
| Finished | Oct 09 09:11:09 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759602515 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.2759602515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2286634391 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 446440586 ps |
| CPU time | 71.02 seconds |
| Started | Oct 09 09:10:58 AM UTC 24 |
| Finished | Oct 09 09:12:11 AM UTC 24 |
| Peak memory | 375240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 286634391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma x_throughput.2286634391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1928964030 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 71514771 ps |
| CPU time | 5.89 seconds |
| Started | Oct 09 09:11:50 AM UTC 24 |
| Finished | Oct 09 09:11:57 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928964030 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.1928964030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3546112829 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 636978427 ps |
| CPU time | 13.64 seconds |
| Started | Oct 09 09:11:48 AM UTC 24 |
| Finished | Oct 09 09:12:03 AM UTC 24 |
| Peak memory | 222856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546112829 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.3546112829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.779664855 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 16066647151 ps |
| CPU time | 98.64 seconds |
| Started | Oct 09 09:10:10 AM UTC 24 |
| Finished | Oct 09 09:11:50 AM UTC 24 |
| Peak memory | 356824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779664855 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.779664855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.842160469 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4806537260 ps |
| CPU time | 18.68 seconds |
| Started | Oct 09 09:10:52 AM UTC 24 |
| Finished | Oct 09 09:11:12 AM UTC 24 |
| Peak memory | 212612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842160469 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.842160469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1565228721 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 13663485848 ps |
| CPU time | 394.33 seconds |
| Started | Oct 09 09:10:55 AM UTC 24 |
| Finished | Oct 09 09:17:35 AM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565228721 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acc ess_b2b.1565228721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.4110472008 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 28779755 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 09:11:45 AM UTC 24 |
| Finished | Oct 09 09:11:47 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110472008 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.4110472008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_readback_err.965022959 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 29173570 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 09:11:51 AM UTC 24 |
| Finished | Oct 09 09:11:54 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965022959 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_readback_err.965022959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.3108238201 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1776251734 ps |
| CPU time | 351.83 seconds |
| Started | Oct 09 09:11:28 AM UTC 24 |
| Finished | Oct 09 09:17:24 AM UTC 24 |
| Peak memory | 381400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108238201 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3108238201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2225528867 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 574369128 ps |
| CPU time | 49.32 seconds |
| Started | Oct 09 09:10:06 AM UTC 24 |
| Finished | Oct 09 09:10:57 AM UTC 24 |
| Peak memory | 340348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225528867 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2225528867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4245123314 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 4359967167 ps |
| CPU time | 942.06 seconds |
| Started | Oct 09 09:11:56 AM UTC 24 |
| Finished | Oct 09 09:27:49 AM UTC 24 |
| Peak memory | 383680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424512331 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.4245123314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.763595942 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 26788735212 ps |
| CPU time | 599.96 seconds |
| Started | Oct 09 09:11:55 AM UTC 24 |
| Finished | Oct 09 09:22:02 AM UTC 24 |
| Peak memory | 387584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763595942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.763595942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.888028736 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 21042011521 ps |
| CPU time | 381.61 seconds |
| Started | Oct 09 09:10:49 AM UTC 24 |
| Finished | Oct 09 09:17:16 AM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888028736 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.888028736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.4137576708 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 908039993 ps |
| CPU time | 88.88 seconds |
| Started | Oct 09 09:11:03 AM UTC 24 |
| Finished | Oct 09 09:12:34 AM UTC 24 |
| Peak memory | 379528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4137576708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.4137576708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.74694538 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1059113990 ps |
| CPU time | 260.35 seconds |
| Started | Oct 09 09:12:42 AM UTC 24 |
| Finished | Oct 09 09:17:06 AM UTC 24 |
| Peak memory | 383452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74694538 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during_k ey_req.74694538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.172071838 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 12081008 ps |
| CPU time | 1 seconds |
| Started | Oct 09 09:13:22 AM UTC 24 |
| Finished | Oct 09 09:13:24 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172071838 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.172071838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.3120011006 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1404831930 ps |
| CPU time | 65.03 seconds |
| Started | Oct 09 09:12:01 AM UTC 24 |
| Finished | Oct 09 09:13:08 AM UTC 24 |
| Peak memory | 212580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120011006 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.3120011006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2870258808 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 9149557565 ps |
| CPU time | 336.29 seconds |
| Started | Oct 09 09:12:56 AM UTC 24 |
| Finished | Oct 09 09:18:37 AM UTC 24 |
| Peak memory | 358856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870258808 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.2870258808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1790457138 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8964859612 ps |
| CPU time | 17.49 seconds |
| Started | Oct 09 09:12:41 AM UTC 24 |
| Finished | Oct 09 09:13:00 AM UTC 24 |
| Peak memory | 222904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790457138 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1790457138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.376764308 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 100866228 ps |
| CPU time | 32.83 seconds |
| Started | Oct 09 09:12:21 AM UTC 24 |
| Finished | Oct 09 09:12:55 AM UTC 24 |
| Peak memory | 311956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 76764308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_max _throughput.376764308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2165323669 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 405149594 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 09:13:09 AM UTC 24 |
| Finished | Oct 09 09:13:15 AM UTC 24 |
| Peak memory | 222712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165323669 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.2165323669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1255967404 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 352182207 ps |
| CPU time | 12.27 seconds |
| Started | Oct 09 09:13:08 AM UTC 24 |
| Finished | Oct 09 09:13:21 AM UTC 24 |
| Peak memory | 222728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255967404 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.1255967404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2600242900 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 6166487573 ps |
| CPU time | 627.8 seconds |
| Started | Oct 09 09:12:00 AM UTC 24 |
| Finished | Oct 09 09:22:36 AM UTC 24 |
| Peak memory | 381428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600242900 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.2600242900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3296937217 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 316212164 ps |
| CPU time | 11 seconds |
| Started | Oct 09 09:12:07 AM UTC 24 |
| Finished | Oct 09 09:12:20 AM UTC 24 |
| Peak memory | 212580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296937217 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.3296937217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3269834487 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 9508053621 ps |
| CPU time | 428.17 seconds |
| Started | Oct 09 09:12:11 AM UTC 24 |
| Finished | Oct 09 09:19:26 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269834487 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acc ess_b2b.3269834487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.4123920055 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 52511869 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 09:13:04 AM UTC 24 |
| Finished | Oct 09 09:13:07 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123920055 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.4123920055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_readback_err.1987422302 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 184289047 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 09:13:15 AM UTC 24 |
| Finished | Oct 09 09:13:17 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987422302 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_readback_err.1987422302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.528583800 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 12163660168 ps |
| CPU time | 139.02 seconds |
| Started | Oct 09 09:13:00 AM UTC 24 |
| Finished | Oct 09 09:15:22 AM UTC 24 |
| Peak memory | 299540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528583800 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.528583800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3177399972 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 156426923 ps |
| CPU time | 6.57 seconds |
| Started | Oct 09 09:11:58 AM UTC 24 |
| Finished | Oct 09 09:12:06 AM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177399972 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3177399972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2182810042 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 61398300433 ps |
| CPU time | 3958.5 seconds |
| Started | Oct 09 09:13:18 AM UTC 24 |
| Finished | Oct 09 10:19:58 AM UTC 24 |
| Peak memory | 387148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218281004 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.2182810042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3539810114 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2176564916 ps |
| CPU time | 38.17 seconds |
| Started | Oct 09 09:13:16 AM UTC 24 |
| Finished | Oct 09 09:13:56 AM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539810114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3539810114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.683412810 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1636358706 ps |
| CPU time | 216.77 seconds |
| Started | Oct 09 09:12:04 AM UTC 24 |
| Finished | Oct 09 09:15:45 AM UTC 24 |
| Peak memory | 212872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683412810 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.683412810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2275044305 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 525430611 ps |
| CPU time | 58.42 seconds |
| Started | Oct 09 09:12:35 AM UTC 24 |
| Finished | Oct 09 09:13:35 AM UTC 24 |
| Peak memory | 350840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2275044305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t hroughput_w_partial_write.2275044305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2334911724 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2307300445 ps |
| CPU time | 468.97 seconds |
| Started | Oct 09 09:14:23 AM UTC 24 |
| Finished | Oct 09 09:22:18 AM UTC 24 |
| Peak memory | 373240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334911724 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during _key_req.2334911724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2833743090 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 15346406 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 09:14:52 AM UTC 24 |
| Finished | Oct 09 09:14:54 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833743090 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2833743090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.1794709960 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2589209268 ps |
| CPU time | 69.95 seconds |
| Started | Oct 09 09:13:36 AM UTC 24 |
| Finished | Oct 09 09:14:48 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794709960 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.1794709960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.613700332 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6751377310 ps |
| CPU time | 601.11 seconds |
| Started | Oct 09 09:14:27 AM UTC 24 |
| Finished | Oct 09 09:24:35 AM UTC 24 |
| Peak memory | 381456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613700332 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.613700332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2839785944 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1149864940 ps |
| CPU time | 12.04 seconds |
| Started | Oct 09 09:14:22 AM UTC 24 |
| Finished | Oct 09 09:14:35 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839785944 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2839785944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3156500872 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 173082797 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 09:14:19 AM UTC 24 |
| Finished | Oct 09 09:14:22 AM UTC 24 |
| Peak memory | 221544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 156500872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma x_throughput.3156500872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2163417311 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 966076092 ps |
| CPU time | 7.22 seconds |
| Started | Oct 09 09:14:42 AM UTC 24 |
| Finished | Oct 09 09:14:50 AM UTC 24 |
| Peak memory | 223028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163417311 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.2163417311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1122743157 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1324821974 ps |
| CPU time | 6.85 seconds |
| Started | Oct 09 09:14:40 AM UTC 24 |
| Finished | Oct 09 09:14:47 AM UTC 24 |
| Peak memory | 212564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122743157 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.1122743157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3144820091 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3683490963 ps |
| CPU time | 337.97 seconds |
| Started | Oct 09 09:13:26 AM UTC 24 |
| Finished | Oct 09 09:19:08 AM UTC 24 |
| Peak memory | 383420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144820091 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.3144820091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2987001729 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2841377318 ps |
| CPU time | 84.15 seconds |
| Started | Oct 09 09:13:49 AM UTC 24 |
| Finished | Oct 09 09:15:15 AM UTC 24 |
| Peak memory | 350908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987001729 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.2987001729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.323754055 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 43774959107 ps |
| CPU time | 329.62 seconds |
| Started | Oct 09 09:13:56 AM UTC 24 |
| Finished | Oct 09 09:19:31 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323754055 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acce ss_b2b.323754055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2084336851 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 219805162 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 09:14:36 AM UTC 24 |
| Finished | Oct 09 09:14:39 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084336851 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2084336851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_readback_err.429763863 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 121551185 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 09:14:49 AM UTC 24 |
| Finished | Oct 09 09:14:52 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429763863 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_readback_err.429763863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.901925931 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2641891993 ps |
| CPU time | 94.85 seconds |
| Started | Oct 09 09:14:30 AM UTC 24 |
| Finished | Oct 09 09:16:07 AM UTC 24 |
| Peak memory | 311828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901925931 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.901925931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.628672836 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 131678147 ps |
| CPU time | 50.33 seconds |
| Started | Oct 09 09:13:26 AM UTC 24 |
| Finished | Oct 09 09:14:18 AM UTC 24 |
| Peak memory | 313812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628672836 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.628672836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.553804054 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 33365083228 ps |
| CPU time | 2650.55 seconds |
| Started | Oct 09 09:14:51 AM UTC 24 |
| Finished | Oct 09 09:59:32 AM UTC 24 |
| Peak memory | 385524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553804054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.553804054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4001679644 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1988589786 ps |
| CPU time | 134.23 seconds |
| Started | Oct 09 09:14:49 AM UTC 24 |
| Finished | Oct 09 09:17:06 AM UTC 24 |
| Peak memory | 326148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001679644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.4001679644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.928563587 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5759720944 ps |
| CPU time | 307.66 seconds |
| Started | Oct 09 09:13:43 AM UTC 24 |
| Finished | Oct 09 09:18:55 AM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928563587 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.928563587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.642569315 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 270388831 ps |
| CPU time | 67.75 seconds |
| Started | Oct 09 09:14:21 AM UTC 24 |
| Finished | Oct 09 09:15:30 AM UTC 24 |
| Peak memory | 366992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 642569315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_th roughput_w_partial_write.642569315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1362648654 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 458092255 ps |
| CPU time | 166.96 seconds |
| Started | Oct 09 09:16:18 AM UTC 24 |
| Finished | Oct 09 09:19:08 AM UTC 24 |
| Peak memory | 381560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362648654 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during _key_req.1362648654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2782409158 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 16829203 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 09:17:06 AM UTC 24 |
| Finished | Oct 09 09:17:08 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782409158 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2782409158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2207238938 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2737217039 ps |
| CPU time | 50.95 seconds |
| Started | Oct 09 09:15:23 AM UTC 24 |
| Finished | Oct 09 09:16:15 AM UTC 24 |
| Peak memory | 212924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207238938 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.2207238938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.854245781 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4459365394 ps |
| CPU time | 617.57 seconds |
| Started | Oct 09 09:16:24 AM UTC 24 |
| Finished | Oct 09 09:26:49 AM UTC 24 |
| Peak memory | 383488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854245781 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.854245781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.285419101 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2717251604 ps |
| CPU time | 5.1 seconds |
| Started | Oct 09 09:16:16 AM UTC 24 |
| Finished | Oct 09 09:16:23 AM UTC 24 |
| Peak memory | 222824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285419101 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.285419101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1946987331 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 216106846 ps |
| CPU time | 70.01 seconds |
| Started | Oct 09 09:15:56 AM UTC 24 |
| Finished | Oct 09 09:17:08 AM UTC 24 |
| Peak memory | 340432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 946987331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ma x_throughput.1946987331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2937378851 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 90645794 ps |
| CPU time | 7.11 seconds |
| Started | Oct 09 09:16:37 AM UTC 24 |
| Finished | Oct 09 09:16:45 AM UTC 24 |
| Peak memory | 222764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937378851 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.2937378851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3054539346 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 276995631 ps |
| CPU time | 7.23 seconds |
| Started | Oct 09 09:16:27 AM UTC 24 |
| Finished | Oct 09 09:16:36 AM UTC 24 |
| Peak memory | 212564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054539346 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.3054539346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.73002916 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 18723488211 ps |
| CPU time | 930.24 seconds |
| Started | Oct 09 09:15:16 AM UTC 24 |
| Finished | Oct 09 09:30:57 AM UTC 24 |
| Peak memory | 383612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73002916 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.73002916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3793754161 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 294213908 ps |
| CPU time | 8.09 seconds |
| Started | Oct 09 09:15:46 AM UTC 24 |
| Finished | Oct 09 09:15:55 AM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793754161 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.3793754161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2136231121 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 17535145356 ps |
| CPU time | 351.82 seconds |
| Started | Oct 09 09:15:53 AM UTC 24 |
| Finished | Oct 09 09:21:50 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136231121 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc ess_b2b.2136231121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.963358950 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 28721081 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 09:16:24 AM UTC 24 |
| Finished | Oct 09 09:16:27 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963358950 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.963358950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2948636739 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 30452663 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 09:16:46 AM UTC 24 |
| Finished | Oct 09 09:16:48 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948636739 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_readback_err.2948636739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.3221354395 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2680194829 ps |
| CPU time | 1127.56 seconds |
| Started | Oct 09 09:16:24 AM UTC 24 |
| Finished | Oct 09 09:35:26 AM UTC 24 |
| Peak memory | 385744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221354395 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3221354395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.1125794896 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 901289256 ps |
| CPU time | 55.57 seconds |
| Started | Oct 09 09:14:55 AM UTC 24 |
| Finished | Oct 09 09:15:53 AM UTC 24 |
| Peak memory | 326020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125794896 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1125794896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3151845512 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 78093490687 ps |
| CPU time | 4359.83 seconds |
| Started | Oct 09 09:16:51 AM UTC 24 |
| Finished | Oct 09 10:30:17 AM UTC 24 |
| Peak memory | 389112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315184551 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.3151845512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4175991936 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2998049314 ps |
| CPU time | 854.19 seconds |
| Started | Oct 09 09:16:49 AM UTC 24 |
| Finished | Oct 09 09:31:12 AM UTC 24 |
| Peak memory | 387856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175991936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.4175991936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2899070897 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 6907450466 ps |
| CPU time | 308 seconds |
| Started | Oct 09 09:15:32 AM UTC 24 |
| Finished | Oct 09 09:20:44 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899070897 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2899070897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1655988113 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 418814150 ps |
| CPU time | 95.3 seconds |
| Started | Oct 09 09:16:08 AM UTC 24 |
| Finished | Oct 09 09:17:46 AM UTC 24 |
| Peak memory | 379268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1655988113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t hroughput_w_partial_write.1655988113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1423035360 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1415951006 ps |
| CPU time | 571.86 seconds |
| Started | Oct 09 09:17:55 AM UTC 24 |
| Finished | Oct 09 09:27:35 AM UTC 24 |
| Peak memory | 383360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423035360 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during _key_req.1423035360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.679668066 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 21362716 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 09:18:43 AM UTC 24 |
| Finished | Oct 09 09:18:45 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679668066 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.679668066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2995319602 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1069158027 ps |
| CPU time | 72.55 seconds |
| Started | Oct 09 09:17:10 AM UTC 24 |
| Finished | Oct 09 09:18:24 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995319602 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.2995319602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.3657361573 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 6419947158 ps |
| CPU time | 847.31 seconds |
| Started | Oct 09 09:17:59 AM UTC 24 |
| Finished | Oct 09 09:32:16 AM UTC 24 |
| Peak memory | 379392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657361573 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.3657361573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3952806476 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 684221574 ps |
| CPU time | 6.83 seconds |
| Started | Oct 09 09:17:46 AM UTC 24 |
| Finished | Oct 09 09:17:54 AM UTC 24 |
| Peak memory | 212612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952806476 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.3952806476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3129407825 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 101466361 ps |
| CPU time | 34.38 seconds |
| Started | Oct 09 09:17:35 AM UTC 24 |
| Finished | Oct 09 09:18:12 AM UTC 24 |
| Peak memory | 314072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 129407825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma x_throughput.3129407825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3530897482 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1994741108 ps |
| CPU time | 8.61 seconds |
| Started | Oct 09 09:18:29 AM UTC 24 |
| Finished | Oct 09 09:18:39 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530897482 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.3530897482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.659545357 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3378727231 ps |
| CPU time | 12.49 seconds |
| Started | Oct 09 09:18:28 AM UTC 24 |
| Finished | Oct 09 09:18:42 AM UTC 24 |
| Peak memory | 222988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659545357 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.659545357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1268511511 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 90576026 ps |
| CPU time | 17.02 seconds |
| Started | Oct 09 09:17:25 AM UTC 24 |
| Finished | Oct 09 09:17:43 AM UTC 24 |
| Peak memory | 266616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268511511 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.1268511511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3528332325 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 12835672500 ps |
| CPU time | 375.91 seconds |
| Started | Oct 09 09:17:27 AM UTC 24 |
| Finished | Oct 09 09:23:48 AM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528332325 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc ess_b2b.3528332325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1148089080 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 31427805 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 09:18:25 AM UTC 24 |
| Finished | Oct 09 09:18:27 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148089080 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1148089080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_readback_err.845502099 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 37644997 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 09:18:38 AM UTC 24 |
| Finished | Oct 09 09:18:41 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845502099 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_readback_err.845502099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.3035953050 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 59149911593 ps |
| CPU time | 1742.91 seconds |
| Started | Oct 09 09:18:13 AM UTC 24 |
| Finished | Oct 09 09:47:36 AM UTC 24 |
| Peak memory | 385484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035953050 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3035953050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.268588509 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 129125905 ps |
| CPU time | 102.07 seconds |
| Started | Oct 09 09:17:07 AM UTC 24 |
| Finished | Oct 09 09:18:52 AM UTC 24 |
| Peak memory | 375448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268588509 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.268588509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.402236388 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 18057640224 ps |
| CPU time | 1469.28 seconds |
| Started | Oct 09 09:18:42 AM UTC 24 |
| Finished | Oct 09 09:43:28 AM UTC 24 |
| Peak memory | 385732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402236388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.402236388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2898758009 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 7805857475 ps |
| CPU time | 69.98 seconds |
| Started | Oct 09 09:18:40 AM UTC 24 |
| Finished | Oct 09 09:19:51 AM UTC 24 |
| Peak memory | 225204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898758009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2898758009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.563377028 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3795909199 ps |
| CPU time | 375.05 seconds |
| Started | Oct 09 09:17:17 AM UTC 24 |
| Finished | Oct 09 09:23:37 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563377028 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.563377028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.346991248 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 257762575 ps |
| CPU time | 59.61 seconds |
| Started | Oct 09 09:17:44 AM UTC 24 |
| Finished | Oct 09 09:18:46 AM UTC 24 |
| Peak memory | 362944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 346991248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_th roughput_w_partial_write.346991248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.4257775205 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 50888054449 ps |
| CPU time | 944.68 seconds |
| Started | Oct 09 08:50:21 AM UTC 24 |
| Finished | Oct 09 09:06:16 AM UTC 24 |
| Peak memory | 385740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257775205 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_ key_req.4257775205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.4089269700 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12640281 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 08:50:46 AM UTC 24 |
| Finished | Oct 09 08:50:48 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089269700 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4089269700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2088726082 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 10397472831 ps |
| CPU time | 56.07 seconds |
| Started | Oct 09 08:50:07 AM UTC 24 |
| Finished | Oct 09 08:51:05 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088726082 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.2088726082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1547928543 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 7657602156 ps |
| CPU time | 475 seconds |
| Started | Oct 09 08:50:25 AM UTC 24 |
| Finished | Oct 09 08:58:26 AM UTC 24 |
| Peak memory | 383492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547928543 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.1547928543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4030951623 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2249742027 ps |
| CPU time | 11.42 seconds |
| Started | Oct 09 08:50:20 AM UTC 24 |
| Finished | Oct 09 08:50:32 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030951623 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.4030951623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.4149719974 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 88951015 ps |
| CPU time | 29.01 seconds |
| Started | Oct 09 08:50:15 AM UTC 24 |
| Finished | Oct 09 08:50:45 AM UTC 24 |
| Peak memory | 287192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 149719974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max _throughput.4149719974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.107940061 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 373551581 ps |
| CPU time | 5.25 seconds |
| Started | Oct 09 08:50:34 AM UTC 24 |
| Finished | Oct 09 08:50:40 AM UTC 24 |
| Peak memory | 222764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107940061 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.107940061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3297009471 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 364325108 ps |
| CPU time | 9.16 seconds |
| Started | Oct 09 08:50:34 AM UTC 24 |
| Finished | Oct 09 08:50:44 AM UTC 24 |
| Peak memory | 222800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297009471 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.3297009471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.3396499361 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 15694038900 ps |
| CPU time | 668.74 seconds |
| Started | Oct 09 08:50:06 AM UTC 24 |
| Finished | Oct 09 09:01:23 AM UTC 24 |
| Peak memory | 350668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396499361 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.3396499361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1322462084 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1231209398 ps |
| CPU time | 9.59 seconds |
| Started | Oct 09 08:50:09 AM UTC 24 |
| Finished | Oct 09 08:50:20 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322462084 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.1322462084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1170994700 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 73091435 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 08:50:31 AM UTC 24 |
| Finished | Oct 09 08:50:34 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170994700 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1170994700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_readback_err.2638365370 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 103969753 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 08:50:35 AM UTC 24 |
| Finished | Oct 09 08:50:38 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638365370 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_readback_err.2638365370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.3296713811 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 51584749850 ps |
| CPU time | 585.55 seconds |
| Started | Oct 09 08:50:26 AM UTC 24 |
| Finished | Oct 09 09:00:18 AM UTC 24 |
| Peak memory | 381388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296713811 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3296713811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3076953609 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 886992540 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 08:50:45 AM UTC 24 |
| Finished | Oct 09 08:50:51 AM UTC 24 |
| Peak memory | 248352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076953609 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3076953609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.3998922530 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 793114398 ps |
| CPU time | 18.16 seconds |
| Started | Oct 09 08:50:05 AM UTC 24 |
| Finished | Oct 09 08:50:24 AM UTC 24 |
| Peak memory | 212912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998922530 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3998922530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3395346549 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 16230538298 ps |
| CPU time | 2897.99 seconds |
| Started | Oct 09 08:50:42 AM UTC 24 |
| Finished | Oct 09 09:39:29 AM UTC 24 |
| Peak memory | 383620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339534654 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.3395346549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2747114521 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12978485834 ps |
| CPU time | 89.28 seconds |
| Started | Oct 09 08:50:39 AM UTC 24 |
| Finished | Oct 09 08:52:11 AM UTC 24 |
| Peak memory | 287300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747114521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2747114521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1901289736 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2050716372 ps |
| CPU time | 224.8 seconds |
| Started | Oct 09 08:50:08 AM UTC 24 |
| Finished | Oct 09 08:53:57 AM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901289736 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.1901289736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4206919581 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 171229689 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 08:50:16 AM UTC 24 |
| Finished | Oct 09 08:50:19 AM UTC 24 |
| Peak memory | 222604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4206919581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th roughput_w_partial_write.4206919581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2976284648 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3761216821 ps |
| CPU time | 857 seconds |
| Started | Oct 09 09:19:09 AM UTC 24 |
| Finished | Oct 09 09:33:37 AM UTC 24 |
| Peak memory | 383504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976284648 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during _key_req.2976284648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.86417321 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 11857592 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 09:19:39 AM UTC 24 |
| Finished | Oct 09 09:19:41 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86417321 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.86417321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3347738809 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 8618455798 ps |
| CPU time | 84.49 seconds |
| Started | Oct 09 09:18:52 AM UTC 24 |
| Finished | Oct 09 09:20:19 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347738809 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3347738809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.4045288151 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 32966824346 ps |
| CPU time | 443.43 seconds |
| Started | Oct 09 09:19:11 AM UTC 24 |
| Finished | Oct 09 09:26:40 AM UTC 24 |
| Peak memory | 377348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045288151 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.4045288151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.74139984 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 207349414 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 09:19:08 AM UTC 24 |
| Finished | Oct 09 09:19:13 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74139984 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.74139984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1981104413 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 380732533 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 09:19:07 AM UTC 24 |
| Finished | Oct 09 09:19:09 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 981104413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ma x_throughput.1981104413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3484258001 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 88659464 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 09:19:31 AM UTC 24 |
| Finished | Oct 09 09:19:37 AM UTC 24 |
| Peak memory | 223032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484258001 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3484258001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.727073128 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 960119751 ps |
| CPU time | 6.49 seconds |
| Started | Oct 09 09:19:29 AM UTC 24 |
| Finished | Oct 09 09:19:38 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727073128 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.727073128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.211043656 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3657670843 ps |
| CPU time | 265.53 seconds |
| Started | Oct 09 09:18:47 AM UTC 24 |
| Finished | Oct 09 09:23:17 AM UTC 24 |
| Peak memory | 381448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211043656 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.211043656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3175809474 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 508102166 ps |
| CPU time | 62.97 seconds |
| Started | Oct 09 09:18:57 AM UTC 24 |
| Finished | Oct 09 09:20:01 AM UTC 24 |
| Peak memory | 332212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175809474 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.3175809474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2436638802 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 32548384331 ps |
| CPU time | 508.02 seconds |
| Started | Oct 09 09:19:03 AM UTC 24 |
| Finished | Oct 09 09:27:38 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436638802 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc ess_b2b.2436638802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.125668827 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 31926015 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 09:19:27 AM UTC 24 |
| Finished | Oct 09 09:19:30 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125668827 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.125668827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_readback_err.1383143360 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 30010656 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 09:19:32 AM UTC 24 |
| Finished | Oct 09 09:19:35 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383143360 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_readback_err.1383143360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.410310037 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 77679306031 ps |
| CPU time | 1342.56 seconds |
| Started | Oct 09 09:19:14 AM UTC 24 |
| Finished | Oct 09 09:41:51 AM UTC 24 |
| Peak memory | 385556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410310037 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.410310037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2646378763 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 243856129 ps |
| CPU time | 18.57 seconds |
| Started | Oct 09 09:18:46 AM UTC 24 |
| Finished | Oct 09 09:19:06 AM UTC 24 |
| Peak memory | 212848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646378763 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2646378763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3709568472 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 39734922596 ps |
| CPU time | 1503.63 seconds |
| Started | Oct 09 09:19:38 AM UTC 24 |
| Finished | Oct 09 09:44:58 AM UTC 24 |
| Peak memory | 379392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370956847 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.3709568472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4049441558 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2303965915 ps |
| CPU time | 349.84 seconds |
| Started | Oct 09 09:19:36 AM UTC 24 |
| Finished | Oct 09 09:25:31 AM UTC 24 |
| Peak memory | 383696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049441558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.4049441558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.101426426 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2833486628 ps |
| CPU time | 288.34 seconds |
| Started | Oct 09 09:18:53 AM UTC 24 |
| Finished | Oct 09 09:23:46 AM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101426426 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.101426426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2987075401 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1810054432 ps |
| CPU time | 18.67 seconds |
| Started | Oct 09 09:19:08 AM UTC 24 |
| Finished | Oct 09 09:19:28 AM UTC 24 |
| Peak memory | 297420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2987075401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t hroughput_w_partial_write.2987075401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.4134238187 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 9865945156 ps |
| CPU time | 386.57 seconds |
| Started | Oct 09 09:20:17 AM UTC 24 |
| Finished | Oct 09 09:26:49 AM UTC 24 |
| Peak memory | 383756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134238187 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during _key_req.4134238187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2717997679 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 54450935 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 09:20:44 AM UTC 24 |
| Finished | Oct 09 09:20:47 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717997679 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2717997679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2117091092 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3866788594 ps |
| CPU time | 22.09 seconds |
| Started | Oct 09 09:19:52 AM UTC 24 |
| Finished | Oct 09 09:20:16 AM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117091092 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.2117091092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1773349025 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 8520401512 ps |
| CPU time | 737.92 seconds |
| Started | Oct 09 09:20:19 AM UTC 24 |
| Finished | Oct 09 09:32:46 AM UTC 24 |
| Peak memory | 377264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773349025 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.1773349025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3085414729 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 154382891 ps |
| CPU time | 3.46 seconds |
| Started | Oct 09 09:20:17 AM UTC 24 |
| Finished | Oct 09 09:20:22 AM UTC 24 |
| Peak memory | 222784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085414729 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.3085414729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3472452882 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 351183169 ps |
| CPU time | 36.01 seconds |
| Started | Oct 09 09:20:06 AM UTC 24 |
| Finished | Oct 09 09:20:43 AM UTC 24 |
| Peak memory | 303552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 472452882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma x_throughput.3472452882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.407601813 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 151051234 ps |
| CPU time | 7.07 seconds |
| Started | Oct 09 09:20:36 AM UTC 24 |
| Finished | Oct 09 09:20:44 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407601813 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.407601813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.630551901 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1245850270 ps |
| CPU time | 7.72 seconds |
| Started | Oct 09 09:20:26 AM UTC 24 |
| Finished | Oct 09 09:20:35 AM UTC 24 |
| Peak memory | 224852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630551901 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.630551901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1155813326 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 26818446371 ps |
| CPU time | 1218.54 seconds |
| Started | Oct 09 09:19:49 AM UTC 24 |
| Finished | Oct 09 09:40:21 AM UTC 24 |
| Peak memory | 385620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155813326 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.1155813326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2325292991 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 212892420 ps |
| CPU time | 4.46 seconds |
| Started | Oct 09 09:20:02 AM UTC 24 |
| Finished | Oct 09 09:20:08 AM UTC 24 |
| Peak memory | 212848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325292991 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2325292991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1414773699 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 17644526013 ps |
| CPU time | 434.03 seconds |
| Started | Oct 09 09:20:03 AM UTC 24 |
| Finished | Oct 09 09:27:22 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414773699 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc ess_b2b.1414773699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.418725205 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 150146389 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 09:20:23 AM UTC 24 |
| Finished | Oct 09 09:20:25 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418725205 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.418725205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_readback_err.2587586028 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 83715575 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 09:20:39 AM UTC 24 |
| Finished | Oct 09 09:20:42 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587586028 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_readback_err.2587586028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1979504386 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 16339413367 ps |
| CPU time | 84.43 seconds |
| Started | Oct 09 09:20:20 AM UTC 24 |
| Finished | Oct 09 09:21:47 AM UTC 24 |
| Peak memory | 332380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979504386 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1979504386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.58306364 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 358567436 ps |
| CPU time | 8.74 seconds |
| Started | Oct 09 09:19:42 AM UTC 24 |
| Finished | Oct 09 09:19:52 AM UTC 24 |
| Peak memory | 242084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58306364 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.58306364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.671788527 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 25536163474 ps |
| CPU time | 1145.38 seconds |
| Started | Oct 09 09:20:42 AM UTC 24 |
| Finished | Oct 09 09:40:01 AM UTC 24 |
| Peak memory | 383492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671788527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.671788527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.37847493 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3849588046 ps |
| CPU time | 301.35 seconds |
| Started | Oct 09 09:19:53 AM UTC 24 |
| Finished | Oct 09 09:24:59 AM UTC 24 |
| Peak memory | 212576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37847493 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.37847493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2671157346 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 182145961 ps |
| CPU time | 81.95 seconds |
| Started | Oct 09 09:20:09 AM UTC 24 |
| Finished | Oct 09 09:21:33 AM UTC 24 |
| Peak memory | 373384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2671157346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_t hroughput_w_partial_write.2671157346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1056526720 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 14976891373 ps |
| CPU time | 751.47 seconds |
| Started | Oct 09 09:21:55 AM UTC 24 |
| Finished | Oct 09 09:34:35 AM UTC 24 |
| Peak memory | 371216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056526720 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during _key_req.1056526720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4040446595 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 41039086 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 09:22:18 AM UTC 24 |
| Finished | Oct 09 09:22:20 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040446595 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.4040446595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3387532579 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 29026144194 ps |
| CPU time | 72.35 seconds |
| Started | Oct 09 09:20:48 AM UTC 24 |
| Finished | Oct 09 09:22:02 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387532579 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.3387532579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.2819240650 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 5282325672 ps |
| CPU time | 779.66 seconds |
| Started | Oct 09 09:22:00 AM UTC 24 |
| Finished | Oct 09 09:35:08 AM UTC 24 |
| Peak memory | 379600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819240650 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.2819240650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.4177242258 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 121957050 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 09:21:51 AM UTC 24 |
| Finished | Oct 09 09:21:54 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177242258 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.4177242258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1000263304 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 393320134 ps |
| CPU time | 46.72 seconds |
| Started | Oct 09 09:21:47 AM UTC 24 |
| Finished | Oct 09 09:22:36 AM UTC 24 |
| Peak memory | 311764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 000263304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ma x_throughput.1000263304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1865579903 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 339230732 ps |
| CPU time | 8.93 seconds |
| Started | Oct 09 09:22:06 AM UTC 24 |
| Finished | Oct 09 09:22:17 AM UTC 24 |
| Peak memory | 222840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865579903 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.1865579903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.475743085 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1774422860 ps |
| CPU time | 11.79 seconds |
| Started | Oct 09 09:22:03 AM UTC 24 |
| Finished | Oct 09 09:22:16 AM UTC 24 |
| Peak memory | 222800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475743085 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.475743085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.555188831 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1907789094 ps |
| CPU time | 111.42 seconds |
| Started | Oct 09 09:20:46 AM UTC 24 |
| Finished | Oct 09 09:22:39 AM UTC 24 |
| Peak memory | 303452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555188831 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.555188831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4013892293 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1933964001 ps |
| CPU time | 31.8 seconds |
| Started | Oct 09 09:21:34 AM UTC 24 |
| Finished | Oct 09 09:22:08 AM UTC 24 |
| Peak memory | 293276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013892293 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.4013892293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1534523682 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 4640544571 ps |
| CPU time | 405.21 seconds |
| Started | Oct 09 09:21:38 AM UTC 24 |
| Finished | Oct 09 09:28:29 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534523682 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc ess_b2b.1534523682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3921730012 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 136397928 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 09:22:03 AM UTC 24 |
| Finished | Oct 09 09:22:05 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921730012 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3921730012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_readback_err.2928001539 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 189887734 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 09:22:09 AM UTC 24 |
| Finished | Oct 09 09:22:11 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928001539 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_readback_err.2928001539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.2355738799 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1830242628 ps |
| CPU time | 605.4 seconds |
| Started | Oct 09 09:22:02 AM UTC 24 |
| Finished | Oct 09 09:32:15 AM UTC 24 |
| Peak memory | 385760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355738799 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2355738799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.2341137520 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3077026278 ps |
| CPU time | 60.51 seconds |
| Started | Oct 09 09:20:46 AM UTC 24 |
| Finished | Oct 09 09:21:48 AM UTC 24 |
| Peak memory | 340420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341137520 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2341137520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1133722604 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 27622060935 ps |
| CPU time | 2671.57 seconds |
| Started | Oct 09 09:22:17 AM UTC 24 |
| Finished | Oct 09 10:07:18 AM UTC 24 |
| Peak memory | 387140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113372260 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.1133722604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4181334842 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1954626246 ps |
| CPU time | 562.9 seconds |
| Started | Oct 09 09:22:13 AM UTC 24 |
| Finished | Oct 09 09:31:43 AM UTC 24 |
| Peak memory | 389588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181334842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.4181334842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.821866482 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2594636510 ps |
| CPU time | 269.72 seconds |
| Started | Oct 09 09:21:02 AM UTC 24 |
| Finished | Oct 09 09:25:36 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821866482 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.821866482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2088967610 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 269199176 ps |
| CPU time | 9.29 seconds |
| Started | Oct 09 09:21:49 AM UTC 24 |
| Finished | Oct 09 09:21:59 AM UTC 24 |
| Peak memory | 262608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2088967610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t hroughput_w_partial_write.2088967610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2672197940 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3278686203 ps |
| CPU time | 755.18 seconds |
| Started | Oct 09 09:23:18 AM UTC 24 |
| Finished | Oct 09 09:36:02 AM UTC 24 |
| Peak memory | 383432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672197940 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during _key_req.2672197940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4287339121 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 46150597 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 09:24:09 AM UTC 24 |
| Finished | Oct 09 09:24:11 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287339121 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.4287339121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2336486646 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 16695200693 ps |
| CPU time | 113.87 seconds |
| Started | Oct 09 09:22:27 AM UTC 24 |
| Finished | Oct 09 09:24:24 AM UTC 24 |
| Peak memory | 212844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336486646 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.2336486646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1015263425 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 15958868568 ps |
| CPU time | 844.2 seconds |
| Started | Oct 09 09:23:26 AM UTC 24 |
| Finished | Oct 09 09:37:40 AM UTC 24 |
| Peak memory | 383512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015263425 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.1015263425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1535148010 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1676075659 ps |
| CPU time | 11.21 seconds |
| Started | Oct 09 09:23:13 AM UTC 24 |
| Finished | Oct 09 09:23:25 AM UTC 24 |
| Peak memory | 212600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535148010 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.1535148010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2379628520 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 139304625 ps |
| CPU time | 79.41 seconds |
| Started | Oct 09 09:22:50 AM UTC 24 |
| Finished | Oct 09 09:24:11 AM UTC 24 |
| Peak memory | 379536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 379628520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma x_throughput.2379628520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.1979557157 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 96027268 ps |
| CPU time | 4 seconds |
| Started | Oct 09 09:23:51 AM UTC 24 |
| Finished | Oct 09 09:23:56 AM UTC 24 |
| Peak memory | 222788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979557157 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.1979557157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2904666026 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4753738851 ps |
| CPU time | 17.87 seconds |
| Started | Oct 09 09:23:50 AM UTC 24 |
| Finished | Oct 09 09:24:09 AM UTC 24 |
| Peak memory | 222932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904666026 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2904666026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3355829415 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 40676871592 ps |
| CPU time | 741.47 seconds |
| Started | Oct 09 09:22:21 AM UTC 24 |
| Finished | Oct 09 09:34:51 AM UTC 24 |
| Peak memory | 371412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355829415 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.3355829415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.3059226189 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 253144074 ps |
| CPU time | 10.9 seconds |
| Started | Oct 09 09:22:37 AM UTC 24 |
| Finished | Oct 09 09:22:49 AM UTC 24 |
| Peak memory | 244244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059226189 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.3059226189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3162197377 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 12203091397 ps |
| CPU time | 234.33 seconds |
| Started | Oct 09 09:22:40 AM UTC 24 |
| Finished | Oct 09 09:26:38 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162197377 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acc ess_b2b.3162197377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.4147168290 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 43021376 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 09:23:47 AM UTC 24 |
| Finished | Oct 09 09:23:49 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147168290 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.4147168290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_readback_err.767133333 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 29212102 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 09:23:51 AM UTC 24 |
| Finished | Oct 09 09:23:53 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767133333 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_readback_err.767133333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.4030688623 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2220392302 ps |
| CPU time | 988.18 seconds |
| Started | Oct 09 09:23:38 AM UTC 24 |
| Finished | Oct 09 09:40:18 AM UTC 24 |
| Peak memory | 385684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030688623 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.4030688623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.47130437 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 722596712 ps |
| CPU time | 5.81 seconds |
| Started | Oct 09 09:22:19 AM UTC 24 |
| Finished | Oct 09 09:22:26 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47130437 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.47130437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3583975397 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 10146295524 ps |
| CPU time | 3572.72 seconds |
| Started | Oct 09 09:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:11 AM UTC 24 |
| Peak memory | 387024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358397539 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.3583975397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.45026245 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2693990411 ps |
| CPU time | 75.32 seconds |
| Started | Oct 09 09:23:54 AM UTC 24 |
| Finished | Oct 09 09:25:11 AM UTC 24 |
| Peak memory | 315864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45026245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.45026245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1951502359 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 6176257558 ps |
| CPU time | 342 seconds |
| Started | Oct 09 09:22:37 AM UTC 24 |
| Finished | Oct 09 09:28:24 AM UTC 24 |
| Peak memory | 212580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951502359 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1951502359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1762206453 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 136886288 ps |
| CPU time | 71.59 seconds |
| Started | Oct 09 09:23:12 AM UTC 24 |
| Finished | Oct 09 09:24:25 AM UTC 24 |
| Peak memory | 354768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1762206453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_t hroughput_w_partial_write.1762206453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.4204704684 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 21146972050 ps |
| CPU time | 1441.31 seconds |
| Started | Oct 09 09:25:19 AM UTC 24 |
| Finished | Oct 09 09:49:36 AM UTC 24 |
| Peak memory | 383760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204704684 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during _key_req.4204704684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3521210016 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 15846886 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 09:26:21 AM UTC 24 |
| Finished | Oct 09 09:26:23 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521210016 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3521210016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1764034076 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 23243942546 ps |
| CPU time | 64.08 seconds |
| Started | Oct 09 09:24:25 AM UTC 24 |
| Finished | Oct 09 09:25:30 AM UTC 24 |
| Peak memory | 212688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764034076 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.1764034076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.326022000 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5546174356 ps |
| CPU time | 474.5 seconds |
| Started | Oct 09 09:25:28 AM UTC 24 |
| Finished | Oct 09 09:33:29 AM UTC 24 |
| Peak memory | 360888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326022000 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.326022000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2983218468 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 253687605 ps |
| CPU time | 4 seconds |
| Started | Oct 09 09:25:13 AM UTC 24 |
| Finished | Oct 09 09:25:18 AM UTC 24 |
| Peak memory | 212548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983218468 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.2983218468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.544905426 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 96773170 ps |
| CPU time | 36.47 seconds |
| Started | Oct 09 09:24:48 AM UTC 24 |
| Finished | Oct 09 09:25:26 AM UTC 24 |
| Peak memory | 307596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 44905426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_max _throughput.544905426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1855575344 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 109446299 ps |
| CPU time | 4.75 seconds |
| Started | Oct 09 09:25:36 AM UTC 24 |
| Finished | Oct 09 09:25:42 AM UTC 24 |
| Peak memory | 222848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855575344 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.1855575344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1372970216 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1677395007 ps |
| CPU time | 15.13 seconds |
| Started | Oct 09 09:25:35 AM UTC 24 |
| Finished | Oct 09 09:25:52 AM UTC 24 |
| Peak memory | 222736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372970216 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.1372970216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3426234197 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 28577070462 ps |
| CPU time | 862.83 seconds |
| Started | Oct 09 09:24:12 AM UTC 24 |
| Finished | Oct 09 09:38:46 AM UTC 24 |
| Peak memory | 350916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426234197 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.3426234197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4007909257 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1933056162 ps |
| CPU time | 105.84 seconds |
| Started | Oct 09 09:24:32 AM UTC 24 |
| Finished | Oct 09 09:26:20 AM UTC 24 |
| Peak memory | 375172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007909257 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.4007909257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1378346301 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5493535544 ps |
| CPU time | 429.49 seconds |
| Started | Oct 09 09:24:36 AM UTC 24 |
| Finished | Oct 09 09:31:51 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378346301 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc ess_b2b.1378346301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1824110943 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 118906411 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 09:25:32 AM UTC 24 |
| Finished | Oct 09 09:25:34 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824110943 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1824110943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3158202568 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 47961319 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 09:25:43 AM UTC 24 |
| Finished | Oct 09 09:25:46 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158202568 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_readback_err.3158202568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.350430610 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 146599696222 ps |
| CPU time | 1034.44 seconds |
| Started | Oct 09 09:25:31 AM UTC 24 |
| Finished | Oct 09 09:42:57 AM UTC 24 |
| Peak memory | 383492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350430610 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.350430610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3401981713 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2293545919 ps |
| CPU time | 17.37 seconds |
| Started | Oct 09 09:24:12 AM UTC 24 |
| Finished | Oct 09 09:24:31 AM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401981713 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3401981713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.434064425 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 53647876767 ps |
| CPU time | 3667.95 seconds |
| Started | Oct 09 09:25:53 AM UTC 24 |
| Finished | Oct 09 10:27:39 AM UTC 24 |
| Peak memory | 386952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434064425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.434064425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2930445698 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1974414760 ps |
| CPU time | 258.45 seconds |
| Started | Oct 09 09:24:26 AM UTC 24 |
| Finished | Oct 09 09:28:48 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930445698 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.2930445698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1996003818 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 558232573 ps |
| CPU time | 77.03 seconds |
| Started | Oct 09 09:25:00 AM UTC 24 |
| Finished | Oct 09 09:26:20 AM UTC 24 |
| Peak memory | 371016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1996003818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t hroughput_w_partial_write.1996003818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.722147954 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 9636831282 ps |
| CPU time | 327.92 seconds |
| Started | Oct 09 09:27:23 AM UTC 24 |
| Finished | Oct 09 09:32:55 AM UTC 24 |
| Peak memory | 367128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722147954 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during_ key_req.722147954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1797509091 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 23495569 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 09:27:50 AM UTC 24 |
| Finished | Oct 09 09:27:52 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797509091 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1797509091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1281904747 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 11554818568 ps |
| CPU time | 87.12 seconds |
| Started | Oct 09 09:26:39 AM UTC 24 |
| Finished | Oct 09 09:28:08 AM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281904747 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.1281904747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.1226047644 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3264063774 ps |
| CPU time | 874.9 seconds |
| Started | Oct 09 09:27:24 AM UTC 24 |
| Finished | Oct 09 09:42:10 AM UTC 24 |
| Peak memory | 375508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226047644 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.1226047644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3140241811 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 187490559 ps |
| CPU time | 5.05 seconds |
| Started | Oct 09 09:27:15 AM UTC 24 |
| Finished | Oct 09 09:27:21 AM UTC 24 |
| Peak memory | 225076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140241811 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.3140241811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1087592613 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 400269559 ps |
| CPU time | 22.94 seconds |
| Started | Oct 09 09:26:50 AM UTC 24 |
| Finished | Oct 09 09:27:14 AM UTC 24 |
| Peak memory | 301520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 087592613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma x_throughput.1087592613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.49659654 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 727579874 ps |
| CPU time | 5.25 seconds |
| Started | Oct 09 09:27:35 AM UTC 24 |
| Finished | Oct 09 09:27:42 AM UTC 24 |
| Peak memory | 222844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49659654 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.49659654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.4054964759 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 8732803289 ps |
| CPU time | 14.44 seconds |
| Started | Oct 09 09:27:35 AM UTC 24 |
| Finished | Oct 09 09:27:51 AM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054964759 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.4054964759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3690186910 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 62262407121 ps |
| CPU time | 1229.22 seconds |
| Started | Oct 09 09:26:24 AM UTC 24 |
| Finished | Oct 09 09:47:07 AM UTC 24 |
| Peak memory | 371204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690186910 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.3690186910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2767083406 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 426365106 ps |
| CPU time | 38.89 seconds |
| Started | Oct 09 09:26:50 AM UTC 24 |
| Finished | Oct 09 09:27:30 AM UTC 24 |
| Peak memory | 305544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767083406 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.2767083406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3146451659 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 29342185098 ps |
| CPU time | 350.43 seconds |
| Started | Oct 09 09:26:50 AM UTC 24 |
| Finished | Oct 09 09:32:45 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146451659 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc ess_b2b.3146451659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3234340652 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 85032808 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 09:27:32 AM UTC 24 |
| Finished | Oct 09 09:27:35 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234340652 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3234340652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2921336478 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 32423882 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 09:27:39 AM UTC 24 |
| Finished | Oct 09 09:27:41 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921336478 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_readback_err.2921336478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.725780307 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 11142288443 ps |
| CPU time | 912.61 seconds |
| Started | Oct 09 09:27:31 AM UTC 24 |
| Finished | Oct 09 09:42:54 AM UTC 24 |
| Peak memory | 379616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725780307 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.725780307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1187417820 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1977284205 ps |
| CPU time | 26.03 seconds |
| Started | Oct 09 09:26:21 AM UTC 24 |
| Finished | Oct 09 09:26:49 AM UTC 24 |
| Peak memory | 212688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187417820 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1187417820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.265355924 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 19184525922 ps |
| CPU time | 1399.94 seconds |
| Started | Oct 09 09:27:43 AM UTC 24 |
| Finished | Oct 09 09:51:17 AM UTC 24 |
| Peak memory | 393644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265355924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.265355924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3474389689 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1404670706 ps |
| CPU time | 163.51 seconds |
| Started | Oct 09 09:27:43 AM UTC 24 |
| Finished | Oct 09 09:30:29 AM UTC 24 |
| Peak memory | 371072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474389689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3474389689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2061424290 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 8572661561 ps |
| CPU time | 262.34 seconds |
| Started | Oct 09 09:26:41 AM UTC 24 |
| Finished | Oct 09 09:31:07 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061424290 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.2061424290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2198668936 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1823058937 ps |
| CPU time | 85.58 seconds |
| Started | Oct 09 09:27:14 AM UTC 24 |
| Finished | Oct 09 09:28:42 AM UTC 24 |
| Peak memory | 379272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2198668936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t hroughput_w_partial_write.2198668936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.299166077 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3060822884 ps |
| CPU time | 1133.35 seconds |
| Started | Oct 09 09:28:42 AM UTC 24 |
| Finished | Oct 09 09:47:49 AM UTC 24 |
| Peak memory | 383476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299166077 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_ key_req.299166077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2505765458 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 16259094 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 09:30:58 AM UTC 24 |
| Finished | Oct 09 09:31:00 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505765458 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2505765458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.4126424281 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 642361563 ps |
| CPU time | 32.73 seconds |
| Started | Oct 09 09:27:56 AM UTC 24 |
| Finished | Oct 09 09:28:31 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126424281 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.4126424281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3909492194 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 55952968159 ps |
| CPU time | 989.43 seconds |
| Started | Oct 09 09:28:49 AM UTC 24 |
| Finished | Oct 09 09:45:30 AM UTC 24 |
| Peak memory | 379360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909492194 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.3909492194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3968116235 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 336012504 ps |
| CPU time | 6.43 seconds |
| Started | Oct 09 09:28:41 AM UTC 24 |
| Finished | Oct 09 09:28:49 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968116235 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.3968116235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.123899643 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 81714284 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 09:28:32 AM UTC 24 |
| Finished | Oct 09 09:28:38 AM UTC 24 |
| Peak memory | 246212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 23899643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_max _throughput.123899643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3213877 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 229049189 ps |
| CPU time | 4.15 seconds |
| Started | Oct 09 09:29:10 AM UTC 24 |
| Finished | Oct 09 09:29:15 AM UTC 24 |
| Peak memory | 223060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213877 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.3213877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1381306505 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3431568592 ps |
| CPU time | 12.36 seconds |
| Started | Oct 09 09:28:56 AM UTC 24 |
| Finished | Oct 09 09:29:09 AM UTC 24 |
| Peak memory | 222988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381306505 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.1381306505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.2537157106 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 21200023611 ps |
| CPU time | 867.32 seconds |
| Started | Oct 09 09:27:53 AM UTC 24 |
| Finished | Oct 09 09:42:30 AM UTC 24 |
| Peak memory | 383484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537157106 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.2537157106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2511877462 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2527637429 ps |
| CPU time | 14.31 seconds |
| Started | Oct 09 09:28:25 AM UTC 24 |
| Finished | Oct 09 09:28:40 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511877462 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.2511877462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.358235900 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 16271103585 ps |
| CPU time | 471.38 seconds |
| Started | Oct 09 09:28:30 AM UTC 24 |
| Finished | Oct 09 09:36:28 AM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358235900 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acce ss_b2b.358235900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1197526685 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 27547186 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 09:28:53 AM UTC 24 |
| Finished | Oct 09 09:28:55 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197526685 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1197526685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_readback_err.1721215955 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 32011460 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 09:29:16 AM UTC 24 |
| Finished | Oct 09 09:29:19 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721215955 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_readback_err.1721215955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3875801334 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 41192901751 ps |
| CPU time | 739.65 seconds |
| Started | Oct 09 09:28:50 AM UTC 24 |
| Finished | Oct 09 09:41:18 AM UTC 24 |
| Peak memory | 381376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875801334 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3875801334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.3792983790 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 161024870 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 09:27:52 AM UTC 24 |
| Finished | Oct 09 09:27:55 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792983790 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3792983790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2953829353 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 663926034175 ps |
| CPU time | 5180.29 seconds |
| Started | Oct 09 09:30:31 AM UTC 24 |
| Finished | Oct 09 10:57:46 AM UTC 24 |
| Peak memory | 387028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295382935 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.2953829353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2428114567 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2609114654 ps |
| CPU time | 100.62 seconds |
| Started | Oct 09 09:29:19 AM UTC 24 |
| Finished | Oct 09 09:31:02 AM UTC 24 |
| Peak memory | 367112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428114567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2428114567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3579504432 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 6031260877 ps |
| CPU time | 320.36 seconds |
| Started | Oct 09 09:28:09 AM UTC 24 |
| Finished | Oct 09 09:33:34 AM UTC 24 |
| Peak memory | 212580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579504432 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.3579504432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.231948658 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 518770501 ps |
| CPU time | 11.94 seconds |
| Started | Oct 09 09:28:39 AM UTC 24 |
| Finished | Oct 09 09:28:52 AM UTC 24 |
| Peak memory | 270728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 231948658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_th roughput_w_partial_write.231948658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2017145898 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 19094364316 ps |
| CPU time | 1246.98 seconds |
| Started | Oct 09 09:32:04 AM UTC 24 |
| Finished | Oct 09 09:53:07 AM UTC 24 |
| Peak memory | 383628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017145898 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during _key_req.2017145898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1712157014 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 32891866 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 09:32:35 AM UTC 24 |
| Finished | Oct 09 09:32:37 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712157014 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1712157014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.1191826373 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 12739798467 ps |
| CPU time | 76.88 seconds |
| Started | Oct 09 09:31:08 AM UTC 24 |
| Finished | Oct 09 09:32:27 AM UTC 24 |
| Peak memory | 212652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191826373 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.1191826373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.772613931 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 8711641449 ps |
| CPU time | 1127.41 seconds |
| Started | Oct 09 09:32:16 AM UTC 24 |
| Finished | Oct 09 09:51:16 AM UTC 24 |
| Peak memory | 383676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772613931 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.772613931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2623953447 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1656723762 ps |
| CPU time | 8.16 seconds |
| Started | Oct 09 09:31:53 AM UTC 24 |
| Finished | Oct 09 09:32:03 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623953447 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.2623953447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.996003482 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 101996971 ps |
| CPU time | 40.03 seconds |
| Started | Oct 09 09:31:44 AM UTC 24 |
| Finished | Oct 09 09:32:26 AM UTC 24 |
| Peak memory | 313740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 96003482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_max _throughput.996003482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2364388652 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 240320499 ps |
| CPU time | 4.15 seconds |
| Started | Oct 09 09:32:26 AM UTC 24 |
| Finished | Oct 09 09:32:31 AM UTC 24 |
| Peak memory | 222840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364388652 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.2364388652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3434545870 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 234344688 ps |
| CPU time | 8.2 seconds |
| Started | Oct 09 09:32:24 AM UTC 24 |
| Finished | Oct 09 09:32:33 AM UTC 24 |
| Peak memory | 222804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434545870 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.3434545870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2242491854 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3412449400 ps |
| CPU time | 926.36 seconds |
| Started | Oct 09 09:31:03 AM UTC 24 |
| Finished | Oct 09 09:46:41 AM UTC 24 |
| Peak memory | 385420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242491854 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2242491854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2994940485 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2745762348 ps |
| CPU time | 17.67 seconds |
| Started | Oct 09 09:31:19 AM UTC 24 |
| Finished | Oct 09 09:31:38 AM UTC 24 |
| Peak memory | 212864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994940485 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.2994940485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.688540328 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 21375488327 ps |
| CPU time | 346.21 seconds |
| Started | Oct 09 09:31:39 AM UTC 24 |
| Finished | Oct 09 09:37:30 AM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688540328 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acce ss_b2b.688540328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3220445332 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 43010873 ps |
| CPU time | 1 seconds |
| Started | Oct 09 09:32:21 AM UTC 24 |
| Finished | Oct 09 09:32:23 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220445332 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3220445332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_readback_err.681999691 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 108297178 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 09:32:28 AM UTC 24 |
| Finished | Oct 09 09:32:31 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681999691 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_readback_err.681999691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.3055675101 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 8056485743 ps |
| CPU time | 605.79 seconds |
| Started | Oct 09 09:32:17 AM UTC 24 |
| Finished | Oct 09 09:42:30 AM UTC 24 |
| Peak memory | 373208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055675101 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3055675101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.262315080 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2738073369 ps |
| CPU time | 14.98 seconds |
| Started | Oct 09 09:31:01 AM UTC 24 |
| Finished | Oct 09 09:31:17 AM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262315080 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.262315080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1541329722 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 826353890685 ps |
| CPU time | 4770.29 seconds |
| Started | Oct 09 09:32:33 AM UTC 24 |
| Finished | Oct 09 10:52:55 AM UTC 24 |
| Peak memory | 389112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154132972 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.1541329722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3584612416 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 11910492521 ps |
| CPU time | 265.83 seconds |
| Started | Oct 09 09:32:32 AM UTC 24 |
| Finished | Oct 09 09:37:01 AM UTC 24 |
| Peak memory | 379384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584612416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3584612416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2842513802 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 10257219833 ps |
| CPU time | 307.09 seconds |
| Started | Oct 09 09:31:13 AM UTC 24 |
| Finished | Oct 09 09:36:24 AM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842513802 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2842513802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1648573589 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 344860469 ps |
| CPU time | 26.61 seconds |
| Started | Oct 09 09:31:52 AM UTC 24 |
| Finished | Oct 09 09:32:20 AM UTC 24 |
| Peak memory | 289224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1648573589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t hroughput_w_partial_write.1648573589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3832576760 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5359786475 ps |
| CPU time | 1103.04 seconds |
| Started | Oct 09 09:33:38 AM UTC 24 |
| Finished | Oct 09 09:52:13 AM UTC 24 |
| Peak memory | 385744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832576760 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during _key_req.3832576760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.4244537985 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 44322803 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 09:34:03 AM UTC 24 |
| Finished | Oct 09 09:34:05 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244537985 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.4244537985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.2753822789 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 13365952190 ps |
| CPU time | 73.51 seconds |
| Started | Oct 09 09:32:47 AM UTC 24 |
| Finished | Oct 09 09:34:02 AM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753822789 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.2753822789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.180083483 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 57543375232 ps |
| CPU time | 803.18 seconds |
| Started | Oct 09 09:33:43 AM UTC 24 |
| Finished | Oct 09 09:47:16 AM UTC 24 |
| Peak memory | 383488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180083483 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.180083483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3051706368 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2529139686 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 09:33:35 AM UTC 24 |
| Finished | Oct 09 09:33:43 AM UTC 24 |
| Peak memory | 223036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051706368 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.3051706368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3959384418 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 562151325 ps |
| CPU time | 81.69 seconds |
| Started | Oct 09 09:33:08 AM UTC 24 |
| Finished | Oct 09 09:34:31 AM UTC 24 |
| Peak memory | 375440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 959384418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ma x_throughput.3959384418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.4129796500 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 167185955 ps |
| CPU time | 6.66 seconds |
| Started | Oct 09 09:33:49 AM UTC 24 |
| Finished | Oct 09 09:33:57 AM UTC 24 |
| Peak memory | 222992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129796500 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.4129796500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.4063379032 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 977582353 ps |
| CPU time | 7.01 seconds |
| Started | Oct 09 09:33:48 AM UTC 24 |
| Finished | Oct 09 09:33:56 AM UTC 24 |
| Peak memory | 222728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063379032 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.4063379032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3730523007 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1521815237 ps |
| CPU time | 551.18 seconds |
| Started | Oct 09 09:32:47 AM UTC 24 |
| Finished | Oct 09 09:42:05 AM UTC 24 |
| Peak memory | 383428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730523007 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.3730523007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2249827162 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 157748553 ps |
| CPU time | 8.31 seconds |
| Started | Oct 09 09:32:57 AM UTC 24 |
| Finished | Oct 09 09:33:07 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249827162 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.2249827162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1103361855 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 12579052292 ps |
| CPU time | 399.35 seconds |
| Started | Oct 09 09:33:01 AM UTC 24 |
| Finished | Oct 09 09:39:46 AM UTC 24 |
| Peak memory | 212612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103361855 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acc ess_b2b.1103361855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.211011033 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 44150601 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 09:33:45 AM UTC 24 |
| Finished | Oct 09 09:33:48 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211011033 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.211011033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_readback_err.1103407066 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 33576862 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 09:33:57 AM UTC 24 |
| Finished | Oct 09 09:33:59 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103407066 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_readback_err.1103407066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.41537313 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 6432555650 ps |
| CPU time | 1184.35 seconds |
| Started | Oct 09 09:33:44 AM UTC 24 |
| Finished | Oct 09 09:53:42 AM UTC 24 |
| Peak memory | 381388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41537313 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.41537313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2985878915 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 63978927 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 09:32:47 AM UTC 24 |
| Finished | Oct 09 09:32:50 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985878915 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2985878915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1123371159 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 10600399121 ps |
| CPU time | 3434.04 seconds |
| Started | Oct 09 09:34:00 AM UTC 24 |
| Finished | Oct 09 10:31:52 AM UTC 24 |
| Peak memory | 395260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112337115 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.1123371159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.926041343 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 422888363 ps |
| CPU time | 9.95 seconds |
| Started | Oct 09 09:33:58 AM UTC 24 |
| Finished | Oct 09 09:34:09 AM UTC 24 |
| Peak memory | 222920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926041343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.926041343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3704273540 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 7376669875 ps |
| CPU time | 180.03 seconds |
| Started | Oct 09 09:32:51 AM UTC 24 |
| Finished | Oct 09 09:35:54 AM UTC 24 |
| Peak memory | 212576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704273540 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.3704273540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1755917758 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 297280860 ps |
| CPU time | 13.08 seconds |
| Started | Oct 09 09:33:30 AM UTC 24 |
| Finished | Oct 09 09:33:44 AM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1755917758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t hroughput_w_partial_write.1755917758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3229660588 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 5841315200 ps |
| CPU time | 505.67 seconds |
| Started | Oct 09 09:35:09 AM UTC 24 |
| Finished | Oct 09 09:43:41 AM UTC 24 |
| Peak memory | 381456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229660588 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.3229660588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2695751712 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 17745369 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 09:35:48 AM UTC 24 |
| Finished | Oct 09 09:35:50 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695751712 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2695751712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3207233700 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 6299432607 ps |
| CPU time | 58.33 seconds |
| Started | Oct 09 09:34:11 AM UTC 24 |
| Finished | Oct 09 09:35:11 AM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207233700 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.3207233700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.2877050955 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 6125631754 ps |
| CPU time | 843.3 seconds |
| Started | Oct 09 09:35:09 AM UTC 24 |
| Finished | Oct 09 09:49:23 AM UTC 24 |
| Peak memory | 381464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877050955 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.2877050955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2186969434 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 5509712811 ps |
| CPU time | 9.61 seconds |
| Started | Oct 09 09:34:57 AM UTC 24 |
| Finished | Oct 09 09:35:08 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186969434 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.2186969434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2016001156 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 120698903 ps |
| CPU time | 44.84 seconds |
| Started | Oct 09 09:34:37 AM UTC 24 |
| Finished | Oct 09 09:35:23 AM UTC 24 |
| Peak memory | 348556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 016001156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma x_throughput.2016001156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1839029150 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 179939754 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 09:35:27 AM UTC 24 |
| Finished | Oct 09 09:35:36 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839029150 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.1839029150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2975560412 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1389510960 ps |
| CPU time | 8 seconds |
| Started | Oct 09 09:35:27 AM UTC 24 |
| Finished | Oct 09 09:35:36 AM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975560412 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.2975560412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1790993509 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 10950253489 ps |
| CPU time | 985.54 seconds |
| Started | Oct 09 09:34:11 AM UTC 24 |
| Finished | Oct 09 09:50:47 AM UTC 24 |
| Peak memory | 385556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790993509 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.1790993509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.431692795 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 95204478 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 09:34:32 AM UTC 24 |
| Finished | Oct 09 09:34:36 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431692795 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.431692795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.298555027 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3555346330 ps |
| CPU time | 299.39 seconds |
| Started | Oct 09 09:34:36 AM UTC 24 |
| Finished | Oct 09 09:39:39 AM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298555027 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acce ss_b2b.298555027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3307613904 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 76366784 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 09:35:24 AM UTC 24 |
| Finished | Oct 09 09:35:26 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307613904 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3307613904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1108383474 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 62488942 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 09:35:37 AM UTC 24 |
| Finished | Oct 09 09:35:40 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108383474 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_readback_err.1108383474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.1375711135 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 16072946317 ps |
| CPU time | 742.57 seconds |
| Started | Oct 09 09:35:11 AM UTC 24 |
| Finished | Oct 09 09:47:43 AM UTC 24 |
| Peak memory | 385628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375711135 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1375711135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.2213387049 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 62896382 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 09:34:06 AM UTC 24 |
| Finished | Oct 09 09:34:10 AM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213387049 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2213387049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1683402972 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 26401078381 ps |
| CPU time | 1985.62 seconds |
| Started | Oct 09 09:35:40 AM UTC 24 |
| Finished | Oct 09 10:09:08 AM UTC 24 |
| Peak memory | 379592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168340297 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.1683402972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1936038554 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1803995572 ps |
| CPU time | 63.39 seconds |
| Started | Oct 09 09:35:37 AM UTC 24 |
| Finished | Oct 09 09:36:42 AM UTC 24 |
| Peak memory | 266700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936038554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1936038554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3124319696 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 4032779449 ps |
| CPU time | 196.41 seconds |
| Started | Oct 09 09:34:19 AM UTC 24 |
| Finished | Oct 09 09:37:39 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124319696 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.3124319696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3173436328 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1385681272 ps |
| CPU time | 54.38 seconds |
| Started | Oct 09 09:34:52 AM UTC 24 |
| Finished | Oct 09 09:35:48 AM UTC 24 |
| Peak memory | 348632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3173436328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t hroughput_w_partial_write.3173436328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3065417639 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5070910013 ps |
| CPU time | 643.61 seconds |
| Started | Oct 09 08:51:06 AM UTC 24 |
| Finished | Oct 09 09:01:58 AM UTC 24 |
| Peak memory | 385544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065417639 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_ key_req.3065417639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.115032004 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 14511451 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 08:51:48 AM UTC 24 |
| Finished | Oct 09 08:51:51 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115032004 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.115032004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.666874267 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2843277160 ps |
| CPU time | 56.99 seconds |
| Started | Oct 09 08:50:49 AM UTC 24 |
| Finished | Oct 09 08:51:48 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666874267 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.666874267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.798780324 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2905356043 ps |
| CPU time | 908.51 seconds |
| Started | Oct 09 08:51:09 AM UTC 24 |
| Finished | Oct 09 09:06:28 AM UTC 24 |
| Peak memory | 377348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798780324 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.798780324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.266333393 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 241196446 ps |
| CPU time | 3.23 seconds |
| Started | Oct 09 08:51:05 AM UTC 24 |
| Finished | Oct 09 08:51:09 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266333393 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.266333393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.954539966 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 403045049 ps |
| CPU time | 36.73 seconds |
| Started | Oct 09 08:50:53 AM UTC 24 |
| Finished | Oct 09 08:51:31 AM UTC 24 |
| Peak memory | 319884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 54539966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_ throughput.954539966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3581685854 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 905610225 ps |
| CPU time | 9.24 seconds |
| Started | Oct 09 08:51:32 AM UTC 24 |
| Finished | Oct 09 08:51:42 AM UTC 24 |
| Peak memory | 222756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581685854 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.3581685854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2186933969 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 226841589 ps |
| CPU time | 7.75 seconds |
| Started | Oct 09 08:51:25 AM UTC 24 |
| Finished | Oct 09 08:51:34 AM UTC 24 |
| Peak memory | 222800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186933969 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.2186933969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2854768900 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 677672420 ps |
| CPU time | 17.3 seconds |
| Started | Oct 09 08:50:49 AM UTC 24 |
| Finished | Oct 09 08:51:08 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854768900 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.2854768900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.215793320 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 601721335 ps |
| CPU time | 91.15 seconds |
| Started | Oct 09 08:50:52 AM UTC 24 |
| Finished | Oct 09 08:52:25 AM UTC 24 |
| Peak memory | 362892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215793320 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.215793320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.468027332 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 12215341083 ps |
| CPU time | 352.57 seconds |
| Started | Oct 09 08:50:53 AM UTC 24 |
| Finished | Oct 09 08:56:50 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468027332 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acces s_b2b.468027332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2845583694 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 27167202 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 08:51:21 AM UTC 24 |
| Finished | Oct 09 08:51:24 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845583694 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2845583694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_readback_err.4159756760 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 32541006 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 08:51:35 AM UTC 24 |
| Finished | Oct 09 08:51:37 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159756760 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_readback_err.4159756760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.3690042470 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13962723990 ps |
| CPU time | 996.52 seconds |
| Started | Oct 09 08:51:10 AM UTC 24 |
| Finished | Oct 09 09:07:58 AM UTC 24 |
| Peak memory | 377560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690042470 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3690042470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2568205455 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1254605598 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 08:51:43 AM UTC 24 |
| Finished | Oct 09 08:51:47 AM UTC 24 |
| Peak memory | 248456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568205455 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.2568205455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.650545573 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 375767809 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 08:50:46 AM UTC 24 |
| Finished | Oct 09 08:50:51 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650545573 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.650545573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3325653766 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 60318398389 ps |
| CPU time | 1963.63 seconds |
| Started | Oct 09 08:51:42 AM UTC 24 |
| Finished | Oct 09 09:24:48 AM UTC 24 |
| Peak memory | 385444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332565376 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3325653766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3903667287 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 17839979361 ps |
| CPU time | 65.99 seconds |
| Started | Oct 09 08:51:38 AM UTC 24 |
| Finished | Oct 09 08:52:46 AM UTC 24 |
| Peak memory | 309752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903667287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3903667287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1445167942 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1618755432 ps |
| CPU time | 216.88 seconds |
| Started | Oct 09 08:50:51 AM UTC 24 |
| Finished | Oct 09 08:54:32 AM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445167942 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.1445167942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1064356955 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 282094091 ps |
| CPU time | 91.43 seconds |
| Started | Oct 09 08:50:53 AM UTC 24 |
| Finished | Oct 09 08:52:26 AM UTC 24 |
| Peak memory | 369036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1064356955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th roughput_w_partial_write.1064356955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1730290145 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2327124658 ps |
| CPU time | 534.13 seconds |
| Started | Oct 09 09:37:08 AM UTC 24 |
| Finished | Oct 09 09:46:09 AM UTC 24 |
| Peak memory | 379380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730290145 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during _key_req.1730290145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2841202631 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 28731208 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 09:37:48 AM UTC 24 |
| Finished | Oct 09 09:37:50 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841202631 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.2841202631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1420293731 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2401448844 ps |
| CPU time | 46.53 seconds |
| Started | Oct 09 09:36:03 AM UTC 24 |
| Finished | Oct 09 09:36:51 AM UTC 24 |
| Peak memory | 212684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420293731 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.1420293731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3275474813 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3863506551 ps |
| CPU time | 274 seconds |
| Started | Oct 09 09:37:10 AM UTC 24 |
| Finished | Oct 09 09:41:48 AM UTC 24 |
| Peak memory | 379352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275474813 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.3275474813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3838473040 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 4316231990 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 09:37:03 AM UTC 24 |
| Finished | Oct 09 09:37:09 AM UTC 24 |
| Peak memory | 212592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838473040 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.3838473040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3822820392 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 137980683 ps |
| CPU time | 95.71 seconds |
| Started | Oct 09 09:36:43 AM UTC 24 |
| Finished | Oct 09 09:38:21 AM UTC 24 |
| Peak memory | 379264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 822820392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma x_throughput.3822820392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2113708706 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 601507401 ps |
| CPU time | 5.96 seconds |
| Started | Oct 09 09:37:40 AM UTC 24 |
| Finished | Oct 09 09:37:47 AM UTC 24 |
| Peak memory | 222992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113708706 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.2113708706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.659259838 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 164446042 ps |
| CPU time | 5.57 seconds |
| Started | Oct 09 09:37:34 AM UTC 24 |
| Finished | Oct 09 09:37:41 AM UTC 24 |
| Peak memory | 212684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659259838 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.659259838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2643201116 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 30199665370 ps |
| CPU time | 440.53 seconds |
| Started | Oct 09 09:35:55 AM UTC 24 |
| Finished | Oct 09 09:43:21 AM UTC 24 |
| Peak memory | 381392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643201116 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2643201116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1295724181 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 98513239 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 09:36:29 AM UTC 24 |
| Finished | Oct 09 09:36:34 AM UTC 24 |
| Peak memory | 221540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295724181 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.1295724181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.835518144 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 31833935729 ps |
| CPU time | 431.22 seconds |
| Started | Oct 09 09:36:35 AM UTC 24 |
| Finished | Oct 09 09:43:52 AM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835518144 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acce ss_b2b.835518144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3536165591 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 78086056 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 09:37:31 AM UTC 24 |
| Finished | Oct 09 09:37:33 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536165591 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3536165591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_readback_err.612995079 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 31549435 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 09:37:41 AM UTC 24 |
| Finished | Oct 09 09:37:43 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612995079 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_readback_err.612995079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.988196530 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2047907096 ps |
| CPU time | 628.77 seconds |
| Started | Oct 09 09:37:15 AM UTC 24 |
| Finished | Oct 09 09:47:52 AM UTC 24 |
| Peak memory | 377228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988196530 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.988196530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3291342396 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2339490559 ps |
| CPU time | 81.05 seconds |
| Started | Oct 09 09:35:51 AM UTC 24 |
| Finished | Oct 09 09:37:15 AM UTC 24 |
| Peak memory | 363164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291342396 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3291342396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.343739316 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 22862938721 ps |
| CPU time | 2646.13 seconds |
| Started | Oct 09 09:37:44 AM UTC 24 |
| Finished | Oct 09 10:22:20 AM UTC 24 |
| Peak memory | 387016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343739316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.343739316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3334363526 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1731101236 ps |
| CPU time | 456.77 seconds |
| Started | Oct 09 09:37:42 AM UTC 24 |
| Finished | Oct 09 09:45:25 AM UTC 24 |
| Peak memory | 369104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334363526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3334363526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1968929622 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2119335486 ps |
| CPU time | 226.96 seconds |
| Started | Oct 09 09:36:25 AM UTC 24 |
| Finished | Oct 09 09:40:16 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968929622 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.1968929622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.573039859 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 599359083 ps |
| CPU time | 105.96 seconds |
| Started | Oct 09 09:36:51 AM UTC 24 |
| Finished | Oct 09 09:38:40 AM UTC 24 |
| Peak memory | 379280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 573039859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_th roughput_w_partial_write.573039859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.237309292 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2107094090 ps |
| CPU time | 467.48 seconds |
| Started | Oct 09 09:39:46 AM UTC 24 |
| Finished | Oct 09 09:47:39 AM UTC 24 |
| Peak memory | 354644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237309292 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during_ key_req.237309292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2792507226 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 23272303 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 09:40:17 AM UTC 24 |
| Finished | Oct 09 09:40:19 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792507226 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2792507226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3327893298 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 30231679686 ps |
| CPU time | 83.04 seconds |
| Started | Oct 09 09:38:23 AM UTC 24 |
| Finished | Oct 09 09:39:48 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327893298 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.3327893298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.2195925285 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2328380055 ps |
| CPU time | 1023.63 seconds |
| Started | Oct 09 09:39:47 AM UTC 24 |
| Finished | Oct 09 09:57:03 AM UTC 24 |
| Peak memory | 379272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195925285 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.2195925285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.853391271 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 346302859 ps |
| CPU time | 6.1 seconds |
| Started | Oct 09 09:39:40 AM UTC 24 |
| Finished | Oct 09 09:39:48 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853391271 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.853391271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2178645807 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 336392804 ps |
| CPU time | 86.69 seconds |
| Started | Oct 09 09:39:20 AM UTC 24 |
| Finished | Oct 09 09:40:49 AM UTC 24 |
| Peak memory | 371152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 178645807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma x_throughput.2178645807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1641811640 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 141667768 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 09:40:02 AM UTC 24 |
| Finished | Oct 09 09:40:07 AM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641811640 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1641811640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4039383010 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 473205641 ps |
| CPU time | 8.06 seconds |
| Started | Oct 09 09:39:52 AM UTC 24 |
| Finished | Oct 09 09:40:01 AM UTC 24 |
| Peak memory | 222728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039383010 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.4039383010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1118282510 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 6535842351 ps |
| CPU time | 504.47 seconds |
| Started | Oct 09 09:38:13 AM UTC 24 |
| Finished | Oct 09 09:46:45 AM UTC 24 |
| Peak memory | 365188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118282510 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.1118282510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1227357283 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2214403199 ps |
| CPU time | 19.03 seconds |
| Started | Oct 09 09:38:47 AM UTC 24 |
| Finished | Oct 09 09:39:07 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227357283 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1227357283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.547235719 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 11285857882 ps |
| CPU time | 259.67 seconds |
| Started | Oct 09 09:39:08 AM UTC 24 |
| Finished | Oct 09 09:43:32 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547235719 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acce ss_b2b.547235719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2698863472 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 69086319 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 09:39:49 AM UTC 24 |
| Finished | Oct 09 09:39:51 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698863472 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2698863472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_readback_err.255189751 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 103545497 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 09:40:02 AM UTC 24 |
| Finished | Oct 09 09:40:05 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255189751 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_readback_err.255189751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3073120713 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 18347500879 ps |
| CPU time | 318.17 seconds |
| Started | Oct 09 09:39:48 AM UTC 24 |
| Finished | Oct 09 09:45:11 AM UTC 24 |
| Peak memory | 367136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073120713 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3073120713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2589454103 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 3118471623 ps |
| CPU time | 20.38 seconds |
| Started | Oct 09 09:37:51 AM UTC 24 |
| Finished | Oct 09 09:38:13 AM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589454103 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2589454103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3072405036 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 41946776295 ps |
| CPU time | 2798.14 seconds |
| Started | Oct 09 09:40:08 AM UTC 24 |
| Finished | Oct 09 10:27:15 AM UTC 24 |
| Peak memory | 395172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307240503 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.3072405036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1004615611 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 9103882641 ps |
| CPU time | 558.07 seconds |
| Started | Oct 09 09:40:06 AM UTC 24 |
| Finished | Oct 09 09:49:31 AM UTC 24 |
| Peak memory | 389632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004615611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1004615611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1405787441 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 3959848740 ps |
| CPU time | 191.88 seconds |
| Started | Oct 09 09:38:41 AM UTC 24 |
| Finished | Oct 09 09:41:56 AM UTC 24 |
| Peak memory | 212848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405787441 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.1405787441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1946834647 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 150441117 ps |
| CPU time | 13.18 seconds |
| Started | Oct 09 09:39:30 AM UTC 24 |
| Finished | Oct 09 09:39:45 AM UTC 24 |
| Peak memory | 262784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1946834647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t hroughput_w_partial_write.1946834647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2475085264 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3339592930 ps |
| CPU time | 325.49 seconds |
| Started | Oct 09 09:42:02 AM UTC 24 |
| Finished | Oct 09 09:47:32 AM UTC 24 |
| Peak memory | 379316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475085264 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.2475085264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.581057069 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 19298079 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 09:42:31 AM UTC 24 |
| Finished | Oct 09 09:42:34 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581057069 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.581057069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.3457824043 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 13895769759 ps |
| CPU time | 99.13 seconds |
| Started | Oct 09 09:40:22 AM UTC 24 |
| Finished | Oct 09 09:42:04 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457824043 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.3457824043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3596130081 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 24300955908 ps |
| CPU time | 665.9 seconds |
| Started | Oct 09 09:42:05 AM UTC 24 |
| Finished | Oct 09 09:53:19 AM UTC 24 |
| Peak memory | 383672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596130081 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.3596130081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2407390400 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 258698905 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 09:41:56 AM UTC 24 |
| Finished | Oct 09 09:42:01 AM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407390400 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.2407390400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2443825640 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 513112284 ps |
| CPU time | 109.56 seconds |
| Started | Oct 09 09:41:49 AM UTC 24 |
| Finished | Oct 09 09:43:41 AM UTC 24 |
| Peak memory | 381328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 443825640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma x_throughput.2443825640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4201862999 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 181525423 ps |
| CPU time | 5.66 seconds |
| Started | Oct 09 09:42:15 AM UTC 24 |
| Finished | Oct 09 09:42:22 AM UTC 24 |
| Peak memory | 222784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201862999 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.4201862999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1291769427 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 878848897 ps |
| CPU time | 14.37 seconds |
| Started | Oct 09 09:42:14 AM UTC 24 |
| Finished | Oct 09 09:42:30 AM UTC 24 |
| Peak memory | 222736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291769427 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.1291769427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.82691562 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 16126415112 ps |
| CPU time | 1639.33 seconds |
| Started | Oct 09 09:40:20 AM UTC 24 |
| Finished | Oct 09 10:07:58 AM UTC 24 |
| Peak memory | 385740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82691562 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.82691562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1520591062 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 730886801 ps |
| CPU time | 81.91 seconds |
| Started | Oct 09 09:40:50 AM UTC 24 |
| Finished | Oct 09 09:42:14 AM UTC 24 |
| Peak memory | 366984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520591062 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1520591062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3353031423 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 15234630140 ps |
| CPU time | 417.62 seconds |
| Started | Oct 09 09:41:19 AM UTC 24 |
| Finished | Oct 09 09:48:22 AM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353031423 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acc ess_b2b.3353031423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2507521165 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 56741997 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 09:42:11 AM UTC 24 |
| Finished | Oct 09 09:42:13 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507521165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2507521165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_readback_err.4030115265 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 177530084 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 09:42:23 AM UTC 24 |
| Finished | Oct 09 09:42:26 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030115265 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_readback_err.4030115265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.179904162 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 14601154732 ps |
| CPU time | 457.97 seconds |
| Started | Oct 09 09:42:06 AM UTC 24 |
| Finished | Oct 09 09:49:50 AM UTC 24 |
| Peak memory | 375228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179904162 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.179904162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.2362272821 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 71597796 ps |
| CPU time | 4.31 seconds |
| Started | Oct 09 09:40:19 AM UTC 24 |
| Finished | Oct 09 09:40:24 AM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362272821 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2362272821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3024423364 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4782993936 ps |
| CPU time | 926.04 seconds |
| Started | Oct 09 09:42:27 AM UTC 24 |
| Finished | Oct 09 09:58:03 AM UTC 24 |
| Peak memory | 379300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302442336 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.3024423364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2871158959 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 5589321447 ps |
| CPU time | 48.71 seconds |
| Started | Oct 09 09:42:25 AM UTC 24 |
| Finished | Oct 09 09:43:15 AM UTC 24 |
| Peak memory | 291420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871158959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2871158959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.4280619718 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2650320063 ps |
| CPU time | 274.21 seconds |
| Started | Oct 09 09:40:25 AM UTC 24 |
| Finished | Oct 09 09:45:04 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280619718 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.4280619718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.4219559879 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 215596553 ps |
| CPU time | 29.7 seconds |
| Started | Oct 09 09:41:52 AM UTC 24 |
| Finished | Oct 09 09:42:23 AM UTC 24 |
| Peak memory | 311680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4219559879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t hroughput_w_partial_write.4219559879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2619896920 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 10114515841 ps |
| CPU time | 529.49 seconds |
| Started | Oct 09 09:43:25 AM UTC 24 |
| Finished | Oct 09 09:52:20 AM UTC 24 |
| Peak memory | 383500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619896920 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during _key_req.2619896920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.614585646 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 17348786 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 09:43:42 AM UTC 24 |
| Finished | Oct 09 09:43:44 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614585646 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.614585646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2402395261 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 6948538543 ps |
| CPU time | 54.25 seconds |
| Started | Oct 09 09:42:34 AM UTC 24 |
| Finished | Oct 09 09:43:30 AM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402395261 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.2402395261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2322411892 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3795010201 ps |
| CPU time | 104.18 seconds |
| Started | Oct 09 09:43:29 AM UTC 24 |
| Finished | Oct 09 09:45:15 AM UTC 24 |
| Peak memory | 242136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322411892 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.2322411892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3785941740 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 742786859 ps |
| CPU time | 5.86 seconds |
| Started | Oct 09 09:43:21 AM UTC 24 |
| Finished | Oct 09 09:43:29 AM UTC 24 |
| Peak memory | 222840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785941740 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.3785941740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2908887632 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 155292949 ps |
| CPU time | 13.92 seconds |
| Started | Oct 09 09:43:08 AM UTC 24 |
| Finished | Oct 09 09:43:23 AM UTC 24 |
| Peak memory | 281040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 908887632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma x_throughput.2908887632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.84081866 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 171100833 ps |
| CPU time | 6.07 seconds |
| Started | Oct 09 09:43:33 AM UTC 24 |
| Finished | Oct 09 09:43:40 AM UTC 24 |
| Peak memory | 223020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84081866 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.84081866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1098103389 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 5436659056 ps |
| CPU time | 16.08 seconds |
| Started | Oct 09 09:43:33 AM UTC 24 |
| Finished | Oct 09 09:43:50 AM UTC 24 |
| Peak memory | 222792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098103389 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.1098103389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3618087216 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2825356760 ps |
| CPU time | 453.12 seconds |
| Started | Oct 09 09:42:31 AM UTC 24 |
| Finished | Oct 09 09:50:11 AM UTC 24 |
| Peak memory | 385448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618087216 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.3618087216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3747548447 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 185150683 ps |
| CPU time | 60.57 seconds |
| Started | Oct 09 09:42:56 AM UTC 24 |
| Finished | Oct 09 09:43:58 AM UTC 24 |
| Peak memory | 356696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747548447 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.3747548447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1202835202 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 23472991463 ps |
| CPU time | 368.53 seconds |
| Started | Oct 09 09:42:58 AM UTC 24 |
| Finished | Oct 09 09:49:12 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202835202 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc ess_b2b.1202835202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2617998915 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 45952998 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 09:43:31 AM UTC 24 |
| Finished | Oct 09 09:43:33 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617998915 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2617998915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_readback_err.3167233470 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 139520222 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 09:43:34 AM UTC 24 |
| Finished | Oct 09 09:43:37 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167233470 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_readback_err.3167233470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2527106690 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1813671663 ps |
| CPU time | 504.72 seconds |
| Started | Oct 09 09:43:30 AM UTC 24 |
| Finished | Oct 09 09:52:01 AM UTC 24 |
| Peak memory | 352656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527106690 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2527106690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.599224444 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 782677809 ps |
| CPU time | 18.85 seconds |
| Started | Oct 09 09:42:31 AM UTC 24 |
| Finished | Oct 09 09:42:52 AM UTC 24 |
| Peak memory | 212616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599224444 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.599224444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2924579897 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 36065817013 ps |
| CPU time | 497.25 seconds |
| Started | Oct 09 09:43:38 AM UTC 24 |
| Finished | Oct 09 09:52:02 AM UTC 24 |
| Peak memory | 350900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292457989 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.2924579897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3566520627 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 779674361 ps |
| CPU time | 96.93 seconds |
| Started | Oct 09 09:43:34 AM UTC 24 |
| Finished | Oct 09 09:45:13 AM UTC 24 |
| Peak memory | 293396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566520627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3566520627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2150647641 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2623390230 ps |
| CPU time | 303.28 seconds |
| Started | Oct 09 09:42:52 AM UTC 24 |
| Finished | Oct 09 09:48:01 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150647641 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.2150647641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.156062023 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1521633822 ps |
| CPU time | 16.48 seconds |
| Started | Oct 09 09:43:15 AM UTC 24 |
| Finished | Oct 09 09:43:33 AM UTC 24 |
| Peak memory | 279004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 156062023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_th roughput_w_partial_write.156062023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3917576236 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 783001504 ps |
| CPU time | 136.92 seconds |
| Started | Oct 09 09:44:34 AM UTC 24 |
| Finished | Oct 09 09:46:53 AM UTC 24 |
| Peak memory | 346564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917576236 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during _key_req.3917576236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.564292484 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 23849868 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 09:45:13 AM UTC 24 |
| Finished | Oct 09 09:45:15 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564292484 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.564292484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2249393952 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1863536261 ps |
| CPU time | 37.18 seconds |
| Started | Oct 09 09:43:45 AM UTC 24 |
| Finished | Oct 09 09:44:24 AM UTC 24 |
| Peak memory | 212548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249393952 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.2249393952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.2707866256 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 223355216883 ps |
| CPU time | 889.44 seconds |
| Started | Oct 09 09:44:38 AM UTC 24 |
| Finished | Oct 09 09:59:38 AM UTC 24 |
| Peak memory | 385484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707866256 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.2707866256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1006663420 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4341127496 ps |
| CPU time | 10.98 seconds |
| Started | Oct 09 09:44:25 AM UTC 24 |
| Finished | Oct 09 09:44:37 AM UTC 24 |
| Peak memory | 212864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006663420 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.1006663420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3396306350 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 478710011 ps |
| CPU time | 45.61 seconds |
| Started | Oct 09 09:43:59 AM UTC 24 |
| Finished | Oct 09 09:44:46 AM UTC 24 |
| Peak memory | 356816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 396306350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ma x_throughput.3396306350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1357053761 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 213280735 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 09:45:05 AM UTC 24 |
| Finished | Oct 09 09:45:11 AM UTC 24 |
| Peak memory | 222784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357053761 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.1357053761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3855777710 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 86650048 ps |
| CPU time | 6.21 seconds |
| Started | Oct 09 09:45:02 AM UTC 24 |
| Finished | Oct 09 09:45:09 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855777710 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.3855777710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.4219515026 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1338482920 ps |
| CPU time | 99.8 seconds |
| Started | Oct 09 09:43:42 AM UTC 24 |
| Finished | Oct 09 09:45:24 AM UTC 24 |
| Peak memory | 319940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219515026 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.4219515026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2735160591 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 226142853 ps |
| CPU time | 14.69 seconds |
| Started | Oct 09 09:43:51 AM UTC 24 |
| Finished | Oct 09 09:44:07 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735160591 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.2735160591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3411424291 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 46357411585 ps |
| CPU time | 398.19 seconds |
| Started | Oct 09 09:43:53 AM UTC 24 |
| Finished | Oct 09 09:50:37 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411424291 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc ess_b2b.3411424291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1392860454 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 76421275 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 09:44:58 AM UTC 24 |
| Finished | Oct 09 09:45:01 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392860454 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1392860454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_readback_err.1127913270 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 31843196 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 09:45:10 AM UTC 24 |
| Finished | Oct 09 09:45:12 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127913270 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_readback_err.1127913270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.3739702360 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5040483296 ps |
| CPU time | 191.04 seconds |
| Started | Oct 09 09:44:46 AM UTC 24 |
| Finished | Oct 09 09:48:01 AM UTC 24 |
| Peak memory | 375188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739702360 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3739702360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.4034907343 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 317471567 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 09:43:42 AM UTC 24 |
| Finished | Oct 09 09:43:46 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034907343 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.4034907343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1560668418 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 58551640742 ps |
| CPU time | 2284.04 seconds |
| Started | Oct 09 09:45:12 AM UTC 24 |
| Finished | Oct 09 10:23:40 AM UTC 24 |
| Peak memory | 387500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156066841 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.1560668418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3560611509 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1333659455 ps |
| CPU time | 366.02 seconds |
| Started | Oct 09 09:45:12 AM UTC 24 |
| Finished | Oct 09 09:51:23 AM UTC 24 |
| Peak memory | 367296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560611509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3560611509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.16788212 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 67134585265 ps |
| CPU time | 323.78 seconds |
| Started | Oct 09 09:43:47 AM UTC 24 |
| Finished | Oct 09 09:49:16 AM UTC 24 |
| Peak memory | 212600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16788212 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.16788212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3713429359 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 464835584 ps |
| CPU time | 23.34 seconds |
| Started | Oct 09 09:44:09 AM UTC 24 |
| Finished | Oct 09 09:44:33 AM UTC 24 |
| Peak memory | 280960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3713429359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t hroughput_w_partial_write.3713429359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2159177290 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1836750105 ps |
| CPU time | 405.94 seconds |
| Started | Oct 09 09:46:09 AM UTC 24 |
| Finished | Oct 09 09:53:01 AM UTC 24 |
| Peak memory | 377344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159177290 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during _key_req.2159177290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.876620563 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 11605349 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 09:46:48 AM UTC 24 |
| Finished | Oct 09 09:46:50 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876620563 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.876620563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.340201453 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 11766034272 ps |
| CPU time | 53.05 seconds |
| Started | Oct 09 09:45:16 AM UTC 24 |
| Finished | Oct 09 09:46:11 AM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340201453 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.340201453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.935967470 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 268562118 ps |
| CPU time | 2.49 seconds |
| Started | Oct 09 09:46:05 AM UTC 24 |
| Finished | Oct 09 09:46:08 AM UTC 24 |
| Peak memory | 222968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935967470 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.935967470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1990081944 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 85703936 ps |
| CPU time | 29.07 seconds |
| Started | Oct 09 09:45:33 AM UTC 24 |
| Finished | Oct 09 09:46:04 AM UTC 24 |
| Peak memory | 289232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 990081944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma x_throughput.1990081944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.281294171 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 90751826 ps |
| CPU time | 6.36 seconds |
| Started | Oct 09 09:46:40 AM UTC 24 |
| Finished | Oct 09 09:46:47 AM UTC 24 |
| Peak memory | 222832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281294171 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.281294171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2830757316 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 290267124 ps |
| CPU time | 6.85 seconds |
| Started | Oct 09 09:46:30 AM UTC 24 |
| Finished | Oct 09 09:46:38 AM UTC 24 |
| Peak memory | 223120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830757316 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.2830757316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.18952086 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 123454623803 ps |
| CPU time | 801.61 seconds |
| Started | Oct 09 09:45:16 AM UTC 24 |
| Finished | Oct 09 09:58:48 AM UTC 24 |
| Peak memory | 379396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18952086 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.18952086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3716573427 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 413752494 ps |
| CPU time | 9.84 seconds |
| Started | Oct 09 09:45:26 AM UTC 24 |
| Finished | Oct 09 09:45:37 AM UTC 24 |
| Peak memory | 212648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716573427 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.3716573427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3611709962 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 58482624968 ps |
| CPU time | 407.18 seconds |
| Started | Oct 09 09:45:31 AM UTC 24 |
| Finished | Oct 09 09:52:24 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611709962 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acc ess_b2b.3611709962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.476316846 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 45263807 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 09:46:26 AM UTC 24 |
| Finished | Oct 09 09:46:28 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476316846 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.476316846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_readback_err.635787911 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 51366899 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 09:46:42 AM UTC 24 |
| Finished | Oct 09 09:46:45 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635787911 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_readback_err.635787911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.3002129627 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 11166098020 ps |
| CPU time | 860.65 seconds |
| Started | Oct 09 09:46:13 AM UTC 24 |
| Finished | Oct 09 10:00:45 AM UTC 24 |
| Peak memory | 381468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002129627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.3002129627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.181954364 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1476496097 ps |
| CPU time | 122.73 seconds |
| Started | Oct 09 09:45:14 AM UTC 24 |
| Finished | Oct 09 09:47:20 AM UTC 24 |
| Peak memory | 373136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181954364 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.181954364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3689360298 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 39234286836 ps |
| CPU time | 2318.1 seconds |
| Started | Oct 09 09:46:46 AM UTC 24 |
| Finished | Oct 09 10:25:48 AM UTC 24 |
| Peak memory | 385624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368936029 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.3689360298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4017994683 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 324096819 ps |
| CPU time | 69.09 seconds |
| Started | Oct 09 09:46:46 AM UTC 24 |
| Finished | Oct 09 09:47:57 AM UTC 24 |
| Peak memory | 338628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017994683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4017994683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1472568335 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 14180300317 ps |
| CPU time | 365.9 seconds |
| Started | Oct 09 09:45:25 AM UTC 24 |
| Finished | Oct 09 09:51:36 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472568335 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.1472568335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1002228150 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 262582277 ps |
| CPU time | 44.89 seconds |
| Started | Oct 09 09:45:38 AM UTC 24 |
| Finished | Oct 09 09:46:25 AM UTC 24 |
| Peak memory | 350664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1002228150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t hroughput_w_partial_write.1002228150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3653982821 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 32310792690 ps |
| CPU time | 1095.97 seconds |
| Started | Oct 09 09:47:37 AM UTC 24 |
| Finished | Oct 09 10:06:05 AM UTC 24 |
| Peak memory | 383484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653982821 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during _key_req.3653982821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1835306011 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 13263920 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 09:47:54 AM UTC 24 |
| Finished | Oct 09 09:47:57 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835306011 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1835306011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.791443751 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1698112605 ps |
| CPU time | 45.47 seconds |
| Started | Oct 09 09:46:57 AM UTC 24 |
| Finished | Oct 09 09:47:44 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791443751 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.791443751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1105647968 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 9377710496 ps |
| CPU time | 357.96 seconds |
| Started | Oct 09 09:47:40 AM UTC 24 |
| Finished | Oct 09 09:53:44 AM UTC 24 |
| Peak memory | 373448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105647968 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.1105647968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3156888067 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2097942487 ps |
| CPU time | 9.25 seconds |
| Started | Oct 09 09:47:33 AM UTC 24 |
| Finished | Oct 09 09:47:43 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156888067 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.3156888067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.985358188 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 470261255 ps |
| CPU time | 76.61 seconds |
| Started | Oct 09 09:47:16 AM UTC 24 |
| Finished | Oct 09 09:48:35 AM UTC 24 |
| Peak memory | 381252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 85358188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max _throughput.985358188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.3983090967 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 215766412 ps |
| CPU time | 3.59 seconds |
| Started | Oct 09 09:47:48 AM UTC 24 |
| Finished | Oct 09 09:47:52 AM UTC 24 |
| Peak memory | 222800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983090967 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.3983090967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2953492180 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 234771773 ps |
| CPU time | 5.68 seconds |
| Started | Oct 09 09:47:45 AM UTC 24 |
| Finished | Oct 09 09:47:52 AM UTC 24 |
| Peak memory | 222868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953492180 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.2953492180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3801418860 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 9384167106 ps |
| CPU time | 442.99 seconds |
| Started | Oct 09 09:46:54 AM UTC 24 |
| Finished | Oct 09 09:54:23 AM UTC 24 |
| Peak memory | 367316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801418860 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.3801418860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4066100393 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 122267387 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 09:47:08 AM UTC 24 |
| Finished | Oct 09 09:47:14 AM UTC 24 |
| Peak memory | 221324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066100393 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.4066100393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1008196980 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 26070043910 ps |
| CPU time | 371.2 seconds |
| Started | Oct 09 09:47:15 AM UTC 24 |
| Finished | Oct 09 09:53:32 AM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008196980 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acc ess_b2b.1008196980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3012197957 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 90870116 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 09:47:44 AM UTC 24 |
| Finished | Oct 09 09:47:47 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012197957 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3012197957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_readback_err.3865394021 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 36358208 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 09:47:50 AM UTC 24 |
| Finished | Oct 09 09:47:53 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865394021 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_readback_err.3865394021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.3666634683 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2800625469 ps |
| CPU time | 860.64 seconds |
| Started | Oct 09 09:47:44 AM UTC 24 |
| Finished | Oct 09 10:02:16 AM UTC 24 |
| Peak memory | 377368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666634683 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3666634683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.4087213035 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 76763775 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 09:46:52 AM UTC 24 |
| Finished | Oct 09 09:46:58 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087213035 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.4087213035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3802564460 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 5137179519 ps |
| CPU time | 1115.62 seconds |
| Started | Oct 09 09:47:54 AM UTC 24 |
| Finished | Oct 09 10:06:43 AM UTC 24 |
| Peak memory | 383668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380256446 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.3802564460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.830848717 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1556055300 ps |
| CPU time | 212.24 seconds |
| Started | Oct 09 09:47:54 AM UTC 24 |
| Finished | Oct 09 09:51:30 AM UTC 24 |
| Peak memory | 397836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830848717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.830848717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1109509695 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 14696893161 ps |
| CPU time | 479.43 seconds |
| Started | Oct 09 09:46:59 AM UTC 24 |
| Finished | Oct 09 09:55:05 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109509695 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.1109509695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3087260735 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 108719652 ps |
| CPU time | 43.18 seconds |
| Started | Oct 09 09:47:21 AM UTC 24 |
| Finished | Oct 09 09:48:05 AM UTC 24 |
| Peak memory | 311680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3087260735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t hroughput_w_partial_write.3087260735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.785776516 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1843050565 ps |
| CPU time | 631.36 seconds |
| Started | Oct 09 09:48:28 AM UTC 24 |
| Finished | Oct 09 09:59:07 AM UTC 24 |
| Peak memory | 383352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785776516 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_ key_req.785776516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.385274594 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 42637985 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 09:49:16 AM UTC 24 |
| Finished | Oct 09 09:49:18 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385274594 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.385274594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1604755364 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 19423066502 ps |
| CPU time | 80.32 seconds |
| Started | Oct 09 09:47:58 AM UTC 24 |
| Finished | Oct 09 09:49:21 AM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604755364 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.1604755364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.538266405 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 31568340660 ps |
| CPU time | 624.6 seconds |
| Started | Oct 09 09:48:36 AM UTC 24 |
| Finished | Oct 09 09:59:09 AM UTC 24 |
| Peak memory | 373444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538266405 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.538266405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.812566996 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 695122544 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 09:48:23 AM UTC 24 |
| Finished | Oct 09 09:48:27 AM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812566996 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.812566996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.769476856 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1399237310 ps |
| CPU time | 32.78 seconds |
| Started | Oct 09 09:48:18 AM UTC 24 |
| Finished | Oct 09 09:48:52 AM UTC 24 |
| Peak memory | 330108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 69476856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max _throughput.769476856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2680382578 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 175255333 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 09:49:04 AM UTC 24 |
| Finished | Oct 09 09:49:10 AM UTC 24 |
| Peak memory | 223036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680382578 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.2680382578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.261980897 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 232023376 ps |
| CPU time | 6 seconds |
| Started | Oct 09 09:48:56 AM UTC 24 |
| Finished | Oct 09 09:49:03 AM UTC 24 |
| Peak memory | 222996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261980897 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.261980897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2739490967 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 9852530868 ps |
| CPU time | 354.46 seconds |
| Started | Oct 09 09:47:58 AM UTC 24 |
| Finished | Oct 09 09:53:58 AM UTC 24 |
| Peak memory | 367052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739490967 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.2739490967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1408620722 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3847492414 ps |
| CPU time | 13.58 seconds |
| Started | Oct 09 09:48:01 AM UTC 24 |
| Finished | Oct 09 09:48:17 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408620722 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.1408620722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1508976984 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 50628870795 ps |
| CPU time | 331.35 seconds |
| Started | Oct 09 09:48:07 AM UTC 24 |
| Finished | Oct 09 09:53:44 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508976984 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc ess_b2b.1508976984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.38692796 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 189371763 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 09:48:53 AM UTC 24 |
| Finished | Oct 09 09:48:55 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38692796 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.38692796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_readback_err.1664192067 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 153021072 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 09:49:11 AM UTC 24 |
| Finished | Oct 09 09:49:13 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664192067 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_readback_err.1664192067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.4158661109 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 14645898632 ps |
| CPU time | 474.7 seconds |
| Started | Oct 09 09:48:44 AM UTC 24 |
| Finished | Oct 09 09:56:45 AM UTC 24 |
| Peak memory | 385824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158661109 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.4158661109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.3522325587 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1063317579 ps |
| CPU time | 22.21 seconds |
| Started | Oct 09 09:47:54 AM UTC 24 |
| Finished | Oct 09 09:48:18 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522325587 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3522325587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1408291104 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 47485048406 ps |
| CPU time | 2947 seconds |
| Started | Oct 09 09:49:14 AM UTC 24 |
| Finished | Oct 09 10:38:52 AM UTC 24 |
| Peak memory | 395280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140829110 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.1408291104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2160997328 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2364177621 ps |
| CPU time | 23.4 seconds |
| Started | Oct 09 09:49:13 AM UTC 24 |
| Finished | Oct 09 09:49:38 AM UTC 24 |
| Peak memory | 223220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160997328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2160997328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.250080147 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4845679231 ps |
| CPU time | 505.63 seconds |
| Started | Oct 09 09:48:01 AM UTC 24 |
| Finished | Oct 09 09:56:34 AM UTC 24 |
| Peak memory | 212660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250080147 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.250080147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4226543366 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 192414475 ps |
| CPU time | 22.94 seconds |
| Started | Oct 09 09:48:19 AM UTC 24 |
| Finished | Oct 09 09:48:43 AM UTC 24 |
| Peak memory | 299400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4226543366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t hroughput_w_partial_write.4226543366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.353715720 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 524796515 ps |
| CPU time | 96.45 seconds |
| Started | Oct 09 09:50:12 AM UTC 24 |
| Finished | Oct 09 09:51:50 AM UTC 24 |
| Peak memory | 375248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353715720 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during_ key_req.353715720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.607695945 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 40792713 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 09:51:06 AM UTC 24 |
| Finished | Oct 09 09:51:08 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607695945 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.607695945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2195694721 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4343136635 ps |
| CPU time | 90.68 seconds |
| Started | Oct 09 09:49:24 AM UTC 24 |
| Finished | Oct 09 09:50:56 AM UTC 24 |
| Peak memory | 212612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195694721 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.2195694721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.3981321314 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 15224945798 ps |
| CPU time | 888.47 seconds |
| Started | Oct 09 09:50:17 AM UTC 24 |
| Finished | Oct 09 10:05:17 AM UTC 24 |
| Peak memory | 383496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981321314 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.3981321314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2719841952 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1231987173 ps |
| CPU time | 12.76 seconds |
| Started | Oct 09 09:50:01 AM UTC 24 |
| Finished | Oct 09 09:50:15 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719841952 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.2719841952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1132884586 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 138516550 ps |
| CPU time | 90.47 seconds |
| Started | Oct 09 09:49:39 AM UTC 24 |
| Finished | Oct 09 09:51:12 AM UTC 24 |
| Peak memory | 379600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 132884586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ma x_throughput.1132884586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3517328461 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 576104282 ps |
| CPU time | 6.55 seconds |
| Started | Oct 09 09:50:57 AM UTC 24 |
| Finished | Oct 09 09:51:05 AM UTC 24 |
| Peak memory | 222796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517328461 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.3517328461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.472915615 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 118241050 ps |
| CPU time | 7.55 seconds |
| Started | Oct 09 09:50:51 AM UTC 24 |
| Finished | Oct 09 09:51:00 AM UTC 24 |
| Peak memory | 222876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472915615 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.472915615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.668817783 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 6362495698 ps |
| CPU time | 342.58 seconds |
| Started | Oct 09 09:49:21 AM UTC 24 |
| Finished | Oct 09 09:55:09 AM UTC 24 |
| Peak memory | 373256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668817783 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.668817783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3337456386 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 336119827 ps |
| CPU time | 26.73 seconds |
| Started | Oct 09 09:49:32 AM UTC 24 |
| Finished | Oct 09 09:50:00 AM UTC 24 |
| Peak memory | 278940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337456386 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.3337456386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1328242579 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3575406512 ps |
| CPU time | 310.17 seconds |
| Started | Oct 09 09:49:37 AM UTC 24 |
| Finished | Oct 09 09:54:52 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328242579 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc ess_b2b.1328242579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1549281192 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 100142841 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 09:50:48 AM UTC 24 |
| Finished | Oct 09 09:50:50 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549281192 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1549281192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_readback_err.2767785561 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 148950652 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 09:51:00 AM UTC 24 |
| Finished | Oct 09 09:51:03 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767785561 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_readback_err.2767785561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1850046387 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 14700052916 ps |
| CPU time | 763.03 seconds |
| Started | Oct 09 09:50:38 AM UTC 24 |
| Finished | Oct 09 10:03:30 AM UTC 24 |
| Peak memory | 385760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850046387 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1850046387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.236589035 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 297111855 ps |
| CPU time | 5.76 seconds |
| Started | Oct 09 09:49:19 AM UTC 24 |
| Finished | Oct 09 09:49:26 AM UTC 24 |
| Peak memory | 235916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236589035 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.236589035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3950631021 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 618052809001 ps |
| CPU time | 3082.73 seconds |
| Started | Oct 09 09:51:05 AM UTC 24 |
| Finished | Oct 09 10:42:59 AM UTC 24 |
| Peak memory | 395276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395063102 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.3950631021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.728040848 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1591460962 ps |
| CPU time | 54.27 seconds |
| Started | Oct 09 09:51:04 AM UTC 24 |
| Finished | Oct 09 09:52:00 AM UTC 24 |
| Peak memory | 225272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728040848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.728040848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.451026419 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 9215142889 ps |
| CPU time | 227.11 seconds |
| Started | Oct 09 09:49:27 AM UTC 24 |
| Finished | Oct 09 09:53:17 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451026419 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.451026419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2563537599 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 763069119 ps |
| CPU time | 71.53 seconds |
| Started | Oct 09 09:49:50 AM UTC 24 |
| Finished | Oct 09 09:51:04 AM UTC 24 |
| Peak memory | 379200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2563537599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t hroughput_w_partial_write.2563537599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2554185027 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3183795895 ps |
| CPU time | 451.74 seconds |
| Started | Oct 09 09:51:48 AM UTC 24 |
| Finished | Oct 09 09:59:26 AM UTC 24 |
| Peak memory | 383396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554185027 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during _key_req.2554185027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2115969517 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 25519569 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 09:52:03 AM UTC 24 |
| Finished | Oct 09 09:52:05 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115969517 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2115969517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.1582712589 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 579943018 ps |
| CPU time | 28.72 seconds |
| Started | Oct 09 09:51:17 AM UTC 24 |
| Finished | Oct 09 09:51:47 AM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582712589 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.1582712589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3167353014 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 9934760633 ps |
| CPU time | 717.84 seconds |
| Started | Oct 09 09:51:51 AM UTC 24 |
| Finished | Oct 09 10:03:58 AM UTC 24 |
| Peak memory | 369104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167353014 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.3167353014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2483607240 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 378222803 ps |
| CPU time | 6.23 seconds |
| Started | Oct 09 09:51:45 AM UTC 24 |
| Finished | Oct 09 09:51:52 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483607240 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2483607240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1332145028 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 72251483 ps |
| CPU time | 17.79 seconds |
| Started | Oct 09 09:51:31 AM UTC 24 |
| Finished | Oct 09 09:51:51 AM UTC 24 |
| Peak memory | 270800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 332145028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ma x_throughput.1332145028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3421165844 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 423262318 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 09:51:57 AM UTC 24 |
| Finished | Oct 09 09:52:02 AM UTC 24 |
| Peak memory | 222964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421165844 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.3421165844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3857923844 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1591564849 ps |
| CPU time | 8.47 seconds |
| Started | Oct 09 09:51:55 AM UTC 24 |
| Finished | Oct 09 09:52:04 AM UTC 24 |
| Peak memory | 223088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857923844 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.3857923844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4269207135 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4383614419 ps |
| CPU time | 365.02 seconds |
| Started | Oct 09 09:51:12 AM UTC 24 |
| Finished | Oct 09 09:57:23 AM UTC 24 |
| Peak memory | 364988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269207135 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.4269207135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3963574522 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 564844945 ps |
| CPU time | 19.06 seconds |
| Started | Oct 09 09:51:24 AM UTC 24 |
| Finished | Oct 09 09:51:44 AM UTC 24 |
| Peak memory | 212608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963574522 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.3963574522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.411426389 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 76393068859 ps |
| CPU time | 528.21 seconds |
| Started | Oct 09 09:51:27 AM UTC 24 |
| Finished | Oct 09 10:00:22 AM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411426389 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acce ss_b2b.411426389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3830036528 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 82076864 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 09:51:54 AM UTC 24 |
| Finished | Oct 09 09:51:56 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830036528 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3830036528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3924050875 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 32272855 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 09:52:01 AM UTC 24 |
| Finished | Oct 09 09:52:03 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924050875 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_readback_err.3924050875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2596949181 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 15837849006 ps |
| CPU time | 575.22 seconds |
| Started | Oct 09 09:51:51 AM UTC 24 |
| Finished | Oct 09 10:01:34 AM UTC 24 |
| Peak memory | 356812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596949181 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2596949181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2750756752 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 854378188 ps |
| CPU time | 42.85 seconds |
| Started | Oct 09 09:51:09 AM UTC 24 |
| Finished | Oct 09 09:51:53 AM UTC 24 |
| Peak memory | 311748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750756752 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2750756752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3109400901 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 78429851329 ps |
| CPU time | 2535.89 seconds |
| Started | Oct 09 09:52:03 AM UTC 24 |
| Finished | Oct 09 10:34:47 AM UTC 24 |
| Peak memory | 385040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310940090 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.3109400901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2491852779 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1118669389 ps |
| CPU time | 181.59 seconds |
| Started | Oct 09 09:52:02 AM UTC 24 |
| Finished | Oct 09 09:55:07 AM UTC 24 |
| Peak memory | 385484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491852779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2491852779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1860979152 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 14258414496 ps |
| CPU time | 246.57 seconds |
| Started | Oct 09 09:51:18 AM UTC 24 |
| Finished | Oct 09 09:55:29 AM UTC 24 |
| Peak memory | 212576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860979152 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.1860979152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1802193092 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 235372934 ps |
| CPU time | 34.22 seconds |
| Started | Oct 09 09:51:36 AM UTC 24 |
| Finished | Oct 09 09:52:12 AM UTC 24 |
| Peak memory | 328408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1802193092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_t hroughput_w_partial_write.1802193092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3351239911 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2416362044 ps |
| CPU time | 492.95 seconds |
| Started | Oct 09 08:52:37 AM UTC 24 |
| Finished | Oct 09 09:00:56 AM UTC 24 |
| Peak memory | 355024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351239911 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_ key_req.3351239911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2027832063 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 70774176 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 08:53:16 AM UTC 24 |
| Finished | Oct 09 08:53:18 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027832063 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2027832063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.909427713 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1726615711 ps |
| CPU time | 65.88 seconds |
| Started | Oct 09 08:51:52 AM UTC 24 |
| Finished | Oct 09 08:52:59 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909427713 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.909427713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2980983478 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 11249008102 ps |
| CPU time | 1301.04 seconds |
| Started | Oct 09 08:52:45 AM UTC 24 |
| Finished | Oct 09 09:14:41 AM UTC 24 |
| Peak memory | 381636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980983478 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.2980983478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.229737776 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1134666507 ps |
| CPU time | 10 seconds |
| Started | Oct 09 08:52:32 AM UTC 24 |
| Finished | Oct 09 08:52:44 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229737776 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.229737776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.4122255436 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 80809314 ps |
| CPU time | 3.96 seconds |
| Started | Oct 09 08:52:26 AM UTC 24 |
| Finished | Oct 09 08:52:32 AM UTC 24 |
| Peak memory | 229228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 122255436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max _throughput.4122255436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1075000975 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 356199168 ps |
| CPU time | 6.8 seconds |
| Started | Oct 09 08:53:08 AM UTC 24 |
| Finished | Oct 09 08:53:16 AM UTC 24 |
| Peak memory | 222760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075000975 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.1075000975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1271303143 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 355652979 ps |
| CPU time | 9.43 seconds |
| Started | Oct 09 08:53:07 AM UTC 24 |
| Finished | Oct 09 08:53:17 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271303143 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.1271303143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.859656873 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6039969141 ps |
| CPU time | 485.44 seconds |
| Started | Oct 09 08:51:50 AM UTC 24 |
| Finished | Oct 09 09:00:01 AM UTC 24 |
| Peak memory | 383456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859656873 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.859656873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2828450351 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 456058656 ps |
| CPU time | 45.27 seconds |
| Started | Oct 09 08:52:09 AM UTC 24 |
| Finished | Oct 09 08:52:56 AM UTC 24 |
| Peak memory | 303740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828450351 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.2828450351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2714210784 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 14354468353 ps |
| CPU time | 401 seconds |
| Started | Oct 09 08:52:12 AM UTC 24 |
| Finished | Oct 09 08:58:59 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714210784 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce ss_b2b.2714210784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.916381841 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 27850240 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 08:52:57 AM UTC 24 |
| Finished | Oct 09 08:52:59 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916381841 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.916381841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_readback_err.249864618 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 67722700 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 08:53:08 AM UTC 24 |
| Finished | Oct 09 08:53:10 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249864618 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_readback_err.249864618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.987261497 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 60950450843 ps |
| CPU time | 1655.67 seconds |
| Started | Oct 09 08:52:47 AM UTC 24 |
| Finished | Oct 09 09:20:40 AM UTC 24 |
| Peak memory | 381648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987261497 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.987261497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2376147496 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 63348909 ps |
| CPU time | 10.34 seconds |
| Started | Oct 09 08:51:48 AM UTC 24 |
| Finished | Oct 09 08:52:00 AM UTC 24 |
| Peak memory | 246160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376147496 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2376147496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.360829478 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 103606793087 ps |
| CPU time | 3876.42 seconds |
| Started | Oct 09 08:53:11 AM UTC 24 |
| Finished | Oct 09 09:58:30 AM UTC 24 |
| Peak memory | 387064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360829478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.360829478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.587839745 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 8203287171 ps |
| CPU time | 226.41 seconds |
| Started | Oct 09 08:52:01 AM UTC 24 |
| Finished | Oct 09 08:55:51 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587839745 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.587839745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3474340005 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 57425545 ps |
| CPU time | 7.26 seconds |
| Started | Oct 09 08:52:27 AM UTC 24 |
| Finished | Oct 09 08:52:36 AM UTC 24 |
| Peak memory | 246428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3474340005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th roughput_w_partial_write.3474340005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3834477968 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 13414396682 ps |
| CPU time | 885.58 seconds |
| Started | Oct 09 09:53:04 AM UTC 24 |
| Finished | Oct 09 10:08:00 AM UTC 24 |
| Peak memory | 383404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834477968 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during _key_req.3834477968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1991114882 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 13148660 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 09:53:22 AM UTC 24 |
| Finished | Oct 09 09:53:24 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991114882 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1991114882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.608633497 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1097916490 ps |
| CPU time | 19.68 seconds |
| Started | Oct 09 09:52:07 AM UTC 24 |
| Finished | Oct 09 09:52:28 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608633497 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.608633497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3091600693 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 18006637977 ps |
| CPU time | 1117.77 seconds |
| Started | Oct 09 09:53:08 AM UTC 24 |
| Finished | Oct 09 10:11:59 AM UTC 24 |
| Peak memory | 383512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091600693 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.3091600693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3439137303 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 452650195 ps |
| CPU time | 6.63 seconds |
| Started | Oct 09 09:53:02 AM UTC 24 |
| Finished | Oct 09 09:53:10 AM UTC 24 |
| Peak memory | 222852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439137303 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.3439137303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.4134742256 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 105925482 ps |
| CPU time | 47.25 seconds |
| Started | Oct 09 09:52:25 AM UTC 24 |
| Finished | Oct 09 09:53:14 AM UTC 24 |
| Peak memory | 330116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 134742256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ma x_throughput.4134742256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.4036919515 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 265466756 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 09:53:15 AM UTC 24 |
| Finished | Oct 09 09:53:21 AM UTC 24 |
| Peak memory | 223088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036919515 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.4036919515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2125120746 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 82968248 ps |
| CPU time | 5.15 seconds |
| Started | Oct 09 09:53:14 AM UTC 24 |
| Finished | Oct 09 09:53:20 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125120746 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2125120746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1620097469 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 17404581073 ps |
| CPU time | 950.36 seconds |
| Started | Oct 09 09:52:05 AM UTC 24 |
| Finished | Oct 09 10:08:06 AM UTC 24 |
| Peak memory | 385740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620097469 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1620097469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.650383970 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 180896826 ps |
| CPU time | 47.66 seconds |
| Started | Oct 09 09:52:14 AM UTC 24 |
| Finished | Oct 09 09:53:03 AM UTC 24 |
| Peak memory | 332412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650383970 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.650383970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3243414841 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 16327980498 ps |
| CPU time | 219.39 seconds |
| Started | Oct 09 09:52:21 AM UTC 24 |
| Finished | Oct 09 09:56:05 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243414841 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc ess_b2b.3243414841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3013266493 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 31499775 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 09:53:11 AM UTC 24 |
| Finished | Oct 09 09:53:13 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013266493 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3013266493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_readback_err.1558099455 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 328145640 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 09:53:18 AM UTC 24 |
| Finished | Oct 09 09:53:21 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558099455 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_readback_err.1558099455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1642523622 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 29530681153 ps |
| CPU time | 1247.61 seconds |
| Started | Oct 09 09:53:11 AM UTC 24 |
| Finished | Oct 09 10:14:13 AM UTC 24 |
| Peak memory | 385568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642523622 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1642523622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3295304102 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 711328108 ps |
| CPU time | 76.78 seconds |
| Started | Oct 09 09:52:04 AM UTC 24 |
| Finished | Oct 09 09:53:23 AM UTC 24 |
| Peak memory | 364940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295304102 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3295304102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.1976608781 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 6959162433 ps |
| CPU time | 719.95 seconds |
| Started | Oct 09 09:53:22 AM UTC 24 |
| Finished | Oct 09 10:05:31 AM UTC 24 |
| Peak memory | 377608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197660878 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.1976608781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3210519824 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 11140612329 ps |
| CPU time | 269.22 seconds |
| Started | Oct 09 09:53:21 AM UTC 24 |
| Finished | Oct 09 09:57:54 AM UTC 24 |
| Peak memory | 385600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210519824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3210519824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1641908767 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2181778939 ps |
| CPU time | 251.23 seconds |
| Started | Oct 09 09:52:13 AM UTC 24 |
| Finished | Oct 09 09:56:28 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641908767 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.1641908767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.25151721 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1316467684 ps |
| CPU time | 39.78 seconds |
| Started | Oct 09 09:52:28 AM UTC 24 |
| Finished | Oct 09 09:53:10 AM UTC 24 |
| Peak memory | 315912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 25151721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_thr oughput_w_partial_write.25151721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1665338836 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 8447680431 ps |
| CPU time | 748.06 seconds |
| Started | Oct 09 09:53:53 AM UTC 24 |
| Finished | Oct 09 10:06:30 AM UTC 24 |
| Peak memory | 354752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665338836 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during _key_req.1665338836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.94405815 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 13020913 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 09:54:49 AM UTC 24 |
| Finished | Oct 09 09:54:51 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94405815 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.94405815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3544647750 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5632316952 ps |
| CPU time | 24.9 seconds |
| Started | Oct 09 09:53:25 AM UTC 24 |
| Finished | Oct 09 09:53:51 AM UTC 24 |
| Peak memory | 212924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544647750 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.3544647750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.177336405 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1705740526 ps |
| CPU time | 417.81 seconds |
| Started | Oct 09 09:53:56 AM UTC 24 |
| Finished | Oct 09 10:00:59 AM UTC 24 |
| Peak memory | 373172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177336405 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.177336405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3631298145 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 290292113 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 09:53:52 AM UTC 24 |
| Finished | Oct 09 09:53:55 AM UTC 24 |
| Peak memory | 222852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631298145 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.3631298145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2174414961 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 830734118 ps |
| CPU time | 52.77 seconds |
| Started | Oct 09 09:53:45 AM UTC 24 |
| Finished | Oct 09 09:54:39 AM UTC 24 |
| Peak memory | 324168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 174414961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma x_throughput.2174414961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3881703075 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 351372706 ps |
| CPU time | 7.78 seconds |
| Started | Oct 09 09:54:39 AM UTC 24 |
| Finished | Oct 09 09:54:48 AM UTC 24 |
| Peak memory | 222848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881703075 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.3881703075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.690395949 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 207401323 ps |
| CPU time | 11.83 seconds |
| Started | Oct 09 09:54:27 AM UTC 24 |
| Finished | Oct 09 09:54:40 AM UTC 24 |
| Peak memory | 222872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690395949 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.690395949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.501330863 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 16273580760 ps |
| CPU time | 197.96 seconds |
| Started | Oct 09 09:53:24 AM UTC 24 |
| Finished | Oct 09 09:56:45 AM UTC 24 |
| Peak memory | 352716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501330863 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.501330863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2210026771 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 677118821 ps |
| CPU time | 18.07 seconds |
| Started | Oct 09 09:53:32 AM UTC 24 |
| Finished | Oct 09 09:53:52 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210026771 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.2210026771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2343364485 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 6369529883 ps |
| CPU time | 258 seconds |
| Started | Oct 09 09:53:44 AM UTC 24 |
| Finished | Oct 09 09:58:06 AM UTC 24 |
| Peak memory | 212876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343364485 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc ess_b2b.2343364485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3501720783 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 27614184 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 09:54:24 AM UTC 24 |
| Finished | Oct 09 09:54:26 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501720783 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3501720783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_readback_err.2477580090 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 54267346 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 09:54:40 AM UTC 24 |
| Finished | Oct 09 09:54:43 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477580090 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_readback_err.2477580090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1187128422 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 20790426983 ps |
| CPU time | 1370.66 seconds |
| Started | Oct 09 09:53:58 AM UTC 24 |
| Finished | Oct 09 10:17:04 AM UTC 24 |
| Peak memory | 383628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187128422 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1187128422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.4129964094 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 150833878 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 09:53:23 AM UTC 24 |
| Finished | Oct 09 09:53:28 AM UTC 24 |
| Peak memory | 212652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129964094 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4129964094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.4169468258 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 29699891494 ps |
| CPU time | 1658.17 seconds |
| Started | Oct 09 09:54:43 AM UTC 24 |
| Finished | Oct 09 10:22:39 AM UTC 24 |
| Peak memory | 385536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416946825 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.4169468258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.978799782 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2308418275 ps |
| CPU time | 331.7 seconds |
| Started | Oct 09 09:54:41 AM UTC 24 |
| Finished | Oct 09 10:00:18 AM UTC 24 |
| Peak memory | 389716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978799782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.978799782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.503576046 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3558313041 ps |
| CPU time | 373.71 seconds |
| Started | Oct 09 09:53:29 AM UTC 24 |
| Finished | Oct 09 09:59:48 AM UTC 24 |
| Peak memory | 212616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503576046 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.503576046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2737686257 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 447985984 ps |
| CPU time | 51.04 seconds |
| Started | Oct 09 09:53:45 AM UTC 24 |
| Finished | Oct 09 09:54:38 AM UTC 24 |
| Peak memory | 350656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2737686257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t hroughput_w_partial_write.2737686257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2420683363 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1868785638 ps |
| CPU time | 28.27 seconds |
| Started | Oct 09 09:56:15 AM UTC 24 |
| Finished | Oct 09 09:56:45 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420683363 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during _key_req.2420683363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.288232260 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 16217813 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 09:56:45 AM UTC 24 |
| Finished | Oct 09 09:56:47 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288232260 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.288232260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3302401709 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4325272494 ps |
| CPU time | 70.87 seconds |
| Started | Oct 09 09:55:06 AM UTC 24 |
| Finished | Oct 09 09:56:19 AM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302401709 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.3302401709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.2416630772 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 9974898597 ps |
| CPU time | 419.26 seconds |
| Started | Oct 09 09:56:20 AM UTC 24 |
| Finished | Oct 09 10:03:25 AM UTC 24 |
| Peak memory | 356816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416630772 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.2416630772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1199818051 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 164105508 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 09:56:11 AM UTC 24 |
| Finished | Oct 09 09:56:14 AM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199818051 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.1199818051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.3757730409 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 207838149 ps |
| CPU time | 99.16 seconds |
| Started | Oct 09 09:55:33 AM UTC 24 |
| Finished | Oct 09 09:57:14 AM UTC 24 |
| Peak memory | 379272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 757730409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma x_throughput.3757730409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2466389454 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 333925909 ps |
| CPU time | 3.84 seconds |
| Started | Oct 09 09:56:35 AM UTC 24 |
| Finished | Oct 09 09:56:40 AM UTC 24 |
| Peak memory | 222792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466389454 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.2466389454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.15615885 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 901086278 ps |
| CPU time | 7.37 seconds |
| Started | Oct 09 09:56:33 AM UTC 24 |
| Finished | Oct 09 09:56:41 AM UTC 24 |
| Peak memory | 222736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15615885 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.15615885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1651194681 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 5013575521 ps |
| CPU time | 104.78 seconds |
| Started | Oct 09 09:54:53 AM UTC 24 |
| Finished | Oct 09 09:56:41 AM UTC 24 |
| Peak memory | 336388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651194681 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.1651194681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2004908242 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1062792617 ps |
| CPU time | 20.69 seconds |
| Started | Oct 09 09:55:09 AM UTC 24 |
| Finished | Oct 09 09:55:32 AM UTC 24 |
| Peak memory | 212548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004908242 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.2004908242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3800990082 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 53969586632 ps |
| CPU time | 389.78 seconds |
| Started | Oct 09 09:55:30 AM UTC 24 |
| Finished | Oct 09 10:02:05 AM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800990082 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acc ess_b2b.3800990082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.140447781 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 246022806 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 09:56:30 AM UTC 24 |
| Finished | Oct 09 09:56:32 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140447781 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.140447781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_readback_err.1112258746 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 152856264 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 09:56:41 AM UTC 24 |
| Finished | Oct 09 09:56:44 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112258746 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_readback_err.1112258746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3559701715 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 72468518043 ps |
| CPU time | 1214.44 seconds |
| Started | Oct 09 09:56:25 AM UTC 24 |
| Finished | Oct 09 10:16:54 AM UTC 24 |
| Peak memory | 373280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559701715 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3559701715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.1750667501 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 264239191 ps |
| CPU time | 90.46 seconds |
| Started | Oct 09 09:54:52 AM UTC 24 |
| Finished | Oct 09 09:56:24 AM UTC 24 |
| Peak memory | 377228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750667501 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1750667501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1863664640 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4610721116 ps |
| CPU time | 1121.49 seconds |
| Started | Oct 09 09:56:42 AM UTC 24 |
| Finished | Oct 09 10:15:37 AM UTC 24 |
| Peak memory | 379636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186366464 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.1863664640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.996491345 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 19371082120 ps |
| CPU time | 226.48 seconds |
| Started | Oct 09 09:55:08 AM UTC 24 |
| Finished | Oct 09 09:58:58 AM UTC 24 |
| Peak memory | 212912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996491345 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.996491345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.4003834536 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 182696305 ps |
| CPU time | 3.42 seconds |
| Started | Oct 09 09:56:06 AM UTC 24 |
| Finished | Oct 09 09:56:10 AM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4003834536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.4003834536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.161442432 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 8612019359 ps |
| CPU time | 980.15 seconds |
| Started | Oct 09 09:57:55 AM UTC 24 |
| Finished | Oct 09 10:14:27 AM UTC 24 |
| Peak memory | 383424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161442432 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during_ key_req.161442432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.4174571271 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 53009253 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 09:58:21 AM UTC 24 |
| Finished | Oct 09 09:58:23 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174571271 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.4174571271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.1707749133 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 228750570 ps |
| CPU time | 19.52 seconds |
| Started | Oct 09 09:56:47 AM UTC 24 |
| Finished | Oct 09 09:57:08 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707749133 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.1707749133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2982813365 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 16111026084 ps |
| CPU time | 296.81 seconds |
| Started | Oct 09 09:57:57 AM UTC 24 |
| Finished | Oct 09 10:02:58 AM UTC 24 |
| Peak memory | 383624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982813365 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.2982813365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.609994857 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 827722254 ps |
| CPU time | 9.24 seconds |
| Started | Oct 09 09:57:46 AM UTC 24 |
| Finished | Oct 09 09:57:56 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609994857 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.609994857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.2963095148 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 170323955 ps |
| CPU time | 84.86 seconds |
| Started | Oct 09 09:57:15 AM UTC 24 |
| Finished | Oct 09 09:58:42 AM UTC 24 |
| Peak memory | 379344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 963095148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma x_throughput.2963095148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.716080529 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 155808376 ps |
| CPU time | 6.86 seconds |
| Started | Oct 09 09:58:08 AM UTC 24 |
| Finished | Oct 09 09:58:16 AM UTC 24 |
| Peak memory | 223100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716080529 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.716080529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.4275532215 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 353125631 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 09:58:06 AM UTC 24 |
| Finished | Oct 09 09:58:20 AM UTC 24 |
| Peak memory | 222852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275532215 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.4275532215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2193836422 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 6408784320 ps |
| CPU time | 624.26 seconds |
| Started | Oct 09 09:56:46 AM UTC 24 |
| Finished | Oct 09 10:07:18 AM UTC 24 |
| Peak memory | 379592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193836422 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.2193836422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1928278405 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 793408597 ps |
| CPU time | 39.19 seconds |
| Started | Oct 09 09:57:04 AM UTC 24 |
| Finished | Oct 09 09:57:45 AM UTC 24 |
| Peak memory | 313784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928278405 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.1928278405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1897823174 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 12509959638 ps |
| CPU time | 305.01 seconds |
| Started | Oct 09 09:57:08 AM UTC 24 |
| Finished | Oct 09 10:02:18 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897823174 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc ess_b2b.1897823174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2791801683 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 80788518 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 09:58:04 AM UTC 24 |
| Finished | Oct 09 09:58:07 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791801683 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.2791801683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_readback_err.1411663751 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 325676334 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 09:58:09 AM UTC 24 |
| Finished | Oct 09 09:58:12 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411663751 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_readback_err.1411663751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.519620326 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 23866231620 ps |
| CPU time | 682.84 seconds |
| Started | Oct 09 09:58:00 AM UTC 24 |
| Finished | Oct 09 10:09:32 AM UTC 24 |
| Peak memory | 377480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519620326 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.519620326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.92619375 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 110887053 ps |
| CPU time | 71.9 seconds |
| Started | Oct 09 09:56:46 AM UTC 24 |
| Finished | Oct 09 09:57:59 AM UTC 24 |
| Peak memory | 338332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92619375 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.92619375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3567798033 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 28457457525 ps |
| CPU time | 2267.62 seconds |
| Started | Oct 09 09:58:17 AM UTC 24 |
| Finished | Oct 09 10:36:30 AM UTC 24 |
| Peak memory | 389128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356779803 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.3567798033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3801497963 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2791291198 ps |
| CPU time | 62.22 seconds |
| Started | Oct 09 09:58:13 AM UTC 24 |
| Finished | Oct 09 09:59:17 AM UTC 24 |
| Peak memory | 277004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801497963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3801497963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.1363387313 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 19406195913 ps |
| CPU time | 212.61 seconds |
| Started | Oct 09 09:56:48 AM UTC 24 |
| Finished | Oct 09 10:00:24 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363387313 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.1363387313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3661132953 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 207804944 ps |
| CPU time | 42.74 seconds |
| Started | Oct 09 09:57:24 AM UTC 24 |
| Finished | Oct 09 09:58:08 AM UTC 24 |
| Peak memory | 303560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3661132953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_t hroughput_w_partial_write.3661132953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4141517453 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5684877769 ps |
| CPU time | 969.3 seconds |
| Started | Oct 09 09:59:10 AM UTC 24 |
| Finished | Oct 09 10:15:30 AM UTC 24 |
| Peak memory | 383492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141517453 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during _key_req.4141517453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1933503421 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 16511457 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 09:59:34 AM UTC 24 |
| Finished | Oct 09 09:59:36 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933503421 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1933503421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.453808573 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 5850660389 ps |
| CPU time | 47.19 seconds |
| Started | Oct 09 09:58:35 AM UTC 24 |
| Finished | Oct 09 09:59:25 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453808573 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.453808573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.246042504 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 20352005003 ps |
| CPU time | 2063.34 seconds |
| Started | Oct 09 09:59:13 AM UTC 24 |
| Finished | Oct 09 10:33:57 AM UTC 24 |
| Peak memory | 383440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246042504 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.246042504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1855117622 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 672274068 ps |
| CPU time | 10.98 seconds |
| Started | Oct 09 09:59:08 AM UTC 24 |
| Finished | Oct 09 09:59:21 AM UTC 24 |
| Peak memory | 212820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855117622 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.1855117622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2657424029 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 43376362 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 09:58:59 AM UTC 24 |
| Finished | Oct 09 09:59:02 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 657424029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ma x_throughput.2657424029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3445008811 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 246997233 ps |
| CPU time | 6.51 seconds |
| Started | Oct 09 09:59:25 AM UTC 24 |
| Finished | Oct 09 09:59:33 AM UTC 24 |
| Peak memory | 222920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445008811 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.3445008811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3136018112 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 357270277 ps |
| CPU time | 7.23 seconds |
| Started | Oct 09 09:59:25 AM UTC 24 |
| Finished | Oct 09 09:59:33 AM UTC 24 |
| Peak memory | 223116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136018112 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.3136018112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2592494195 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 40586302928 ps |
| CPU time | 207.84 seconds |
| Started | Oct 09 09:58:30 AM UTC 24 |
| Finished | Oct 09 10:02:02 AM UTC 24 |
| Peak memory | 360840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592494195 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.2592494195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.398734524 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 576620176 ps |
| CPU time | 21.96 seconds |
| Started | Oct 09 09:58:49 AM UTC 24 |
| Finished | Oct 09 09:59:12 AM UTC 24 |
| Peak memory | 212552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398734524 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.398734524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1088667171 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 21907896035 ps |
| CPU time | 557.75 seconds |
| Started | Oct 09 09:58:57 AM UTC 24 |
| Finished | Oct 09 10:08:22 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088667171 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc ess_b2b.1088667171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.739744894 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 81430881 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 09:59:22 AM UTC 24 |
| Finished | Oct 09 09:59:24 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739744894 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.739744894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_readback_err.2925731570 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 113346386 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 09:59:26 AM UTC 24 |
| Finished | Oct 09 09:59:29 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925731570 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_readback_err.2925731570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.2857513078 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2145084362 ps |
| CPU time | 309.61 seconds |
| Started | Oct 09 09:59:18 AM UTC 24 |
| Finished | Oct 09 10:04:32 AM UTC 24 |
| Peak memory | 377484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857513078 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2857513078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.2644256916 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 97229196 ps |
| CPU time | 9.68 seconds |
| Started | Oct 09 09:58:24 AM UTC 24 |
| Finished | Oct 09 09:58:35 AM UTC 24 |
| Peak memory | 246036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644256916 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2644256916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2667478434 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 45564873430 ps |
| CPU time | 2482.16 seconds |
| Started | Oct 09 09:59:33 AM UTC 24 |
| Finished | Oct 09 10:41:24 AM UTC 24 |
| Peak memory | 387092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266747843 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.2667478434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4060387879 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1398351450 ps |
| CPU time | 9.41 seconds |
| Started | Oct 09 09:59:29 AM UTC 24 |
| Finished | Oct 09 09:59:40 AM UTC 24 |
| Peak memory | 222860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060387879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.4060387879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1572419946 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2328170701 ps |
| CPU time | 250.32 seconds |
| Started | Oct 09 09:58:43 AM UTC 24 |
| Finished | Oct 09 10:02:57 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572419946 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1572419946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3759244104 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 148712804 ps |
| CPU time | 92.5 seconds |
| Started | Oct 09 09:59:02 AM UTC 24 |
| Finished | Oct 09 10:00:37 AM UTC 24 |
| Peak memory | 377232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3759244104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t hroughput_w_partial_write.3759244104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3885915038 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1481185210 ps |
| CPU time | 181.08 seconds |
| Started | Oct 09 10:00:25 AM UTC 24 |
| Finished | Oct 09 10:03:29 AM UTC 24 |
| Peak memory | 352644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885915038 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during _key_req.3885915038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1052702530 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 40077243 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 10:01:01 AM UTC 24 |
| Finished | Oct 09 10:01:03 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052702530 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1052702530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.860292892 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 3256034039 ps |
| CPU time | 58.36 seconds |
| Started | Oct 09 09:59:39 AM UTC 24 |
| Finished | Oct 09 10:00:39 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860292892 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.860292892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3020176706 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1829595205 ps |
| CPU time | 223.13 seconds |
| Started | Oct 09 10:00:26 AM UTC 24 |
| Finished | Oct 09 10:04:13 AM UTC 24 |
| Peak memory | 360848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020176706 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3020176706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1983091712 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 473023614 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:00:22 AM UTC 24 |
| Finished | Oct 09 10:00:26 AM UTC 24 |
| Peak memory | 212652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983091712 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.1983091712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.4126035888 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 137497345 ps |
| CPU time | 101.6 seconds |
| Started | Oct 09 09:59:55 AM UTC 24 |
| Finished | Oct 09 10:01:39 AM UTC 24 |
| Peak memory | 379544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 126035888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ma x_throughput.4126035888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2515629726 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 43121438 ps |
| CPU time | 4.34 seconds |
| Started | Oct 09 10:00:46 AM UTC 24 |
| Finished | Oct 09 10:00:51 AM UTC 24 |
| Peak memory | 223096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515629726 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.2515629726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1554919284 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1832179188 ps |
| CPU time | 13.52 seconds |
| Started | Oct 09 10:00:45 AM UTC 24 |
| Finished | Oct 09 10:01:00 AM UTC 24 |
| Peak memory | 222728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554919284 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.1554919284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.845663410 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 16214930972 ps |
| CPU time | 718.22 seconds |
| Started | Oct 09 09:59:37 AM UTC 24 |
| Finished | Oct 09 10:11:44 AM UTC 24 |
| Peak memory | 383416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845663410 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.845663410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.730800759 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 120342440 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 09:59:49 AM UTC 24 |
| Finished | Oct 09 09:59:54 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730800759 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.730800759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.633785257 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 49207423055 ps |
| CPU time | 481.84 seconds |
| Started | Oct 09 09:59:53 AM UTC 24 |
| Finished | Oct 09 10:08:01 AM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633785257 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acce ss_b2b.633785257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.509373668 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 162242216 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 10:00:41 AM UTC 24 |
| Finished | Oct 09 10:00:44 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509373668 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.509373668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_readback_err.1679189313 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 105083776 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 10:00:52 AM UTC 24 |
| Finished | Oct 09 10:00:55 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679189313 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_readback_err.1679189313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.2705941223 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 95278393480 ps |
| CPU time | 1736.79 seconds |
| Started | Oct 09 10:00:38 AM UTC 24 |
| Finished | Oct 09 10:29:54 AM UTC 24 |
| Peak memory | 381392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705941223 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2705941223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.1563963245 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1894001788 ps |
| CPU time | 15.55 seconds |
| Started | Oct 09 09:59:35 AM UTC 24 |
| Finished | Oct 09 09:59:52 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563963245 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1563963245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1530715382 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 28419237152 ps |
| CPU time | 1847.47 seconds |
| Started | Oct 09 10:01:01 AM UTC 24 |
| Finished | Oct 09 10:32:09 AM UTC 24 |
| Peak memory | 385524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153071538 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.1530715382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1492708255 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 16388966478 ps |
| CPU time | 112.21 seconds |
| Started | Oct 09 10:00:55 AM UTC 24 |
| Finished | Oct 09 10:02:50 AM UTC 24 |
| Peak memory | 305936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492708255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1492708255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.58289271 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 3312847990 ps |
| CPU time | 249.07 seconds |
| Started | Oct 09 09:59:41 AM UTC 24 |
| Finished | Oct 09 10:03:55 AM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58289271 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.58289271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3669188782 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 161672801 ps |
| CPU time | 78.08 seconds |
| Started | Oct 09 10:00:19 AM UTC 24 |
| Finished | Oct 09 10:01:39 AM UTC 24 |
| Peak memory | 379608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3669188782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t hroughput_w_partial_write.3669188782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.169035177 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 6139348410 ps |
| CPU time | 702.77 seconds |
| Started | Oct 09 10:02:17 AM UTC 24 |
| Finished | Oct 09 10:14:09 AM UTC 24 |
| Peak memory | 383352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169035177 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during_ key_req.169035177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4245314722 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 38802393 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:02:58 AM UTC 24 |
| Finished | Oct 09 10:03:00 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245314722 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.4245314722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.2167677521 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4886752213 ps |
| CPU time | 82.89 seconds |
| Started | Oct 09 10:01:35 AM UTC 24 |
| Finished | Oct 09 10:03:01 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167677521 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.2167677521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3800539951 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2553147476 ps |
| CPU time | 1029.41 seconds |
| Started | Oct 09 10:02:18 AM UTC 24 |
| Finished | Oct 09 10:19:41 AM UTC 24 |
| Peak memory | 383496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800539951 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.3800539951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.251456485 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1308904242 ps |
| CPU time | 7.93 seconds |
| Started | Oct 09 10:02:10 AM UTC 24 |
| Finished | Oct 09 10:02:19 AM UTC 24 |
| Peak memory | 222780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251456485 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.251456485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3361869226 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 38839731 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 10:02:07 AM UTC 24 |
| Finished | Oct 09 10:02:10 AM UTC 24 |
| Peak memory | 221544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 361869226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ma x_throughput.3361869226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2076751220 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 345242441 ps |
| CPU time | 7.55 seconds |
| Started | Oct 09 10:02:41 AM UTC 24 |
| Finished | Oct 09 10:02:49 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076751220 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.2076751220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3585120420 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 9462938034 ps |
| CPU time | 15.24 seconds |
| Started | Oct 09 10:02:24 AM UTC 24 |
| Finished | Oct 09 10:02:40 AM UTC 24 |
| Peak memory | 222784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585120420 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.3585120420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3825059317 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2569647257 ps |
| CPU time | 339.15 seconds |
| Started | Oct 09 10:01:32 AM UTC 24 |
| Finished | Oct 09 10:07:16 AM UTC 24 |
| Peak memory | 383748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825059317 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.3825059317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.929743025 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 1197744526 ps |
| CPU time | 22.92 seconds |
| Started | Oct 09 10:01:40 AM UTC 24 |
| Finished | Oct 09 10:02:05 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929743025 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.929743025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3710583437 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 11108001234 ps |
| CPU time | 218.4 seconds |
| Started | Oct 09 10:02:03 AM UTC 24 |
| Finished | Oct 09 10:05:45 AM UTC 24 |
| Peak memory | 212868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710583437 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc ess_b2b.3710583437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4052211138 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 242488453 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 10:02:21 AM UTC 24 |
| Finished | Oct 09 10:02:23 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052211138 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.4052211138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1498696125 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 94391687 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 10:02:50 AM UTC 24 |
| Finished | Oct 09 10:02:53 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498696125 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_readback_err.1498696125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.820828390 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 25754052661 ps |
| CPU time | 320.66 seconds |
| Started | Oct 09 10:02:19 AM UTC 24 |
| Finished | Oct 09 10:07:45 AM UTC 24 |
| Peak memory | 354772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820828390 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.820828390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2395283176 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 97572068 ps |
| CPU time | 25.72 seconds |
| Started | Oct 09 10:01:04 AM UTC 24 |
| Finished | Oct 09 10:01:31 AM UTC 24 |
| Peak memory | 295364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395283176 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2395283176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.4179895384 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 31521117881 ps |
| CPU time | 2185.88 seconds |
| Started | Oct 09 10:02:53 AM UTC 24 |
| Finished | Oct 09 10:39:44 AM UTC 24 |
| Peak memory | 385688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417989538 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.4179895384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1169674419 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 807988134 ps |
| CPU time | 404.96 seconds |
| Started | Oct 09 10:02:51 AM UTC 24 |
| Finished | Oct 09 10:09:42 AM UTC 24 |
| Peak memory | 387556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169674419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1169674419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.958342353 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 4240039148 ps |
| CPU time | 264.01 seconds |
| Started | Oct 09 10:01:39 AM UTC 24 |
| Finished | Oct 09 10:06:08 AM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958342353 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.958342353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3036418816 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 284760789 ps |
| CPU time | 9.41 seconds |
| Started | Oct 09 10:02:07 AM UTC 24 |
| Finished | Oct 09 10:02:17 AM UTC 24 |
| Peak memory | 262608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3036418816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t hroughput_w_partial_write.3036418816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3181291204 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 197016324 ps |
| CPU time | 13.96 seconds |
| Started | Oct 09 10:03:46 AM UTC 24 |
| Finished | Oct 09 10:04:01 AM UTC 24 |
| Peak memory | 278976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181291204 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during _key_req.3181291204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2210529529 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 41815944 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:04:14 AM UTC 24 |
| Finished | Oct 09 10:04:16 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210529529 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2210529529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3906120697 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 785083952 ps |
| CPU time | 20.1 seconds |
| Started | Oct 09 10:03:02 AM UTC 24 |
| Finished | Oct 09 10:03:23 AM UTC 24 |
| Peak memory | 212844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906120697 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.3906120697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.3321101244 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 1200704255 ps |
| CPU time | 145.92 seconds |
| Started | Oct 09 10:03:55 AM UTC 24 |
| Finished | Oct 09 10:06:24 AM UTC 24 |
| Peak memory | 338392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321101244 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.3321101244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1229942000 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4439232003 ps |
| CPU time | 7.95 seconds |
| Started | Oct 09 10:03:45 AM UTC 24 |
| Finished | Oct 09 10:03:54 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229942000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.1229942000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4210923581 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 522946361 ps |
| CPU time | 104.13 seconds |
| Started | Oct 09 10:03:30 AM UTC 24 |
| Finished | Oct 09 10:05:17 AM UTC 24 |
| Peak memory | 381252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 210923581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ma x_throughput.4210923581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.838804862 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 60376268 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 10:04:02 AM UTC 24 |
| Finished | Oct 09 10:04:08 AM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838804862 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.838804862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1211489016 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 286810796 ps |
| CPU time | 8.48 seconds |
| Started | Oct 09 10:04:02 AM UTC 24 |
| Finished | Oct 09 10:04:12 AM UTC 24 |
| Peak memory | 222820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211489016 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.1211489016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3056002345 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 44210349973 ps |
| CPU time | 117.36 seconds |
| Started | Oct 09 10:03:02 AM UTC 24 |
| Finished | Oct 09 10:05:01 AM UTC 24 |
| Peak memory | 352964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056002345 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.3056002345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2721248211 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 959130353 ps |
| CPU time | 16.59 seconds |
| Started | Oct 09 10:03:26 AM UTC 24 |
| Finished | Oct 09 10:03:44 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721248211 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2721248211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2506433046 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 54210353200 ps |
| CPU time | 346.82 seconds |
| Started | Oct 09 10:03:26 AM UTC 24 |
| Finished | Oct 09 10:09:18 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506433046 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc ess_b2b.2506433046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2342070333 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 82916795 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 10:03:59 AM UTC 24 |
| Finished | Oct 09 10:04:01 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342070333 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2342070333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_readback_err.1124099088 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 101934845 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 10:04:09 AM UTC 24 |
| Finished | Oct 09 10:04:11 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124099088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_readback_err.1124099088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.3098422601 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 6363483400 ps |
| CPU time | 542 seconds |
| Started | Oct 09 10:03:56 AM UTC 24 |
| Finished | Oct 09 10:13:05 AM UTC 24 |
| Peak memory | 385632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098422601 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3098422601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.4234856823 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 358219888 ps |
| CPU time | 23.9 seconds |
| Started | Oct 09 10:02:59 AM UTC 24 |
| Finished | Oct 09 10:03:25 AM UTC 24 |
| Peak memory | 297340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234856823 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.4234856823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1153429323 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 22774431210 ps |
| CPU time | 889.62 seconds |
| Started | Oct 09 10:04:13 AM UTC 24 |
| Finished | Oct 09 10:19:13 AM UTC 24 |
| Peak memory | 385576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115342932 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.1153429323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2293768342 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3765745369 ps |
| CPU time | 383.34 seconds |
| Started | Oct 09 10:03:24 AM UTC 24 |
| Finished | Oct 09 10:09:53 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293768342 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.2293768342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2082033601 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 300582451 ps |
| CPU time | 12.96 seconds |
| Started | Oct 09 10:03:30 AM UTC 24 |
| Finished | Oct 09 10:03:45 AM UTC 24 |
| Peak memory | 262536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2082033601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t hroughput_w_partial_write.2082033601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4224668094 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 2642182980 ps |
| CPU time | 482.01 seconds |
| Started | Oct 09 10:05:52 AM UTC 24 |
| Finished | Oct 09 10:14:01 AM UTC 24 |
| Peak memory | 381632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224668094 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during _key_req.4224668094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2626757170 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 37604775 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:06:21 AM UTC 24 |
| Finished | Oct 09 10:06:23 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626757170 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2626757170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.2430367388 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 6786154118 ps |
| CPU time | 75.63 seconds |
| Started | Oct 09 10:04:33 AM UTC 24 |
| Finished | Oct 09 10:05:51 AM UTC 24 |
| Peak memory | 212576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430367388 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.2430367388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.4214720999 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 5659225110 ps |
| CPU time | 283.86 seconds |
| Started | Oct 09 10:06:02 AM UTC 24 |
| Finished | Oct 09 10:10:50 AM UTC 24 |
| Peak memory | 383512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214720999 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.4214720999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1359599343 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2441103748 ps |
| CPU time | 14.09 seconds |
| Started | Oct 09 10:05:45 AM UTC 24 |
| Finished | Oct 09 10:06:01 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359599343 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.1359599343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.771785550 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 93878382 ps |
| CPU time | 32.3 seconds |
| Started | Oct 09 10:05:32 AM UTC 24 |
| Finished | Oct 09 10:06:06 AM UTC 24 |
| Peak memory | 307596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 71785550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max _throughput.771785550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1211700674 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 175731113 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 10:06:10 AM UTC 24 |
| Finished | Oct 09 10:06:19 AM UTC 24 |
| Peak memory | 222792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211700674 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.1211700674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2100943951 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 146829512 ps |
| CPU time | 5.9 seconds |
| Started | Oct 09 10:06:09 AM UTC 24 |
| Finished | Oct 09 10:06:16 AM UTC 24 |
| Peak memory | 222988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100943951 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.2100943951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.58400756 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 1146496126 ps |
| CPU time | 460.23 seconds |
| Started | Oct 09 10:04:26 AM UTC 24 |
| Finished | Oct 09 10:12:12 AM UTC 24 |
| Peak memory | 381308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58400756 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.58400756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3876326310 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 820037285 ps |
| CPU time | 24.12 seconds |
| Started | Oct 09 10:05:18 AM UTC 24 |
| Finished | Oct 09 10:05:43 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876326310 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.3876326310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3521143785 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 21349009771 ps |
| CPU time | 300.19 seconds |
| Started | Oct 09 10:05:18 AM UTC 24 |
| Finished | Oct 09 10:10:23 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521143785 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc ess_b2b.3521143785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3697600683 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 73660046 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:06:07 AM UTC 24 |
| Finished | Oct 09 10:06:09 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697600683 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3697600683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_readback_err.25559749 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 30079558 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:06:17 AM UTC 24 |
| Finished | Oct 09 10:06:20 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25559749 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_readback_err.25559749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3084368829 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 7083040853 ps |
| CPU time | 816.79 seconds |
| Started | Oct 09 10:06:06 AM UTC 24 |
| Finished | Oct 09 10:19:52 AM UTC 24 |
| Peak memory | 385740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084368829 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3084368829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.796741229 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 163028578 ps |
| CPU time | 6.75 seconds |
| Started | Oct 09 10:04:17 AM UTC 24 |
| Finished | Oct 09 10:04:25 AM UTC 24 |
| Peak memory | 238232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796741229 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.796741229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2900033566 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 34866736778 ps |
| CPU time | 2344.81 seconds |
| Started | Oct 09 10:06:20 AM UTC 24 |
| Finished | Oct 09 10:45:52 AM UTC 24 |
| Peak memory | 387092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290003356 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.2900033566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2555594114 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 1729776290 ps |
| CPU time | 131.58 seconds |
| Started | Oct 09 10:06:19 AM UTC 24 |
| Finished | Oct 09 10:08:34 AM UTC 24 |
| Peak memory | 387528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555594114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2555594114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2955215635 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 2108050779 ps |
| CPU time | 220 seconds |
| Started | Oct 09 10:05:03 AM UTC 24 |
| Finished | Oct 09 10:08:46 AM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955215635 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.2955215635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2819759361 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 182911961 ps |
| CPU time | 32.62 seconds |
| Started | Oct 09 10:05:44 AM UTC 24 |
| Finished | Oct 09 10:06:18 AM UTC 24 |
| Peak memory | 299392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2819759361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t hroughput_w_partial_write.2819759361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3076477809 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 4033097863 ps |
| CPU time | 648.59 seconds |
| Started | Oct 09 10:07:33 AM UTC 24 |
| Finished | Oct 09 10:18:30 AM UTC 24 |
| Peak memory | 383700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076477809 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during _key_req.3076477809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.260486916 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 67050888 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:08:02 AM UTC 24 |
| Finished | Oct 09 10:08:04 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260486916 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.260486916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.3878143227 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 6467297827 ps |
| CPU time | 70.36 seconds |
| Started | Oct 09 10:06:31 AM UTC 24 |
| Finished | Oct 09 10:07:43 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878143227 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.3878143227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1576745875 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3316794687 ps |
| CPU time | 78.86 seconds |
| Started | Oct 09 10:07:36 AM UTC 24 |
| Finished | Oct 09 10:08:57 AM UTC 24 |
| Peak memory | 360904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576745875 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1576745875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1066027969 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 1994402184 ps |
| CPU time | 9.17 seconds |
| Started | Oct 09 10:07:25 AM UTC 24 |
| Finished | Oct 09 10:07:35 AM UTC 24 |
| Peak memory | 222828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066027969 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.1066027969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1787717755 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 371590408 ps |
| CPU time | 3.81 seconds |
| Started | Oct 09 10:07:19 AM UTC 24 |
| Finished | Oct 09 10:07:24 AM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 787717755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma x_throughput.1787717755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3914745392 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 159539154 ps |
| CPU time | 4.2 seconds |
| Started | Oct 09 10:07:54 AM UTC 24 |
| Finished | Oct 09 10:07:59 AM UTC 24 |
| Peak memory | 222828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914745392 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.3914745392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1423135066 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1134281865 ps |
| CPU time | 15.2 seconds |
| Started | Oct 09 10:07:49 AM UTC 24 |
| Finished | Oct 09 10:08:05 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423135066 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.1423135066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3212689314 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 23066251361 ps |
| CPU time | 650.11 seconds |
| Started | Oct 09 10:06:25 AM UTC 24 |
| Finished | Oct 09 10:17:23 AM UTC 24 |
| Peak memory | 377288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212689314 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.3212689314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1093510274 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 1865981364 ps |
| CPU time | 22.33 seconds |
| Started | Oct 09 10:07:08 AM UTC 24 |
| Finished | Oct 09 10:07:32 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093510274 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.1093510274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1488092205 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 23191598086 ps |
| CPU time | 238.76 seconds |
| Started | Oct 09 10:07:18 AM UTC 24 |
| Finished | Oct 09 10:11:21 AM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488092205 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc ess_b2b.1488092205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1704702456 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 58856925 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:07:46 AM UTC 24 |
| Finished | Oct 09 10:07:48 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704702456 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1704702456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_readback_err.3071248056 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 85734282 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 10:07:59 AM UTC 24 |
| Finished | Oct 09 10:08:02 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071248056 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_readback_err.3071248056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.4035435859 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 1569863772 ps |
| CPU time | 89.81 seconds |
| Started | Oct 09 10:07:44 AM UTC 24 |
| Finished | Oct 09 10:09:16 AM UTC 24 |
| Peak memory | 373260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035435859 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.4035435859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.358779707 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 150390946 ps |
| CPU time | 99.14 seconds |
| Started | Oct 09 10:06:24 AM UTC 24 |
| Finished | Oct 09 10:08:05 AM UTC 24 |
| Peak memory | 379284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358779707 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.358779707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1650661173 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3853847051 ps |
| CPU time | 753.59 seconds |
| Started | Oct 09 10:08:01 AM UTC 24 |
| Finished | Oct 09 10:20:44 AM UTC 24 |
| Peak memory | 383492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165066117 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.1650661173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.262969440 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1786986221 ps |
| CPU time | 163.01 seconds |
| Started | Oct 09 10:08:00 AM UTC 24 |
| Finished | Oct 09 10:10:46 AM UTC 24 |
| Peak memory | 356832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262969440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.262969440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1430057476 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2692036312 ps |
| CPU time | 302.16 seconds |
| Started | Oct 09 10:06:44 AM UTC 24 |
| Finished | Oct 09 10:11:52 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430057476 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.1430057476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2425045913 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 754520156 ps |
| CPU time | 31.75 seconds |
| Started | Oct 09 10:07:20 AM UTC 24 |
| Finished | Oct 09 10:07:53 AM UTC 24 |
| Peak memory | 297336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2425045913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t hroughput_w_partial_write.2425045913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3518915459 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 8415216340 ps |
| CPU time | 1199.29 seconds |
| Started | Oct 09 08:54:05 AM UTC 24 |
| Finished | Oct 09 09:14:19 AM UTC 24 |
| Peak memory | 383680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518915459 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_ key_req.3518915459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2705339739 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 13802150 ps |
| CPU time | 1 seconds |
| Started | Oct 09 08:54:54 AM UTC 24 |
| Finished | Oct 09 08:54:56 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705339739 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2705339739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.694182812 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 716651378 ps |
| CPU time | 22.87 seconds |
| Started | Oct 09 08:53:19 AM UTC 24 |
| Finished | Oct 09 08:53:44 AM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694182812 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.694182812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.1726183605 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 9651978868 ps |
| CPU time | 634.73 seconds |
| Started | Oct 09 08:54:13 AM UTC 24 |
| Finished | Oct 09 09:04:56 AM UTC 24 |
| Peak memory | 383436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726183605 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.1726183605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3484846711 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5287381981 ps |
| CPU time | 9.31 seconds |
| Started | Oct 09 08:54:01 AM UTC 24 |
| Finished | Oct 09 08:54:12 AM UTC 24 |
| Peak memory | 222832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484846711 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.3484846711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2019505881 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 153313607 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 08:53:58 AM UTC 24 |
| Finished | Oct 09 08:54:01 AM UTC 24 |
| Peak memory | 221684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 019505881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max _throughput.2019505881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.396761714 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1594987417 ps |
| CPU time | 7.11 seconds |
| Started | Oct 09 08:54:37 AM UTC 24 |
| Finished | Oct 09 08:54:45 AM UTC 24 |
| Peak memory | 223100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396761714 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.396761714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3691638438 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2119069919 ps |
| CPU time | 16.17 seconds |
| Started | Oct 09 08:54:36 AM UTC 24 |
| Finished | Oct 09 08:54:53 AM UTC 24 |
| Peak memory | 223060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691638438 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.3691638438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.4060409904 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 7364854476 ps |
| CPU time | 857.28 seconds |
| Started | Oct 09 08:53:19 AM UTC 24 |
| Finished | Oct 09 09:07:47 AM UTC 24 |
| Peak memory | 383328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060409904 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.4060409904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.773131274 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 168086180 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 08:53:45 AM UTC 24 |
| Finished | Oct 09 08:53:47 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773131274 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.773131274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1258940548 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 15903398333 ps |
| CPU time | 415.13 seconds |
| Started | Oct 09 08:53:48 AM UTC 24 |
| Finished | Oct 09 09:00:49 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258940548 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce ss_b2b.1258940548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1254932687 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 47298893 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 08:54:34 AM UTC 24 |
| Finished | Oct 09 08:54:36 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254932687 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1254932687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_readback_err.34434711 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 155755513 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 08:54:46 AM UTC 24 |
| Finished | Oct 09 08:54:48 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34434711 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_readback_err.34434711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.1785396925 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 252115013 ps |
| CPU time | 18.52 seconds |
| Started | Oct 09 08:53:18 AM UTC 24 |
| Finished | Oct 09 08:53:38 AM UTC 24 |
| Peak memory | 258504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785396925 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1785396925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2784301615 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 176802680258 ps |
| CPU time | 3005.82 seconds |
| Started | Oct 09 08:54:53 AM UTC 24 |
| Finished | Oct 09 09:45:32 AM UTC 24 |
| Peak memory | 387656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278430161 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.2784301615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1084616099 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 7227891574 ps |
| CPU time | 363.75 seconds |
| Started | Oct 09 08:53:39 AM UTC 24 |
| Finished | Oct 09 08:59:47 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084616099 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.1084616099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3005157855 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 253025940 ps |
| CPU time | 71.07 seconds |
| Started | Oct 09 08:53:59 AM UTC 24 |
| Finished | Oct 09 08:55:12 AM UTC 24 |
| Peak memory | 348560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3005157855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th roughput_w_partial_write.3005157855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2986551755 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3642458682 ps |
| CPU time | 1454.32 seconds |
| Started | Oct 09 08:56:31 AM UTC 24 |
| Finished | Oct 09 09:21:01 AM UTC 24 |
| Peak memory | 383680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986551755 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_ key_req.2986551755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.592723888 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 22423505 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 08:57:11 AM UTC 24 |
| Finished | Oct 09 08:57:13 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592723888 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.592723888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.3897762068 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 55324430317 ps |
| CPU time | 93.04 seconds |
| Started | Oct 09 08:55:23 AM UTC 24 |
| Finished | Oct 09 08:56:58 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897762068 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.3897762068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.3565113175 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 29922488293 ps |
| CPU time | 299.92 seconds |
| Started | Oct 09 08:56:32 AM UTC 24 |
| Finished | Oct 09 09:01:36 AM UTC 24 |
| Peak memory | 346704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565113175 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.3565113175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3015751856 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 483244157 ps |
| CPU time | 7.76 seconds |
| Started | Oct 09 08:56:19 AM UTC 24 |
| Finished | Oct 09 08:56:28 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015751856 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.3015751856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1916576417 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 35656618 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 08:56:02 AM UTC 24 |
| Finished | Oct 09 08:56:05 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 916576417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max _throughput.1916576417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.322925430 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 208602944 ps |
| CPU time | 8.57 seconds |
| Started | Oct 09 08:56:58 AM UTC 24 |
| Finished | Oct 09 08:57:07 AM UTC 24 |
| Peak memory | 222788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322925430 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.322925430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3693600351 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 442016806 ps |
| CPU time | 14.67 seconds |
| Started | Oct 09 08:56:55 AM UTC 24 |
| Finished | Oct 09 08:57:11 AM UTC 24 |
| Peak memory | 222796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693600351 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.3693600351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3977514472 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2175448572 ps |
| CPU time | 41.1 seconds |
| Started | Oct 09 08:55:13 AM UTC 24 |
| Finished | Oct 09 08:55:56 AM UTC 24 |
| Peak memory | 301500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977514472 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.3977514472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1270967574 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 9122890552 ps |
| CPU time | 90.96 seconds |
| Started | Oct 09 08:55:52 AM UTC 24 |
| Finished | Oct 09 08:57:25 AM UTC 24 |
| Peak memory | 379324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270967574 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1270967574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3560879020 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 12515786624 ps |
| CPU time | 310.87 seconds |
| Started | Oct 09 08:55:57 AM UTC 24 |
| Finished | Oct 09 09:01:12 AM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560879020 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce ss_b2b.3560879020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3736022676 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 28325202 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 08:56:51 AM UTC 24 |
| Finished | Oct 09 08:56:54 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736022676 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3736022676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_readback_err.2239569777 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 100669355 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 08:56:59 AM UTC 24 |
| Finished | Oct 09 08:57:01 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239569777 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_readback_err.2239569777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3396372333 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 15546566370 ps |
| CPU time | 1056.7 seconds |
| Started | Oct 09 08:56:32 AM UTC 24 |
| Finished | Oct 09 09:14:21 AM UTC 24 |
| Peak memory | 383696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396372333 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3396372333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.706930925 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1557741083 ps |
| CPU time | 23.03 seconds |
| Started | Oct 09 08:54:57 AM UTC 24 |
| Finished | Oct 09 08:55:22 AM UTC 24 |
| Peak memory | 212572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706930925 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.706930925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3885374503 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 9850225994 ps |
| CPU time | 806.47 seconds |
| Started | Oct 09 08:57:08 AM UTC 24 |
| Finished | Oct 09 09:10:43 AM UTC 24 |
| Peak memory | 383420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388537450 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.3885374503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1702364831 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 11967581901 ps |
| CPU time | 410.22 seconds |
| Started | Oct 09 08:55:36 AM UTC 24 |
| Finished | Oct 09 09:02:32 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702364831 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1702364831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4263349664 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 80826687 ps |
| CPU time | 15.4 seconds |
| Started | Oct 09 08:56:05 AM UTC 24 |
| Finished | Oct 09 08:56:22 AM UTC 24 |
| Peak memory | 262532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4263349664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th roughput_w_partial_write.4263349664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.296426643 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8295055123 ps |
| CPU time | 782.77 seconds |
| Started | Oct 09 08:58:37 AM UTC 24 |
| Finished | Oct 09 09:11:49 AM UTC 24 |
| Peak memory | 383484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296426643 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_k ey_req.296426643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.816807023 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 13796919 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 08:59:21 AM UTC 24 |
| Finished | Oct 09 08:59:24 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816807023 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.816807023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.651299382 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 772987209 ps |
| CPU time | 58.99 seconds |
| Started | Oct 09 08:57:26 AM UTC 24 |
| Finished | Oct 09 08:58:27 AM UTC 24 |
| Peak memory | 212544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651299382 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.651299382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2771375256 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 8069282279 ps |
| CPU time | 594.83 seconds |
| Started | Oct 09 08:58:40 AM UTC 24 |
| Finished | Oct 09 09:08:42 AM UTC 24 |
| Peak memory | 377556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771375256 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2771375256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.688764838 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 850561247 ps |
| CPU time | 6.35 seconds |
| Started | Oct 09 08:58:31 AM UTC 24 |
| Finished | Oct 09 08:58:39 AM UTC 24 |
| Peak memory | 222832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688764838 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.688764838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1131889749 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 42499871 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 08:58:27 AM UTC 24 |
| Finished | Oct 09 08:58:30 AM UTC 24 |
| Peak memory | 221544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 131889749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max _throughput.1131889749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2313110080 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 757730093 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 08:58:59 AM UTC 24 |
| Finished | Oct 09 08:59:05 AM UTC 24 |
| Peak memory | 222776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313110080 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.2313110080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1563653896 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1843293787 ps |
| CPU time | 16.04 seconds |
| Started | Oct 09 08:58:43 AM UTC 24 |
| Finished | Oct 09 08:59:00 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563653896 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.1563653896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3086553308 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 5826808861 ps |
| CPU time | 1255.04 seconds |
| Started | Oct 09 08:57:19 AM UTC 24 |
| Finished | Oct 09 09:18:28 AM UTC 24 |
| Peak memory | 383496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086553308 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.3086553308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2952811486 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 201465091 ps |
| CPU time | 65.89 seconds |
| Started | Oct 09 08:57:29 AM UTC 24 |
| Finished | Oct 09 08:58:37 AM UTC 24 |
| Peak memory | 352580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952811486 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.2952811486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2123100700 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 31721748019 ps |
| CPU time | 351.23 seconds |
| Started | Oct 09 08:57:46 AM UTC 24 |
| Finished | Oct 09 09:03:42 AM UTC 24 |
| Peak memory | 212564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123100700 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acce ss_b2b.2123100700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1941041800 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 30228811 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 08:58:40 AM UTC 24 |
| Finished | Oct 09 08:58:42 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941041800 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1941041800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1202706409 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 41250523 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 08:59:01 AM UTC 24 |
| Finished | Oct 09 08:59:04 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202706409 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_readback_err.1202706409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2362661049 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 177995506 ps |
| CPU time | 11.97 seconds |
| Started | Oct 09 08:57:14 AM UTC 24 |
| Finished | Oct 09 08:57:27 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362661049 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2362661049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2042616209 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 31085807466 ps |
| CPU time | 2386.97 seconds |
| Started | Oct 09 08:59:06 AM UTC 24 |
| Finished | Oct 09 09:39:19 AM UTC 24 |
| Peak memory | 385468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204261620 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.2042616209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2680633801 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2679445092 ps |
| CPU time | 294.93 seconds |
| Started | Oct 09 08:57:29 AM UTC 24 |
| Finished | Oct 09 09:02:28 AM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680633801 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.2680633801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3916576820 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 495029475 ps |
| CPU time | 56.24 seconds |
| Started | Oct 09 08:58:28 AM UTC 24 |
| Finished | Oct 09 08:59:26 AM UTC 24 |
| Peak memory | 344776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3916576820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th roughput_w_partial_write.3916576820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3019514011 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4703172621 ps |
| CPU time | 311.98 seconds |
| Started | Oct 09 09:00:31 AM UTC 24 |
| Finished | Oct 09 09:05:48 AM UTC 24 |
| Peak memory | 377616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019514011 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_ key_req.3019514011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2957357971 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 22138427 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 09:00:56 AM UTC 24 |
| Finished | Oct 09 09:00:58 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957357971 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2957357971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2703353741 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2566650562 ps |
| CPU time | 68.42 seconds |
| Started | Oct 09 08:59:28 AM UTC 24 |
| Finished | Oct 09 09:00:38 AM UTC 24 |
| Peak memory | 212820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703353741 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.2703353741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3749903384 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 11102988155 ps |
| CPU time | 1025.97 seconds |
| Started | Oct 09 09:00:40 AM UTC 24 |
| Finished | Oct 09 09:17:57 AM UTC 24 |
| Peak memory | 379540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749903384 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3749903384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3718103458 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1495296259 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 09:00:21 AM UTC 24 |
| Finished | Oct 09 09:00:30 AM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718103458 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.3718103458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2954227145 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 103906862 ps |
| CPU time | 41.42 seconds |
| Started | Oct 09 09:00:12 AM UTC 24 |
| Finished | Oct 09 09:00:55 AM UTC 24 |
| Peak memory | 311764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 954227145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max _throughput.2954227145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3543403049 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 320738351 ps |
| CPU time | 7.26 seconds |
| Started | Oct 09 09:00:50 AM UTC 24 |
| Finished | Oct 09 09:00:59 AM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543403049 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.3543403049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.4134658712 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 184767140 ps |
| CPU time | 13.45 seconds |
| Started | Oct 09 09:00:47 AM UTC 24 |
| Finished | Oct 09 09:01:02 AM UTC 24 |
| Peak memory | 223064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134658712 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.4134658712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1919485146 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 72158583317 ps |
| CPU time | 1448.21 seconds |
| Started | Oct 09 08:59:25 AM UTC 24 |
| Finished | Oct 09 09:23:50 AM UTC 24 |
| Peak memory | 383368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919485146 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.1919485146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3243866554 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3876224825 ps |
| CPU time | 21.69 seconds |
| Started | Oct 09 08:59:48 AM UTC 24 |
| Finished | Oct 09 09:00:11 AM UTC 24 |
| Peak memory | 212688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243866554 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3243866554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2376682531 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 22501599697 ps |
| CPU time | 278.51 seconds |
| Started | Oct 09 09:00:02 AM UTC 24 |
| Finished | Oct 09 09:04:53 AM UTC 24 |
| Peak memory | 212868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376682531 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce ss_b2b.2376682531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1014278749 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 80952266 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 09:00:44 AM UTC 24 |
| Finished | Oct 09 09:00:46 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014278749 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1014278749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_readback_err.87965347 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 34398443 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 09:00:51 AM UTC 24 |
| Finished | Oct 09 09:00:54 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87965347 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_readback_err.87965347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1833830118 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 37642019922 ps |
| CPU time | 1331.28 seconds |
| Started | Oct 09 09:00:41 AM UTC 24 |
| Finished | Oct 09 09:23:07 AM UTC 24 |
| Peak memory | 383420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833830118 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1833830118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2687510788 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 292145229 ps |
| CPU time | 7.83 seconds |
| Started | Oct 09 08:59:24 AM UTC 24 |
| Finished | Oct 09 08:59:34 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687510788 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2687510788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1546710961 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 8029069929 ps |
| CPU time | 215.27 seconds |
| Started | Oct 09 08:59:35 AM UTC 24 |
| Finished | Oct 09 09:03:13 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546710961 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.1546710961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4043588243 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 368049118 ps |
| CPU time | 81.34 seconds |
| Started | Oct 09 09:00:19 AM UTC 24 |
| Finished | Oct 09 09:01:43 AM UTC 24 |
| Peak memory | 381324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4043588243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th roughput_w_partial_write.4043588243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2409535956 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 6556640990 ps |
| CPU time | 1120.92 seconds |
| Started | Oct 09 09:01:26 AM UTC 24 |
| Finished | Oct 09 09:20:20 AM UTC 24 |
| Peak memory | 383756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409535956 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_ key_req.2409535956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3247118059 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 12080652 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 09:01:51 AM UTC 24 |
| Finished | Oct 09 09:01:52 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247118059 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.3247118059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2605708929 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 31162872535 ps |
| CPU time | 105.98 seconds |
| Started | Oct 09 09:01:03 AM UTC 24 |
| Finished | Oct 09 09:02:51 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605708929 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.2605708929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3164920638 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 34047247724 ps |
| CPU time | 1549.06 seconds |
| Started | Oct 09 09:01:27 AM UTC 24 |
| Finished | Oct 09 09:27:31 AM UTC 24 |
| Peak memory | 385732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164920638 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.3164920638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2122920662 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 503203505 ps |
| CPU time | 3.62 seconds |
| Started | Oct 09 09:01:25 AM UTC 24 |
| Finished | Oct 09 09:01:30 AM UTC 24 |
| Peak memory | 224964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122920662 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2122920662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3998572763 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 132264780 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 09:01:23 AM UTC 24 |
| Finished | Oct 09 09:01:26 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 998572763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max _throughput.3998572763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.810174109 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 670837292 ps |
| CPU time | 8.16 seconds |
| Started | Oct 09 09:01:40 AM UTC 24 |
| Finished | Oct 09 09:01:50 AM UTC 24 |
| Peak memory | 222844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810174109 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.810174109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.20532464 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 135116828 ps |
| CPU time | 12.17 seconds |
| Started | Oct 09 09:01:37 AM UTC 24 |
| Finished | Oct 09 09:01:50 AM UTC 24 |
| Peak memory | 222964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20532464 -assert nopostp roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.20532464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2527433088 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2237065341 ps |
| CPU time | 209.22 seconds |
| Started | Oct 09 09:00:59 AM UTC 24 |
| Finished | Oct 09 09:04:32 AM UTC 24 |
| Peak memory | 377276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527433088 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.2527433088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.549054477 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3602408400 ps |
| CPU time | 19.66 seconds |
| Started | Oct 09 09:01:15 AM UTC 24 |
| Finished | Oct 09 09:01:36 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549054477 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.549054477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3680583547 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 206493659004 ps |
| CPU time | 519.3 seconds |
| Started | Oct 09 09:01:19 AM UTC 24 |
| Finished | Oct 09 09:10:05 AM UTC 24 |
| Peak memory | 212648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680583547 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acce ss_b2b.3680583547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.168948443 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 46237143 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 09:01:37 AM UTC 24 |
| Finished | Oct 09 09:01:39 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168948443 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.168948443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_readback_err.2795922266 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 29152099 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 09:01:40 AM UTC 24 |
| Finished | Oct 09 09:01:43 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795922266 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_readback_err.2795922266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4165524207 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1455981668 ps |
| CPU time | 261.86 seconds |
| Started | Oct 09 09:01:32 AM UTC 24 |
| Finished | Oct 09 09:05:58 AM UTC 24 |
| Peak memory | 359052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165524207 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.4165524207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3237914753 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 444903276 ps |
| CPU time | 13.24 seconds |
| Started | Oct 09 09:00:59 AM UTC 24 |
| Finished | Oct 09 09:01:14 AM UTC 24 |
| Peak memory | 212616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237914753 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3237914753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3832317697 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5648056405 ps |
| CPU time | 868.16 seconds |
| Started | Oct 09 09:01:44 AM UTC 24 |
| Finished | Oct 09 09:16:23 AM UTC 24 |
| Peak memory | 383424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383231769 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.3832317697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3829673884 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 418751078 ps |
| CPU time | 20.19 seconds |
| Started | Oct 09 09:01:43 AM UTC 24 |
| Finished | Oct 09 09:02:05 AM UTC 24 |
| Peak memory | 223116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829673884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3829673884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4089198307 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6875637178 ps |
| CPU time | 357 seconds |
| Started | Oct 09 09:01:13 AM UTC 24 |
| Finished | Oct 09 09:07:15 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089198307 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.4089198307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.873647811 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 451271039 ps |
| CPU time | 47.92 seconds |
| Started | Oct 09 09:01:24 AM UTC 24 |
| Finished | Oct 09 09:02:14 AM UTC 24 |
| Peak memory | 328020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 873647811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_thr oughput_w_partial_write.873647811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
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