| T801 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.501330863 |
|
|
Oct 09 09:53:24 AM UTC 24 |
Oct 09 09:56:45 AM UTC 24 |
16273580760 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.288232260 |
|
|
Oct 09 09:56:45 AM UTC 24 |
Oct 09 09:56:47 AM UTC 24 |
16217813 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.2195925285 |
|
|
Oct 09 09:39:47 AM UTC 24 |
Oct 09 09:57:03 AM UTC 24 |
2328380055 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.1707749133 |
|
|
Oct 09 09:56:47 AM UTC 24 |
Oct 09 09:57:08 AM UTC 24 |
228750570 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.3757730409 |
|
|
Oct 09 09:55:33 AM UTC 24 |
Oct 09 09:57:14 AM UTC 24 |
207838149 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4269207135 |
|
|
Oct 09 09:51:12 AM UTC 24 |
Oct 09 09:57:23 AM UTC 24 |
4383614419 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1928278405 |
|
|
Oct 09 09:57:04 AM UTC 24 |
Oct 09 09:57:45 AM UTC 24 |
793408597 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3210519824 |
|
|
Oct 09 09:53:21 AM UTC 24 |
Oct 09 09:57:54 AM UTC 24 |
11140612329 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.609994857 |
|
|
Oct 09 09:57:46 AM UTC 24 |
Oct 09 09:57:56 AM UTC 24 |
827722254 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.92619375 |
|
|
Oct 09 09:56:46 AM UTC 24 |
Oct 09 09:57:59 AM UTC 24 |
110887053 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3024423364 |
|
|
Oct 09 09:42:27 AM UTC 24 |
Oct 09 09:58:03 AM UTC 24 |
4782993936 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2343364485 |
|
|
Oct 09 09:53:44 AM UTC 24 |
Oct 09 09:58:06 AM UTC 24 |
6369529883 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2791801683 |
|
|
Oct 09 09:58:04 AM UTC 24 |
Oct 09 09:58:07 AM UTC 24 |
80788518 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3661132953 |
|
|
Oct 09 09:57:24 AM UTC 24 |
Oct 09 09:58:08 AM UTC 24 |
207804944 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_readback_err.1411663751 |
|
|
Oct 09 09:58:09 AM UTC 24 |
Oct 09 09:58:12 AM UTC 24 |
325676334 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.716080529 |
|
|
Oct 09 09:58:08 AM UTC 24 |
Oct 09 09:58:16 AM UTC 24 |
155808376 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.4275532215 |
|
|
Oct 09 09:58:06 AM UTC 24 |
Oct 09 09:58:20 AM UTC 24 |
353125631 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.4174571271 |
|
|
Oct 09 09:58:21 AM UTC 24 |
Oct 09 09:58:23 AM UTC 24 |
53009253 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.360829478 |
|
|
Oct 09 08:53:11 AM UTC 24 |
Oct 09 09:58:30 AM UTC 24 |
103606793087 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.2644256916 |
|
|
Oct 09 09:58:24 AM UTC 24 |
Oct 09 09:58:35 AM UTC 24 |
97229196 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.2963095148 |
|
|
Oct 09 09:57:15 AM UTC 24 |
Oct 09 09:58:42 AM UTC 24 |
170323955 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.18952086 |
|
|
Oct 09 09:45:16 AM UTC 24 |
Oct 09 09:58:48 AM UTC 24 |
123454623803 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.996491345 |
|
|
Oct 09 09:55:08 AM UTC 24 |
Oct 09 09:58:58 AM UTC 24 |
19371082120 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2657424029 |
|
|
Oct 09 09:58:59 AM UTC 24 |
Oct 09 09:59:02 AM UTC 24 |
43376362 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.785776516 |
|
|
Oct 09 09:48:28 AM UTC 24 |
Oct 09 09:59:07 AM UTC 24 |
1843050565 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.538266405 |
|
|
Oct 09 09:48:36 AM UTC 24 |
Oct 09 09:59:09 AM UTC 24 |
31568340660 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.398734524 |
|
|
Oct 09 09:58:49 AM UTC 24 |
Oct 09 09:59:12 AM UTC 24 |
576620176 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3801497963 |
|
|
Oct 09 09:58:13 AM UTC 24 |
Oct 09 09:59:17 AM UTC 24 |
2791291198 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1855117622 |
|
|
Oct 09 09:59:08 AM UTC 24 |
Oct 09 09:59:21 AM UTC 24 |
672274068 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.739744894 |
|
|
Oct 09 09:59:22 AM UTC 24 |
Oct 09 09:59:24 AM UTC 24 |
81430881 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.453808573 |
|
|
Oct 09 09:58:35 AM UTC 24 |
Oct 09 09:59:25 AM UTC 24 |
5850660389 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2554185027 |
|
|
Oct 09 09:51:48 AM UTC 24 |
Oct 09 09:59:26 AM UTC 24 |
3183795895 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_readback_err.2925731570 |
|
|
Oct 09 09:59:26 AM UTC 24 |
Oct 09 09:59:29 AM UTC 24 |
113346386 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.553804054 |
|
|
Oct 09 09:14:51 AM UTC 24 |
Oct 09 09:59:32 AM UTC 24 |
33365083228 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3445008811 |
|
|
Oct 09 09:59:25 AM UTC 24 |
Oct 09 09:59:33 AM UTC 24 |
246997233 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3136018112 |
|
|
Oct 09 09:59:25 AM UTC 24 |
Oct 09 09:59:33 AM UTC 24 |
357270277 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1933503421 |
|
|
Oct 09 09:59:34 AM UTC 24 |
Oct 09 09:59:36 AM UTC 24 |
16511457 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.2707866256 |
|
|
Oct 09 09:44:38 AM UTC 24 |
Oct 09 09:59:38 AM UTC 24 |
223355216883 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4060387879 |
|
|
Oct 09 09:59:29 AM UTC 24 |
Oct 09 09:59:40 AM UTC 24 |
1398351450 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.503576046 |
|
|
Oct 09 09:53:29 AM UTC 24 |
Oct 09 09:59:48 AM UTC 24 |
3558313041 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.1563963245 |
|
|
Oct 09 09:59:35 AM UTC 24 |
Oct 09 09:59:52 AM UTC 24 |
1894001788 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.730800759 |
|
|
Oct 09 09:59:49 AM UTC 24 |
Oct 09 09:59:54 AM UTC 24 |
120342440 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.978799782 |
|
|
Oct 09 09:54:41 AM UTC 24 |
Oct 09 10:00:18 AM UTC 24 |
2308418275 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.411426389 |
|
|
Oct 09 09:51:27 AM UTC 24 |
Oct 09 10:00:22 AM UTC 24 |
76393068859 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.1363387313 |
|
|
Oct 09 09:56:48 AM UTC 24 |
Oct 09 10:00:24 AM UTC 24 |
19406195913 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1983091712 |
|
|
Oct 09 10:00:22 AM UTC 24 |
Oct 09 10:00:26 AM UTC 24 |
473023614 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3759244104 |
|
|
Oct 09 09:59:02 AM UTC 24 |
Oct 09 10:00:37 AM UTC 24 |
148712804 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.860292892 |
|
|
Oct 09 09:59:39 AM UTC 24 |
Oct 09 10:00:39 AM UTC 24 |
3256034039 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.509373668 |
|
|
Oct 09 10:00:41 AM UTC 24 |
Oct 09 10:00:44 AM UTC 24 |
162242216 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.3002129627 |
|
|
Oct 09 09:46:13 AM UTC 24 |
Oct 09 10:00:45 AM UTC 24 |
11166098020 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2515629726 |
|
|
Oct 09 10:00:46 AM UTC 24 |
Oct 09 10:00:51 AM UTC 24 |
43121438 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_readback_err.1679189313 |
|
|
Oct 09 10:00:52 AM UTC 24 |
Oct 09 10:00:55 AM UTC 24 |
105083776 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.177336405 |
|
|
Oct 09 09:53:56 AM UTC 24 |
Oct 09 10:00:59 AM UTC 24 |
1705740526 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1554919284 |
|
|
Oct 09 10:00:45 AM UTC 24 |
Oct 09 10:01:00 AM UTC 24 |
1832179188 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1052702530 |
|
|
Oct 09 10:01:01 AM UTC 24 |
Oct 09 10:01:03 AM UTC 24 |
40077243 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2395283176 |
|
|
Oct 09 10:01:04 AM UTC 24 |
Oct 09 10:01:31 AM UTC 24 |
97572068 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2596949181 |
|
|
Oct 09 09:51:51 AM UTC 24 |
Oct 09 10:01:34 AM UTC 24 |
15837849006 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.4126035888 |
|
|
Oct 09 09:59:55 AM UTC 24 |
Oct 09 10:01:39 AM UTC 24 |
137497345 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3669188782 |
|
|
Oct 09 10:00:19 AM UTC 24 |
Oct 09 10:01:39 AM UTC 24 |
161672801 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2592494195 |
|
|
Oct 09 09:58:30 AM UTC 24 |
Oct 09 10:02:02 AM UTC 24 |
40586302928 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3800990082 |
|
|
Oct 09 09:55:30 AM UTC 24 |
Oct 09 10:02:05 AM UTC 24 |
53969586632 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.929743025 |
|
|
Oct 09 10:01:40 AM UTC 24 |
Oct 09 10:02:05 AM UTC 24 |
1197744526 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3361869226 |
|
|
Oct 09 10:02:07 AM UTC 24 |
Oct 09 10:02:10 AM UTC 24 |
38839731 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.3666634683 |
|
|
Oct 09 09:47:44 AM UTC 24 |
Oct 09 10:02:16 AM UTC 24 |
2800625469 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3036418816 |
|
|
Oct 09 10:02:07 AM UTC 24 |
Oct 09 10:02:17 AM UTC 24 |
284760789 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1897823174 |
|
|
Oct 09 09:57:08 AM UTC 24 |
Oct 09 10:02:18 AM UTC 24 |
12509959638 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.251456485 |
|
|
Oct 09 10:02:10 AM UTC 24 |
Oct 09 10:02:19 AM UTC 24 |
1308904242 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4052211138 |
|
|
Oct 09 10:02:21 AM UTC 24 |
Oct 09 10:02:23 AM UTC 24 |
242488453 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3585120420 |
|
|
Oct 09 10:02:24 AM UTC 24 |
Oct 09 10:02:40 AM UTC 24 |
9462938034 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2076751220 |
|
|
Oct 09 10:02:41 AM UTC 24 |
Oct 09 10:02:49 AM UTC 24 |
345242441 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1492708255 |
|
|
Oct 09 10:00:55 AM UTC 24 |
Oct 09 10:02:50 AM UTC 24 |
16388966478 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1498696125 |
|
|
Oct 09 10:02:50 AM UTC 24 |
Oct 09 10:02:53 AM UTC 24 |
94391687 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1572419946 |
|
|
Oct 09 09:58:43 AM UTC 24 |
Oct 09 10:02:57 AM UTC 24 |
2328170701 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2982813365 |
|
|
Oct 09 09:57:57 AM UTC 24 |
Oct 09 10:02:58 AM UTC 24 |
16111026084 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4245314722 |
|
|
Oct 09 10:02:58 AM UTC 24 |
Oct 09 10:03:00 AM UTC 24 |
38802393 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.2167677521 |
|
|
Oct 09 10:01:35 AM UTC 24 |
Oct 09 10:03:01 AM UTC 24 |
4886752213 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3906120697 |
|
|
Oct 09 10:03:02 AM UTC 24 |
Oct 09 10:03:23 AM UTC 24 |
785083952 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.4234856823 |
|
|
Oct 09 10:02:59 AM UTC 24 |
Oct 09 10:03:25 AM UTC 24 |
358219888 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.2416630772 |
|
|
Oct 09 09:56:20 AM UTC 24 |
Oct 09 10:03:25 AM UTC 24 |
9974898597 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3885915038 |
|
|
Oct 09 10:00:25 AM UTC 24 |
Oct 09 10:03:29 AM UTC 24 |
1481185210 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1850046387 |
|
|
Oct 09 09:50:38 AM UTC 24 |
Oct 09 10:03:30 AM UTC 24 |
14700052916 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2721248211 |
|
|
Oct 09 10:03:26 AM UTC 24 |
Oct 09 10:03:44 AM UTC 24 |
959130353 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2082033601 |
|
|
Oct 09 10:03:30 AM UTC 24 |
Oct 09 10:03:45 AM UTC 24 |
300582451 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1229942000 |
|
|
Oct 09 10:03:45 AM UTC 24 |
Oct 09 10:03:54 AM UTC 24 |
4439232003 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.58289271 |
|
|
Oct 09 09:59:41 AM UTC 24 |
Oct 09 10:03:55 AM UTC 24 |
3312847990 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3167353014 |
|
|
Oct 09 09:51:51 AM UTC 24 |
Oct 09 10:03:58 AM UTC 24 |
9934760633 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3181291204 |
|
|
Oct 09 10:03:46 AM UTC 24 |
Oct 09 10:04:01 AM UTC 24 |
197016324 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2342070333 |
|
|
Oct 09 10:03:59 AM UTC 24 |
Oct 09 10:04:01 AM UTC 24 |
82916795 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.838804862 |
|
|
Oct 09 10:04:02 AM UTC 24 |
Oct 09 10:04:08 AM UTC 24 |
60376268 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_readback_err.1124099088 |
|
|
Oct 09 10:04:09 AM UTC 24 |
Oct 09 10:04:11 AM UTC 24 |
101934845 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1211489016 |
|
|
Oct 09 10:04:02 AM UTC 24 |
Oct 09 10:04:12 AM UTC 24 |
286810796 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3020176706 |
|
|
Oct 09 10:00:26 AM UTC 24 |
Oct 09 10:04:13 AM UTC 24 |
1829595205 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2210529529 |
|
|
Oct 09 10:04:14 AM UTC 24 |
Oct 09 10:04:16 AM UTC 24 |
41815944 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.796741229 |
|
|
Oct 09 10:04:17 AM UTC 24 |
Oct 09 10:04:25 AM UTC 24 |
163028578 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.2857513078 |
|
|
Oct 09 09:59:18 AM UTC 24 |
Oct 09 10:04:32 AM UTC 24 |
2145084362 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3056002345 |
|
|
Oct 09 10:03:02 AM UTC 24 |
Oct 09 10:05:01 AM UTC 24 |
44210349973 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.3981321314 |
|
|
Oct 09 09:50:17 AM UTC 24 |
Oct 09 10:05:17 AM UTC 24 |
15224945798 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4210923581 |
|
|
Oct 09 10:03:30 AM UTC 24 |
Oct 09 10:05:17 AM UTC 24 |
522946361 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.1976608781 |
|
|
Oct 09 09:53:22 AM UTC 24 |
Oct 09 10:05:31 AM UTC 24 |
6959162433 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3876326310 |
|
|
Oct 09 10:05:18 AM UTC 24 |
Oct 09 10:05:43 AM UTC 24 |
820037285 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3710583437 |
|
|
Oct 09 10:02:03 AM UTC 24 |
Oct 09 10:05:45 AM UTC 24 |
11108001234 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.2430367388 |
|
|
Oct 09 10:04:33 AM UTC 24 |
Oct 09 10:05:51 AM UTC 24 |
6786154118 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1359599343 |
|
|
Oct 09 10:05:45 AM UTC 24 |
Oct 09 10:06:01 AM UTC 24 |
2441103748 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3653982821 |
|
|
Oct 09 09:47:37 AM UTC 24 |
Oct 09 10:06:05 AM UTC 24 |
32310792690 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.771785550 |
|
|
Oct 09 10:05:32 AM UTC 24 |
Oct 09 10:06:06 AM UTC 24 |
93878382 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.958342353 |
|
|
Oct 09 10:01:39 AM UTC 24 |
Oct 09 10:06:08 AM UTC 24 |
4240039148 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3697600683 |
|
|
Oct 09 10:06:07 AM UTC 24 |
Oct 09 10:06:09 AM UTC 24 |
73660046 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2100943951 |
|
|
Oct 09 10:06:09 AM UTC 24 |
Oct 09 10:06:16 AM UTC 24 |
146829512 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2819759361 |
|
|
Oct 09 10:05:44 AM UTC 24 |
Oct 09 10:06:18 AM UTC 24 |
182911961 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1211700674 |
|
|
Oct 09 10:06:10 AM UTC 24 |
Oct 09 10:06:19 AM UTC 24 |
175731113 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_readback_err.25559749 |
|
|
Oct 09 10:06:17 AM UTC 24 |
Oct 09 10:06:20 AM UTC 24 |
30079558 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2626757170 |
|
|
Oct 09 10:06:21 AM UTC 24 |
Oct 09 10:06:23 AM UTC 24 |
37604775 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.3321101244 |
|
|
Oct 09 10:03:55 AM UTC 24 |
Oct 09 10:06:24 AM UTC 24 |
1200704255 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1665338836 |
|
|
Oct 09 09:53:53 AM UTC 24 |
Oct 09 10:06:30 AM UTC 24 |
8447680431 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3802564460 |
|
|
Oct 09 09:47:54 AM UTC 24 |
Oct 09 10:06:43 AM UTC 24 |
5137179519 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3825059317 |
|
|
Oct 09 10:01:32 AM UTC 24 |
Oct 09 10:07:16 AM UTC 24 |
2569647257 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2193836422 |
|
|
Oct 09 09:56:46 AM UTC 24 |
Oct 09 10:07:18 AM UTC 24 |
6408784320 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1133722604 |
|
|
Oct 09 09:22:17 AM UTC 24 |
Oct 09 10:07:18 AM UTC 24 |
27622060935 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1787717755 |
|
|
Oct 09 10:07:19 AM UTC 24 |
Oct 09 10:07:24 AM UTC 24 |
371590408 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1093510274 |
|
|
Oct 09 10:07:08 AM UTC 24 |
Oct 09 10:07:32 AM UTC 24 |
1865981364 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1066027969 |
|
|
Oct 09 10:07:25 AM UTC 24 |
Oct 09 10:07:35 AM UTC 24 |
1994402184 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.3878143227 |
|
|
Oct 09 10:06:31 AM UTC 24 |
Oct 09 10:07:43 AM UTC 24 |
6467297827 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.820828390 |
|
|
Oct 09 10:02:19 AM UTC 24 |
Oct 09 10:07:45 AM UTC 24 |
25754052661 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1704702456 |
|
|
Oct 09 10:07:46 AM UTC 24 |
Oct 09 10:07:48 AM UTC 24 |
58856925 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2425045913 |
|
|
Oct 09 10:07:20 AM UTC 24 |
Oct 09 10:07:53 AM UTC 24 |
754520156 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.82691562 |
|
|
Oct 09 09:40:20 AM UTC 24 |
Oct 09 10:07:58 AM UTC 24 |
16126415112 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3914745392 |
|
|
Oct 09 10:07:54 AM UTC 24 |
Oct 09 10:07:59 AM UTC 24 |
159539154 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3834477968 |
|
|
Oct 09 09:53:04 AM UTC 24 |
Oct 09 10:08:00 AM UTC 24 |
13414396682 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.633785257 |
|
|
Oct 09 09:59:53 AM UTC 24 |
Oct 09 10:08:01 AM UTC 24 |
49207423055 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_readback_err.3071248056 |
|
|
Oct 09 10:07:59 AM UTC 24 |
Oct 09 10:08:02 AM UTC 24 |
85734282 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.260486916 |
|
|
Oct 09 10:08:02 AM UTC 24 |
Oct 09 10:08:04 AM UTC 24 |
67050888 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.358779707 |
|
|
Oct 09 10:06:24 AM UTC 24 |
Oct 09 10:08:05 AM UTC 24 |
150390946 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1423135066 |
|
|
Oct 09 10:07:49 AM UTC 24 |
Oct 09 10:08:05 AM UTC 24 |
1134281865 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1620097469 |
|
|
Oct 09 09:52:05 AM UTC 24 |
Oct 09 10:08:06 AM UTC 24 |
17404581073 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1088667171 |
|
|
Oct 09 09:58:57 AM UTC 24 |
Oct 09 10:08:22 AM UTC 24 |
21907896035 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2555594114 |
|
|
Oct 09 10:06:19 AM UTC 24 |
Oct 09 10:08:34 AM UTC 24 |
1729776290 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2955215635 |
|
|
Oct 09 10:05:03 AM UTC 24 |
Oct 09 10:08:46 AM UTC 24 |
2108050779 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1576745875 |
|
|
Oct 09 10:07:36 AM UTC 24 |
Oct 09 10:08:57 AM UTC 24 |
3316794687 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1683402972 |
|
|
Oct 09 09:35:40 AM UTC 24 |
Oct 09 10:09:08 AM UTC 24 |
26401078381 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.4035435859 |
|
|
Oct 09 10:07:44 AM UTC 24 |
Oct 09 10:09:16 AM UTC 24 |
1569863772 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2506433046 |
|
|
Oct 09 10:03:26 AM UTC 24 |
Oct 09 10:09:18 AM UTC 24 |
54210353200 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.519620326 |
|
|
Oct 09 09:58:00 AM UTC 24 |
Oct 09 10:09:32 AM UTC 24 |
23866231620 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1169674419 |
|
|
Oct 09 10:02:51 AM UTC 24 |
Oct 09 10:09:42 AM UTC 24 |
807988134 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2293768342 |
|
|
Oct 09 10:03:24 AM UTC 24 |
Oct 09 10:09:53 AM UTC 24 |
3765745369 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3521143785 |
|
|
Oct 09 10:05:18 AM UTC 24 |
Oct 09 10:10:23 AM UTC 24 |
21349009771 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.262969440 |
|
|
Oct 09 10:08:00 AM UTC 24 |
Oct 09 10:10:46 AM UTC 24 |
1786986221 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.4214720999 |
|
|
Oct 09 10:06:02 AM UTC 24 |
Oct 09 10:10:50 AM UTC 24 |
5659225110 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1488092205 |
|
|
Oct 09 10:07:18 AM UTC 24 |
Oct 09 10:11:21 AM UTC 24 |
23191598086 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.845663410 |
|
|
Oct 09 09:59:37 AM UTC 24 |
Oct 09 10:11:44 AM UTC 24 |
16214930972 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1430057476 |
|
|
Oct 09 10:06:44 AM UTC 24 |
Oct 09 10:11:52 AM UTC 24 |
2692036312 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3091600693 |
|
|
Oct 09 09:53:08 AM UTC 24 |
Oct 09 10:11:59 AM UTC 24 |
18006637977 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.58400756 |
|
|
Oct 09 10:04:26 AM UTC 24 |
Oct 09 10:12:12 AM UTC 24 |
1146496126 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.3098422601 |
|
|
Oct 09 10:03:56 AM UTC 24 |
Oct 09 10:13:05 AM UTC 24 |
6363483400 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4224668094 |
|
|
Oct 09 10:05:52 AM UTC 24 |
Oct 09 10:14:01 AM UTC 24 |
2642182980 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.169035177 |
|
|
Oct 09 10:02:17 AM UTC 24 |
Oct 09 10:14:09 AM UTC 24 |
6139348410 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1642523622 |
|
|
Oct 09 09:53:11 AM UTC 24 |
Oct 09 10:14:13 AM UTC 24 |
29530681153 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.161442432 |
|
|
Oct 09 09:57:55 AM UTC 24 |
Oct 09 10:14:27 AM UTC 24 |
8612019359 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3965902177 |
|
|
Oct 09 09:08:23 AM UTC 24 |
Oct 09 10:14:29 AM UTC 24 |
226843005793 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4141517453 |
|
|
Oct 09 09:59:10 AM UTC 24 |
Oct 09 10:15:30 AM UTC 24 |
5684877769 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1863664640 |
|
|
Oct 09 09:56:42 AM UTC 24 |
Oct 09 10:15:37 AM UTC 24 |
4610721116 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3559701715 |
|
|
Oct 09 09:56:25 AM UTC 24 |
Oct 09 10:16:54 AM UTC 24 |
72468518043 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1187128422 |
|
|
Oct 09 09:53:58 AM UTC 24 |
Oct 09 10:17:04 AM UTC 24 |
20790426983 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3212689314 |
|
|
Oct 09 10:06:25 AM UTC 24 |
Oct 09 10:17:23 AM UTC 24 |
23066251361 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3076477809 |
|
|
Oct 09 10:07:33 AM UTC 24 |
Oct 09 10:18:30 AM UTC 24 |
4033097863 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1153429323 |
|
|
Oct 09 10:04:13 AM UTC 24 |
Oct 09 10:19:13 AM UTC 24 |
22774431210 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3800539951 |
|
|
Oct 09 10:02:18 AM UTC 24 |
Oct 09 10:19:41 AM UTC 24 |
2553147476 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3084368829 |
|
|
Oct 09 10:06:06 AM UTC 24 |
Oct 09 10:19:52 AM UTC 24 |
7083040853 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2182810042 |
|
|
Oct 09 09:13:18 AM UTC 24 |
Oct 09 10:19:58 AM UTC 24 |
61398300433 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1650661173 |
|
|
Oct 09 10:08:01 AM UTC 24 |
Oct 09 10:20:44 AM UTC 24 |
3853847051 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.343739316 |
|
|
Oct 09 09:37:44 AM UTC 24 |
Oct 09 10:22:20 AM UTC 24 |
22862938721 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.4169468258 |
|
|
Oct 09 09:54:43 AM UTC 24 |
Oct 09 10:22:39 AM UTC 24 |
29699891494 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1560668418 |
|
|
Oct 09 09:45:12 AM UTC 24 |
Oct 09 10:23:40 AM UTC 24 |
58551640742 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3583975397 |
|
|
Oct 09 09:23:57 AM UTC 24 |
Oct 09 10:24:11 AM UTC 24 |
10146295524 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.105750790 |
|
|
Oct 09 09:06:45 AM UTC 24 |
Oct 09 10:24:17 AM UTC 24 |
62397145295 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3689360298 |
|
|
Oct 09 09:46:46 AM UTC 24 |
Oct 09 10:25:48 AM UTC 24 |
39234286836 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3072405036 |
|
|
Oct 09 09:40:08 AM UTC 24 |
Oct 09 10:27:15 AM UTC 24 |
41946776295 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.434064425 |
|
|
Oct 09 09:25:53 AM UTC 24 |
Oct 09 10:27:39 AM UTC 24 |
53647876767 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.2705941223 |
|
|
Oct 09 10:00:38 AM UTC 24 |
Oct 09 10:29:54 AM UTC 24 |
95278393480 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3151845512 |
|
|
Oct 09 09:16:51 AM UTC 24 |
Oct 09 10:30:17 AM UTC 24 |
78093490687 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1123371159 |
|
|
Oct 09 09:34:00 AM UTC 24 |
Oct 09 10:31:52 AM UTC 24 |
10600399121 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1530715382 |
|
|
Oct 09 10:01:01 AM UTC 24 |
Oct 09 10:32:09 AM UTC 24 |
28419237152 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3202707676 |
|
|
Oct 09 09:09:53 AM UTC 24 |
Oct 09 10:33:35 AM UTC 24 |
152873876191 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.246042504 |
|
|
Oct 09 09:59:13 AM UTC 24 |
Oct 09 10:33:57 AM UTC 24 |
20352005003 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3109400901 |
|
|
Oct 09 09:52:03 AM UTC 24 |
Oct 09 10:34:47 AM UTC 24 |
78429851329 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3567798033 |
|
|
Oct 09 09:58:17 AM UTC 24 |
Oct 09 10:36:30 AM UTC 24 |
28457457525 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1408291104 |
|
|
Oct 09 09:49:14 AM UTC 24 |
Oct 09 10:38:52 AM UTC 24 |
47485048406 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.4179895384 |
|
|
Oct 09 10:02:53 AM UTC 24 |
Oct 09 10:39:44 AM UTC 24 |
31521117881 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2667478434 |
|
|
Oct 09 09:59:33 AM UTC 24 |
Oct 09 10:41:24 AM UTC 24 |
45564873430 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2510534855 |
|
|
Oct 09 08:50:01 AM UTC 24 |
Oct 09 10:42:44 AM UTC 24 |
450510921999 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3950631021 |
|
|
Oct 09 09:51:05 AM UTC 24 |
Oct 09 10:42:59 AM UTC 24 |
618052809001 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2900033566 |
|
|
Oct 09 10:06:20 AM UTC 24 |
Oct 09 10:45:52 AM UTC 24 |
34866736778 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1541329722 |
|
|
Oct 09 09:32:33 AM UTC 24 |
Oct 09 10:52:55 AM UTC 24 |
826353890685 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2953829353 |
|
|
Oct 09 09:30:31 AM UTC 24 |
Oct 09 10:57:46 AM UTC 24 |
663926034175 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3108216818 |
|
|
Oct 09 10:08:07 AM UTC 24 |
Oct 09 10:08:09 AM UTC 24 |
42956274 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1629534077 |
|
|
Oct 09 10:08:05 AM UTC 24 |
Oct 09 10:08:09 AM UTC 24 |
65250458 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2922901823 |
|
|
Oct 09 10:08:07 AM UTC 24 |
Oct 09 10:08:09 AM UTC 24 |
14043572 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3812903925 |
|
|
Oct 09 10:08:02 AM UTC 24 |
Oct 09 10:08:09 AM UTC 24 |
2015918719 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3132494921 |
|
|
Oct 09 10:08:07 AM UTC 24 |
Oct 09 10:08:10 AM UTC 24 |
115589484 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1939170632 |
|
|
Oct 09 10:08:10 AM UTC 24 |
Oct 09 10:08:12 AM UTC 24 |
46202634 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1096348038 |
|
|
Oct 09 10:08:10 AM UTC 24 |
Oct 09 10:08:12 AM UTC 24 |
74834018 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.96899992 |
|
|
Oct 09 10:08:10 AM UTC 24 |
Oct 09 10:08:13 AM UTC 24 |
106769172 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.195996836 |
|
|
Oct 09 10:08:10 AM UTC 24 |
Oct 09 10:08:13 AM UTC 24 |
213640965 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1838406076 |
|
|
Oct 09 10:08:14 AM UTC 24 |
Oct 09 10:08:16 AM UTC 24 |
27360828 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.950510568 |
|
|
Oct 09 10:08:11 AM UTC 24 |
Oct 09 10:08:16 AM UTC 24 |
824314569 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1849754605 |
|
|
Oct 09 10:08:15 AM UTC 24 |
Oct 09 10:08:17 AM UTC 24 |
66990512 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4207395235 |
|
|
Oct 09 10:08:14 AM UTC 24 |
Oct 09 10:08:18 AM UTC 24 |
345193792 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.715918399 |
|
|
Oct 09 10:08:17 AM UTC 24 |
Oct 09 10:08:19 AM UTC 24 |
51172071 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2313004315 |
|
|
Oct 09 10:08:18 AM UTC 24 |
Oct 09 10:08:21 AM UTC 24 |
198038125 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.393970708 |
|
|
Oct 09 10:08:17 AM UTC 24 |
Oct 09 10:08:21 AM UTC 24 |
649345246 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1356455355 |
|
|
Oct 09 10:08:14 AM UTC 24 |
Oct 09 10:08:22 AM UTC 24 |
137956249 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1344829726 |
|
|
Oct 09 10:08:18 AM UTC 24 |
Oct 09 10:08:23 AM UTC 24 |
109982454 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1217318119 |
|
|
Oct 09 10:08:23 AM UTC 24 |
Oct 09 10:08:25 AM UTC 24 |
30218583 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2060084308 |
|
|
Oct 09 10:08:23 AM UTC 24 |
Oct 09 10:08:25 AM UTC 24 |
14691782 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4201398332 |
|
|
Oct 09 10:08:22 AM UTC 24 |
Oct 09 10:08:26 AM UTC 24 |
277405406 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.763174854 |
|
|
Oct 09 10:08:20 AM UTC 24 |
Oct 09 10:08:27 AM UTC 24 |
1200158300 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2258063268 |
|
|
Oct 09 10:08:24 AM UTC 24 |
Oct 09 10:08:27 AM UTC 24 |
177967515 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3484141471 |
|
|
Oct 09 10:08:26 AM UTC 24 |
Oct 09 10:08:28 AM UTC 24 |
23379588 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.550301026 |
|
|
Oct 09 10:08:23 AM UTC 24 |
Oct 09 10:08:29 AM UTC 24 |
667426115 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.101503659 |
|
|
Oct 09 10:08:26 AM UTC 24 |
Oct 09 10:08:29 AM UTC 24 |
85981988 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4278183688 |
|
|
Oct 09 10:08:27 AM UTC 24 |
Oct 09 10:08:29 AM UTC 24 |
81730478 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3288727201 |
|
|
Oct 09 10:08:30 AM UTC 24 |
Oct 09 10:08:32 AM UTC 24 |
17780677 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2698213332 |
|
|
Oct 09 10:08:30 AM UTC 24 |
Oct 09 10:08:32 AM UTC 24 |
12993780 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1072363266 |
|
|
Oct 09 10:08:29 AM UTC 24 |
Oct 09 10:08:33 AM UTC 24 |
649610532 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2112069199 |
|
|
Oct 09 10:08:30 AM UTC 24 |
Oct 09 10:08:33 AM UTC 24 |
31697825 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4023047691 |
|
|
Oct 09 10:08:29 AM UTC 24 |
Oct 09 10:08:35 AM UTC 24 |
461503636 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3101740761 |
|
|
Oct 09 10:08:29 AM UTC 24 |
Oct 09 10:08:35 AM UTC 24 |
44374655 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2741024508 |
|
|
Oct 09 10:08:34 AM UTC 24 |
Oct 09 10:08:36 AM UTC 24 |
27804565 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2807541101 |
|
|
Oct 09 10:08:34 AM UTC 24 |
Oct 09 10:08:36 AM UTC 24 |
164444420 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3905019272 |
|
|
Oct 09 10:08:35 AM UTC 24 |
Oct 09 10:08:38 AM UTC 24 |
105720736 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.293860826 |
|
|
Oct 09 10:08:36 AM UTC 24 |
Oct 09 10:08:38 AM UTC 24 |
14119066 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1931739886 |
|
|
Oct 09 10:08:36 AM UTC 24 |
Oct 09 10:08:38 AM UTC 24 |
53890216 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2902694878 |
|
|
Oct 09 10:08:35 AM UTC 24 |
Oct 09 10:08:40 AM UTC 24 |
801756717 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1329885459 |
|
|
Oct 09 10:08:36 AM UTC 24 |
Oct 09 10:08:41 AM UTC 24 |
585599235 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2268629614 |
|
|
Oct 09 10:08:39 AM UTC 24 |
Oct 09 10:08:41 AM UTC 24 |
97171314 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3401790416 |
|
|
Oct 09 10:08:36 AM UTC 24 |
Oct 09 10:08:41 AM UTC 24 |
2155575532 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4216351449 |
|
|
Oct 09 10:08:40 AM UTC 24 |
Oct 09 10:08:42 AM UTC 24 |
26131723 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.925230834 |
|
|
Oct 09 10:08:35 AM UTC 24 |
Oct 09 10:08:43 AM UTC 24 |
138953834 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4246721731 |
|
|
Oct 09 10:08:40 AM UTC 24 |
Oct 09 10:08:43 AM UTC 24 |
44915335 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.488981571 |
|
|
Oct 09 10:08:43 AM UTC 24 |
Oct 09 10:08:45 AM UTC 24 |
31322018 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1539318587 |
|
|
Oct 09 10:08:53 AM UTC 24 |
Oct 09 10:08:56 AM UTC 24 |
413497656 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.51859761 |
|
|
Oct 09 10:08:43 AM UTC 24 |
Oct 09 10:08:45 AM UTC 24 |
16497330 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1156870175 |
|
|
Oct 09 10:08:41 AM UTC 24 |
Oct 09 10:08:45 AM UTC 24 |
209156180 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3763310842 |
|
|
Oct 09 10:08:41 AM UTC 24 |
Oct 09 10:08:47 AM UTC 24 |
83180383 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1455974462 |
|
|
Oct 09 10:08:45 AM UTC 24 |
Oct 09 10:08:47 AM UTC 24 |
38223163 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3461747974 |
|
|
Oct 09 10:08:44 AM UTC 24 |
Oct 09 10:08:47 AM UTC 24 |
70180705 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1065592493 |
|
|
Oct 09 10:08:47 AM UTC 24 |
Oct 09 10:08:49 AM UTC 24 |
45596157 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3528765459 |
|
|
Oct 09 10:08:45 AM UTC 24 |
Oct 09 10:08:50 AM UTC 24 |
479617193 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2753726162 |
|
|
Oct 09 10:08:44 AM UTC 24 |
Oct 09 10:08:50 AM UTC 24 |
948488304 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2482128323 |
|
|
Oct 09 10:08:45 AM UTC 24 |
Oct 09 10:08:51 AM UTC 24 |
2868353381 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2264263536 |
|
|
Oct 09 10:08:48 AM UTC 24 |
Oct 09 10:08:51 AM UTC 24 |
50313885 ps |