| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3307613904 |
|
|
Oct 09 09:35:24 AM UTC 24 |
Oct 09 09:35:26 AM UTC 24 |
76366784 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1839029150 |
|
|
Oct 09 09:35:27 AM UTC 24 |
Oct 09 09:35:36 AM UTC 24 |
179939754 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2975560412 |
|
|
Oct 09 09:35:27 AM UTC 24 |
Oct 09 09:35:36 AM UTC 24 |
1389510960 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1108383474 |
|
|
Oct 09 09:35:37 AM UTC 24 |
Oct 09 09:35:40 AM UTC 24 |
62488942 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3173436328 |
|
|
Oct 09 09:34:52 AM UTC 24 |
Oct 09 09:35:48 AM UTC 24 |
1385681272 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2695751712 |
|
|
Oct 09 09:35:48 AM UTC 24 |
Oct 09 09:35:50 AM UTC 24 |
17745369 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3704273540 |
|
|
Oct 09 09:32:51 AM UTC 24 |
Oct 09 09:35:54 AM UTC 24 |
7376669875 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2672197940 |
|
|
Oct 09 09:23:18 AM UTC 24 |
Oct 09 09:36:02 AM UTC 24 |
3278686203 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2842513802 |
|
|
Oct 09 09:31:13 AM UTC 24 |
Oct 09 09:36:24 AM UTC 24 |
10257219833 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.358235900 |
|
|
Oct 09 09:28:30 AM UTC 24 |
Oct 09 09:36:28 AM UTC 24 |
16271103585 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1295724181 |
|
|
Oct 09 09:36:29 AM UTC 24 |
Oct 09 09:36:34 AM UTC 24 |
98513239 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1936038554 |
|
|
Oct 09 09:35:37 AM UTC 24 |
Oct 09 09:36:42 AM UTC 24 |
1803995572 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1420293731 |
|
|
Oct 09 09:36:03 AM UTC 24 |
Oct 09 09:36:51 AM UTC 24 |
2401448844 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3584612416 |
|
|
Oct 09 09:32:32 AM UTC 24 |
Oct 09 09:37:01 AM UTC 24 |
11910492521 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3382585670 |
|
|
Oct 09 09:08:36 AM UTC 24 |
Oct 09 09:37:07 AM UTC 24 |
16180501883 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3838473040 |
|
|
Oct 09 09:37:03 AM UTC 24 |
Oct 09 09:37:09 AM UTC 24 |
4316231990 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3291342396 |
|
|
Oct 09 09:35:51 AM UTC 24 |
Oct 09 09:37:15 AM UTC 24 |
2339490559 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.688540328 |
|
|
Oct 09 09:31:39 AM UTC 24 |
Oct 09 09:37:30 AM UTC 24 |
21375488327 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3536165591 |
|
|
Oct 09 09:37:31 AM UTC 24 |
Oct 09 09:37:33 AM UTC 24 |
78086056 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3124319696 |
|
|
Oct 09 09:34:19 AM UTC 24 |
Oct 09 09:37:39 AM UTC 24 |
4032779449 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1015263425 |
|
|
Oct 09 09:23:26 AM UTC 24 |
Oct 09 09:37:40 AM UTC 24 |
15958868568 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.659259838 |
|
|
Oct 09 09:37:34 AM UTC 24 |
Oct 09 09:37:41 AM UTC 24 |
164446042 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_readback_err.612995079 |
|
|
Oct 09 09:37:41 AM UTC 24 |
Oct 09 09:37:43 AM UTC 24 |
31549435 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2113708706 |
|
|
Oct 09 09:37:40 AM UTC 24 |
Oct 09 09:37:47 AM UTC 24 |
601507401 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2841202631 |
|
|
Oct 09 09:37:48 AM UTC 24 |
Oct 09 09:37:50 AM UTC 24 |
28731208 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2589454103 |
|
|
Oct 09 09:37:51 AM UTC 24 |
Oct 09 09:38:13 AM UTC 24 |
3118471623 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3822820392 |
|
|
Oct 09 09:36:43 AM UTC 24 |
Oct 09 09:38:21 AM UTC 24 |
137980683 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.573039859 |
|
|
Oct 09 09:36:51 AM UTC 24 |
Oct 09 09:38:40 AM UTC 24 |
599359083 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3426234197 |
|
|
Oct 09 09:24:12 AM UTC 24 |
Oct 09 09:38:46 AM UTC 24 |
28577070462 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1227357283 |
|
|
Oct 09 09:38:47 AM UTC 24 |
Oct 09 09:39:07 AM UTC 24 |
2214403199 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2042616209 |
|
|
Oct 09 08:59:06 AM UTC 24 |
Oct 09 09:39:19 AM UTC 24 |
31085807466 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3395346549 |
|
|
Oct 09 08:50:42 AM UTC 24 |
Oct 09 09:39:29 AM UTC 24 |
16230538298 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.298555027 |
|
|
Oct 09 09:34:36 AM UTC 24 |
Oct 09 09:39:39 AM UTC 24 |
3555346330 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1946834647 |
|
|
Oct 09 09:39:30 AM UTC 24 |
Oct 09 09:39:45 AM UTC 24 |
150441117 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1103361855 |
|
|
Oct 09 09:33:01 AM UTC 24 |
Oct 09 09:39:46 AM UTC 24 |
12579052292 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3327893298 |
|
|
Oct 09 09:38:23 AM UTC 24 |
Oct 09 09:39:48 AM UTC 24 |
30231679686 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.853391271 |
|
|
Oct 09 09:39:40 AM UTC 24 |
Oct 09 09:39:48 AM UTC 24 |
346302859 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2698863472 |
|
|
Oct 09 09:39:49 AM UTC 24 |
Oct 09 09:39:51 AM UTC 24 |
69086319 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.671788527 |
|
|
Oct 09 09:20:42 AM UTC 24 |
Oct 09 09:40:01 AM UTC 24 |
25536163474 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4039383010 |
|
|
Oct 09 09:39:52 AM UTC 24 |
Oct 09 09:40:01 AM UTC 24 |
473205641 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_readback_err.255189751 |
|
|
Oct 09 09:40:02 AM UTC 24 |
Oct 09 09:40:05 AM UTC 24 |
103545497 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1641811640 |
|
|
Oct 09 09:40:02 AM UTC 24 |
Oct 09 09:40:07 AM UTC 24 |
141667768 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1968929622 |
|
|
Oct 09 09:36:25 AM UTC 24 |
Oct 09 09:40:16 AM UTC 24 |
2119335486 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.4030688623 |
|
|
Oct 09 09:23:38 AM UTC 24 |
Oct 09 09:40:18 AM UTC 24 |
2220392302 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2792507226 |
|
|
Oct 09 09:40:17 AM UTC 24 |
Oct 09 09:40:19 AM UTC 24 |
23272303 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1155813326 |
|
|
Oct 09 09:19:49 AM UTC 24 |
Oct 09 09:40:21 AM UTC 24 |
26818446371 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.2362272821 |
|
|
Oct 09 09:40:19 AM UTC 24 |
Oct 09 09:40:24 AM UTC 24 |
71597796 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2178645807 |
|
|
Oct 09 09:39:20 AM UTC 24 |
Oct 09 09:40:49 AM UTC 24 |
336392804 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3875801334 |
|
|
Oct 09 09:28:50 AM UTC 24 |
Oct 09 09:41:18 AM UTC 24 |
41192901751 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3275474813 |
|
|
Oct 09 09:37:10 AM UTC 24 |
Oct 09 09:41:48 AM UTC 24 |
3863506551 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.410310037 |
|
|
Oct 09 09:19:14 AM UTC 24 |
Oct 09 09:41:51 AM UTC 24 |
77679306031 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1405787441 |
|
|
Oct 09 09:38:41 AM UTC 24 |
Oct 09 09:41:56 AM UTC 24 |
3959848740 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2407390400 |
|
|
Oct 09 09:41:56 AM UTC 24 |
Oct 09 09:42:01 AM UTC 24 |
258698905 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.3457824043 |
|
|
Oct 09 09:40:22 AM UTC 24 |
Oct 09 09:42:04 AM UTC 24 |
13895769759 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3730523007 |
|
|
Oct 09 09:32:47 AM UTC 24 |
Oct 09 09:42:05 AM UTC 24 |
1521815237 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.1226047644 |
|
|
Oct 09 09:27:24 AM UTC 24 |
Oct 09 09:42:10 AM UTC 24 |
3264063774 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2507521165 |
|
|
Oct 09 09:42:11 AM UTC 24 |
Oct 09 09:42:13 AM UTC 24 |
56741997 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1520591062 |
|
|
Oct 09 09:40:50 AM UTC 24 |
Oct 09 09:42:14 AM UTC 24 |
730886801 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4201862999 |
|
|
Oct 09 09:42:15 AM UTC 24 |
Oct 09 09:42:22 AM UTC 24 |
181525423 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.4219559879 |
|
|
Oct 09 09:41:52 AM UTC 24 |
Oct 09 09:42:23 AM UTC 24 |
215596553 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_readback_err.4030115265 |
|
|
Oct 09 09:42:23 AM UTC 24 |
Oct 09 09:42:26 AM UTC 24 |
177530084 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1291769427 |
|
|
Oct 09 09:42:14 AM UTC 24 |
Oct 09 09:42:30 AM UTC 24 |
878848897 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.3055675101 |
|
|
Oct 09 09:32:17 AM UTC 24 |
Oct 09 09:42:30 AM UTC 24 |
8056485743 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.2537157106 |
|
|
Oct 09 09:27:53 AM UTC 24 |
Oct 09 09:42:30 AM UTC 24 |
21200023611 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.581057069 |
|
|
Oct 09 09:42:31 AM UTC 24 |
Oct 09 09:42:34 AM UTC 24 |
19298079 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.599224444 |
|
|
Oct 09 09:42:31 AM UTC 24 |
Oct 09 09:42:52 AM UTC 24 |
782677809 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.725780307 |
|
|
Oct 09 09:27:31 AM UTC 24 |
Oct 09 09:42:54 AM UTC 24 |
11142288443 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.350430610 |
|
|
Oct 09 09:25:31 AM UTC 24 |
Oct 09 09:42:57 AM UTC 24 |
146599696222 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2871158959 |
|
|
Oct 09 09:42:25 AM UTC 24 |
Oct 09 09:43:15 AM UTC 24 |
5589321447 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2643201116 |
|
|
Oct 09 09:35:55 AM UTC 24 |
Oct 09 09:43:21 AM UTC 24 |
30199665370 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.340201453 |
|
|
Oct 09 09:45:16 AM UTC 24 |
Oct 09 09:46:11 AM UTC 24 |
11766034272 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2908887632 |
|
|
Oct 09 09:43:08 AM UTC 24 |
Oct 09 09:43:23 AM UTC 24 |
155292949 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.402236388 |
|
|
Oct 09 09:18:42 AM UTC 24 |
Oct 09 09:43:28 AM UTC 24 |
18057640224 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3785941740 |
|
|
Oct 09 09:43:21 AM UTC 24 |
Oct 09 09:43:29 AM UTC 24 |
742786859 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2402395261 |
|
|
Oct 09 09:42:34 AM UTC 24 |
Oct 09 09:43:30 AM UTC 24 |
6948538543 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2750756752 |
|
|
Oct 09 09:51:09 AM UTC 24 |
Oct 09 09:51:53 AM UTC 24 |
854378188 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.547235719 |
|
|
Oct 09 09:39:08 AM UTC 24 |
Oct 09 09:43:32 AM UTC 24 |
11285857882 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.156062023 |
|
|
Oct 09 09:43:15 AM UTC 24 |
Oct 09 09:43:33 AM UTC 24 |
1521633822 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2617998915 |
|
|
Oct 09 09:43:31 AM UTC 24 |
Oct 09 09:43:33 AM UTC 24 |
45952998 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_readback_err.3167233470 |
|
|
Oct 09 09:43:34 AM UTC 24 |
Oct 09 09:43:37 AM UTC 24 |
139520222 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.84081866 |
|
|
Oct 09 09:43:33 AM UTC 24 |
Oct 09 09:43:40 AM UTC 24 |
171100833 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3229660588 |
|
|
Oct 09 09:35:09 AM UTC 24 |
Oct 09 09:43:41 AM UTC 24 |
5841315200 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2443825640 |
|
|
Oct 09 09:41:49 AM UTC 24 |
Oct 09 09:43:41 AM UTC 24 |
513112284 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.614585646 |
|
|
Oct 09 09:43:42 AM UTC 24 |
Oct 09 09:43:44 AM UTC 24 |
17348786 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.4034907343 |
|
|
Oct 09 09:43:42 AM UTC 24 |
Oct 09 09:43:46 AM UTC 24 |
317471567 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1098103389 |
|
|
Oct 09 09:43:33 AM UTC 24 |
Oct 09 09:43:50 AM UTC 24 |
5436659056 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.835518144 |
|
|
Oct 09 09:36:35 AM UTC 24 |
Oct 09 09:43:52 AM UTC 24 |
31833935729 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3747548447 |
|
|
Oct 09 09:42:56 AM UTC 24 |
Oct 09 09:43:58 AM UTC 24 |
185150683 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2735160591 |
|
|
Oct 09 09:43:51 AM UTC 24 |
Oct 09 09:44:07 AM UTC 24 |
226142853 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2249393952 |
|
|
Oct 09 09:43:45 AM UTC 24 |
Oct 09 09:44:24 AM UTC 24 |
1863536261 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3713429359 |
|
|
Oct 09 09:44:09 AM UTC 24 |
Oct 09 09:44:33 AM UTC 24 |
464835584 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1006663420 |
|
|
Oct 09 09:44:25 AM UTC 24 |
Oct 09 09:44:37 AM UTC 24 |
4341127496 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3396306350 |
|
|
Oct 09 09:43:59 AM UTC 24 |
Oct 09 09:44:46 AM UTC 24 |
478710011 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3709568472 |
|
|
Oct 09 09:19:38 AM UTC 24 |
Oct 09 09:44:58 AM UTC 24 |
39734922596 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1392860454 |
|
|
Oct 09 09:44:58 AM UTC 24 |
Oct 09 09:45:01 AM UTC 24 |
76421275 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.4280619718 |
|
|
Oct 09 09:40:25 AM UTC 24 |
Oct 09 09:45:04 AM UTC 24 |
2650320063 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3855777710 |
|
|
Oct 09 09:45:02 AM UTC 24 |
Oct 09 09:45:09 AM UTC 24 |
86650048 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3073120713 |
|
|
Oct 09 09:39:48 AM UTC 24 |
Oct 09 09:45:11 AM UTC 24 |
18347500879 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1357053761 |
|
|
Oct 09 09:45:05 AM UTC 24 |
Oct 09 09:45:11 AM UTC 24 |
213280735 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_readback_err.1127913270 |
|
|
Oct 09 09:45:10 AM UTC 24 |
Oct 09 09:45:12 AM UTC 24 |
31843196 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3566520627 |
|
|
Oct 09 09:43:34 AM UTC 24 |
Oct 09 09:45:13 AM UTC 24 |
779674361 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.564292484 |
|
|
Oct 09 09:45:13 AM UTC 24 |
Oct 09 09:45:15 AM UTC 24 |
23849868 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2322411892 |
|
|
Oct 09 09:43:29 AM UTC 24 |
Oct 09 09:45:15 AM UTC 24 |
3795010201 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.4219515026 |
|
|
Oct 09 09:43:42 AM UTC 24 |
Oct 09 09:45:24 AM UTC 24 |
1338482920 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3334363526 |
|
|
Oct 09 09:37:42 AM UTC 24 |
Oct 09 09:45:25 AM UTC 24 |
1731101236 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3909492194 |
|
|
Oct 09 09:28:49 AM UTC 24 |
Oct 09 09:45:30 AM UTC 24 |
55952968159 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2784301615 |
|
|
Oct 09 08:54:53 AM UTC 24 |
Oct 09 09:45:32 AM UTC 24 |
176802680258 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3716573427 |
|
|
Oct 09 09:45:26 AM UTC 24 |
Oct 09 09:45:37 AM UTC 24 |
413752494 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1990081944 |
|
|
Oct 09 09:45:33 AM UTC 24 |
Oct 09 09:46:04 AM UTC 24 |
85703936 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.935967470 |
|
|
Oct 09 09:46:05 AM UTC 24 |
Oct 09 09:46:08 AM UTC 24 |
268562118 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1730290145 |
|
|
Oct 09 09:37:08 AM UTC 24 |
Oct 09 09:46:09 AM UTC 24 |
2327124658 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3830036528 |
|
|
Oct 09 09:51:54 AM UTC 24 |
Oct 09 09:51:56 AM UTC 24 |
82076864 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1002228150 |
|
|
Oct 09 09:45:38 AM UTC 24 |
Oct 09 09:46:25 AM UTC 24 |
262582277 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.476316846 |
|
|
Oct 09 09:46:26 AM UTC 24 |
Oct 09 09:46:28 AM UTC 24 |
45263807 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2830757316 |
|
|
Oct 09 09:46:30 AM UTC 24 |
Oct 09 09:46:38 AM UTC 24 |
290267124 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2242491854 |
|
|
Oct 09 09:31:03 AM UTC 24 |
Oct 09 09:46:41 AM UTC 24 |
3412449400 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_readback_err.635787911 |
|
|
Oct 09 09:46:42 AM UTC 24 |
Oct 09 09:46:45 AM UTC 24 |
51366899 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1118282510 |
|
|
Oct 09 09:38:13 AM UTC 24 |
Oct 09 09:46:45 AM UTC 24 |
6535842351 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.281294171 |
|
|
Oct 09 09:46:40 AM UTC 24 |
Oct 09 09:46:47 AM UTC 24 |
90751826 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.876620563 |
|
|
Oct 09 09:46:48 AM UTC 24 |
Oct 09 09:46:50 AM UTC 24 |
11605349 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3917576236 |
|
|
Oct 09 09:44:34 AM UTC 24 |
Oct 09 09:46:53 AM UTC 24 |
783001504 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.4087213035 |
|
|
Oct 09 09:46:52 AM UTC 24 |
Oct 09 09:46:58 AM UTC 24 |
76763775 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3690186910 |
|
|
Oct 09 09:26:24 AM UTC 24 |
Oct 09 09:47:07 AM UTC 24 |
62262407121 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4066100393 |
|
|
Oct 09 09:47:08 AM UTC 24 |
Oct 09 09:47:14 AM UTC 24 |
122267387 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.180083483 |
|
|
Oct 09 09:33:43 AM UTC 24 |
Oct 09 09:47:16 AM UTC 24 |
57543375232 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.181954364 |
|
|
Oct 09 09:45:14 AM UTC 24 |
Oct 09 09:47:20 AM UTC 24 |
1476496097 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2475085264 |
|
|
Oct 09 09:42:02 AM UTC 24 |
Oct 09 09:47:32 AM UTC 24 |
3339592930 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.3035953050 |
|
|
Oct 09 09:18:13 AM UTC 24 |
Oct 09 09:47:36 AM UTC 24 |
59149911593 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.237309292 |
|
|
Oct 09 09:39:46 AM UTC 24 |
Oct 09 09:47:39 AM UTC 24 |
2107094090 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.1375711135 |
|
|
Oct 09 09:35:11 AM UTC 24 |
Oct 09 09:47:43 AM UTC 24 |
16072946317 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3156888067 |
|
|
Oct 09 09:47:33 AM UTC 24 |
Oct 09 09:47:43 AM UTC 24 |
2097942487 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.791443751 |
|
|
Oct 09 09:46:57 AM UTC 24 |
Oct 09 09:47:44 AM UTC 24 |
1698112605 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3012197957 |
|
|
Oct 09 09:47:44 AM UTC 24 |
Oct 09 09:47:47 AM UTC 24 |
90870116 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.299166077 |
|
|
Oct 09 09:28:42 AM UTC 24 |
Oct 09 09:47:49 AM UTC 24 |
3060822884 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2953492180 |
|
|
Oct 09 09:47:45 AM UTC 24 |
Oct 09 09:47:52 AM UTC 24 |
234771773 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.988196530 |
|
|
Oct 09 09:37:15 AM UTC 24 |
Oct 09 09:47:52 AM UTC 24 |
2047907096 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.3983090967 |
|
|
Oct 09 09:47:48 AM UTC 24 |
Oct 09 09:47:52 AM UTC 24 |
215766412 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_readback_err.3865394021 |
|
|
Oct 09 09:47:50 AM UTC 24 |
Oct 09 09:47:53 AM UTC 24 |
36358208 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1835306011 |
|
|
Oct 09 09:47:54 AM UTC 24 |
Oct 09 09:47:57 AM UTC 24 |
13263920 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4017994683 |
|
|
Oct 09 09:46:46 AM UTC 24 |
Oct 09 09:47:57 AM UTC 24 |
324096819 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.3739702360 |
|
|
Oct 09 09:44:46 AM UTC 24 |
Oct 09 09:48:01 AM UTC 24 |
5040483296 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2150647641 |
|
|
Oct 09 09:42:52 AM UTC 24 |
Oct 09 09:48:01 AM UTC 24 |
2623390230 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3087260735 |
|
|
Oct 09 09:47:21 AM UTC 24 |
Oct 09 09:48:05 AM UTC 24 |
108719652 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1408620722 |
|
|
Oct 09 09:48:01 AM UTC 24 |
Oct 09 09:48:17 AM UTC 24 |
3847492414 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.3522325587 |
|
|
Oct 09 09:47:54 AM UTC 24 |
Oct 09 09:48:18 AM UTC 24 |
1063317579 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3353031423 |
|
|
Oct 09 09:41:19 AM UTC 24 |
Oct 09 09:48:22 AM UTC 24 |
15234630140 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.812566996 |
|
|
Oct 09 09:48:23 AM UTC 24 |
Oct 09 09:48:27 AM UTC 24 |
695122544 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.985358188 |
|
|
Oct 09 09:47:16 AM UTC 24 |
Oct 09 09:48:35 AM UTC 24 |
470261255 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4226543366 |
|
|
Oct 09 09:48:19 AM UTC 24 |
Oct 09 09:48:43 AM UTC 24 |
192414475 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.769476856 |
|
|
Oct 09 09:48:18 AM UTC 24 |
Oct 09 09:48:52 AM UTC 24 |
1399237310 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.38692796 |
|
|
Oct 09 09:48:53 AM UTC 24 |
Oct 09 09:48:55 AM UTC 24 |
189371763 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.261980897 |
|
|
Oct 09 09:48:56 AM UTC 24 |
Oct 09 09:49:03 AM UTC 24 |
232023376 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2680382578 |
|
|
Oct 09 09:49:04 AM UTC 24 |
Oct 09 09:49:10 AM UTC 24 |
175255333 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1202835202 |
|
|
Oct 09 09:42:58 AM UTC 24 |
Oct 09 09:49:12 AM UTC 24 |
23472991463 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_readback_err.1664192067 |
|
|
Oct 09 09:49:11 AM UTC 24 |
Oct 09 09:49:13 AM UTC 24 |
153021072 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.16788212 |
|
|
Oct 09 09:43:47 AM UTC 24 |
Oct 09 09:49:16 AM UTC 24 |
67134585265 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.385274594 |
|
|
Oct 09 09:49:16 AM UTC 24 |
Oct 09 09:49:18 AM UTC 24 |
42637985 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1604755364 |
|
|
Oct 09 09:47:58 AM UTC 24 |
Oct 09 09:49:21 AM UTC 24 |
19423066502 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.2877050955 |
|
|
Oct 09 09:35:09 AM UTC 24 |
Oct 09 09:49:23 AM UTC 24 |
6125631754 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.236589035 |
|
|
Oct 09 09:49:19 AM UTC 24 |
Oct 09 09:49:26 AM UTC 24 |
297111855 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1004615611 |
|
|
Oct 09 09:40:06 AM UTC 24 |
Oct 09 09:49:31 AM UTC 24 |
9103882641 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.4204704684 |
|
|
Oct 09 09:25:19 AM UTC 24 |
Oct 09 09:49:36 AM UTC 24 |
21146972050 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2160997328 |
|
|
Oct 09 09:49:13 AM UTC 24 |
Oct 09 09:49:38 AM UTC 24 |
2364177621 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.179904162 |
|
|
Oct 09 09:42:06 AM UTC 24 |
Oct 09 09:49:50 AM UTC 24 |
14601154732 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3337456386 |
|
|
Oct 09 09:49:32 AM UTC 24 |
Oct 09 09:50:00 AM UTC 24 |
336119827 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3618087216 |
|
|
Oct 09 09:42:31 AM UTC 24 |
Oct 09 09:50:11 AM UTC 24 |
2825356760 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2719841952 |
|
|
Oct 09 09:50:01 AM UTC 24 |
Oct 09 09:50:15 AM UTC 24 |
1231987173 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3411424291 |
|
|
Oct 09 09:43:53 AM UTC 24 |
Oct 09 09:50:37 AM UTC 24 |
46357411585 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1790993509 |
|
|
Oct 09 09:34:11 AM UTC 24 |
Oct 09 09:50:47 AM UTC 24 |
10950253489 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1549281192 |
|
|
Oct 09 09:50:48 AM UTC 24 |
Oct 09 09:50:50 AM UTC 24 |
100142841 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2195694721 |
|
|
Oct 09 09:49:24 AM UTC 24 |
Oct 09 09:50:56 AM UTC 24 |
4343136635 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.472915615 |
|
|
Oct 09 09:50:51 AM UTC 24 |
Oct 09 09:51:00 AM UTC 24 |
118241050 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_readback_err.2767785561 |
|
|
Oct 09 09:51:00 AM UTC 24 |
Oct 09 09:51:03 AM UTC 24 |
148950652 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2563537599 |
|
|
Oct 09 09:49:50 AM UTC 24 |
Oct 09 09:51:04 AM UTC 24 |
763069119 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3517328461 |
|
|
Oct 09 09:50:57 AM UTC 24 |
Oct 09 09:51:05 AM UTC 24 |
576104282 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.607695945 |
|
|
Oct 09 09:51:06 AM UTC 24 |
Oct 09 09:51:08 AM UTC 24 |
40792713 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1132884586 |
|
|
Oct 09 09:49:39 AM UTC 24 |
Oct 09 09:51:12 AM UTC 24 |
138516550 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.772613931 |
|
|
Oct 09 09:32:16 AM UTC 24 |
Oct 09 09:51:16 AM UTC 24 |
8711641449 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.265355924 |
|
|
Oct 09 09:27:43 AM UTC 24 |
Oct 09 09:51:17 AM UTC 24 |
19184525922 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3560611509 |
|
|
Oct 09 09:45:12 AM UTC 24 |
Oct 09 09:51:23 AM UTC 24 |
1333659455 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.830848717 |
|
|
Oct 09 09:47:54 AM UTC 24 |
Oct 09 09:51:30 AM UTC 24 |
1556055300 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1472568335 |
|
|
Oct 09 09:45:25 AM UTC 24 |
Oct 09 09:51:36 AM UTC 24 |
14180300317 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3963574522 |
|
|
Oct 09 09:51:24 AM UTC 24 |
Oct 09 09:51:44 AM UTC 24 |
564844945 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.1582712589 |
|
|
Oct 09 09:51:17 AM UTC 24 |
Oct 09 09:51:47 AM UTC 24 |
579943018 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.353715720 |
|
|
Oct 09 09:50:12 AM UTC 24 |
Oct 09 09:51:50 AM UTC 24 |
524796515 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1332145028 |
|
|
Oct 09 09:51:31 AM UTC 24 |
Oct 09 09:51:51 AM UTC 24 |
72251483 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2483607240 |
|
|
Oct 09 09:51:45 AM UTC 24 |
Oct 09 09:51:52 AM UTC 24 |
378222803 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.728040848 |
|
|
Oct 09 09:51:04 AM UTC 24 |
Oct 09 09:52:00 AM UTC 24 |
1591460962 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2527106690 |
|
|
Oct 09 09:43:30 AM UTC 24 |
Oct 09 09:52:01 AM UTC 24 |
1813671663 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3421165844 |
|
|
Oct 09 09:51:57 AM UTC 24 |
Oct 09 09:52:02 AM UTC 24 |
423262318 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2924579897 |
|
|
Oct 09 09:43:38 AM UTC 24 |
Oct 09 09:52:02 AM UTC 24 |
36065817013 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3924050875 |
|
|
Oct 09 09:52:01 AM UTC 24 |
Oct 09 09:52:03 AM UTC 24 |
32272855 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3857923844 |
|
|
Oct 09 09:51:55 AM UTC 24 |
Oct 09 09:52:04 AM UTC 24 |
1591564849 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2115969517 |
|
|
Oct 09 09:52:03 AM UTC 24 |
Oct 09 09:52:05 AM UTC 24 |
25519569 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1802193092 |
|
|
Oct 09 09:51:36 AM UTC 24 |
Oct 09 09:52:12 AM UTC 24 |
235372934 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3832576760 |
|
|
Oct 09 09:33:38 AM UTC 24 |
Oct 09 09:52:13 AM UTC 24 |
5359786475 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2619896920 |
|
|
Oct 09 09:43:25 AM UTC 24 |
Oct 09 09:52:20 AM UTC 24 |
10114515841 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3611709962 |
|
|
Oct 09 09:45:31 AM UTC 24 |
Oct 09 09:52:24 AM UTC 24 |
58482624968 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.608633497 |
|
|
Oct 09 09:52:07 AM UTC 24 |
Oct 09 09:52:28 AM UTC 24 |
1097916490 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2159177290 |
|
|
Oct 09 09:46:09 AM UTC 24 |
Oct 09 09:53:01 AM UTC 24 |
1836750105 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.650383970 |
|
|
Oct 09 09:52:14 AM UTC 24 |
Oct 09 09:53:03 AM UTC 24 |
180896826 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2017145898 |
|
|
Oct 09 09:32:04 AM UTC 24 |
Oct 09 09:53:07 AM UTC 24 |
19094364316 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.25151721 |
|
|
Oct 09 09:52:28 AM UTC 24 |
Oct 09 09:53:10 AM UTC 24 |
1316467684 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3439137303 |
|
|
Oct 09 09:53:02 AM UTC 24 |
Oct 09 09:53:10 AM UTC 24 |
452650195 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3013266493 |
|
|
Oct 09 09:53:11 AM UTC 24 |
Oct 09 09:53:13 AM UTC 24 |
31499775 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.4134742256 |
|
|
Oct 09 09:52:25 AM UTC 24 |
Oct 09 09:53:14 AM UTC 24 |
105925482 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.451026419 |
|
|
Oct 09 09:49:27 AM UTC 24 |
Oct 09 09:53:17 AM UTC 24 |
9215142889 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3596130081 |
|
|
Oct 09 09:42:05 AM UTC 24 |
Oct 09 09:53:19 AM UTC 24 |
24300955908 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2125120746 |
|
|
Oct 09 09:53:14 AM UTC 24 |
Oct 09 09:53:20 AM UTC 24 |
82968248 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_readback_err.1558099455 |
|
|
Oct 09 09:53:18 AM UTC 24 |
Oct 09 09:53:21 AM UTC 24 |
328145640 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.4036919515 |
|
|
Oct 09 09:53:15 AM UTC 24 |
Oct 09 09:53:21 AM UTC 24 |
265466756 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3295304102 |
|
|
Oct 09 09:52:04 AM UTC 24 |
Oct 09 09:53:23 AM UTC 24 |
711328108 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1991114882 |
|
|
Oct 09 09:53:22 AM UTC 24 |
Oct 09 09:53:24 AM UTC 24 |
13148660 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.4129964094 |
|
|
Oct 09 09:53:23 AM UTC 24 |
Oct 09 09:53:28 AM UTC 24 |
150833878 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1008196980 |
|
|
Oct 09 09:47:15 AM UTC 24 |
Oct 09 09:53:32 AM UTC 24 |
26070043910 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.41537313 |
|
|
Oct 09 09:33:44 AM UTC 24 |
Oct 09 09:53:42 AM UTC 24 |
6432555650 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1508976984 |
|
|
Oct 09 09:48:07 AM UTC 24 |
Oct 09 09:53:44 AM UTC 24 |
50628870795 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1105647968 |
|
|
Oct 09 09:47:40 AM UTC 24 |
Oct 09 09:53:44 AM UTC 24 |
9377710496 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3544647750 |
|
|
Oct 09 09:53:25 AM UTC 24 |
Oct 09 09:53:51 AM UTC 24 |
5632316952 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2210026771 |
|
|
Oct 09 09:53:32 AM UTC 24 |
Oct 09 09:53:52 AM UTC 24 |
677118821 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3631298145 |
|
|
Oct 09 09:53:52 AM UTC 24 |
Oct 09 09:53:55 AM UTC 24 |
290292113 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2739490967 |
|
|
Oct 09 09:47:58 AM UTC 24 |
Oct 09 09:53:58 AM UTC 24 |
9852530868 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3801418860 |
|
|
Oct 09 09:46:54 AM UTC 24 |
Oct 09 09:54:23 AM UTC 24 |
9384167106 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3501720783 |
|
|
Oct 09 09:54:24 AM UTC 24 |
Oct 09 09:54:26 AM UTC 24 |
27614184 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2737686257 |
|
|
Oct 09 09:53:45 AM UTC 24 |
Oct 09 09:54:38 AM UTC 24 |
447985984 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2174414961 |
|
|
Oct 09 09:53:45 AM UTC 24 |
Oct 09 09:54:39 AM UTC 24 |
830734118 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.690395949 |
|
|
Oct 09 09:54:27 AM UTC 24 |
Oct 09 09:54:40 AM UTC 24 |
207401323 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_readback_err.2477580090 |
|
|
Oct 09 09:54:40 AM UTC 24 |
Oct 09 09:54:43 AM UTC 24 |
54267346 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3881703075 |
|
|
Oct 09 09:54:39 AM UTC 24 |
Oct 09 09:54:48 AM UTC 24 |
351372706 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.94405815 |
|
|
Oct 09 09:54:49 AM UTC 24 |
Oct 09 09:54:51 AM UTC 24 |
13020913 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1328242579 |
|
|
Oct 09 09:49:37 AM UTC 24 |
Oct 09 09:54:52 AM UTC 24 |
3575406512 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1109509695 |
|
|
Oct 09 09:46:59 AM UTC 24 |
Oct 09 09:55:05 AM UTC 24 |
14696893161 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2491852779 |
|
|
Oct 09 09:52:02 AM UTC 24 |
Oct 09 09:55:07 AM UTC 24 |
1118669389 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.668817783 |
|
|
Oct 09 09:49:21 AM UTC 24 |
Oct 09 09:55:09 AM UTC 24 |
6362495698 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1860979152 |
|
|
Oct 09 09:51:18 AM UTC 24 |
Oct 09 09:55:29 AM UTC 24 |
14258414496 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2004908242 |
|
|
Oct 09 09:55:09 AM UTC 24 |
Oct 09 09:55:32 AM UTC 24 |
1062792617 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3243414841 |
|
|
Oct 09 09:52:21 AM UTC 24 |
Oct 09 09:56:05 AM UTC 24 |
16327980498 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.4003834536 |
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|
Oct 09 09:56:06 AM UTC 24 |
Oct 09 09:56:10 AM UTC 24 |
182696305 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1199818051 |
|
|
Oct 09 09:56:11 AM UTC 24 |
Oct 09 09:56:14 AM UTC 24 |
164105508 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3302401709 |
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|
Oct 09 09:55:06 AM UTC 24 |
Oct 09 09:56:19 AM UTC 24 |
4325272494 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.1750667501 |
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|
Oct 09 09:54:52 AM UTC 24 |
Oct 09 09:56:24 AM UTC 24 |
264239191 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1641908767 |
|
|
Oct 09 09:52:13 AM UTC 24 |
Oct 09 09:56:28 AM UTC 24 |
2181778939 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.140447781 |
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|
Oct 09 09:56:30 AM UTC 24 |
Oct 09 09:56:32 AM UTC 24 |
246022806 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.250080147 |
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Oct 09 09:48:01 AM UTC 24 |
Oct 09 09:56:34 AM UTC 24 |
4845679231 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2466389454 |
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|
Oct 09 09:56:35 AM UTC 24 |
Oct 09 09:56:40 AM UTC 24 |
333925909 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1651194681 |
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|
Oct 09 09:54:53 AM UTC 24 |
Oct 09 09:56:41 AM UTC 24 |
5013575521 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.15615885 |
|
|
Oct 09 09:56:33 AM UTC 24 |
Oct 09 09:56:41 AM UTC 24 |
901086278 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_readback_err.1112258746 |
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Oct 09 09:56:41 AM UTC 24 |
Oct 09 09:56:44 AM UTC 24 |
152856264 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2420683363 |
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|
Oct 09 09:56:15 AM UTC 24 |
Oct 09 09:56:45 AM UTC 24 |
1868785638 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.4158661109 |
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|
Oct 09 09:48:44 AM UTC 24 |
Oct 09 09:56:45 AM UTC 24 |
14645898632 ps |