| T305 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1268648931 |
|
|
Oct 12 04:50:54 AM UTC 24 |
Oct 12 04:51:05 AM UTC 24 |
785927585 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1997426258 |
|
|
Oct 12 04:43:05 AM UTC 24 |
Oct 12 04:51:06 AM UTC 24 |
4285015689 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1022889894 |
|
|
Oct 12 04:50:22 AM UTC 24 |
Oct 12 04:51:12 AM UTC 24 |
530663871 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3080654240 |
|
|
Oct 12 04:45:30 AM UTC 24 |
Oct 12 04:52:03 AM UTC 24 |
10371577516 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.157001743 |
|
|
Oct 12 04:48:47 AM UTC 24 |
Oct 12 04:52:04 AM UTC 24 |
1137202019 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.4002368817 |
|
|
Oct 12 04:52:04 AM UTC 24 |
Oct 12 04:52:06 AM UTC 24 |
115114610 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3056289354 |
|
|
Oct 12 04:50:40 AM UTC 24 |
Oct 12 04:52:15 AM UTC 24 |
150853500 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3135590453 |
|
|
Oct 12 04:52:07 AM UTC 24 |
Oct 12 04:52:15 AM UTC 24 |
97187313 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_readback_err.1609331210 |
|
|
Oct 12 04:52:16 AM UTC 24 |
Oct 12 04:52:19 AM UTC 24 |
36831232 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3311725765 |
|
|
Oct 12 04:52:05 AM UTC 24 |
Oct 12 04:52:22 AM UTC 24 |
1626809139 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.3275914090 |
|
|
Oct 12 04:52:22 AM UTC 24 |
Oct 12 04:52:24 AM UTC 24 |
16826500 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3300624293 |
|
|
Oct 12 04:45:13 AM UTC 24 |
Oct 12 04:52:27 AM UTC 24 |
5221164835 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.1481629797 |
|
|
Oct 12 04:52:25 AM UTC 24 |
Oct 12 04:52:39 AM UTC 24 |
1065933093 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2910531766 |
|
|
Oct 12 04:46:30 AM UTC 24 |
Oct 12 04:52:59 AM UTC 24 |
19307428125 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1190789306 |
|
|
Oct 12 04:47:45 AM UTC 24 |
Oct 12 04:53:06 AM UTC 24 |
5368349888 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2320227166 |
|
|
Oct 12 04:50:05 AM UTC 24 |
Oct 12 04:53:07 AM UTC 24 |
7162999558 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.2010321500 |
|
|
Oct 12 04:52:40 AM UTC 24 |
Oct 12 04:53:21 AM UTC 24 |
1316402046 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.4093253501 |
|
|
Oct 12 04:53:07 AM UTC 24 |
Oct 12 04:53:24 AM UTC 24 |
1598632923 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.998586730 |
|
|
Oct 12 04:53:22 AM UTC 24 |
Oct 12 04:53:32 AM UTC 24 |
307161727 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.189817110 |
|
|
Oct 12 04:53:32 AM UTC 24 |
Oct 12 04:53:37 AM UTC 24 |
263034181 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4050175817 |
|
|
Oct 12 04:46:39 AM UTC 24 |
Oct 12 04:53:44 AM UTC 24 |
32959556494 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.615145093 |
|
|
Oct 12 04:43:20 AM UTC 24 |
Oct 12 04:53:46 AM UTC 24 |
11274976309 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3670447011 |
|
|
Oct 12 04:53:24 AM UTC 24 |
Oct 12 04:53:53 AM UTC 24 |
168939570 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3468346326 |
|
|
Oct 12 04:53:54 AM UTC 24 |
Oct 12 04:53:56 AM UTC 24 |
35070975 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.296215750 |
|
|
Oct 12 04:38:39 AM UTC 24 |
Oct 12 04:54:02 AM UTC 24 |
3170659585 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3407868524 |
|
|
Oct 12 04:54:03 AM UTC 24 |
Oct 12 04:54:08 AM UTC 24 |
357485303 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3274590882 |
|
|
Oct 12 04:53:57 AM UTC 24 |
Oct 12 04:54:11 AM UTC 24 |
2016906210 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_readback_err.527206553 |
|
|
Oct 12 04:54:09 AM UTC 24 |
Oct 12 04:54:12 AM UTC 24 |
225866826 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.399257640 |
|
|
Oct 12 04:47:13 AM UTC 24 |
Oct 12 04:54:44 AM UTC 24 |
3637104205 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.400344253 |
|
|
Oct 12 04:54:45 AM UTC 24 |
Oct 12 04:54:47 AM UTC 24 |
23710165 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2528542779 |
|
|
Oct 12 04:47:52 AM UTC 24 |
Oct 12 04:54:58 AM UTC 24 |
6845276297 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.845508053 |
|
|
Oct 12 04:38:39 AM UTC 24 |
Oct 12 04:55:03 AM UTC 24 |
12301059442 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.2027434255 |
|
|
Oct 12 04:54:48 AM UTC 24 |
Oct 12 04:55:13 AM UTC 24 |
1094449130 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3463561233 |
|
|
Oct 12 04:45:21 AM UTC 24 |
Oct 12 04:55:24 AM UTC 24 |
9264364210 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.841890543 |
|
|
Oct 12 04:55:04 AM UTC 24 |
Oct 12 04:55:25 AM UTC 24 |
235587565 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.3845907305 |
|
|
Oct 12 04:43:43 AM UTC 24 |
Oct 12 04:55:37 AM UTC 24 |
34717780983 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.957694147 |
|
|
Oct 12 04:55:24 AM UTC 24 |
Oct 12 04:55:38 AM UTC 24 |
514023672 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.3777787718 |
|
|
Oct 12 04:55:38 AM UTC 24 |
Oct 12 04:55:40 AM UTC 24 |
118318691 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2364467912 |
|
|
Oct 12 04:47:42 AM UTC 24 |
Oct 12 04:55:45 AM UTC 24 |
31143511649 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.83069479 |
|
|
Oct 12 04:55:39 AM UTC 24 |
Oct 12 04:55:46 AM UTC 24 |
353494541 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.3648671808 |
|
|
Oct 12 04:47:24 AM UTC 24 |
Oct 12 04:56:07 AM UTC 24 |
8100638735 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3307785040 |
|
|
Oct 12 04:36:43 AM UTC 24 |
Oct 12 04:56:08 AM UTC 24 |
3998313209 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.167001191 |
|
|
Oct 12 04:56:07 AM UTC 24 |
Oct 12 04:56:10 AM UTC 24 |
43765390 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1426949130 |
|
|
Oct 12 04:56:08 AM UTC 24 |
Oct 12 04:56:16 AM UTC 24 |
352860813 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_readback_err.402651461 |
|
|
Oct 12 04:56:17 AM UTC 24 |
Oct 12 04:56:19 AM UTC 24 |
104811728 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3587703305 |
|
|
Oct 12 04:56:11 AM UTC 24 |
Oct 12 04:56:20 AM UTC 24 |
185586139 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.239994860 |
|
|
Oct 12 04:52:16 AM UTC 24 |
Oct 12 04:56:26 AM UTC 24 |
1320501620 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.1107263126 |
|
|
Oct 12 04:55:27 AM UTC 24 |
Oct 12 04:56:26 AM UTC 24 |
107450722 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1429390020 |
|
|
Oct 12 04:56:27 AM UTC 24 |
Oct 12 04:56:29 AM UTC 24 |
17743366 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3833824378 |
|
|
Oct 12 04:49:57 AM UTC 24 |
Oct 12 04:56:33 AM UTC 24 |
13685170548 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2761611012 |
|
|
Oct 12 04:56:20 AM UTC 24 |
Oct 12 04:56:35 AM UTC 24 |
362846685 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1366522277 |
|
|
Oct 12 04:48:04 AM UTC 24 |
Oct 12 04:56:41 AM UTC 24 |
30748237613 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3825814058 |
|
|
Oct 12 04:56:27 AM UTC 24 |
Oct 12 04:56:49 AM UTC 24 |
859896693 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.900465566 |
|
|
Oct 12 04:39:36 AM UTC 24 |
Oct 12 04:56:54 AM UTC 24 |
25348412581 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1964804733 |
|
|
Oct 12 04:56:58 AM UTC 24 |
Oct 12 04:57:01 AM UTC 24 |
116115126 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3345251815 |
|
|
Oct 12 04:41:16 AM UTC 24 |
Oct 12 04:57:07 AM UTC 24 |
69142295661 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.831860655 |
|
|
Oct 12 04:56:55 AM UTC 24 |
Oct 12 04:57:10 AM UTC 24 |
72339145 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2016865308 |
|
|
Oct 12 04:56:42 AM UTC 24 |
Oct 12 04:57:11 AM UTC 24 |
1069835009 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3266156772 |
|
|
Oct 12 04:57:02 AM UTC 24 |
Oct 12 04:57:12 AM UTC 24 |
3905129298 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.3762619263 |
|
|
Oct 12 04:56:34 AM UTC 24 |
Oct 12 04:57:14 AM UTC 24 |
534822579 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1814558592 |
|
|
Oct 12 04:57:13 AM UTC 24 |
Oct 12 04:57:15 AM UTC 24 |
45006224 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2727324829 |
|
|
Oct 12 04:57:16 AM UTC 24 |
Oct 12 04:57:23 AM UTC 24 |
845958484 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.866416809 |
|
|
Oct 12 04:57:16 AM UTC 24 |
Oct 12 04:57:23 AM UTC 24 |
383334779 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_readback_err.3921611231 |
|
|
Oct 12 04:57:24 AM UTC 24 |
Oct 12 04:57:26 AM UTC 24 |
124952998 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2306277535 |
|
|
Oct 12 04:50:16 AM UTC 24 |
Oct 12 04:57:31 AM UTC 24 |
20003256323 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2152382792 |
|
|
Oct 12 04:57:31 AM UTC 24 |
Oct 12 04:57:34 AM UTC 24 |
22931185 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3265363894 |
|
|
Oct 12 04:53:00 AM UTC 24 |
Oct 12 04:57:53 AM UTC 24 |
2762527251 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.3591524995 |
|
|
Oct 12 04:57:34 AM UTC 24 |
Oct 12 04:57:57 AM UTC 24 |
664163449 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1974166615 |
|
|
Oct 12 04:32:49 AM UTC 24 |
Oct 12 04:58:02 AM UTC 24 |
41005391686 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1714970689 |
|
|
Oct 12 04:53:08 AM UTC 24 |
Oct 12 04:58:14 AM UTC 24 |
15799619264 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3592967189 |
|
|
Oct 12 04:55:14 AM UTC 24 |
Oct 12 04:58:15 AM UTC 24 |
6384170628 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1046923376 |
|
|
Oct 12 04:42:46 AM UTC 24 |
Oct 12 04:58:29 AM UTC 24 |
162354073143 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1877637862 |
|
|
Oct 12 04:57:58 AM UTC 24 |
Oct 12 04:58:31 AM UTC 24 |
5343553494 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1754053476 |
|
|
Oct 12 04:58:29 AM UTC 24 |
Oct 12 04:58:36 AM UTC 24 |
95131574 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.919017540 |
|
|
Oct 12 04:58:15 AM UTC 24 |
Oct 12 04:58:38 AM UTC 24 |
3361934058 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1452503054 |
|
|
Oct 12 04:58:37 AM UTC 24 |
Oct 12 04:58:48 AM UTC 24 |
596693458 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1534624742 |
|
|
Oct 12 04:58:32 AM UTC 24 |
Oct 12 04:59:28 AM UTC 24 |
508999708 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.324311763 |
|
|
Oct 12 04:58:49 AM UTC 24 |
Oct 12 04:59:31 AM UTC 24 |
1986694525 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.88808103 |
|
|
Oct 12 04:59:29 AM UTC 24 |
Oct 12 04:59:31 AM UTC 24 |
30475515 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2249910021 |
|
|
Oct 12 04:59:32 AM UTC 24 |
Oct 12 04:59:39 AM UTC 24 |
249970550 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1974289762 |
|
|
Oct 12 04:57:11 AM UTC 24 |
Oct 12 04:59:40 AM UTC 24 |
2031054005 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2015044801 |
|
|
Oct 12 04:54:12 AM UTC 24 |
Oct 12 04:59:41 AM UTC 24 |
6048515793 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_readback_err.1337461744 |
|
|
Oct 12 04:59:40 AM UTC 24 |
Oct 12 04:59:42 AM UTC 24 |
50300112 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1462674693 |
|
|
Oct 12 04:59:43 AM UTC 24 |
Oct 12 04:59:45 AM UTC 24 |
94112654 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1030056258 |
|
|
Oct 12 04:59:31 AM UTC 24 |
Oct 12 04:59:46 AM UTC 24 |
903719586 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1397675019 |
|
|
Oct 12 04:46:05 AM UTC 24 |
Oct 12 04:59:49 AM UTC 24 |
4848114147 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.973571542 |
|
|
Oct 12 04:59:46 AM UTC 24 |
Oct 12 05:00:06 AM UTC 24 |
810162331 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2171639134 |
|
|
Oct 12 04:47:00 AM UTC 24 |
Oct 12 05:00:10 AM UTC 24 |
15452577756 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.147240217 |
|
|
Oct 12 04:29:55 AM UTC 24 |
Oct 12 05:00:27 AM UTC 24 |
32864608247 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3943046250 |
|
|
Oct 12 04:59:41 AM UTC 24 |
Oct 12 05:00:42 AM UTC 24 |
7086243129 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2904925345 |
|
|
Oct 12 05:00:11 AM UTC 24 |
Oct 12 05:00:42 AM UTC 24 |
1037216753 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.2423773163 |
|
|
Oct 12 04:59:50 AM UTC 24 |
Oct 12 05:00:45 AM UTC 24 |
10488833492 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3566651788 |
|
|
Oct 12 05:00:43 AM UTC 24 |
Oct 12 05:00:50 AM UTC 24 |
200087711 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1845802395 |
|
|
Oct 12 05:00:43 AM UTC 24 |
Oct 12 05:00:54 AM UTC 24 |
432953965 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.179748845 |
|
|
Oct 12 04:59:02 AM UTC 24 |
Oct 12 05:01:05 AM UTC 24 |
3600804900 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3247462142 |
|
|
Oct 12 05:01:06 AM UTC 24 |
Oct 12 05:01:08 AM UTC 24 |
33028210 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.191946933 |
|
|
Oct 12 05:01:09 AM UTC 24 |
Oct 12 05:01:25 AM UTC 24 |
461415454 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3494102554 |
|
|
Oct 12 05:01:26 AM UTC 24 |
Oct 12 05:01:32 AM UTC 24 |
101603850 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_readback_err.3838253670 |
|
|
Oct 12 05:01:33 AM UTC 24 |
Oct 12 05:01:36 AM UTC 24 |
119324880 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.3903336799 |
|
|
Oct 12 04:55:46 AM UTC 24 |
Oct 12 05:01:45 AM UTC 24 |
3946965422 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1583021376 |
|
|
Oct 12 05:01:46 AM UTC 24 |
Oct 12 05:01:48 AM UTC 24 |
14444295 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.4284132950 |
|
|
Oct 12 05:01:50 AM UTC 24 |
Oct 12 05:01:57 AM UTC 24 |
215985214 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.2529242586 |
|
|
Oct 12 05:00:35 AM UTC 24 |
Oct 12 05:02:03 AM UTC 24 |
1305070844 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2631071340 |
|
|
Oct 12 05:02:04 AM UTC 24 |
Oct 12 05:02:36 AM UTC 24 |
464691534 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.4250615232 |
|
|
Oct 12 04:42:51 AM UTC 24 |
Oct 12 05:02:37 AM UTC 24 |
3915644506 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1226242087 |
|
|
Oct 12 05:02:38 AM UTC 24 |
Oct 12 05:02:46 AM UTC 24 |
1066623857 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2637153430 |
|
|
Oct 12 04:56:50 AM UTC 24 |
Oct 12 05:02:51 AM UTC 24 |
94392092914 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1409410443 |
|
|
Oct 12 05:02:51 AM UTC 24 |
Oct 12 05:02:54 AM UTC 24 |
49168144 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2056344572 |
|
|
Oct 12 05:02:56 AM UTC 24 |
Oct 12 05:03:00 AM UTC 24 |
109994902 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.2033102729 |
|
|
Oct 12 05:03:00 AM UTC 24 |
Oct 12 05:03:05 AM UTC 24 |
757533438 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.454316318 |
|
|
Oct 12 04:56:36 AM UTC 24 |
Oct 12 05:03:33 AM UTC 24 |
3641506472 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3562713865 |
|
|
Oct 12 04:53:38 AM UTC 24 |
Oct 12 05:03:39 AM UTC 24 |
3387290440 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3305677810 |
|
|
Oct 12 05:03:40 AM UTC 24 |
Oct 12 05:03:43 AM UTC 24 |
29633918 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.3178228812 |
|
|
Oct 12 04:55:25 AM UTC 24 |
Oct 12 05:03:47 AM UTC 24 |
338830823582 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1472406285 |
|
|
Oct 12 04:58:16 AM UTC 24 |
Oct 12 05:03:53 AM UTC 24 |
7638679313 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_readback_err.1193884891 |
|
|
Oct 12 05:03:54 AM UTC 24 |
Oct 12 05:03:56 AM UTC 24 |
114167108 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.4232723629 |
|
|
Oct 12 05:03:43 AM UTC 24 |
Oct 12 05:03:57 AM UTC 24 |
349362519 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2846268565 |
|
|
Oct 12 05:03:49 AM UTC 24 |
Oct 12 05:03:57 AM UTC 24 |
177993333 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.3418274171 |
|
|
Oct 12 04:28:16 AM UTC 24 |
Oct 12 05:03:59 AM UTC 24 |
37563520702 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.2816858247 |
|
|
Oct 12 04:53:48 AM UTC 24 |
Oct 12 05:04:00 AM UTC 24 |
2688079978 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2694429552 |
|
|
Oct 12 05:03:58 AM UTC 24 |
Oct 12 05:04:00 AM UTC 24 |
19329356 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2656826123 |
|
|
Oct 12 04:58:03 AM UTC 24 |
Oct 12 05:04:07 AM UTC 24 |
5511450888 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.336788692 |
|
|
Oct 12 04:40:51 AM UTC 24 |
Oct 12 05:04:10 AM UTC 24 |
35889028253 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.486989684 |
|
|
Oct 12 05:04:11 AM UTC 24 |
Oct 12 05:04:22 AM UTC 24 |
1300011147 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.1922496510 |
|
|
Oct 12 05:04:01 AM UTC 24 |
Oct 12 05:04:52 AM UTC 24 |
6073734870 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.3097278014 |
|
|
Oct 12 05:04:00 AM UTC 24 |
Oct 12 05:04:52 AM UTC 24 |
2082330055 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.530359889 |
|
|
Oct 12 04:49:01 AM UTC 24 |
Oct 12 05:05:00 AM UTC 24 |
12589743938 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1858615481 |
|
|
Oct 12 05:05:00 AM UTC 24 |
Oct 12 05:05:04 AM UTC 24 |
337290369 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1603019084 |
|
|
Oct 12 04:57:08 AM UTC 24 |
Oct 12 05:05:09 AM UTC 24 |
8292278001 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4096518929 |
|
|
Oct 12 05:04:53 AM UTC 24 |
Oct 12 05:05:19 AM UTC 24 |
88423939 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.598640966 |
|
|
Oct 12 05:05:21 AM UTC 24 |
Oct 12 05:05:23 AM UTC 24 |
45828363 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.2486414716 |
|
|
Oct 12 04:57:54 AM UTC 24 |
Oct 12 05:05:23 AM UTC 24 |
2098239527 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.641416161 |
|
|
Oct 12 05:05:24 AM UTC 24 |
Oct 12 05:05:31 AM UTC 24 |
67812218 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_readback_err.2024301426 |
|
|
Oct 12 05:05:29 AM UTC 24 |
Oct 12 05:05:32 AM UTC 24 |
46362508 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.489883418 |
|
|
Oct 12 05:05:24 AM UTC 24 |
Oct 12 05:05:33 AM UTC 24 |
233552146 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.223363079 |
|
|
Oct 12 05:05:34 AM UTC 24 |
Oct 12 05:05:36 AM UTC 24 |
45473480 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.2044955839 |
|
|
Oct 12 04:57:12 AM UTC 24 |
Oct 12 05:05:38 AM UTC 24 |
32261425890 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3599661482 |
|
|
Oct 12 04:57:24 AM UTC 24 |
Oct 12 05:05:49 AM UTC 24 |
19029532680 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3689902003 |
|
|
Oct 12 05:04:53 AM UTC 24 |
Oct 12 05:05:50 AM UTC 24 |
139471472 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.2210665864 |
|
|
Oct 12 05:05:38 AM UTC 24 |
Oct 12 05:06:01 AM UTC 24 |
312129037 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.168873089 |
|
|
Oct 12 05:06:02 AM UTC 24 |
Oct 12 05:06:09 AM UTC 24 |
158344657 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.988381797 |
|
|
Oct 12 04:41:12 AM UTC 24 |
Oct 12 05:06:27 AM UTC 24 |
49381381022 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1062461284 |
|
|
Oct 12 05:05:32 AM UTC 24 |
Oct 12 05:06:33 AM UTC 24 |
1814766098 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2904067508 |
|
|
Oct 12 05:03:57 AM UTC 24 |
Oct 12 05:06:35 AM UTC 24 |
4365271486 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.3501881226 |
|
|
Oct 12 04:51:13 AM UTC 24 |
Oct 12 05:06:35 AM UTC 24 |
11551997677 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.923926902 |
|
|
Oct 12 05:03:01 AM UTC 24 |
Oct 12 05:06:39 AM UTC 24 |
5619423267 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1427498423 |
|
|
Oct 12 05:06:34 AM UTC 24 |
Oct 12 05:06:40 AM UTC 24 |
418676503 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2759512194 |
|
|
Oct 12 05:06:41 AM UTC 24 |
Oct 12 05:06:43 AM UTC 24 |
47012760 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2916735714 |
|
|
Oct 12 05:06:44 AM UTC 24 |
Oct 12 05:06:55 AM UTC 24 |
301209885 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1173921006 |
|
|
Oct 12 05:06:29 AM UTC 24 |
Oct 12 05:06:59 AM UTC 24 |
101591526 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_readback_err.3922629578 |
|
|
Oct 12 05:07:00 AM UTC 24 |
Oct 12 05:07:02 AM UTC 24 |
55131136 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3236451581 |
|
|
Oct 12 05:06:56 AM UTC 24 |
Oct 12 05:07:05 AM UTC 24 |
819058482 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.633355929 |
|
|
Oct 12 05:00:06 AM UTC 24 |
Oct 12 05:07:05 AM UTC 24 |
13791437738 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3056247650 |
|
|
Oct 12 05:07:06 AM UTC 24 |
Oct 12 05:07:08 AM UTC 24 |
14333580 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.703347188 |
|
|
Oct 12 05:06:36 AM UTC 24 |
Oct 12 05:07:08 AM UTC 24 |
736965823 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.315650355 |
|
|
Oct 12 05:05:50 AM UTC 24 |
Oct 12 05:07:11 AM UTC 24 |
1004273336 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.1256708762 |
|
|
Oct 12 05:07:09 AM UTC 24 |
Oct 12 05:07:13 AM UTC 24 |
326507018 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1566746481 |
|
|
Oct 12 05:00:28 AM UTC 24 |
Oct 12 05:07:15 AM UTC 24 |
19525424007 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3002260229 |
|
|
Oct 12 05:02:47 AM UTC 24 |
Oct 12 05:07:19 AM UTC 24 |
16227983677 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2376691413 |
|
|
Oct 12 05:07:15 AM UTC 24 |
Oct 12 05:07:25 AM UTC 24 |
647900858 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2867857099 |
|
|
Oct 12 04:53:46 AM UTC 24 |
Oct 12 05:07:30 AM UTC 24 |
1830244777 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1074511709 |
|
|
Oct 12 05:07:26 AM UTC 24 |
Oct 12 05:07:48 AM UTC 24 |
284140730 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1486620854 |
|
|
Oct 12 05:06:18 AM UTC 24 |
Oct 12 05:07:52 AM UTC 24 |
539268512 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3374451480 |
|
|
Oct 12 04:58:39 AM UTC 24 |
Oct 12 05:07:59 AM UTC 24 |
10307033256 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2971167729 |
|
|
Oct 12 04:52:29 AM UTC 24 |
Oct 12 05:07:59 AM UTC 24 |
12870466747 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1867276144 |
|
|
Oct 12 05:07:03 AM UTC 24 |
Oct 12 05:08:00 AM UTC 24 |
1626451964 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2776765860 |
|
|
Oct 12 05:07:49 AM UTC 24 |
Oct 12 05:08:03 AM UTC 24 |
1234561463 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1971580244 |
|
|
Oct 12 05:08:02 AM UTC 24 |
Oct 12 05:08:04 AM UTC 24 |
29858251 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.4146246822 |
|
|
Oct 12 05:08:04 AM UTC 24 |
Oct 12 05:08:11 AM UTC 24 |
148918860 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3032373297 |
|
|
Oct 12 05:08:05 AM UTC 24 |
Oct 12 05:08:12 AM UTC 24 |
532461354 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3354689518 |
|
|
Oct 12 05:08:12 AM UTC 24 |
Oct 12 05:08:14 AM UTC 24 |
226892268 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2795912794 |
|
|
Oct 12 05:02:37 AM UTC 24 |
Oct 12 05:08:27 AM UTC 24 |
11583977616 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3055529623 |
|
|
Oct 12 05:08:28 AM UTC 24 |
Oct 12 05:08:30 AM UTC 24 |
43775797 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.4291950971 |
|
|
Oct 12 04:48:52 AM UTC 24 |
Oct 12 05:08:33 AM UTC 24 |
74334910278 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.236823200 |
|
|
Oct 12 05:01:58 AM UTC 24 |
Oct 12 05:08:37 AM UTC 24 |
41571282842 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2223363008 |
|
|
Oct 12 05:07:31 AM UTC 24 |
Oct 12 05:08:51 AM UTC 24 |
456424723 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.2282160689 |
|
|
Oct 12 05:08:31 AM UTC 24 |
Oct 12 05:08:52 AM UTC 24 |
653126520 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.1766298474 |
|
|
Oct 12 05:08:53 AM UTC 24 |
Oct 12 05:08:58 AM UTC 24 |
177935575 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3293578191 |
|
|
Oct 12 05:07:11 AM UTC 24 |
Oct 12 05:09:04 AM UTC 24 |
24692053989 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.394704336 |
|
|
Oct 12 04:51:07 AM UTC 24 |
Oct 12 05:09:14 AM UTC 24 |
66222770286 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2538511320 |
|
|
Oct 12 05:08:39 AM UTC 24 |
Oct 12 05:09:15 AM UTC 24 |
1609307926 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2474079045 |
|
|
Oct 12 05:04:07 AM UTC 24 |
Oct 12 05:09:21 AM UTC 24 |
5600171939 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.200709259 |
|
|
Oct 12 05:09:05 AM UTC 24 |
Oct 12 05:09:23 AM UTC 24 |
140458572 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4001709446 |
|
|
Oct 12 05:09:16 AM UTC 24 |
Oct 12 05:09:29 AM UTC 24 |
1149136872 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.3744148105 |
|
|
Oct 12 04:43:26 AM UTC 24 |
Oct 12 05:09:30 AM UTC 24 |
32878684138 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3565944583 |
|
|
Oct 12 04:44:08 AM UTC 24 |
Oct 12 05:09:32 AM UTC 24 |
86572414036 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.2062691104 |
|
|
Oct 12 04:55:47 AM UTC 24 |
Oct 12 05:09:32 AM UTC 24 |
111307382506 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.710875133 |
|
|
Oct 12 04:56:30 AM UTC 24 |
Oct 12 05:09:33 AM UTC 24 |
20784837141 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.406923129 |
|
|
Oct 12 05:09:32 AM UTC 24 |
Oct 12 05:09:34 AM UTC 24 |
30120298 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_readback_err.1227161281 |
|
|
Oct 12 05:09:34 AM UTC 24 |
Oct 12 05:09:37 AM UTC 24 |
140108755 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1705969324 |
|
|
Oct 12 05:09:33 AM UTC 24 |
Oct 12 05:09:40 AM UTC 24 |
77730862 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.2681200216 |
|
|
Oct 12 05:09:33 AM UTC 24 |
Oct 12 05:09:42 AM UTC 24 |
342665061 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.4056482976 |
|
|
Oct 12 05:09:14 AM UTC 24 |
Oct 12 05:09:42 AM UTC 24 |
349250232 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1238531974 |
|
|
Oct 12 05:09:41 AM UTC 24 |
Oct 12 05:09:44 AM UTC 24 |
17327508 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1244133388 |
|
|
Oct 12 05:04:23 AM UTC 24 |
Oct 12 05:09:45 AM UTC 24 |
12358111729 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.4201476908 |
|
|
Oct 12 05:09:43 AM UTC 24 |
Oct 12 05:09:47 AM UTC 24 |
119589573 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3926466285 |
|
|
Oct 12 05:09:48 AM UTC 24 |
Oct 12 05:10:04 AM UTC 24 |
86973222 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.4175741096 |
|
|
Oct 12 05:07:14 AM UTC 24 |
Oct 12 05:10:12 AM UTC 24 |
3920306336 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4150553834 |
|
|
Oct 12 05:08:13 AM UTC 24 |
Oct 12 05:10:15 AM UTC 24 |
12791683355 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2063352449 |
|
|
Oct 12 05:10:12 AM UTC 24 |
Oct 12 05:10:16 AM UTC 24 |
48124476 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3405397969 |
|
|
Oct 12 04:44:22 AM UTC 24 |
Oct 12 05:10:16 AM UTC 24 |
5176910964 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.2791973842 |
|
|
Oct 12 05:09:45 AM UTC 24 |
Oct 12 05:10:21 AM UTC 24 |
429134190 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.4123223686 |
|
|
Oct 12 05:10:17 AM UTC 24 |
Oct 12 05:10:27 AM UTC 24 |
672442328 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1629436120 |
|
|
Oct 12 05:09:35 AM UTC 24 |
Oct 12 05:10:48 AM UTC 24 |
1257555768 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1013611069 |
|
|
Oct 12 05:10:49 AM UTC 24 |
Oct 12 05:10:51 AM UTC 24 |
28911902 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3068788555 |
|
|
Oct 12 05:10:52 AM UTC 24 |
Oct 12 05:11:04 AM UTC 24 |
137169095 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.448610463 |
|
|
Oct 12 05:07:53 AM UTC 24 |
Oct 12 05:11:09 AM UTC 24 |
1789971406 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_readback_err.3675382747 |
|
|
Oct 12 05:11:10 AM UTC 24 |
Oct 12 05:11:13 AM UTC 24 |
50966071 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.4288768197 |
|
|
Oct 12 05:11:05 AM UTC 24 |
Oct 12 05:11:15 AM UTC 24 |
611533543 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.433666538 |
|
|
Oct 12 05:11:16 AM UTC 24 |
Oct 12 05:11:18 AM UTC 24 |
41714715 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1842859629 |
|
|
Oct 12 05:11:19 AM UTC 24 |
Oct 12 05:11:21 AM UTC 24 |
53879846 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.3179155115 |
|
|
Oct 12 05:00:54 AM UTC 24 |
Oct 12 05:11:23 AM UTC 24 |
10573904746 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.768329137 |
|
|
Oct 12 04:54:59 AM UTC 24 |
Oct 12 05:11:28 AM UTC 24 |
16711071699 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2891120307 |
|
|
Oct 12 05:10:16 AM UTC 24 |
Oct 12 05:11:39 AM UTC 24 |
152533463 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1943355583 |
|
|
Oct 12 05:11:41 AM UTC 24 |
Oct 12 05:11:46 AM UTC 24 |
307090056 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3021173544 |
|
|
Oct 12 05:11:14 AM UTC 24 |
Oct 12 05:11:51 AM UTC 24 |
1364477989 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.472070111 |
|
|
Oct 12 05:05:51 AM UTC 24 |
Oct 12 05:11:56 AM UTC 24 |
13709648179 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2924058821 |
|
|
Oct 12 05:03:06 AM UTC 24 |
Oct 12 05:12:09 AM UTC 24 |
38354775016 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.849462779 |
|
|
Oct 12 05:08:52 AM UTC 24 |
Oct 12 05:12:12 AM UTC 24 |
1922015591 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3313578609 |
|
|
Oct 12 04:39:28 AM UTC 24 |
Oct 12 05:12:13 AM UTC 24 |
68765264025 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.302759830 |
|
|
Oct 12 04:51:06 AM UTC 24 |
Oct 12 05:12:20 AM UTC 24 |
7443394057 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2411678805 |
|
|
Oct 12 05:12:23 AM UTC 24 |
Oct 12 05:12:25 AM UTC 24 |
76325621 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3105523015 |
|
|
Oct 12 05:11:57 AM UTC 24 |
Oct 12 05:12:28 AM UTC 24 |
177584702 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1987220522 |
|
|
Oct 12 05:12:10 AM UTC 24 |
Oct 12 05:12:29 AM UTC 24 |
962983047 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1898473591 |
|
|
Oct 12 05:12:26 AM UTC 24 |
Oct 12 05:12:32 AM UTC 24 |
96553382 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_readback_err.3871548656 |
|
|
Oct 12 05:12:30 AM UTC 24 |
Oct 12 05:12:32 AM UTC 24 |
95686862 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2582111064 |
|
|
Oct 12 05:12:29 AM UTC 24 |
Oct 12 05:12:34 AM UTC 24 |
472795014 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.53653513 |
|
|
Oct 12 05:12:34 AM UTC 24 |
Oct 12 05:12:37 AM UTC 24 |
25870529 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4030240731 |
|
|
Oct 12 05:11:52 AM UTC 24 |
Oct 12 05:12:41 AM UTC 24 |
111383243 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1307294963 |
|
|
Oct 12 05:08:34 AM UTC 24 |
Oct 12 05:12:42 AM UTC 24 |
4184511618 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.661041888 |
|
|
Oct 12 05:12:33 AM UTC 24 |
Oct 12 05:12:55 AM UTC 24 |
477309563 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2941489987 |
|
|
Oct 12 05:12:37 AM UTC 24 |
Oct 12 05:12:57 AM UTC 24 |
216600525 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.55824174 |
|
|
Oct 12 05:11:24 AM UTC 24 |
Oct 12 05:13:21 AM UTC 24 |
4876451827 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2231357351 |
|
|
Oct 12 04:55:41 AM UTC 24 |
Oct 12 05:13:28 AM UTC 24 |
16425640022 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3922691467 |
|
|
Oct 12 04:56:21 AM UTC 24 |
Oct 12 05:13:33 AM UTC 24 |
3735898988 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1444764323 |
|
|
Oct 12 05:05:11 AM UTC 24 |
Oct 12 05:13:37 AM UTC 24 |
10640927059 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.956039602 |
|
|
Oct 12 05:13:39 AM UTC 24 |
Oct 12 05:13:46 AM UTC 24 |
422371693 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.99203982 |
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Oct 12 05:12:58 AM UTC 24 |
Oct 12 05:13:48 AM UTC 24 |
3077072757 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1866848461 |
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Oct 12 05:12:43 AM UTC 24 |
Oct 12 05:13:56 AM UTC 24 |
3467210521 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3557157307 |
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Oct 12 05:13:28 AM UTC 24 |
Oct 12 05:14:02 AM UTC 24 |
99219767 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2410730304 |
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Oct 12 05:14:03 AM UTC 24 |
Oct 12 05:14:05 AM UTC 24 |
36657840 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.283006586 |
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Oct 12 05:14:06 AM UTC 24 |
Oct 12 05:14:15 AM UTC 24 |
897444538 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.1813994187 |
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Oct 12 05:14:16 AM UTC 24 |
Oct 12 05:14:21 AM UTC 24 |
175444210 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.479249246 |
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Oct 12 05:13:57 AM UTC 24 |
Oct 12 05:14:23 AM UTC 24 |
1183768492 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_readback_err.780360188 |
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Oct 12 05:14:22 AM UTC 24 |
Oct 12 05:14:25 AM UTC 24 |
89064684 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1188128478 |
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Oct 12 05:08:59 AM UTC 24 |
Oct 12 05:14:35 AM UTC 24 |
14776678101 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.86271030 |
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Oct 12 05:14:36 AM UTC 24 |
Oct 12 05:14:38 AM UTC 24 |
39985091 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.327175534 |
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Oct 12 05:12:42 AM UTC 24 |
Oct 12 05:14:40 AM UTC 24 |
1557100795 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3969422056 |
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Oct 12 05:06:10 AM UTC 24 |
Oct 12 05:14:49 AM UTC 24 |
20160749644 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2319399574 |
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Oct 12 05:14:24 AM UTC 24 |
Oct 12 05:14:51 AM UTC 24 |
2137817370 ps |