| T789 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.615521156 |
|
|
Oct 12 05:36:11 AM UTC 24 |
Oct 12 05:37:29 AM UTC 24 |
1380751367 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3965711022 |
|
|
Oct 12 05:35:06 AM UTC 24 |
Oct 12 05:37:46 AM UTC 24 |
3717223582 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3512006678 |
|
|
Oct 12 05:37:47 AM UTC 24 |
Oct 12 05:37:49 AM UTC 24 |
31531768 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.4234954094 |
|
|
Oct 12 05:37:51 AM UTC 24 |
Oct 12 05:37:59 AM UTC 24 |
527065547 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.4228600200 |
|
|
Oct 12 05:37:49 AM UTC 24 |
Oct 12 05:38:00 AM UTC 24 |
473884393 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_readback_err.3777166311 |
|
|
Oct 12 05:38:00 AM UTC 24 |
Oct 12 05:38:02 AM UTC 24 |
33778991 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.855025452 |
|
|
Oct 12 05:38:01 AM UTC 24 |
Oct 12 05:38:14 AM UTC 24 |
1047852187 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1232827128 |
|
|
Oct 12 05:38:14 AM UTC 24 |
Oct 12 05:38:16 AM UTC 24 |
44467082 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.1720918844 |
|
|
Oct 12 05:38:17 AM UTC 24 |
Oct 12 05:38:24 AM UTC 24 |
259496438 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3958057590 |
|
|
Oct 12 05:30:16 AM UTC 24 |
Oct 12 05:38:56 AM UTC 24 |
21414507112 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.4151812065 |
|
|
Oct 12 05:33:03 AM UTC 24 |
Oct 12 05:38:56 AM UTC 24 |
25318353448 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1484889986 |
|
|
Oct 12 05:31:35 AM UTC 24 |
Oct 12 05:39:16 AM UTC 24 |
14097677593 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3409906897 |
|
|
Oct 12 05:15:36 AM UTC 24 |
Oct 12 05:39:21 AM UTC 24 |
24655249371 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3886410717 |
|
|
Oct 12 05:38:57 AM UTC 24 |
Oct 12 05:39:21 AM UTC 24 |
6612129756 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.4246252287 |
|
|
Oct 12 05:39:22 AM UTC 24 |
Oct 12 05:39:29 AM UTC 24 |
190081457 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2882991951 |
|
|
Oct 12 05:39:29 AM UTC 24 |
Oct 12 05:39:50 AM UTC 24 |
178197995 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2455734594 |
|
|
Oct 12 05:39:51 AM UTC 24 |
Oct 12 05:40:04 AM UTC 24 |
3553305564 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.658917487 |
|
|
Oct 12 05:34:57 AM UTC 24 |
Oct 12 05:40:39 AM UTC 24 |
10296415609 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1441571164 |
|
|
Oct 12 05:39:17 AM UTC 24 |
Oct 12 05:40:47 AM UTC 24 |
583928669 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1195048993 |
|
|
Oct 12 05:34:45 AM UTC 24 |
Oct 12 05:40:48 AM UTC 24 |
4712204336 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1676624662 |
|
|
Oct 12 05:40:49 AM UTC 24 |
Oct 12 05:40:51 AM UTC 24 |
96502084 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2309005513 |
|
|
Oct 12 05:25:27 AM UTC 24 |
Oct 12 05:40:54 AM UTC 24 |
29486095669 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2112555354 |
|
|
Oct 12 05:40:54 AM UTC 24 |
Oct 12 05:40:59 AM UTC 24 |
112981745 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_readback_err.206671805 |
|
|
Oct 12 05:40:59 AM UTC 24 |
Oct 12 05:41:02 AM UTC 24 |
93003855 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.967065155 |
|
|
Oct 12 05:40:52 AM UTC 24 |
Oct 12 05:41:08 AM UTC 24 |
461909012 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2248884798 |
|
|
Oct 12 05:36:37 AM UTC 24 |
Oct 12 05:41:13 AM UTC 24 |
9219780880 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2697311551 |
|
|
Oct 12 05:41:14 AM UTC 24 |
Oct 12 05:41:16 AM UTC 24 |
36912760 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1749335132 |
|
|
Oct 12 05:30:48 AM UTC 24 |
Oct 12 05:41:30 AM UTC 24 |
5391332484 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.2052034785 |
|
|
Oct 12 05:41:17 AM UTC 24 |
Oct 12 05:41:34 AM UTC 24 |
819071058 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.136993945 |
|
|
Oct 12 05:36:19 AM UTC 24 |
Oct 12 05:41:41 AM UTC 24 |
5786499834 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.434127263 |
|
|
Oct 12 05:37:22 AM UTC 24 |
Oct 12 05:41:44 AM UTC 24 |
2284856211 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.4158361475 |
|
|
Oct 12 04:54:12 AM UTC 24 |
Oct 12 05:41:54 AM UTC 24 |
43899176108 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.363055662 |
|
|
Oct 12 05:09:37 AM UTC 24 |
Oct 12 05:42:40 AM UTC 24 |
34027253857 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1181636884 |
|
|
Oct 12 05:41:34 AM UTC 24 |
Oct 12 05:42:57 AM UTC 24 |
18860726019 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2719590842 |
|
|
Oct 12 05:32:43 AM UTC 24 |
Oct 12 05:42:58 AM UTC 24 |
94565614357 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2454098275 |
|
|
Oct 12 05:41:46 AM UTC 24 |
Oct 12 05:43:09 AM UTC 24 |
1315050223 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.4180208281 |
|
|
Oct 12 05:42:59 AM UTC 24 |
Oct 12 05:43:10 AM UTC 24 |
1117603934 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.578358387 |
|
|
Oct 12 05:42:41 AM UTC 24 |
Oct 12 05:43:13 AM UTC 24 |
138066044 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1531661101 |
|
|
Oct 12 05:42:58 AM UTC 24 |
Oct 12 05:43:14 AM UTC 24 |
78548432 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1797378745 |
|
|
Oct 12 05:43:15 AM UTC 24 |
Oct 12 05:43:17 AM UTC 24 |
153739710 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.1717305717 |
|
|
Oct 12 05:38:57 AM UTC 24 |
Oct 12 05:43:17 AM UTC 24 |
2885618753 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.4140008597 |
|
|
Oct 12 05:14:40 AM UTC 24 |
Oct 12 05:43:19 AM UTC 24 |
62839258241 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_readback_err.702851023 |
|
|
Oct 12 05:43:20 AM UTC 24 |
Oct 12 05:43:23 AM UTC 24 |
158435003 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2772223631 |
|
|
Oct 12 05:32:09 AM UTC 24 |
Oct 12 05:43:23 AM UTC 24 |
6125483113 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2775627768 |
|
|
Oct 12 05:43:18 AM UTC 24 |
Oct 12 05:43:24 AM UTC 24 |
427381998 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2358928719 |
|
|
Oct 12 05:43:25 AM UTC 24 |
Oct 12 05:43:27 AM UTC 24 |
17424034 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.664123164 |
|
|
Oct 12 05:43:18 AM UTC 24 |
Oct 12 05:43:28 AM UTC 24 |
350421006 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1784609522 |
|
|
Oct 12 05:39:22 AM UTC 24 |
Oct 12 05:43:51 AM UTC 24 |
19971536085 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2599290182 |
|
|
Oct 12 05:36:17 AM UTC 24 |
Oct 12 05:44:21 AM UTC 24 |
7338840839 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2740722799 |
|
|
Oct 12 05:43:53 AM UTC 24 |
Oct 12 05:44:33 AM UTC 24 |
2255539850 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.3038544872 |
|
|
Oct 12 05:44:34 AM UTC 24 |
Oct 12 05:44:37 AM UTC 24 |
63885884 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3428439089 |
|
|
Oct 12 05:43:28 AM UTC 24 |
Oct 12 05:44:56 AM UTC 24 |
541526550 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2464877800 |
|
|
Oct 12 05:31:51 AM UTC 24 |
Oct 12 05:44:58 AM UTC 24 |
23231129638 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.4267009891 |
|
|
Oct 12 05:10:22 AM UTC 24 |
Oct 12 05:45:02 AM UTC 24 |
65573519154 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.758648570 |
|
|
Oct 12 05:03:58 AM UTC 24 |
Oct 12 05:45:04 AM UTC 24 |
10002741449 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2251089534 |
|
|
Oct 12 05:45:03 AM UTC 24 |
Oct 12 05:45:07 AM UTC 24 |
950696584 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.736990620 |
|
|
Oct 12 05:27:42 AM UTC 24 |
Oct 12 05:45:25 AM UTC 24 |
33139966317 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3302002552 |
|
|
Oct 12 05:44:57 AM UTC 24 |
Oct 12 05:45:42 AM UTC 24 |
201904182 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2956353418 |
|
|
Oct 12 05:45:42 AM UTC 24 |
Oct 12 05:45:45 AM UTC 24 |
26859643 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.2269403429 |
|
|
Oct 12 05:30:48 AM UTC 24 |
Oct 12 05:45:48 AM UTC 24 |
6676945128 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1768213253 |
|
|
Oct 12 05:45:45 AM UTC 24 |
Oct 12 05:45:51 AM UTC 24 |
78019635 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_readback_err.3493769303 |
|
|
Oct 12 05:45:52 AM UTC 24 |
Oct 12 05:45:55 AM UTC 24 |
54637246 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.853877245 |
|
|
Oct 12 05:45:49 AM UTC 24 |
Oct 12 05:45:58 AM UTC 24 |
200869467 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.4250596407 |
|
|
Oct 12 05:37:30 AM UTC 24 |
Oct 12 05:46:04 AM UTC 24 |
3038605019 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1701247498 |
|
|
Oct 12 05:46:06 AM UTC 24 |
Oct 12 05:46:08 AM UTC 24 |
11450012 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.4114105377 |
|
|
Oct 12 05:41:42 AM UTC 24 |
Oct 12 05:46:23 AM UTC 24 |
5573214653 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2763970038 |
|
|
Oct 12 05:46:09 AM UTC 24 |
Oct 12 05:46:34 AM UTC 24 |
3042819390 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2518681398 |
|
|
Oct 12 05:44:59 AM UTC 24 |
Oct 12 05:46:46 AM UTC 24 |
433301734 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.94531348 |
|
|
Oct 12 05:43:24 AM UTC 24 |
Oct 12 05:46:47 AM UTC 24 |
651378356 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.1366410312 |
|
|
Oct 12 05:46:35 AM UTC 24 |
Oct 12 05:46:57 AM UTC 24 |
899358048 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.2034426817 |
|
|
Oct 12 05:46:48 AM UTC 24 |
Oct 12 05:46:57 AM UTC 24 |
1174325129 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1369669969 |
|
|
Oct 12 05:41:56 AM UTC 24 |
Oct 12 05:46:59 AM UTC 24 |
14567283433 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.886352567 |
|
|
Oct 12 05:22:09 AM UTC 24 |
Oct 12 05:47:22 AM UTC 24 |
5082375518 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.72320538 |
|
|
Oct 12 05:47:00 AM UTC 24 |
Oct 12 05:47:22 AM UTC 24 |
162490238 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1777947537 |
|
|
Oct 12 05:47:23 AM UTC 24 |
Oct 12 05:47:29 AM UTC 24 |
378820699 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1691218812 |
|
|
Oct 12 05:46:58 AM UTC 24 |
Oct 12 05:47:42 AM UTC 24 |
108614460 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1655068505 |
|
|
Oct 12 05:33:01 AM UTC 24 |
Oct 12 05:47:48 AM UTC 24 |
25189423029 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.1364903583 |
|
|
Oct 12 05:47:48 AM UTC 24 |
Oct 12 05:47:50 AM UTC 24 |
122551484 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3150305225 |
|
|
Oct 12 05:45:56 AM UTC 24 |
Oct 12 05:48:02 AM UTC 24 |
2268322401 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.301889135 |
|
|
Oct 12 05:47:51 AM UTC 24 |
Oct 12 05:48:08 AM UTC 24 |
658536953 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1016682 |
|
|
Oct 12 05:48:03 AM UTC 24 |
Oct 12 05:48:10 AM UTC 24 |
342954596 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_readback_err.4030983058 |
|
|
Oct 12 05:48:08 AM UTC 24 |
Oct 12 05:48:10 AM UTC 24 |
109884427 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3208195868 |
|
|
Oct 12 05:48:11 AM UTC 24 |
Oct 12 05:48:13 AM UTC 24 |
38933413 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.4208101405 |
|
|
Oct 12 05:30:00 AM UTC 24 |
Oct 12 05:48:14 AM UTC 24 |
6535658678 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.183677625 |
|
|
Oct 12 05:29:13 AM UTC 24 |
Oct 12 05:48:18 AM UTC 24 |
14073842020 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3986181202 |
|
|
Oct 12 05:48:14 AM UTC 24 |
Oct 12 05:48:27 AM UTC 24 |
1835992640 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.94727618 |
|
|
Oct 12 05:08:15 AM UTC 24 |
Oct 12 05:48:31 AM UTC 24 |
11037380278 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.676571238 |
|
|
Oct 12 05:31:46 AM UTC 24 |
Oct 12 05:48:36 AM UTC 24 |
35939026398 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.885451205 |
|
|
Oct 12 05:41:03 AM UTC 24 |
Oct 12 05:48:45 AM UTC 24 |
5895265034 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2101316536 |
|
|
Oct 12 05:48:32 AM UTC 24 |
Oct 12 05:48:49 AM UTC 24 |
236662692 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.1993535949 |
|
|
Oct 12 05:40:40 AM UTC 24 |
Oct 12 05:48:51 AM UTC 24 |
1942750930 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3726096219 |
|
|
Oct 12 05:48:51 AM UTC 24 |
Oct 12 05:48:54 AM UTC 24 |
259773260 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.309353155 |
|
|
Oct 12 05:46:24 AM UTC 24 |
Oct 12 05:48:57 AM UTC 24 |
490693470 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.1101640606 |
|
|
Oct 12 05:41:30 AM UTC 24 |
Oct 12 05:49:00 AM UTC 24 |
24036423383 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.936292307 |
|
|
Oct 12 05:31:07 AM UTC 24 |
Oct 12 05:49:08 AM UTC 24 |
50050333759 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.893349415 |
|
|
Oct 12 05:49:09 AM UTC 24 |
Oct 12 05:49:11 AM UTC 24 |
49375557 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.469157970 |
|
|
Oct 12 04:33:15 AM UTC 24 |
Oct 12 05:49:20 AM UTC 24 |
761289502160 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3635639881 |
|
|
Oct 12 05:48:50 AM UTC 24 |
Oct 12 05:49:21 AM UTC 24 |
533743724 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1812791567 |
|
|
Oct 12 05:30:49 AM UTC 24 |
Oct 12 05:49:23 AM UTC 24 |
164086560153 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.3351687588 |
|
|
Oct 12 05:47:43 AM UTC 24 |
Oct 12 05:49:25 AM UTC 24 |
1230975582 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_readback_err.3587970512 |
|
|
Oct 12 05:49:22 AM UTC 24 |
Oct 12 05:49:25 AM UTC 24 |
77054757 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2027079101 |
|
|
Oct 12 05:49:12 AM UTC 24 |
Oct 12 05:49:27 AM UTC 24 |
463012299 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3771840870 |
|
|
Oct 12 05:49:26 AM UTC 24 |
Oct 12 05:49:29 AM UTC 24 |
43297894 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.1972143883 |
|
|
Oct 12 05:43:11 AM UTC 24 |
Oct 12 05:49:30 AM UTC 24 |
38776075578 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2682227529 |
|
|
Oct 12 05:49:21 AM UTC 24 |
Oct 12 05:49:31 AM UTC 24 |
414737591 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2677914608 |
|
|
Oct 12 05:40:04 AM UTC 24 |
Oct 12 05:49:34 AM UTC 24 |
1951148835 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1991989665 |
|
|
Oct 12 05:48:09 AM UTC 24 |
Oct 12 05:49:39 AM UTC 24 |
1209937933 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.3898852910 |
|
|
Oct 12 05:49:28 AM UTC 24 |
Oct 12 05:49:43 AM UTC 24 |
3204772699 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3614016312 |
|
|
Oct 12 05:49:34 AM UTC 24 |
Oct 12 05:49:45 AM UTC 24 |
71739543 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3713976808 |
|
|
Oct 12 05:49:40 AM UTC 24 |
Oct 12 05:49:47 AM UTC 24 |
184554913 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.508906899 |
|
|
Oct 12 05:48:46 AM UTC 24 |
Oct 12 05:49:52 AM UTC 24 |
370965530 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3775282850 |
|
|
Oct 12 05:49:44 AM UTC 24 |
Oct 12 05:49:53 AM UTC 24 |
121866081 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.685054148 |
|
|
Oct 12 05:49:46 AM UTC 24 |
Oct 12 05:49:53 AM UTC 24 |
451696243 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3589438716 |
|
|
Oct 12 05:49:54 AM UTC 24 |
Oct 12 05:49:56 AM UTC 24 |
54748632 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3253242002 |
|
|
Oct 12 05:35:54 AM UTC 24 |
Oct 12 05:49:57 AM UTC 24 |
3271163519 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.1958731893 |
|
|
Oct 12 05:48:19 AM UTC 24 |
Oct 12 05:49:59 AM UTC 24 |
3781939596 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_readback_err.1870841752 |
|
|
Oct 12 05:49:59 AM UTC 24 |
Oct 12 05:50:02 AM UTC 24 |
57775779 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1560511645 |
|
|
Oct 12 05:49:58 AM UTC 24 |
Oct 12 05:50:03 AM UTC 24 |
358534236 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.352610008 |
|
|
Oct 12 05:49:57 AM UTC 24 |
Oct 12 05:50:07 AM UTC 24 |
305217546 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.146608617 |
|
|
Oct 12 05:50:08 AM UTC 24 |
Oct 12 05:50:10 AM UTC 24 |
18970167 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2497921770 |
|
|
Oct 12 05:44:22 AM UTC 24 |
Oct 12 05:50:17 AM UTC 24 |
3122370921 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1389865948 |
|
|
Oct 12 05:49:31 AM UTC 24 |
Oct 12 05:50:17 AM UTC 24 |
2247406471 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.2399024227 |
|
|
Oct 12 05:50:11 AM UTC 24 |
Oct 12 05:50:21 AM UTC 24 |
67516548 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3536846779 |
|
|
Oct 12 05:33:02 AM UTC 24 |
Oct 12 05:50:23 AM UTC 24 |
37375824272 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2941913029 |
|
|
Oct 12 05:48:55 AM UTC 24 |
Oct 12 05:50:28 AM UTC 24 |
1757506609 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2671503614 |
|
|
Oct 12 05:50:24 AM UTC 24 |
Oct 12 05:50:32 AM UTC 24 |
920268379 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2471149213 |
|
|
Oct 12 05:49:24 AM UTC 24 |
Oct 12 05:50:42 AM UTC 24 |
1865733971 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3856779182 |
|
|
Oct 12 05:45:26 AM UTC 24 |
Oct 12 05:50:43 AM UTC 24 |
13117558942 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2144334224 |
|
|
Oct 12 05:50:44 AM UTC 24 |
Oct 12 05:50:49 AM UTC 24 |
705683464 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1291681821 |
|
|
Oct 12 05:43:29 AM UTC 24 |
Oct 12 05:50:51 AM UTC 24 |
7529683856 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.3375567933 |
|
|
Oct 12 05:28:57 AM UTC 24 |
Oct 12 05:50:55 AM UTC 24 |
38317968308 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.4070963755 |
|
|
Oct 12 05:23:53 AM UTC 24 |
Oct 12 05:51:04 AM UTC 24 |
121782340494 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.194625537 |
|
|
Oct 12 05:51:04 AM UTC 24 |
Oct 12 05:51:07 AM UTC 24 |
91088275 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.166234070 |
|
|
Oct 12 05:18:23 AM UTC 24 |
Oct 12 05:51:10 AM UTC 24 |
20533136102 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.625126739 |
|
|
Oct 12 05:50:50 AM UTC 24 |
Oct 12 05:51:18 AM UTC 24 |
384696710 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1103158598 |
|
|
Oct 12 05:51:11 AM UTC 24 |
Oct 12 05:51:18 AM UTC 24 |
392961630 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.574601499 |
|
|
Oct 12 05:50:18 AM UTC 24 |
Oct 12 05:51:19 AM UTC 24 |
2318755922 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3770233933 |
|
|
Oct 12 05:51:08 AM UTC 24 |
Oct 12 05:51:21 AM UTC 24 |
184308873 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_readback_err.2429139401 |
|
|
Oct 12 05:51:19 AM UTC 24 |
Oct 12 05:51:21 AM UTC 24 |
141482058 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3674903081 |
|
|
Oct 12 05:51:21 AM UTC 24 |
Oct 12 05:51:23 AM UTC 24 |
23603138 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2325293910 |
|
|
Oct 12 05:38:25 AM UTC 24 |
Oct 12 05:51:27 AM UTC 24 |
15097579893 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2964743091 |
|
|
Oct 12 05:50:33 AM UTC 24 |
Oct 12 05:51:29 AM UTC 24 |
512403405 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2323123859 |
|
|
Oct 12 05:44:38 AM UTC 24 |
Oct 12 05:51:57 AM UTC 24 |
4554372974 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3953728330 |
|
|
Oct 12 05:50:43 AM UTC 24 |
Oct 12 05:52:27 AM UTC 24 |
309646889 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.1145792082 |
|
|
Oct 12 05:46:46 AM UTC 24 |
Oct 12 05:52:51 AM UTC 24 |
3788127257 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1932741235 |
|
|
Oct 12 05:51:19 AM UTC 24 |
Oct 12 05:53:07 AM UTC 24 |
1826716688 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.2674770314 |
|
|
Oct 12 05:28:04 AM UTC 24 |
Oct 12 05:53:16 AM UTC 24 |
265463827811 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.101442212 |
|
|
Oct 12 05:14:26 AM UTC 24 |
Oct 12 05:53:16 AM UTC 24 |
35320965758 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3457532637 |
|
|
Oct 12 05:40:48 AM UTC 24 |
Oct 12 05:53:17 AM UTC 24 |
9972821006 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.1827527469 |
|
|
Oct 12 05:48:58 AM UTC 24 |
Oct 12 05:53:18 AM UTC 24 |
8639628097 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2122159554 |
|
|
Oct 12 05:49:32 AM UTC 24 |
Oct 12 05:53:58 AM UTC 24 |
5023428925 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3351761147 |
|
|
Oct 12 05:29:52 AM UTC 24 |
Oct 12 05:54:02 AM UTC 24 |
67036993816 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3679057490 |
|
|
Oct 12 05:48:37 AM UTC 24 |
Oct 12 05:54:25 AM UTC 24 |
12646351854 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3462228945 |
|
|
Oct 12 05:38:03 AM UTC 24 |
Oct 12 05:54:27 AM UTC 24 |
19620329726 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.3570958301 |
|
|
Oct 12 05:35:55 AM UTC 24 |
Oct 12 05:54:40 AM UTC 24 |
3093171449 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3397517510 |
|
|
Oct 12 05:27:42 AM UTC 24 |
Oct 12 05:54:46 AM UTC 24 |
76070405002 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3123475933 |
|
|
Oct 12 05:50:22 AM UTC 24 |
Oct 12 05:54:50 AM UTC 24 |
2491564145 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.2593528490 |
|
|
Oct 12 05:35:56 AM UTC 24 |
Oct 12 05:55:00 AM UTC 24 |
3539829391 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.18899449 |
|
|
Oct 12 05:46:58 AM UTC 24 |
Oct 12 05:55:01 AM UTC 24 |
29776301611 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3393156832 |
|
|
Oct 12 05:37:29 AM UTC 24 |
Oct 12 05:55:07 AM UTC 24 |
32493606560 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2164654311 |
|
|
Oct 12 05:49:36 AM UTC 24 |
Oct 12 05:55:09 AM UTC 24 |
84576157135 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3365600413 |
|
|
Oct 12 05:48:28 AM UTC 24 |
Oct 12 05:55:09 AM UTC 24 |
21690415902 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2348683992 |
|
|
Oct 12 05:07:06 AM UTC 24 |
Oct 12 05:55:10 AM UTC 24 |
132127831906 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4026873644 |
|
|
Oct 12 05:50:17 AM UTC 24 |
Oct 12 05:55:36 AM UTC 24 |
7768187720 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.461136623 |
|
|
Oct 12 05:43:15 AM UTC 24 |
Oct 12 05:55:37 AM UTC 24 |
29151962266 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1532124462 |
|
|
Oct 12 05:49:53 AM UTC 24 |
Oct 12 05:55:39 AM UTC 24 |
10154920850 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1007347409 |
|
|
Oct 12 05:50:29 AM UTC 24 |
Oct 12 05:56:17 AM UTC 24 |
12416262856 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2252952318 |
|
|
Oct 12 05:49:01 AM UTC 24 |
Oct 12 05:56:58 AM UTC 24 |
1258093991 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3735177703 |
|
|
Oct 12 04:45:53 AM UTC 24 |
Oct 12 05:57:28 AM UTC 24 |
776549274565 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.563088288 |
|
|
Oct 12 05:47:23 AM UTC 24 |
Oct 12 05:58:39 AM UTC 24 |
2478905370 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3329070098 |
|
|
Oct 12 05:41:09 AM UTC 24 |
Oct 12 05:59:28 AM UTC 24 |
16384568007 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3905012385 |
|
|
Oct 12 05:49:30 AM UTC 24 |
Oct 12 05:59:56 AM UTC 24 |
35248534418 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.160761222 |
|
|
Oct 12 05:48:15 AM UTC 24 |
Oct 12 06:00:19 AM UTC 24 |
14760511766 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.1568260754 |
|
|
Oct 12 05:50:55 AM UTC 24 |
Oct 12 06:00:51 AM UTC 24 |
51555656132 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.419330820 |
|
|
Oct 12 05:31:46 AM UTC 24 |
Oct 12 06:01:13 AM UTC 24 |
4168486768 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.171615903 |
|
|
Oct 12 05:49:53 AM UTC 24 |
Oct 12 06:01:52 AM UTC 24 |
10054504298 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.2061675724 |
|
|
Oct 12 05:45:08 AM UTC 24 |
Oct 12 06:02:38 AM UTC 24 |
15011297937 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2725018719 |
|
|
Oct 12 05:45:05 AM UTC 24 |
Oct 12 06:02:42 AM UTC 24 |
3456693964 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.3156070504 |
|
|
Oct 12 05:05:33 AM UTC 24 |
Oct 12 06:02:47 AM UTC 24 |
67570334444 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.2068748357 |
|
|
Oct 12 05:49:48 AM UTC 24 |
Oct 12 06:05:09 AM UTC 24 |
30938261929 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1282983007 |
|
|
Oct 12 05:43:10 AM UTC 24 |
Oct 12 06:05:52 AM UTC 24 |
28736838157 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.2191844958 |
|
|
Oct 12 05:47:30 AM UTC 24 |
Oct 12 06:06:00 AM UTC 24 |
19209943036 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3637704377 |
|
|
Oct 12 05:45:59 AM UTC 24 |
Oct 12 06:06:20 AM UTC 24 |
37100969903 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3187967483 |
|
|
Oct 12 05:20:11 AM UTC 24 |
Oct 12 06:07:33 AM UTC 24 |
36832644846 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2250877870 |
|
|
Oct 12 04:37:06 AM UTC 24 |
Oct 12 06:08:24 AM UTC 24 |
135246899826 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.3669625234 |
|
|
Oct 12 05:50:52 AM UTC 24 |
Oct 12 06:09:13 AM UTC 24 |
49666461677 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.637505520 |
|
|
Oct 12 05:36:12 AM UTC 24 |
Oct 12 06:09:54 AM UTC 24 |
126170324842 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2444156707 |
|
|
Oct 12 04:59:42 AM UTC 24 |
Oct 12 06:12:52 AM UTC 24 |
54169684964 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1885832446 |
|
|
Oct 12 05:43:24 AM UTC 24 |
Oct 12 06:14:29 AM UTC 24 |
32396083250 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.637482770 |
|
|
Oct 12 05:26:15 AM UTC 24 |
Oct 12 06:14:34 AM UTC 24 |
141405844135 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.3758639870 |
|
|
Oct 12 05:34:16 AM UTC 24 |
Oct 12 06:14:51 AM UTC 24 |
234523263214 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3697931358 |
|
|
Oct 12 05:24:12 AM UTC 24 |
Oct 12 06:15:20 AM UTC 24 |
36283913828 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.218364165 |
|
|
Oct 12 05:11:15 AM UTC 24 |
Oct 12 06:18:18 AM UTC 24 |
80075943144 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1418906321 |
|
|
Oct 12 05:01:36 AM UTC 24 |
Oct 12 06:20:00 AM UTC 24 |
51280577148 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.4179807439 |
|
|
Oct 12 05:31:01 AM UTC 24 |
Oct 12 06:24:25 AM UTC 24 |
214331681048 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1253848509 |
|
|
Oct 12 05:51:20 AM UTC 24 |
Oct 12 06:26:54 AM UTC 24 |
9449252938 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1311760576 |
|
|
Oct 12 05:48:11 AM UTC 24 |
Oct 12 06:33:45 AM UTC 24 |
12648174894 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2530747297 |
|
|
Oct 12 05:50:05 AM UTC 24 |
Oct 12 06:40:20 AM UTC 24 |
212371484077 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.4213247001 |
|
|
Oct 12 05:49:25 AM UTC 24 |
Oct 12 06:45:51 AM UTC 24 |
51662291104 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3629404536 |
|
|
Oct 12 05:51:24 AM UTC 24 |
Oct 12 05:51:28 AM UTC 24 |
59613868 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2438582139 |
|
|
Oct 12 05:51:22 AM UTC 24 |
Oct 12 05:51:29 AM UTC 24 |
615253243 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1710384530 |
|
|
Oct 12 05:51:30 AM UTC 24 |
Oct 12 05:51:32 AM UTC 24 |
44362185 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1441552820 |
|
|
Oct 12 05:51:30 AM UTC 24 |
Oct 12 05:51:32 AM UTC 24 |
16219009 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4230808996 |
|
|
Oct 12 05:51:30 AM UTC 24 |
Oct 12 05:51:33 AM UTC 24 |
367646756 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3089535293 |
|
|
Oct 12 05:51:28 AM UTC 24 |
Oct 12 05:51:33 AM UTC 24 |
755956354 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1906429869 |
|
|
Oct 12 05:51:33 AM UTC 24 |
Oct 12 05:51:35 AM UTC 24 |
79454540 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1262218999 |
|
|
Oct 12 05:51:33 AM UTC 24 |
Oct 12 05:51:35 AM UTC 24 |
20305394 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3456367804 |
|
|
Oct 12 05:51:34 AM UTC 24 |
Oct 12 05:51:38 AM UTC 24 |
136604384 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.507571073 |
|
|
Oct 12 05:51:36 AM UTC 24 |
Oct 12 05:51:40 AM UTC 24 |
602432452 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1762089701 |
|
|
Oct 12 05:51:38 AM UTC 24 |
Oct 12 05:51:40 AM UTC 24 |
32954991 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3307968405 |
|
|
Oct 12 05:51:34 AM UTC 24 |
Oct 12 05:51:41 AM UTC 24 |
1726638525 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.9912409 |
|
|
Oct 12 05:51:36 AM UTC 24 |
Oct 12 05:51:42 AM UTC 24 |
58844314 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.65954097 |
|
|
Oct 12 05:51:41 AM UTC 24 |
Oct 12 05:51:42 AM UTC 24 |
39343679 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2833804339 |
|
|
Oct 12 05:51:42 AM UTC 24 |
Oct 12 05:51:44 AM UTC 24 |
47035564 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2939732684 |
|
|
Oct 12 05:51:42 AM UTC 24 |
Oct 12 05:51:44 AM UTC 24 |
256215455 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3737261621 |
|
|
Oct 12 05:51:43 AM UTC 24 |
Oct 12 05:51:45 AM UTC 24 |
35033405 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2162585509 |
|
|
Oct 12 05:51:43 AM UTC 24 |
Oct 12 05:51:46 AM UTC 24 |
203467922 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1817082610 |
|
|
Oct 12 05:51:46 AM UTC 24 |
Oct 12 05:51:48 AM UTC 24 |
42519087 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1546248065 |
|
|
Oct 12 05:51:46 AM UTC 24 |
Oct 12 05:51:50 AM UTC 24 |
347260866 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1981751237 |
|
|
Oct 12 05:51:44 AM UTC 24 |
Oct 12 05:51:50 AM UTC 24 |
450079797 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2729812242 |
|
|
Oct 12 05:51:50 AM UTC 24 |
Oct 12 05:51:52 AM UTC 24 |
13400114 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3993129908 |
|
|
Oct 12 05:51:51 AM UTC 24 |
Oct 12 05:51:54 AM UTC 24 |
468786645 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.227975214 |
|
|
Oct 12 05:51:52 AM UTC 24 |
Oct 12 05:51:54 AM UTC 24 |
16090851 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4137488009 |
|
|
Oct 12 05:51:45 AM UTC 24 |
Oct 12 05:51:55 AM UTC 24 |
159138372 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.913179183 |
|
|
Oct 12 05:51:53 AM UTC 24 |
Oct 12 05:51:55 AM UTC 24 |
59904604 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.111869926 |
|
|
Oct 12 05:52:28 AM UTC 24 |
Oct 12 05:52:31 AM UTC 24 |
25358630 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3307430513 |
|
|
Oct 12 05:51:55 AM UTC 24 |
Oct 12 05:51:59 AM UTC 24 |
2995791895 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.847564162 |
|
|
Oct 12 05:51:56 AM UTC 24 |
Oct 12 05:51:59 AM UTC 24 |
264510484 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2682036716 |
|
|
Oct 12 05:51:58 AM UTC 24 |
Oct 12 05:52:00 AM UTC 24 |
15119185 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3518885778 |
|
|
Oct 12 05:51:56 AM UTC 24 |
Oct 12 05:52:00 AM UTC 24 |
52839647 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1915790314 |
|
|
Oct 12 05:52:00 AM UTC 24 |
Oct 12 05:52:02 AM UTC 24 |
18450692 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2140664107 |
|
|
Oct 12 05:52:00 AM UTC 24 |
Oct 12 05:52:02 AM UTC 24 |
69816699 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2631861253 |
|
|
Oct 12 05:52:01 AM UTC 24 |
Oct 12 05:52:03 AM UTC 24 |
47902486 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1965093526 |
|
|
Oct 12 05:52:00 AM UTC 24 |
Oct 12 05:52:03 AM UTC 24 |
44863667 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4103997087 |
|
|
Oct 12 05:52:01 AM UTC 24 |
Oct 12 05:52:04 AM UTC 24 |
68264550 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4239096171 |
|
|
Oct 12 05:52:02 AM UTC 24 |
Oct 12 05:52:06 AM UTC 24 |
30862809 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.741240918 |
|
|
Oct 12 05:52:05 AM UTC 24 |
Oct 12 05:52:07 AM UTC 24 |
22096489 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3653961729 |
|
|
Oct 12 05:52:05 AM UTC 24 |
Oct 12 05:52:07 AM UTC 24 |
39901137 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3357468365 |
|
|
Oct 12 05:52:02 AM UTC 24 |
Oct 12 05:52:09 AM UTC 24 |
480606474 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.441912547 |
|
|
Oct 12 05:52:07 AM UTC 24 |
Oct 12 05:52:09 AM UTC 24 |
32475529 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1770792837 |
|
|
Oct 12 05:52:07 AM UTC 24 |
Oct 12 05:52:09 AM UTC 24 |
48607645 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1710982873 |
|
|
Oct 12 05:52:05 AM UTC 24 |
Oct 12 05:52:10 AM UTC 24 |
945315128 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.981844074 |
|
|
Oct 12 05:52:07 AM UTC 24 |
Oct 12 05:52:10 AM UTC 24 |
323705819 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1463353675 |
|
|
Oct 12 05:52:11 AM UTC 24 |
Oct 12 05:52:13 AM UTC 24 |
14993761 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3738707878 |
|
|
Oct 12 05:52:09 AM UTC 24 |
Oct 12 05:52:14 AM UTC 24 |
131109260 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2177856139 |
|
|
Oct 12 05:52:11 AM UTC 24 |
Oct 12 05:52:14 AM UTC 24 |
116031003 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2600231682 |
|
|
Oct 12 05:52:12 AM UTC 24 |
Oct 12 05:52:14 AM UTC 24 |
24588395 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4183541122 |
|
|
Oct 12 05:52:11 AM UTC 24 |
Oct 12 05:52:15 AM UTC 24 |
96146468 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.759738534 |
|
|
Oct 12 05:52:11 AM UTC 24 |
Oct 12 05:52:17 AM UTC 24 |
793836123 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.159424803 |
|
|
Oct 12 05:52:15 AM UTC 24 |
Oct 12 05:52:18 AM UTC 24 |
185891432 ps |