| T542 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.671560371 |
|
|
Oct 12 05:05:03 AM UTC 24 |
Oct 12 05:14:52 AM UTC 24 |
3854703678 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1993916306 |
|
|
Oct 12 04:26:05 AM UTC 24 |
Oct 12 05:15:01 AM UTC 24 |
8542719940 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3706648289 |
|
|
Oct 12 05:14:54 AM UTC 24 |
Oct 12 05:15:02 AM UTC 24 |
1636989353 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2186994977 |
|
|
Oct 12 05:13:33 AM UTC 24 |
Oct 12 05:15:10 AM UTC 24 |
611129374 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.881706687 |
|
|
Oct 12 05:09:21 AM UTC 24 |
Oct 12 05:15:13 AM UTC 24 |
2084306616 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.660388939 |
|
|
Oct 12 05:07:20 AM UTC 24 |
Oct 12 05:15:17 AM UTC 24 |
69496130676 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.856071024 |
|
|
Oct 12 05:14:49 AM UTC 24 |
Oct 12 05:15:21 AM UTC 24 |
4584697567 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3177014112 |
|
|
Oct 12 05:15:14 AM UTC 24 |
Oct 12 05:15:21 AM UTC 24 |
446437153 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.570381256 |
|
|
Oct 12 05:15:03 AM UTC 24 |
Oct 12 05:15:28 AM UTC 24 |
504602265 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1763674737 |
|
|
Oct 12 05:09:46 AM UTC 24 |
Oct 12 05:15:28 AM UTC 24 |
2868369315 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.1149722295 |
|
|
Oct 12 05:14:39 AM UTC 24 |
Oct 12 05:15:28 AM UTC 24 |
944629238 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1407103295 |
|
|
Oct 12 05:15:28 AM UTC 24 |
Oct 12 05:15:31 AM UTC 24 |
34395053 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2713346404 |
|
|
Oct 12 05:11:28 AM UTC 24 |
Oct 12 05:15:32 AM UTC 24 |
4278867397 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_readback_err.4177740918 |
|
|
Oct 12 05:15:32 AM UTC 24 |
Oct 12 05:15:35 AM UTC 24 |
59103171 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2242246811 |
|
|
Oct 12 05:15:30 AM UTC 24 |
Oct 12 05:15:35 AM UTC 24 |
186175347 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3687616319 |
|
|
Oct 12 05:07:59 AM UTC 24 |
Oct 12 05:15:36 AM UTC 24 |
8807809821 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2672338982 |
|
|
Oct 12 05:15:30 AM UTC 24 |
Oct 12 05:15:36 AM UTC 24 |
74608106 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.120674308 |
|
|
Oct 12 05:15:36 AM UTC 24 |
Oct 12 05:15:38 AM UTC 24 |
20006474 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.1740791342 |
|
|
Oct 12 05:15:37 AM UTC 24 |
Oct 12 05:15:41 AM UTC 24 |
191338803 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.1960509091 |
|
|
Oct 12 05:05:39 AM UTC 24 |
Oct 12 05:15:57 AM UTC 24 |
42131897366 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3796248501 |
|
|
Oct 12 05:15:58 AM UTC 24 |
Oct 12 05:16:01 AM UTC 24 |
65181614 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.486000981 |
|
|
Oct 12 05:00:46 AM UTC 24 |
Oct 12 05:16:04 AM UTC 24 |
3972021233 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.665806762 |
|
|
Oct 12 05:15:39 AM UTC 24 |
Oct 12 05:16:06 AM UTC 24 |
6137782114 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1383560344 |
|
|
Oct 12 05:15:11 AM UTC 24 |
Oct 12 05:16:16 AM UTC 24 |
273249152 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3808604077 |
|
|
Oct 12 05:09:44 AM UTC 24 |
Oct 12 05:16:20 AM UTC 24 |
1948406681 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3361470812 |
|
|
Oct 12 05:15:21 AM UTC 24 |
Oct 12 05:16:28 AM UTC 24 |
6898391999 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2575665170 |
|
|
Oct 12 05:16:16 AM UTC 24 |
Oct 12 05:16:30 AM UTC 24 |
840356160 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1532175088 |
|
|
Oct 12 05:03:34 AM UTC 24 |
Oct 12 05:16:36 AM UTC 24 |
11117635948 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3762009215 |
|
|
Oct 12 05:16:37 AM UTC 24 |
Oct 12 05:16:40 AM UTC 24 |
50196703 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3110365398 |
|
|
Oct 12 05:04:01 AM UTC 24 |
Oct 12 05:16:42 AM UTC 24 |
14690829706 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.282699686 |
|
|
Oct 12 05:10:04 AM UTC 24 |
Oct 12 05:16:47 AM UTC 24 |
14284936286 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1427527583 |
|
|
Oct 12 05:16:40 AM UTC 24 |
Oct 12 05:16:48 AM UTC 24 |
506820392 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1040018092 |
|
|
Oct 12 05:16:43 AM UTC 24 |
Oct 12 05:16:49 AM UTC 24 |
67111214 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_readback_err.595526712 |
|
|
Oct 12 05:16:48 AM UTC 24 |
Oct 12 05:16:51 AM UTC 24 |
90419269 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1981757119 |
|
|
Oct 12 05:16:51 AM UTC 24 |
Oct 12 05:16:54 AM UTC 24 |
45309611 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.2242037254 |
|
|
Oct 12 05:12:56 AM UTC 24 |
Oct 12 05:16:55 AM UTC 24 |
7593079988 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.104787031 |
|
|
Oct 12 04:59:47 AM UTC 24 |
Oct 12 05:16:59 AM UTC 24 |
70159978503 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.412191451 |
|
|
Oct 12 05:16:05 AM UTC 24 |
Oct 12 05:17:05 AM UTC 24 |
434254247 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2458794823 |
|
|
Oct 12 05:16:55 AM UTC 24 |
Oct 12 05:17:10 AM UTC 24 |
195698789 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.473269384 |
|
|
Oct 12 05:07:09 AM UTC 24 |
Oct 12 05:17:16 AM UTC 24 |
11265232816 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3433160556 |
|
|
Oct 12 05:17:10 AM UTC 24 |
Oct 12 05:17:29 AM UTC 24 |
311824739 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.870709952 |
|
|
Oct 12 05:13:22 AM UTC 24 |
Oct 12 05:17:41 AM UTC 24 |
9639418218 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3413392937 |
|
|
Oct 12 05:17:42 AM UTC 24 |
Oct 12 05:17:49 AM UTC 24 |
84656149 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1885520467 |
|
|
Oct 12 05:16:07 AM UTC 24 |
Oct 12 05:17:49 AM UTC 24 |
381898253 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3428085092 |
|
|
Oct 12 05:17:50 AM UTC 24 |
Oct 12 05:17:54 AM UTC 24 |
239160021 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2515202222 |
|
|
Oct 12 05:16:48 AM UTC 24 |
Oct 12 05:17:59 AM UTC 24 |
24394255738 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2709830514 |
|
|
Oct 12 05:15:33 AM UTC 24 |
Oct 12 05:18:01 AM UTC 24 |
1610674397 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1280918959 |
|
|
Oct 12 05:18:01 AM UTC 24 |
Oct 12 05:18:04 AM UTC 24 |
63125151 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2664005166 |
|
|
Oct 12 05:18:04 AM UTC 24 |
Oct 12 05:18:12 AM UTC 24 |
77814062 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.2778648570 |
|
|
Oct 12 05:18:13 AM UTC 24 |
Oct 12 05:18:19 AM UTC 24 |
97127740 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.1757765670 |
|
|
Oct 12 05:17:55 AM UTC 24 |
Oct 12 05:18:20 AM UTC 24 |
567325902 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_readback_err.2749458897 |
|
|
Oct 12 05:18:20 AM UTC 24 |
Oct 12 05:18:22 AM UTC 24 |
30698287 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3261755389 |
|
|
Oct 12 05:17:00 AM UTC 24 |
Oct 12 05:18:24 AM UTC 24 |
8662634869 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.800780786 |
|
|
Oct 12 05:18:24 AM UTC 24 |
Oct 12 05:18:26 AM UTC 24 |
39115760 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3390835600 |
|
|
Oct 12 05:05:04 AM UTC 24 |
Oct 12 05:18:40 AM UTC 24 |
79603603269 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.747935086 |
|
|
Oct 12 05:17:30 AM UTC 24 |
Oct 12 05:18:49 AM UTC 24 |
536712726 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.2014300093 |
|
|
Oct 12 05:18:27 AM UTC 24 |
Oct 12 05:18:54 AM UTC 24 |
1098132814 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.224220563 |
|
|
Oct 12 05:09:31 AM UTC 24 |
Oct 12 05:19:22 AM UTC 24 |
37206566734 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.783959388 |
|
|
Oct 12 05:11:47 AM UTC 24 |
Oct 12 05:19:26 AM UTC 24 |
21671800123 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2859458974 |
|
|
Oct 12 05:19:23 AM UTC 24 |
Oct 12 05:19:26 AM UTC 24 |
272697635 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1072449797 |
|
|
Oct 12 05:06:36 AM UTC 24 |
Oct 12 05:19:38 AM UTC 24 |
25712986067 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2368821897 |
|
|
Oct 12 05:14:51 AM UTC 24 |
Oct 12 05:19:48 AM UTC 24 |
3048170232 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3686612891 |
|
|
Oct 12 05:19:38 AM UTC 24 |
Oct 12 05:19:50 AM UTC 24 |
249982553 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.4234059280 |
|
|
Oct 12 05:19:27 AM UTC 24 |
Oct 12 05:19:57 AM UTC 24 |
360945053 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3696276131 |
|
|
Oct 12 05:19:49 AM UTC 24 |
Oct 12 05:19:59 AM UTC 24 |
624494105 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.73609836 |
|
|
Oct 12 05:20:00 AM UTC 24 |
Oct 12 05:20:02 AM UTC 24 |
122109827 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.2039844071 |
|
|
Oct 12 05:00:51 AM UTC 24 |
Oct 12 05:20:05 AM UTC 24 |
14365827962 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1725849468 |
|
|
Oct 12 05:18:50 AM UTC 24 |
Oct 12 05:20:07 AM UTC 24 |
59481445705 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.3309320889 |
|
|
Oct 12 05:07:59 AM UTC 24 |
Oct 12 05:20:09 AM UTC 24 |
12813649876 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_readback_err.93991865 |
|
|
Oct 12 05:20:07 AM UTC 24 |
Oct 12 05:20:10 AM UTC 24 |
29506196 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1639706175 |
|
|
Oct 12 05:20:03 AM UTC 24 |
Oct 12 05:20:12 AM UTC 24 |
372366936 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1131070801 |
|
|
Oct 12 05:20:06 AM UTC 24 |
Oct 12 05:20:12 AM UTC 24 |
1410980875 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.1556793954 |
|
|
Oct 12 05:18:00 AM UTC 24 |
Oct 12 05:20:14 AM UTC 24 |
3429487402 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.46084649 |
|
|
Oct 12 05:20:13 AM UTC 24 |
Oct 12 05:20:15 AM UTC 24 |
35084644 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1051155131 |
|
|
Oct 12 05:20:13 AM UTC 24 |
Oct 12 05:20:29 AM UTC 24 |
1634698671 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1122786827 |
|
|
Oct 12 05:15:43 AM UTC 24 |
Oct 12 05:20:42 AM UTC 24 |
3150656772 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.3062767920 |
|
|
Oct 12 05:20:16 AM UTC 24 |
Oct 12 05:21:15 AM UTC 24 |
2817408510 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2624877387 |
|
|
Oct 12 05:20:43 AM UTC 24 |
Oct 12 05:21:22 AM UTC 24 |
264603926 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.140746301 |
|
|
Oct 12 05:09:24 AM UTC 24 |
Oct 12 05:21:58 AM UTC 24 |
13703962833 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2864745743 |
|
|
Oct 12 05:21:59 AM UTC 24 |
Oct 12 05:22:05 AM UTC 24 |
136097268 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1966561130 |
|
|
Oct 12 05:18:55 AM UTC 24 |
Oct 12 05:22:08 AM UTC 24 |
8646880886 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.4226171555 |
|
|
Oct 12 05:21:23 AM UTC 24 |
Oct 12 05:22:16 AM UTC 24 |
340471291 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1023785357 |
|
|
Oct 12 05:17:06 AM UTC 24 |
Oct 12 05:22:19 AM UTC 24 |
6366696420 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3136986353 |
|
|
Oct 12 05:22:06 AM UTC 24 |
Oct 12 05:22:21 AM UTC 24 |
2611278015 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.339480087 |
|
|
Oct 12 05:22:22 AM UTC 24 |
Oct 12 05:22:24 AM UTC 24 |
156355760 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2303630283 |
|
|
Oct 12 05:16:29 AM UTC 24 |
Oct 12 05:22:25 AM UTC 24 |
3826056384 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.500045538 |
|
|
Oct 12 05:22:26 AM UTC 24 |
Oct 12 05:22:31 AM UTC 24 |
88931801 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3797177498 |
|
|
Oct 12 05:22:25 AM UTC 24 |
Oct 12 05:22:34 AM UTC 24 |
309510696 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1755972471 |
|
|
Oct 12 05:17:16 AM UTC 24 |
Oct 12 05:22:35 AM UTC 24 |
6829467150 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_readback_err.1118918337 |
|
|
Oct 12 05:22:32 AM UTC 24 |
Oct 12 05:22:35 AM UTC 24 |
126872246 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.326621557 |
|
|
Oct 12 05:22:36 AM UTC 24 |
Oct 12 05:22:39 AM UTC 24 |
11166039 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2542956057 |
|
|
Oct 12 04:49:47 AM UTC 24 |
Oct 12 05:22:47 AM UTC 24 |
48320996346 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.476550134 |
|
|
Oct 12 04:52:19 AM UTC 24 |
Oct 12 05:22:57 AM UTC 24 |
23817080514 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.2537685720 |
|
|
Oct 12 05:22:40 AM UTC 24 |
Oct 12 05:23:22 AM UTC 24 |
510659991 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.555472180 |
|
|
Oct 12 05:22:48 AM UTC 24 |
Oct 12 05:23:31 AM UTC 24 |
874610829 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3099089483 |
|
|
Oct 12 05:20:10 AM UTC 24 |
Oct 12 05:23:33 AM UTC 24 |
7212935719 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1788046730 |
|
|
Oct 12 05:15:02 AM UTC 24 |
Oct 12 05:23:33 AM UTC 24 |
54046718398 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.671710134 |
|
|
Oct 12 05:23:32 AM UTC 24 |
Oct 12 05:23:35 AM UTC 24 |
45053416 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2666815288 |
|
|
Oct 12 05:19:52 AM UTC 24 |
Oct 12 05:23:38 AM UTC 24 |
3934966574 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1449238034 |
|
|
Oct 12 05:23:35 AM UTC 24 |
Oct 12 05:23:42 AM UTC 24 |
202950012 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.4001468483 |
|
|
Oct 12 05:23:39 AM UTC 24 |
Oct 12 05:23:43 AM UTC 24 |
1029114558 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2339775699 |
|
|
Oct 12 05:22:35 AM UTC 24 |
Oct 12 05:23:52 AM UTC 24 |
791186504 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3234089479 |
|
|
Oct 12 05:16:02 AM UTC 24 |
Oct 12 05:23:55 AM UTC 24 |
21908975334 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1430072177 |
|
|
Oct 12 05:23:56 AM UTC 24 |
Oct 12 05:23:58 AM UTC 24 |
112676925 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.4005922265 |
|
|
Oct 12 04:57:27 AM UTC 24 |
Oct 12 05:23:59 AM UTC 24 |
5432832167 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1984917048 |
|
|
Oct 12 05:24:00 AM UTC 24 |
Oct 12 05:24:08 AM UTC 24 |
66779706 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_readback_err.1230839171 |
|
|
Oct 12 05:24:08 AM UTC 24 |
Oct 12 05:24:11 AM UTC 24 |
33165261 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2992382500 |
|
|
Oct 12 05:15:17 AM UTC 24 |
Oct 12 05:24:11 AM UTC 24 |
9765096507 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.2693520514 |
|
|
Oct 12 05:24:12 AM UTC 24 |
Oct 12 05:24:14 AM UTC 24 |
27574842 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.515631006 |
|
|
Oct 12 05:23:59 AM UTC 24 |
Oct 12 05:24:17 AM UTC 24 |
458910288 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3911702219 |
|
|
Oct 12 05:23:34 AM UTC 24 |
Oct 12 05:24:22 AM UTC 24 |
220003651 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.700482367 |
|
|
Oct 12 05:22:58 AM UTC 24 |
Oct 12 05:24:25 AM UTC 24 |
2911795251 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.124212965 |
|
|
Oct 12 05:10:28 AM UTC 24 |
Oct 12 05:24:30 AM UTC 24 |
11052802905 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3614637725 |
|
|
Oct 12 05:24:32 AM UTC 24 |
Oct 12 05:24:37 AM UTC 24 |
208326718 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.1035533540 |
|
|
Oct 12 05:24:15 AM UTC 24 |
Oct 12 05:24:41 AM UTC 24 |
85612567 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.977615629 |
|
|
Oct 12 05:24:12 AM UTC 24 |
Oct 12 05:25:14 AM UTC 24 |
3522167668 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2888717270 |
|
|
Oct 12 05:16:57 AM UTC 24 |
Oct 12 05:25:19 AM UTC 24 |
26218970481 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2193011442 |
|
|
Oct 12 05:25:15 AM UTC 24 |
Oct 12 05:25:26 AM UTC 24 |
625082227 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.3343981891 |
|
|
Oct 12 05:24:22 AM UTC 24 |
Oct 12 05:25:27 AM UTC 24 |
4238477684 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.782756955 |
|
|
Oct 12 05:20:30 AM UTC 24 |
Oct 12 05:25:30 AM UTC 24 |
25388817839 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.853113551 |
|
|
Oct 12 05:25:31 AM UTC 24 |
Oct 12 05:25:33 AM UTC 24 |
33725390 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.988481637 |
|
|
Oct 12 05:25:34 AM UTC 24 |
Oct 12 05:25:46 AM UTC 24 |
143414865 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3118042392 |
|
|
Oct 12 05:25:47 AM UTC 24 |
Oct 12 05:25:55 AM UTC 24 |
176460954 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_readback_err.466224028 |
|
|
Oct 12 05:25:56 AM UTC 24 |
Oct 12 05:25:59 AM UTC 24 |
33112215 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.558829312 |
|
|
Oct 12 05:25:15 AM UTC 24 |
Oct 12 05:26:15 AM UTC 24 |
474213941 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.1747544583 |
|
|
Oct 12 05:16:31 AM UTC 24 |
Oct 12 05:26:16 AM UTC 24 |
2815655094 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.4079439249 |
|
|
Oct 12 05:26:18 AM UTC 24 |
Oct 12 05:26:20 AM UTC 24 |
11883508 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.1117472162 |
|
|
Oct 12 05:26:21 AM UTC 24 |
Oct 12 05:26:26 AM UTC 24 |
335024640 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2509428566 |
|
|
Oct 12 05:24:42 AM UTC 24 |
Oct 12 05:26:30 AM UTC 24 |
146729308 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3868924803 |
|
|
Oct 12 05:22:17 AM UTC 24 |
Oct 12 05:26:37 AM UTC 24 |
8859514835 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3502981596 |
|
|
Oct 12 05:25:19 AM UTC 24 |
Oct 12 05:26:45 AM UTC 24 |
871620812 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.2912796752 |
|
|
Oct 12 05:23:44 AM UTC 24 |
Oct 12 05:27:03 AM UTC 24 |
4043097792 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1583947813 |
|
|
Oct 12 05:26:46 AM UTC 24 |
Oct 12 05:27:05 AM UTC 24 |
1986377844 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.1976428072 |
|
|
Oct 12 05:12:20 AM UTC 24 |
Oct 12 05:27:26 AM UTC 24 |
2931832186 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1925551733 |
|
|
Oct 12 05:10:18 AM UTC 24 |
Oct 12 05:27:32 AM UTC 24 |
9428066086 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.357613233 |
|
|
Oct 12 05:26:31 AM UTC 24 |
Oct 12 05:27:35 AM UTC 24 |
1226724908 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2158255746 |
|
|
Oct 12 05:18:42 AM UTC 24 |
Oct 12 05:27:42 AM UTC 24 |
2362792880 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.827436714 |
|
|
Oct 12 05:15:37 AM UTC 24 |
Oct 12 05:27:42 AM UTC 24 |
2948624696 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1358155055 |
|
|
Oct 12 05:27:33 AM UTC 24 |
Oct 12 05:27:42 AM UTC 24 |
518712696 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1267741974 |
|
|
Oct 12 05:27:43 AM UTC 24 |
Oct 12 05:27:46 AM UTC 24 |
35068546 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.270417157 |
|
|
Oct 12 05:12:33 AM UTC 24 |
Oct 12 05:27:52 AM UTC 24 |
101902306604 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1466797621 |
|
|
Oct 12 05:27:47 AM UTC 24 |
Oct 12 05:27:57 AM UTC 24 |
465109227 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_readback_err.4007929065 |
|
|
Oct 12 05:27:58 AM UTC 24 |
Oct 12 05:28:01 AM UTC 24 |
38270396 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2953639872 |
|
|
Oct 12 05:27:53 AM UTC 24 |
Oct 12 05:28:03 AM UTC 24 |
300813423 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3437920904 |
|
|
Oct 12 05:27:27 AM UTC 24 |
Oct 12 05:28:04 AM UTC 24 |
120824606 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.964712055 |
|
|
Oct 12 05:28:05 AM UTC 24 |
Oct 12 05:28:07 AM UTC 24 |
18335326 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.2735848948 |
|
|
Oct 12 05:17:50 AM UTC 24 |
Oct 12 05:28:13 AM UTC 24 |
4881900558 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2923993695 |
|
|
Oct 12 05:27:07 AM UTC 24 |
Oct 12 05:28:16 AM UTC 24 |
461854300 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1119956490 |
|
|
Oct 12 05:23:34 AM UTC 24 |
Oct 12 05:28:20 AM UTC 24 |
8002099846 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.4271755369 |
|
|
Oct 12 05:23:23 AM UTC 24 |
Oct 12 05:28:21 AM UTC 24 |
18734969793 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.3302826840 |
|
|
Oct 12 05:28:08 AM UTC 24 |
Oct 12 05:28:22 AM UTC 24 |
164526509 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3069729858 |
|
|
Oct 12 05:24:26 AM UTC 24 |
Oct 12 05:28:44 AM UTC 24 |
4526604263 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3261353034 |
|
|
Oct 12 05:27:36 AM UTC 24 |
Oct 12 05:28:48 AM UTC 24 |
891317993 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3757556468 |
|
|
Oct 12 05:19:26 AM UTC 24 |
Oct 12 05:28:49 AM UTC 24 |
226436509969 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1380642607 |
|
|
Oct 12 05:28:51 AM UTC 24 |
Oct 12 05:28:56 AM UTC 24 |
417966450 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1013743150 |
|
|
Oct 12 05:20:15 AM UTC 24 |
Oct 12 05:29:07 AM UTC 24 |
65372443401 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2708232899 |
|
|
Oct 12 05:22:21 AM UTC 24 |
Oct 12 05:29:12 AM UTC 24 |
1634417950 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1331572933 |
|
|
Oct 12 05:28:44 AM UTC 24 |
Oct 12 05:29:40 AM UTC 24 |
130193446 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2126495063 |
|
|
Oct 12 05:29:41 AM UTC 24 |
Oct 12 05:29:43 AM UTC 24 |
164921431 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1087295683 |
|
|
Oct 12 05:28:17 AM UTC 24 |
Oct 12 05:29:44 AM UTC 24 |
10228393175 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1182340514 |
|
|
Oct 12 05:26:37 AM UTC 24 |
Oct 12 05:29:47 AM UTC 24 |
7646220888 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_readback_err.692240983 |
|
|
Oct 12 05:29:49 AM UTC 24 |
Oct 12 05:29:51 AM UTC 24 |
35031366 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1326092506 |
|
|
Oct 12 05:29:45 AM UTC 24 |
Oct 12 05:29:51 AM UTC 24 |
1121971383 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.1695184622 |
|
|
Oct 12 05:13:49 AM UTC 24 |
Oct 12 05:29:56 AM UTC 24 |
69275081545 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3103972102 |
|
|
Oct 12 05:29:57 AM UTC 24 |
Oct 12 05:29:59 AM UTC 24 |
25501927 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3939845897 |
|
|
Oct 12 05:29:44 AM UTC 24 |
Oct 12 05:29:59 AM UTC 24 |
922153421 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.559229084 |
|
|
Oct 12 05:23:43 AM UTC 24 |
Oct 12 05:30:01 AM UTC 24 |
7282918814 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3022173620 |
|
|
Oct 12 05:28:22 AM UTC 24 |
Oct 12 05:30:05 AM UTC 24 |
1284833380 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2728723439 |
|
|
Oct 12 05:30:00 AM UTC 24 |
Oct 12 05:30:15 AM UTC 24 |
528598946 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1037220417 |
|
|
Oct 12 05:28:49 AM UTC 24 |
Oct 12 05:30:24 AM UTC 24 |
146683837 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2792129934 |
|
|
Oct 12 05:30:25 AM UTC 24 |
Oct 12 05:30:27 AM UTC 24 |
130468406 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.980425967 |
|
|
Oct 12 05:30:14 AM UTC 24 |
Oct 12 05:30:31 AM UTC 24 |
1906324207 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3813637188 |
|
|
Oct 12 05:30:32 AM UTC 24 |
Oct 12 05:30:47 AM UTC 24 |
1413621034 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3161720509 |
|
|
Oct 12 05:16:20 AM UTC 24 |
Oct 12 05:30:47 AM UTC 24 |
38890466089 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2993024200 |
|
|
Oct 12 05:30:02 AM UTC 24 |
Oct 12 05:30:49 AM UTC 24 |
3666016025 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1789816223 |
|
|
Oct 12 05:12:13 AM UTC 24 |
Oct 12 05:30:51 AM UTC 24 |
8757608913 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.1570079542 |
|
|
Oct 12 05:25:29 AM UTC 24 |
Oct 12 05:30:53 AM UTC 24 |
1771836958 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.3815344087 |
|
|
Oct 12 05:30:52 AM UTC 24 |
Oct 12 05:30:54 AM UTC 24 |
87344625 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.1440442100 |
|
|
Oct 12 05:12:14 AM UTC 24 |
Oct 12 05:30:56 AM UTC 24 |
18345457897 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_readback_err.3669195535 |
|
|
Oct 12 05:30:57 AM UTC 24 |
Oct 12 05:31:00 AM UTC 24 |
50735827 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2845521417 |
|
|
Oct 12 05:30:55 AM UTC 24 |
Oct 12 05:31:00 AM UTC 24 |
60547145 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4026785568 |
|
|
Oct 12 05:29:52 AM UTC 24 |
Oct 12 05:31:02 AM UTC 24 |
6147009481 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.4178534615 |
|
|
Oct 12 05:30:54 AM UTC 24 |
Oct 12 05:31:03 AM UTC 24 |
659829522 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.4269669518 |
|
|
Oct 12 05:31:04 AM UTC 24 |
Oct 12 05:31:06 AM UTC 24 |
35152245 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.1514247713 |
|
|
Oct 12 05:06:40 AM UTC 24 |
Oct 12 05:31:14 AM UTC 24 |
16454148721 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3393417622 |
|
|
Oct 12 05:24:38 AM UTC 24 |
Oct 12 05:31:24 AM UTC 24 |
16362598920 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2720501282 |
|
|
Oct 12 05:19:57 AM UTC 24 |
Oct 12 05:31:31 AM UTC 24 |
61916470588 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.963439750 |
|
|
Oct 12 05:30:28 AM UTC 24 |
Oct 12 05:31:34 AM UTC 24 |
144003434 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.475668732 |
|
|
Oct 12 05:31:04 AM UTC 24 |
Oct 12 05:31:37 AM UTC 24 |
655723658 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.35057814 |
|
|
Oct 12 05:15:21 AM UTC 24 |
Oct 12 05:31:38 AM UTC 24 |
11767947975 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3862326582 |
|
|
Oct 12 05:26:27 AM UTC 24 |
Oct 12 05:31:38 AM UTC 24 |
1026394631 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3961265841 |
|
|
Oct 12 05:31:39 AM UTC 24 |
Oct 12 05:31:45 AM UTC 24 |
423449853 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1371787471 |
|
|
Oct 12 05:31:39 AM UTC 24 |
Oct 12 05:31:45 AM UTC 24 |
103159317 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3118315538 |
|
|
Oct 12 05:16:49 AM UTC 24 |
Oct 12 05:31:50 AM UTC 24 |
17744909797 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1167038614 |
|
|
Oct 12 05:31:32 AM UTC 24 |
Oct 12 05:31:56 AM UTC 24 |
3013027115 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1512307408 |
|
|
Oct 12 05:31:56 AM UTC 24 |
Oct 12 05:31:58 AM UTC 24 |
28519407 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3581992301 |
|
|
Oct 12 05:29:08 AM UTC 24 |
Oct 12 05:32:01 AM UTC 24 |
2022065660 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1750965221 |
|
|
Oct 12 05:24:17 AM UTC 24 |
Oct 12 05:32:04 AM UTC 24 |
38397829608 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3840728533 |
|
|
Oct 12 05:32:05 AM UTC 24 |
Oct 12 05:32:08 AM UTC 24 |
99138660 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1663718833 |
|
|
Oct 12 05:28:21 AM UTC 24 |
Oct 12 05:32:08 AM UTC 24 |
4385874148 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2067752571 |
|
|
Oct 12 05:32:02 AM UTC 24 |
Oct 12 05:32:08 AM UTC 24 |
220176880 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3439353279 |
|
|
Oct 12 05:21:16 AM UTC 24 |
Oct 12 05:32:08 AM UTC 24 |
25151963214 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1443913148 |
|
|
Oct 12 05:31:59 AM UTC 24 |
Oct 12 05:32:10 AM UTC 24 |
4134990903 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3184970184 |
|
|
Oct 12 05:32:09 AM UTC 24 |
Oct 12 05:32:11 AM UTC 24 |
59130892 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.2179357611 |
|
|
Oct 12 05:31:15 AM UTC 24 |
Oct 12 05:32:33 AM UTC 24 |
9927074537 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.467866652 |
|
|
Oct 12 05:27:04 AM UTC 24 |
Oct 12 05:32:35 AM UTC 24 |
112098047148 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1223376153 |
|
|
Oct 12 05:32:12 AM UTC 24 |
Oct 12 05:32:41 AM UTC 24 |
362373365 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.4292673359 |
|
|
Oct 12 05:31:37 AM UTC 24 |
Oct 12 05:32:43 AM UTC 24 |
314902702 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3157672334 |
|
|
Oct 12 05:32:09 AM UTC 24 |
Oct 12 05:32:52 AM UTC 24 |
117544010 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2041625899 |
|
|
Oct 12 05:32:44 AM UTC 24 |
Oct 12 05:32:54 AM UTC 24 |
92495582 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2033593379 |
|
|
Oct 12 05:32:55 AM UTC 24 |
Oct 12 05:33:01 AM UTC 24 |
1036591804 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2872100559 |
|
|
Oct 12 05:32:36 AM UTC 24 |
Oct 12 05:33:01 AM UTC 24 |
2392508192 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.681315801 |
|
|
Oct 12 05:32:53 AM UTC 24 |
Oct 12 05:33:03 AM UTC 24 |
84453229 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.3536772841 |
|
|
Oct 12 05:22:36 AM UTC 24 |
Oct 12 05:33:26 AM UTC 24 |
17078736634 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.224207215 |
|
|
Oct 12 05:33:28 AM UTC 24 |
Oct 12 05:33:30 AM UTC 24 |
44597920 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.270374845 |
|
|
Oct 12 05:33:31 AM UTC 24 |
Oct 12 05:33:48 AM UTC 24 |
2371235454 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1166565993 |
|
|
Oct 12 05:33:49 AM UTC 24 |
Oct 12 05:33:54 AM UTC 24 |
47566189 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_readback_err.630111590 |
|
|
Oct 12 05:33:54 AM UTC 24 |
Oct 12 05:33:56 AM UTC 24 |
37014491 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3781359062 |
|
|
Oct 12 05:32:09 AM UTC 24 |
Oct 12 05:34:16 AM UTC 24 |
4743734545 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2118359342 |
|
|
Oct 12 05:19:58 AM UTC 24 |
Oct 12 05:34:34 AM UTC 24 |
27673605390 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.834848512 |
|
|
Oct 12 05:34:36 AM UTC 24 |
Oct 12 05:34:38 AM UTC 24 |
20173806 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.4208583218 |
|
|
Oct 12 05:34:39 AM UTC 24 |
Oct 12 05:34:44 AM UTC 24 |
142386119 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3929126676 |
|
|
Oct 12 05:31:25 AM UTC 24 |
Oct 12 05:34:50 AM UTC 24 |
8627816215 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1342797538 |
|
|
Oct 12 05:31:00 AM UTC 24 |
Oct 12 05:34:56 AM UTC 24 |
2128315321 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2067551218 |
|
|
Oct 12 05:30:05 AM UTC 24 |
Oct 12 05:35:00 AM UTC 24 |
10627278219 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3458010996 |
|
|
Oct 12 05:35:01 AM UTC 24 |
Oct 12 05:35:05 AM UTC 24 |
52282129 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2877448382 |
|
|
Oct 12 05:13:47 AM UTC 24 |
Oct 12 05:35:21 AM UTC 24 |
14543794073 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3469441395 |
|
|
Oct 12 05:32:11 AM UTC 24 |
Oct 12 05:35:33 AM UTC 24 |
1001249378 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2006873987 |
|
|
Oct 12 05:28:02 AM UTC 24 |
Oct 12 05:35:51 AM UTC 24 |
2942202258 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1100824587 |
|
|
Oct 12 05:28:23 AM UTC 24 |
Oct 12 05:35:53 AM UTC 24 |
15610778053 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.574113757 |
|
|
Oct 12 05:33:57 AM UTC 24 |
Oct 12 05:35:54 AM UTC 24 |
4955736012 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.885374232 |
|
|
Oct 12 05:34:51 AM UTC 24 |
Oct 12 05:35:55 AM UTC 24 |
4139561250 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.776227662 |
|
|
Oct 12 05:25:59 AM UTC 24 |
Oct 12 05:35:57 AM UTC 24 |
14975794872 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3783230038 |
|
|
Oct 12 05:35:58 AM UTC 24 |
Oct 12 05:36:00 AM UTC 24 |
77080020 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.54269134 |
|
|
Oct 12 05:32:33 AM UTC 24 |
Oct 12 05:36:05 AM UTC 24 |
3972088898 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.104133006 |
|
|
Oct 12 05:35:52 AM UTC 24 |
Oct 12 05:36:07 AM UTC 24 |
3358817404 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_readback_err.344066871 |
|
|
Oct 12 05:36:08 AM UTC 24 |
Oct 12 05:36:10 AM UTC 24 |
92362306 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.1098571745 |
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Oct 12 05:35:34 AM UTC 24 |
Oct 12 05:36:11 AM UTC 24 |
215297586 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2596348965 |
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Oct 12 05:35:23 AM UTC 24 |
Oct 12 05:36:13 AM UTC 24 |
424730655 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.3589436941 |
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Oct 12 05:36:01 AM UTC 24 |
Oct 12 05:36:16 AM UTC 24 |
954374435 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.503629147 |
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Oct 12 05:36:06 AM UTC 24 |
Oct 12 05:36:16 AM UTC 24 |
1190267570 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3755255473 |
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Oct 12 05:36:14 AM UTC 24 |
Oct 12 05:36:16 AM UTC 24 |
54928218 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2801380327 |
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Oct 12 05:28:14 AM UTC 24 |
Oct 12 05:36:18 AM UTC 24 |
5722088100 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.4090428789 |
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Oct 12 05:36:17 AM UTC 24 |
Oct 12 05:36:30 AM UTC 24 |
250253526 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.202021391 |
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Oct 12 05:36:32 AM UTC 24 |
Oct 12 05:36:36 AM UTC 24 |
82742178 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1178642510 |
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Oct 12 05:11:22 AM UTC 24 |
Oct 12 05:36:43 AM UTC 24 |
17668226792 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.407491291 |
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Oct 12 05:36:17 AM UTC 24 |
Oct 12 05:37:03 AM UTC 24 |
1307807804 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.3514890739 |
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Oct 12 05:36:44 AM UTC 24 |
Oct 12 05:37:15 AM UTC 24 |
91233389 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.780802664 |
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Oct 12 05:37:04 AM UTC 24 |
Oct 12 05:37:21 AM UTC 24 |
80113768 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2554097536 |
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Oct 12 05:37:15 AM UTC 24 |
Oct 12 05:37:28 AM UTC 24 |
2300608335 ps |