Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T69,T12,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T69,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T69,T12,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T69,T12,T25
1	0	Covered	T34,T35,T36
1	1	Covered	T69,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T69,T12,T25
0	1	Covered	T70,T94,T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T69,T25,T26
0	1	Covered	T69,T12,T25
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T69,T25,T26
1	-	Covered	T69,T12,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T69,T12,T25
0	1	Covered	T69,T12,T25
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T69,T12,T25
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T69,T12,T25
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T69,T12,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T122,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T69,T12,T25
DetectSt	-	-	-	-	1	-	-	Covered	T70,T94,T100
DetectSt	-	-	-	-	0	1	-	Covered	T69,T12,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T69,T12,T25
StableSt	-	-	-	-	-	-	0	Covered	T69,T25,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	286	0	0
CntIncr_A	7945094	289472	0	0
CntNoWrap_A	7945094	7278444	0	0
DetectStDropOut_A	7945094	3	0	0
DetectedOut_A	7945094	848	0	0
DetectedPulseOut_A	7945094	127	0	0
DisabledIdleSt_A	7945094	6982444	0	0
DisabledNoDetection_A	7945094	6984736	0	0
EnterDebounceSt_A	7945094	166	0	0
EnterDetectSt_A	7945094	130	0	0
EnterStableSt_A	7945094	127	0	0
PulseIsPulse_A	7945094	127	0	0
StayInStableSt	7945094	721	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	6963	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	126	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	286	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	3	0	0
T26	678	2	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	2	0	0
T69	697	2	0	0
T83	0	6	0	0
T84	0	4	0	0
T85	0	4	0	0
T86	0	4	0	0
T87	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	289472	0	0
T12	3346	100	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	183	0	0
T26	678	84	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	68	0	0
T69	697	71	0	0
T83	0	190	0	0
T84	0	100	0	0
T85	0	173	0	0
T86	0	134	0	0
T87	0	58217	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278444	0	0
T12	3346	1340	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	311	0	0
T26	678	275	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	294	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	3	0	0
T70	15936	1	0	0
T94	0	1	0	0
T100	0	1	0	0
T107	697	0	0	0
T108	22954	0	0	0
T109	686	0	0	0
T110	678	0	0	0
T111	693	0	0	0
T112	29772	0	0	0
T113	522	0	0	0
T114	715	0	0	0
T115	15724	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	848	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	8	0	0
T26	678	3	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	9	0	0
T69	697	7	0	0
T83	0	24	0	0
T84	0	18	0	0
T85	0	12	0	0
T86	0	7	0	0
T87	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	127	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	1	0	0
T26	678	1	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	1	0	0
T69	697	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6982444	0	0
T12	3346	1197	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	71	0	0
T26	678	140	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	185	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6984736	0	0
T12	3346	1200	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	71	0	0
T26	678	141	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	186	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	166	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	2	0	0
T26	678	1	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	1	0	0
T69	697	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	130	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	1	0	0
T26	678	1	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	1	0	0
T69	697	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	127	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	1	0	0
T26	678	1	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	1	0	0
T69	697	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	127	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	1	0	0
T26	678	1	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	1	0	0
T69	697	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	721	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	7	0	0
T26	678	2	0	0
T27	4565	0	0	0
T28	411	0	0	0
T45	0	9	0	0
T54	0	8	0	0
T69	697	6	0	0
T83	0	21	0	0
T84	0	16	0	0
T85	0	10	0	0
T86	0	5	0	0
T87	0	4	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6963	0	0
T12	3346	8	0	0
T13	11876	33	0	0
T14	0	6	0	0
T24	526	0	0	0
T25	715	3	0	0
T26	678	3	0	0
T27	4565	19	0	0
T34	5421	21	0	0
T35	12415	27	0	0
T36	3492	19	0	0
T69	697	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	126	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	1	0	0
T26	678	1	0	0
T27	4565	0	0	0
T28	411	0	0	0
T54	0	1	0	0
T69	697	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T61,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Unreachable
1	0	Covered	T14,T17,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T18
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T18
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T48,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	1	-	-	Covered	T61,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T18
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	172	0	0
CntIncr_A	7945094	304991	0	0
CntNoWrap_A	7945094	7278558	0	0
DetectStDropOut_A	7945094	15	0	0
DetectedOut_A	7945094	145324	0	0
DetectedPulseOut_A	7945094	47	0	0
DisabledIdleSt_A	7945094	6650157	0	0
DisabledNoDetection_A	7945094	6652513	0	0
EnterDebounceSt_A	7945094	110	0	0
EnterDetectSt_A	7945094	62	0	0
EnterStableSt_A	7945094	47	0	0
PulseIsPulse_A	7945094	47	0	0
StayInStableSt	7945094	145277	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	6963	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_sticky_sva.StableStDropOut_A	7945094	22331	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	172	0	0
T14	1188	4	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	2	0	0
T18	2225	2	0	0
T19	6331	2	0	0
T29	25174	0	0	0
T48	0	6	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	4	0	0
T60	0	2	0	0
T61	0	6	0	0
T62	0	2	0	0
T121	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	304991	0	0
T14	1188	76	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	16	0	0
T18	2225	35	0	0
T19	6331	67	0	0
T29	25174	0	0	0
T48	0	243	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	86	0	0
T60	0	39	0	0
T61	0	200	0	0
T62	0	87	0	0
T121	0	132072	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278558	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	15	0	0
T47	1027	0	0	0
T61	7777	2	0	0
T62	1883	0	0	0
T76	0	3	0	0
T80	0	2	0	0
T81	0	2	0	0
T103	522	0	0	0
T104	505	0	0	0
T105	497	0	0	0
T106	616	0	0	0
T122	26513	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	440	0	0	0
T129	16674	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	145324	0	0
T14	1188	247	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	131	0	0
T18	2225	160	0	0
T19	6331	138	0	0
T29	25174	0	0	0
T48	0	437	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	208	0	0
T60	0	1	0	0
T62	0	484	0	0
T70	0	137	0	0
T75	0	399	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	47	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	1	0	0
T18	2225	1	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T62	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6650157	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6652513	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	110	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	1	0	0
T18	2225	1	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	5	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	4	0	0
T62	0	1	0	0
T121	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	62	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	1	0	0
T18	2225	1	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T70	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	47	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	1	0	0
T18	2225	1	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T62	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	47	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	1	0	0
T18	2225	1	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T62	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	145277	0	0
T14	1188	245	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	130	0	0
T18	2225	159	0	0
T19	6331	137	0	0
T29	25174	0	0	0
T48	0	436	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	206	0	0
T62	0	483	0	0
T70	0	136	0	0
T75	0	398	0	0
T130	0	227	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6963	0	0
T12	3346	8	0	0
T13	11876	33	0	0
T14	0	6	0	0
T24	526	0	0	0
T25	715	3	0	0
T26	678	3	0	0
T27	4565	19	0	0
T34	5421	21	0	0
T35	12415	27	0	0
T36	3492	19	0	0
T69	697	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	22331	0	0
T14	1188	248	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	322	0	0
T18	2225	353	0	0
T19	6331	55	0	0
T29	25174	0	0	0
T48	0	231	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	339	0	0
T60	0	123	0	0
T62	0	383	0	0
T70	0	134	0	0
T75	0	80	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T36,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T36,T12,T13
1	1	Covered	T36,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T19,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T36,T12,T13
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T50
0	1	Covered	T59,T48,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T50
0	1	Unreachable
1	0	Covered	T17,T19,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T19,T59
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T18
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T19,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T18,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	1	-	-	Covered	T59,T48,T79
DetectSt	-	-	-	-	0	1	-	Covered	T17,T19,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T19,T50
StableSt	-	-	-	-	-	-	0	Covered	T17,T19,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	166	0	0
CntIncr_A	7945094	19027	0	0
CntNoWrap_A	7945094	7278564	0	0
DetectStDropOut_A	7945094	10	0	0
DetectedOut_A	7945094	34196	0	0
DetectedPulseOut_A	7945094	43	0	0
DisabledIdleSt_A	7945094	6650157	0	0
DisabledNoDetection_A	7945094	6652513	0	0
EnterDebounceSt_A	7945094	113	0	0
EnterDetectSt_A	7945094	53	0	0
EnterStableSt_A	7945094	43	0	0
PulseIsPulse_A	7945094	43	0	0
StayInStableSt	7945094	34153	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_sticky_sva.StableStDropOut_A	7945094	521534	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	166	0	0
T14	1188	5	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	2	0	0
T18	2225	4	0	0
T19	6331	2	0	0
T29	25174	0	0	0
T48	0	10	0	0
T50	0	2	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	8	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	19027	0	0
T14	1188	245	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	12	0	0
T18	2225	336	0	0
T19	6331	39	0	0
T29	25174	0	0	0
T48	0	317	0	0
T50	0	91	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	210	0	0
T60	0	98	0	0
T61	0	75	0	0
T62	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278564	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	10	0	0
T39	1821	0	0	0
T48	0	4	0	0
T50	9079	0	0	0
T51	1020	0	0	0
T59	1120	3	0	0
T79	0	1	0	0
T82	18777	0	0	0
T131	0	2	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34196	0	0
T17	114965	63	0	0
T18	2225	0	0	0
T19	6331	112	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T48	0	148	0	0
T50	0	54	0	0
T57	422	0	0	0
T58	615	0	0	0
T60	0	30	0	0
T61	0	303	0	0
T62	0	72	0	0
T75	0	316	0	0
T78	0	431	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	820	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	43	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6650157	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6652513	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	113	0	0
T14	1188	5	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	1	0	0
T18	2225	4	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	5	0	0
T50	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	5	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	53	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T48	0	5	0	0
T50	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T78	0	1	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	43	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	43	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34153	0	0
T17	114965	62	0	0
T18	2225	0	0	0
T19	6331	111	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T48	0	147	0	0
T50	0	53	0	0
T57	422	0	0	0
T58	615	0	0	0
T60	0	29	0	0
T61	0	302	0	0
T62	0	71	0	0
T75	0	315	0	0
T78	0	430	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	818	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	521534	0	0
T17	114965	386	0	0
T18	2225	0	0	0
T19	6331	104	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T48	0	531	0	0
T50	0	34	0	0
T57	422	0	0	0
T58	615	0	0	0
T60	0	27	0	0
T61	0	81	0	0
T62	0	861	0	0
T75	0	172	0	0
T78	0	323	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	131198	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T19,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T59
0	1	Covered	T75,T76,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T59
0	1	Unreachable
1	0	Covered	T14,T19,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T19,T59
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T18
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T19,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T18,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	1	-	-	Covered	T75,T76,T77
DetectSt	-	-	-	-	0	1	-	Covered	T14,T19,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T19,T59
StableSt	-	-	-	-	-	-	0	Covered	T14,T19,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	196	0	0
CntIncr_A	7945094	119935	0	0
CntNoWrap_A	7945094	7278534	0	0
DetectStDropOut_A	7945094	21	0	0
DetectedOut_A	7945094	18936	0	0
DetectedPulseOut_A	7945094	47	0	0
DisabledIdleSt_A	7945094	6650157	0	0
DisabledNoDetection_A	7945094	6652513	0	0
EnterDebounceSt_A	7945094	128	0	0
EnterDetectSt_A	7945094	68	0	0
EnterStableSt_A	7945094	47	0	0
PulseIsPulse_A	7945094	47	0	0
StayInStableSt	7945094	18889	0	0
gen_high_event_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_sticky_sva.StableStDropOut_A	7945094	235035	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	196	0	0
T14	1188	4	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	5	0	0
T18	2225	4	0	0
T19	6331	2	0	0
T29	25174	0	0	0
T48	0	7	0	0
T50	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	119935	0	0
T14	1188	116	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	400	0	0
T18	2225	240	0	0
T19	6331	93	0	0
T29	25174	0	0	0
T48	0	439	0	0
T50	0	11	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	200	0	0
T60	0	15	0	0
T61	0	34	0	0
T62	0	324	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278534	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	21	0	0
T75	1023	2	0	0
T76	1228	2	0	0
T77	0	6	0	0
T137	0	2	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	728	0	0	0
T144	12013	0	0	0
T145	503	0	0	0
T146	490	0	0	0
T147	585	0	0	0
T148	502	0	0	0
T149	15745	0	0	0
T150	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	18936	0	0
T14	1188	240	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T19	6331	128	0	0
T29	25174	0	0	0
T48	0	374	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	366	0	0
T60	0	6	0	0
T61	0	226	0	0
T78	0	60	0	0
T80	0	148	0	0
T81	0	153	0	0
T121	0	684	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	47	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6650157	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6652513	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	128	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	5	0	0
T18	2225	4	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	6	0	0
T50	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	68	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	0	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	47	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	47	0	0
T14	1188	2	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T19	6331	1	0	0
T29	25174	0	0	0
T48	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	18889	0	0
T14	1188	238	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T19	6331	127	0	0
T29	25174	0	0	0
T48	0	373	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	364	0	0
T60	0	5	0	0
T61	0	225	0	0
T78	0	59	0	0
T80	0	147	0	0
T81	0	152	0	0
T121	0	682	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	235035	0	0
T14	1188	241	0	0
T15	13088	0	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T19	6331	55	0	0
T29	25174	0	0	0
T48	0	220	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T59	0	85	0	0
T60	0	149	0	0
T61	0	206	0	0
T78	0	765	0	0
T80	0	48	0	0
T81	0	32431	0	0
T121	0	131351	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T51,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T17,T51,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T51,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T17,T51,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T51,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T51,T45
0	1	Covered	T48,T151,T152
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T51,T45
1	-	Covered	T48,T151,T152

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T51,T45
0	1	Covered	T17,T51,T45
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T51,T45
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T51,T45
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T51,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T153,T154,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T51,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T51,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T151,T152
StableSt	-	-	-	-	-	-	0	Covered	T17,T51,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	64	0	0
CntIncr_A	7945094	134659	0	0
CntNoWrap_A	7945094	7278666	0	0
DetectStDropOut_A	7945094	0	0	0
DetectedOut_A	7945094	83061	0	0
DetectedPulseOut_A	7945094	30	0	0
DisabledIdleSt_A	7945094	6829599	0	0
DisabledNoDetection_A	7945094	6831906	0	0
EnterDebounceSt_A	7945094	34	0	0
EnterDetectSt_A	7945094	30	0	0
EnterStableSt_A	7945094	30	0	0
PulseIsPulse_A	7945094	30	0	0
StayInStableSt	7945094	83014	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	64	0	0
T17	114965	2	0	0
T18	2225	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	9079	0	0	0
T51	1020	2	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	4	0	0
T152	0	4	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	134659	0	0
T17	114965	65	0	0
T18	2225	0	0	0
T45	0	23	0	0
T48	0	22	0	0
T49	0	86	0	0
T50	9079	0	0	0
T51	1020	100	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	186	0	0
T152	0	32	0	0
T156	0	61	0	0
T157	0	76	0	0
T158	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278666	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	83061	0	0
T17	114965	168	0	0
T18	2225	0	0	0
T45	0	40	0	0
T48	0	1	0	0
T49	0	47	0	0
T50	9079	0	0	0
T51	1020	368	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	78	0	0
T152	0	104	0	0
T156	0	311	0	0
T157	0	39	0	0
T158	0	66	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	30	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	9079	0	0	0
T51	1020	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6829599	0	0
T12	3346	553	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6831906	0	0
T12	3346	556	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	9079	0	0	0
T51	1020	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	30	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	9079	0	0	0
T51	1020	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	30	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	9079	0	0	0
T51	1020	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	30	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	9079	0	0	0
T51	1020	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	83014	0	0
T17	114965	166	0	0
T18	2225	0	0	0
T45	0	38	0	0
T49	0	45	0	0
T50	9079	0	0	0
T51	1020	366	0	0
T57	422	0	0	0
T58	615	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T151	0	75	0	0
T152	0	102	0	0
T156	0	309	0	0
T157	0	37	0	0
T158	0	65	0	0
T159	0	164	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	12	0	0
T41	37823	0	0	0
T48	20236	1	0	0
T71	26972	0	0	0
T151	1224	1	0	0
T152	0	2	0	0
T158	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	3	0	0
T164	0	1	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T168	721	0	0	0
T169	431	0	0	0
T170	403	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T16
1	0	Covered	T36,T12,T13
1	1	Covered	T12,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T17
0	1	Covered	T50,T48,T162
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T17
0	1	Covered	T12,T17,T51
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T17
1	-	Covered	T12,T17,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T17
0	1	Covered	T12,T16,T17
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T17
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T49,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T17
DetectSt	-	-	-	-	1	-	-	Covered	T50,T48,T162
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T17,T51
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	108	0	0
CntIncr_A	7945094	72188	0	0
CntNoWrap_A	7945094	7278622	0	0
DetectStDropOut_A	7945094	3	0	0
DetectedOut_A	7945094	9896	0	0
DetectedPulseOut_A	7945094	49	0	0
DisabledIdleSt_A	7945094	7002355	0	0
DisabledNoDetection_A	7945094	7004663	0	0
EnterDebounceSt_A	7945094	57	0	0
EnterDetectSt_A	7945094	52	0	0
EnterStableSt_A	7945094	49	0	0
PulseIsPulse_A	7945094	49	0	0
StayInStableSt	7945094	9824	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	2668	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	108	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	2	0	0
T17	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	8	0	0
T46	0	2	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	72188	0	0
T12	3346	22	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	20	0	0
T17	0	65	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	3084	0	0
T46	0	38	0	0
T48	0	40	0	0
T49	0	86	0	0
T50	0	164	0	0
T51	0	100	0	0
T168	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278622	0	0
T12	3346	1338	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	3	0	0
T39	1821	0	0	0
T48	20236	1	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T162	0	1	0	0
T165	982	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	9896	0	0
T12	3346	48	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	58	0	0
T17	0	109	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	381	0	0
T46	0	79	0	0
T48	0	40	0	0
T51	0	42	0	0
T151	0	134	0	0
T168	0	69	0	0
T171	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	49	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T151	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7002355	0	0
T12	3346	1191	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	304	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7004663	0	0
T12	3346	1194	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	310	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	57	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	5	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	52	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	49	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T151	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	49	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T151	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	9824	0	0
T12	3346	45	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	56	0	0
T17	0	108	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	376	0	0
T46	0	77	0	0
T48	0	39	0	0
T51	0	41	0	0
T151	0	132	0	0
T168	0	68	0	0
T171	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2668	0	0
T12	3346	9	0	0
T13	11876	15	0	0
T14	1188	0	0	0
T16	0	1	0	0
T17	0	13	0	0
T19	0	25	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T36	3492	14	0	0
T57	0	4	0	0
T63	0	4	0	0
T69	697	0	0	0
T119	0	7	0	0
T120	0	18	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	25	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	3	0	0
T48	0	1	0	0
T51	0	1	0	0
T151	0	2	0	0
T159	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0