Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T17,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T17,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T17,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T17,T51
1	0	Covered	T34,T35,T36
1	1	Covered	T12,T17,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T17,T51
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T17,T51
0	1	Covered	T51,T45,T48
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T17,T51
1	-	Covered	T51,T45,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T17,T51
0	1	Covered	T12,T17,T51
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T17,T51
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T17,T51
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T17,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T160,T173,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T17,T51
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T17,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T51,T45,T48
StableSt	-	-	-	-	-	-	0	Covered	T12,T17,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	70	0	0
CntIncr_A	7945094	103759	0	0
CntNoWrap_A	7945094	7278660	0	0
DetectStDropOut_A	7945094	0	0	0
DetectedOut_A	7945094	2830	0	0
DetectedPulseOut_A	7945094	33	0	0
DisabledIdleSt_A	7945094	6878583	0	0
DisabledNoDetection_A	7945094	6880893	0	0
EnterDebounceSt_A	7945094	38	0	0
EnterDetectSt_A	7945094	33	0	0
EnterStableSt_A	7945094	33	0	0
PulseIsPulse_A	7945094	33	0	0
StayInStableSt	7945094	2776	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	70	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	8	0	0
T48	0	4	0	0
T49	0	2	0	0
T51	0	2	0	0
T149	0	2	0	0
T151	0	2	0	0
T159	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	103759	0	0
T12	3346	96	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	2071	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	124	0	0
T48	0	44	0	0
T49	0	86	0	0
T51	0	100	0	0
T149	0	75	0	0
T151	0	93	0	0
T159	0	38	0	0
T175	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278660	0	0
T12	3346	1340	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2830	0	0
T12	3346	331	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	41	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	194	0	0
T48	0	85	0	0
T49	0	47	0	0
T51	0	229	0	0
T149	0	42	0	0
T151	0	323	0	0
T159	0	44	0	0
T175	0	128	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	33	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6878583	0	0
T12	3346	553	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6880893	0	0
T12	3346	556	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	38	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	33	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	33	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	33	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	4	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2776	0	0
T12	3346	329	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	39	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	188	0	0
T48	0	82	0	0
T49	0	45	0	0
T51	0	228	0	0
T149	0	41	0	0
T151	0	321	0	0
T159	0	42	0	0
T175	0	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	11	0	0
T39	1821	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T50	9079	0	0	0
T51	1020	1	0	0
T52	31582	0	0	0
T82	18777	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T149	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T17
1	0	Covered	T36,T12,T13
1	1	Covered	T12,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T17
0	1	Covered	T178,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T17
0	1	Covered	T12,T17,T51
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T17
1	-	Covered	T12,T17,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T17
0	1	Covered	T12,T16,T17
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T17
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T172,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T17
DetectSt	-	-	-	-	1	-	-	Covered	T178,T179
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T17,T51
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	98	0	0
CntIncr_A	7945094	35955	0	0
CntNoWrap_A	7945094	7278632	0	0
DetectStDropOut_A	7945094	3	0	0
DetectedOut_A	7945094	3703	0	0
DetectedPulseOut_A	7945094	43	0	0
DisabledIdleSt_A	7945094	7006490	0	0
DisabledNoDetection_A	7945094	7008803	0	0
EnterDebounceSt_A	7945094	52	0	0
EnterDetectSt_A	7945094	46	0	0
EnterStableSt_A	7945094	43	0	0
PulseIsPulse_A	7945094	43	0	0
StayInStableSt	7945094	3643	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	3046	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	98	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	2	0	0
T17	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	7	0	0
T50	0	6	0	0
T51	0	4	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	35955	0	0
T12	3346	96	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	20	0	0
T17	0	65	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	55	0	0
T46	0	38	0	0
T47	0	76	0	0
T48	0	84	0	0
T50	0	96	0	0
T51	0	200	0	0
T78	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278632	0	0
T12	3346	1340	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	3	0	0
T178	536	1	0	0
T179	8142	2	0	0
T181	21065	0	0	0
T182	818	0	0	0
T183	506	0	0	0
T184	8591	0	0	0
T185	423	0	0	0
T186	16798	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	3703	0	0
T12	3346	259	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	37	0	0
T17	0	170	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	176	0	0
T46	0	79	0	0
T47	0	235	0	0
T48	0	119	0	0
T50	0	147	0	0
T51	0	80	0	0
T78	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	43	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0
T78	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7006490	0	0
T12	3346	553	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7008803	0	0
T12	3346	556	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	52	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	4	0	0
T50	0	3	0	0
T51	0	2	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	46	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0
T78	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	43	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0
T78	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	43	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0
T78	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	3643	0	0
T12	3346	258	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	35	0	0
T17	0	169	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	175	0	0
T46	0	77	0	0
T47	0	233	0	0
T48	0	115	0	0
T50	0	143	0	0
T51	0	77	0	0
T78	0	54	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	3046	0	0
T12	3346	7	0	0
T13	11876	13	0	0
T14	1188	0	0	0
T16	0	1	0	0
T17	0	16	0	0
T24	526	2	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T36	3492	16	0	0
T57	0	2	0	0
T58	0	4	0	0
T63	0	6	0	0
T69	697	0	0	0
T118	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	25	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T159	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T17,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T17,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T17,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T17,T50
1	0	Covered	T34,T35,T36
1	1	Covered	T12,T17,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T17,T50
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T17,T50
0	1	Covered	T12,T17,T50
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T17,T50
1	-	Covered	T12,T17,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T17,T50
0	1	Covered	T12,T17,T50
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T17,T50
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T17,T50
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T17,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T175,T188
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T17,T50
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T17,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T17,T50
StableSt	-	-	-	-	-	-	0	Covered	T12,T17,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	141	0	0
CntIncr_A	7945094	187281	0	0
CntNoWrap_A	7945094	7278589	0	0
DetectStDropOut_A	7945094	0	0	0
DetectedOut_A	7945094	6808	0	0
DetectedPulseOut_A	7945094	68	0	0
DisabledIdleSt_A	7945094	6783722	0	0
DisabledNoDetection_A	7945094	6786026	0	0
EnterDebounceSt_A	7945094	75	0	0
EnterDetectSt_A	7945094	68	0	0
EnterStableSt_A	7945094	68	0	0
PulseIsPulse_A	7945094	68	0	0
StayInStableSt	7945094	6711	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	141	0	0
T12	3346	8	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	3	0	0
T47	0	4	0	0
T50	0	6	0	0
T70	0	4	0	0
T107	0	4	0	0
T114	0	4	0	0
T168	0	2	0	0
T175	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	187281	0	0
T12	3346	214	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	65	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	46	0	0
T47	0	152	0	0
T50	0	146	0	0
T70	0	94	0	0
T107	0	48	0	0
T114	0	108	0	0
T168	0	99	0	0
T175	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278589	0	0
T12	3346	1334	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6808	0	0
T12	3346	326	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	236	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	83	0	0
T47	0	190	0	0
T50	0	323	0	0
T70	0	82	0	0
T107	0	85	0	0
T114	0	43	0	0
T168	0	45	0	0
T175	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	68	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T50	0	3	0	0
T70	0	2	0	0
T107	0	2	0	0
T114	0	2	0	0
T168	0	1	0	0
T175	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6783722	0	0
T12	3346	402	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6786026	0	0
T12	3346	404	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	75	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	2	0	0
T47	0	2	0	0
T50	0	3	0	0
T70	0	2	0	0
T107	0	2	0	0
T114	0	2	0	0
T168	0	1	0	0
T175	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	68	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T50	0	3	0	0
T70	0	2	0	0
T107	0	2	0	0
T114	0	2	0	0
T168	0	1	0	0
T175	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	68	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T50	0	3	0	0
T70	0	2	0	0
T107	0	2	0	0
T114	0	2	0	0
T168	0	1	0	0
T175	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	68	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T50	0	3	0	0
T70	0	2	0	0
T107	0	2	0	0
T114	0	2	0	0
T168	0	1	0	0
T175	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6711	0	0
T12	3346	322	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	235	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	82	0	0
T47	0	187	0	0
T50	0	319	0	0
T70	0	79	0	0
T107	0	83	0	0
T114	0	40	0	0
T168	0	43	0	0
T175	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	38	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T70	0	1	0	0
T107	0	2	0	0
T114	0	1	0	0
T175	0	1	0	0
T189	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T50,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T17,T50,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T50,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T17,T51
1	0	Covered	T34,T35,T36
1	1	Covered	T17,T50,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T50,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T50,T45
0	1	Covered	T50,T45,T47
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T50,T45
1	-	Covered	T50,T45,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T50,T45
0	1	Covered	T17,T50,T45
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T50,T45
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T50,T45
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T50,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T160
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T50,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T50,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T50,T45,T47
StableSt	-	-	-	-	-	-	0	Covered	T17,T50,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	82	0	0
CntIncr_A	7945094	101729	0	0
CntNoWrap_A	7945094	7278648	0	0
DetectStDropOut_A	7945094	0	0	0
DetectedOut_A	7945094	2377	0	0
DetectedPulseOut_A	7945094	40	0	0
DisabledIdleSt_A	7945094	6988509	0	0
DisabledNoDetection_A	7945094	6990811	0	0
EnterDebounceSt_A	7945094	42	0	0
EnterDetectSt_A	7945094	40	0	0
EnterStableSt_A	7945094	40	0	0
PulseIsPulse_A	7945094	40	0	0
StayInStableSt	7945094	2318	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	6607	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	82	0	0
T17	114965	2	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	6	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	9079	4	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	4	0	0
T114	0	2	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	4	0	0
T157	0	2	0	0
T175	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	101729	0	0
T17	114965	65	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	69	0	0
T47	0	76	0	0
T48	0	10	0	0
T50	9079	114	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	48	0	0
T114	0	54	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	32	0	0
T157	0	76	0	0
T175	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278648	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2377	0	0
T17	114965	41	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	163	0	0
T47	0	197	0	0
T48	0	45	0	0
T50	9079	152	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	79	0	0
T114	0	99	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	66	0	0
T157	0	39	0	0
T175	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	40	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	9079	2	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	2	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	2	0	0
T157	0	1	0	0
T175	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6988509	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	304	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6990811	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	310	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	42	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	9079	2	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	2	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	2	0	0
T157	0	1	0	0
T175	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	40	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	9079	2	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	2	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	2	0	0
T157	0	1	0	0
T175	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	40	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	9079	2	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	2	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	2	0	0
T157	0	1	0	0
T175	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	40	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	9079	2	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	2	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	2	0	0
T157	0	1	0	0
T175	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2318	0	0
T17	114965	39	0	0
T18	2225	0	0	0
T39	1821	0	0	0
T45	0	159	0	0
T47	0	196	0	0
T48	0	43	0	0
T50	9079	149	0	0
T57	422	0	0	0
T58	615	0	0	0
T107	0	76	0	0
T114	0	98	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T152	0	63	0	0
T157	0	37	0	0
T175	0	100	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6607	0	0
T12	3346	10	0	0
T13	11876	33	0	0
T14	0	6	0	0
T15	0	9	0	0
T17	0	18	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	29	0	0
T29	0	27	0	0
T34	5421	32	0	0
T35	12415	25	0	0
T36	3492	19	0	0
T69	697	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	20	0	0
T39	1821	0	0	0
T45	163943	2	0	0
T47	0	1	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T107	0	1	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T152	0	1	0	0
T160	0	1	0	0
T175	0	2	0	0
T188	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T12,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T51
0	1	Covered	T17,T49,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T51
0	1	Covered	T12,T51,T50
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T51
1	-	Covered	T12,T51,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T17
0	1	Covered	T12,T16,T17
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T17
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T157,T191,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T17
DetectSt	-	-	-	-	1	-	-	Covered	T17,T49,T179
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T51,T50
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	113	0	0
CntIncr_A	7945094	139895	0	0
CntNoWrap_A	7945094	7278617	0	0
DetectStDropOut_A	7945094	4	0	0
DetectedOut_A	7945094	156434	0	0
DetectedPulseOut_A	7945094	50	0	0
DisabledIdleSt_A	7945094	6889968	0	0
DisabledNoDetection_A	7945094	6892271	0	0
EnterDebounceSt_A	7945094	60	0	0
EnterDetectSt_A	7945094	54	0	0
EnterStableSt_A	7945094	50	0	0
PulseIsPulse_A	7945094	50	0	0
StayInStableSt	7945094	156358	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	113	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	2	0	0
T17	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	8	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0
T107	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	139895	0	0
T12	3346	192	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	20	0	0
T17	0	65	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	2895	0	0
T46	0	38	0	0
T47	0	76	0	0
T48	0	84	0	0
T49	0	172	0	0
T50	0	82	0	0
T51	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278617	0	0
T12	3346	1338	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	4	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T49	843	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T179	8142	2	0	0
T186	16798	0	0	0
T193	12684	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	156434	0	0
T12	3346	93	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	59	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T46	0	40	0	0
T47	0	541	0	0
T48	0	256	0	0
T49	0	46	0	0
T50	0	209	0	0
T51	0	228	0	0
T78	0	1	0	0
T107	0	109	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	50	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T78	0	1	0	0
T107	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6889968	0	0
T12	3346	553	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6892271	0	0
T12	3346	556	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	60	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	54	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T107	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	50	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T78	0	1	0	0
T107	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	50	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	4	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T78	0	1	0	0
T107	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	156358	0	0
T12	3346	91	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	57	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T46	0	38	0	0
T47	0	539	0	0
T48	0	250	0	0
T49	0	44	0	0
T50	0	208	0	0
T51	0	227	0	0
T107	0	106	0	0
T171	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	23	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T78	0	1	0	0
T107	0	1	0	0
T151	0	1	0	0
T158	0	1	0	0
T171	0	1	0	0
T189	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T17,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T45,T47
1	0	Covered	T34,T35,T36
1	1	Covered	T17,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T48,T49
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T48,T49
0	1	Covered	T48,T49,T156
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T48,T49
1	-	Covered	T48,T49,T156

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T48,T49
0	1	Covered	T17,T48,T49
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T48,T49
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T194
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T48,T49
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T48,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T49,T156
StableSt	-	-	-	-	-	-	0	Covered	T17,T48,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	42	0	0
CntIncr_A	7945094	34263	0	0
CntNoWrap_A	7945094	7278688	0	0
DetectStDropOut_A	7945094	0	0	0
DetectedOut_A	7945094	1541	0	0
DetectedPulseOut_A	7945094	20	0	0
DisabledIdleSt_A	7945094	7105394	0	0
DisabledNoDetection_A	7945094	7107717	0	0
EnterDebounceSt_A	7945094	22	0	0
EnterDetectSt_A	7945094	20	0	0
EnterStableSt_A	7945094	20	0	0
PulseIsPulse_A	7945094	20	0	0
StayInStableSt	7945094	1510	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	6291	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	42	0	0
T17	114965	2	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	6	0	0
T49	0	2	0	0
T57	422	0	0	0
T58	615	0	0	0
T67	0	1	0	0
T68	0	2	0	0
T71	26972	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T156	0	4	0	0
T158	0	2	0	0
T161	0	2	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34263	0	0
T17	114965	65	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	71	0	0
T49	0	86	0	0
T57	422	0	0	0
T58	615	0	0	0
T67	0	18	0	0
T68	0	36	0	0
T71	26972	0	0	0
T151	0	93	0	0
T152	0	16	0	0
T156	0	122	0	0
T158	0	22	0	0
T161	0	33164	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278688	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1541	0	0
T17	114965	278	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	60	0	0
T49	0	127	0	0
T57	422	0	0	0
T58	615	0	0	0
T68	0	3	0	0
T71	26972	0	0	0
T151	0	362	0	0
T152	0	8	0	0
T156	0	79	0	0
T158	0	49	0	0
T161	0	43	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T195	0	58	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	20	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	3	0	0
T49	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T68	0	1	0	0
T71	26972	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T156	0	2	0	0
T158	0	1	0	0
T161	0	1	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7105394	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7107717	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	22	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	3	0	0
T49	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T71	26972	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T156	0	2	0	0
T158	0	1	0	0
T161	0	1	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	20	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	3	0	0
T49	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T68	0	1	0	0
T71	26972	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T156	0	2	0	0
T158	0	1	0	0
T161	0	1	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T195	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	20	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	3	0	0
T49	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T68	0	1	0	0
T71	26972	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T156	0	2	0	0
T158	0	1	0	0
T161	0	1	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	20	0	0
T17	114965	1	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	3	0	0
T49	0	1	0	0
T57	422	0	0	0
T58	615	0	0	0
T68	0	1	0	0
T71	26972	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T156	0	2	0	0
T158	0	1	0	0
T161	0	1	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1510	0	0
T17	114965	276	0	0
T18	2225	0	0	0
T41	37823	0	0	0
T48	20236	57	0	0
T49	0	126	0	0
T57	422	0	0	0
T58	615	0	0	0
T68	0	2	0	0
T71	26972	0	0	0
T151	0	361	0	0
T152	0	7	0	0
T156	0	76	0	0
T158	0	47	0	0
T161	0	41	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T195	0	56	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6291	0	0
T12	3346	7	0	0
T13	11876	24	0	0
T15	0	9	0	0
T17	0	13	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	21	0	0
T29	0	31	0	0
T34	5421	24	0	0
T35	12415	34	0	0
T36	3492	18	0	0
T57	0	2	0	0
T69	697	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	8	0	0
T41	37823	0	0	0
T48	20236	3	0	0
T49	843	1	0	0
T71	26972	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T156	0	1	0	0
T165	982	0	0	0
T166	853	0	0	0
T167	13681	0	0	0
T168	721	0	0	0
T169	431	0	0	0
T170	403	0	0	0
T194	0	1	0	0