Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T50,T45,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T50,T45,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T50,T45,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T50,T45
1	0	Covered	T34,T35,T36
1	1	Covered	T50,T45,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T45,T47
0	1	Covered	T78,T151,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T45,T47
0	1	Covered	T45,T47,T48
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T45,T47
1	-	Covered	T45,T47,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T50,T45,T47
0	1	Covered	T50,T45,T47
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T45,T47
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T50,T45,T47
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T45,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T171,T197,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T45,T47
DetectSt	-	-	-	-	1	-	-	Covered	T78,T151,T196
DetectSt	-	-	-	-	0	1	-	Covered	T50,T45,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T47,T48
StableSt	-	-	-	-	-	-	0	Covered	T50,T45,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	120	0	0
CntIncr_A	7945094	108330	0	0
CntNoWrap_A	7945094	7278610	0	0
DetectStDropOut_A	7945094	5	0	0
DetectedOut_A	7945094	30743	0	0
DetectedPulseOut_A	7945094	53	0	0
DisabledIdleSt_A	7945094	7002028	0	0
DisabledNoDetection_A	7945094	7004332	0	0
EnterDebounceSt_A	7945094	64	0	0
EnterDetectSt_A	7945094	58	0	0
EnterStableSt_A	7945094	53	0	0
PulseIsPulse_A	7945094	53	0	0
StayInStableSt	7945094	30662	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	120	0	0
T39	1821	0	0	0
T45	163943	4	0	0
T47	0	4	0	0
T48	0	10	0	0
T50	9079	2	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T78	0	2	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	4	0	0
T156	0	6	0	0
T171	0	1	0	0
T189	0	2	0	0
T197	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	108330	0	0
T39	1821	0	0	0
T45	163943	2941	0	0
T47	0	152	0	0
T48	0	112	0	0
T50	9079	82	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T78	0	72	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	186	0	0
T156	0	183	0	0
T171	0	40	0	0
T189	0	12	0	0
T197	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278610	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	5	0	0
T75	1023	0	0	0
T78	28973	1	0	0
T89	4966	0	0	0
T143	728	0	0	0
T144	12013	0	0	0
T145	503	0	0	0
T146	490	0	0	0
T151	1224	1	0	0
T171	573	0	0	0
T179	0	1	0	0
T196	0	1	0	0
T198	0	1	0	0
T199	411	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	30743	0	0
T39	1821	0	0	0
T45	163943	53	0	0
T47	0	344	0	0
T48	0	198	0	0
T50	9079	126	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T68	0	5	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	190	0	0
T156	0	80	0	0
T159	0	84	0	0
T189	0	62	0	0
T200	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	53	0	0
T39	1821	0	0	0
T45	163943	2	0	0
T47	0	2	0	0
T48	0	5	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T68	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	1	0	0
T156	0	3	0	0
T159	0	1	0	0
T189	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7002028	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7004332	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	64	0	0
T39	1821	0	0	0
T45	163943	3	0	0
T47	0	2	0	0
T48	0	5	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T78	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	2	0	0
T156	0	3	0	0
T171	0	1	0	0
T189	0	1	0	0
T197	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	58	0	0
T39	1821	0	0	0
T45	163943	2	0	0
T47	0	2	0	0
T48	0	5	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T78	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	2	0	0
T156	0	3	0	0
T159	0	1	0	0
T189	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	53	0	0
T39	1821	0	0	0
T45	163943	2	0	0
T47	0	2	0	0
T48	0	5	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T68	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	1	0	0
T156	0	3	0	0
T159	0	1	0	0
T189	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	53	0	0
T39	1821	0	0	0
T45	163943	2	0	0
T47	0	2	0	0
T48	0	5	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T68	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	1	0	0
T156	0	3	0	0
T159	0	1	0	0
T189	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	30662	0	0
T39	1821	0	0	0
T45	163943	51	0	0
T47	0	341	0	0
T48	0	191	0	0
T50	9079	124	0	0
T52	31582	0	0	0
T61	7777	0	0	0
T68	0	4	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T151	0	189	0	0
T156	0	76	0	0
T159	0	82	0	0
T189	0	60	0	0
T200	0	52	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	24	0	0
T45	163943	2	0	0
T47	1027	1	0	0
T48	0	3	0	0
T61	7777	0	0	0
T62	1883	0	0	0
T103	522	0	0	0
T104	505	0	0	0
T105	497	0	0	0
T106	616	0	0	0
T128	440	0	0	0
T129	16674	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T156	0	2	0	0
T161	0	1	0	0
T174	0	1	0	0
T176	0	2	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T45,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T36,T12,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T45,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T50
1	0	Covered	T34,T35,T36
1	1	Covered	T36,T12,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T45,T47
0	1	Covered	T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T45,T47
0	1	Covered	T47,T48,T70
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T45,T47
1	-	Covered	T47,T48,T70

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T45,T47
0	1	Covered	T36,T12,T45
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T45,T47
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T12,T45
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T45,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T153
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T12,T45
DetectSt	-	-	-	-	1	-	-	Covered	T175
DetectSt	-	-	-	-	0	1	-	Covered	T12,T45,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T48,T70
StableSt	-	-	-	-	-	-	0	Covered	T12,T45,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	72	0	0
CntIncr_A	7945094	68885	0	0
CntNoWrap_A	7945094	7278658	0	0
DetectStDropOut_A	7945094	1	0	0
DetectedOut_A	7945094	26525	0	0
DetectedPulseOut_A	7945094	34	0	0
DisabledIdleSt_A	7945094	7001802	0	0
DisabledNoDetection_A	7945094	7004103	0	0
EnterDebounceSt_A	7945094	38	0	0
EnterDetectSt_A	7945094	35	0	0
EnterStableSt_A	7945094	34	0	0
PulseIsPulse_A	7945094	34	0	0
StayInStableSt	7945094	26472	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	6264	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	72	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T70	0	4	0	0
T78	0	2	0	0
T107	0	2	0	0
T152	0	2	0	0
T175	0	2	0	0
T197	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	68885	0	0
T12	3346	11	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T36	3492	25	0	0
T45	0	23	0	0
T47	0	76	0	0
T48	0	20	0	0
T69	697	0	0	0
T70	0	94	0	0
T78	0	72	0	0
T107	0	24	0	0
T175	0	16	0	0
T197	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278658	0	0
T12	3346	1340	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1	0	0
T81	33057	0	0	0
T156	946	0	0	0
T175	639	1	0	0
T197	536	0	0	0
T202	1360	0	0	0
T203	18110	0	0	0
T204	566	0	0	0
T205	3247	0	0	0
T206	703	0	0	0
T207	2743	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	26525	0	0
T12	3346	62	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	41	0	0
T47	0	43	0	0
T48	0	44	0	0
T70	0	82	0	0
T78	0	56	0	0
T107	0	146	0	0
T149	0	117	0	0
T152	0	40	0	0
T197	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T70	0	2	0	0
T78	0	1	0	0
T107	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T197	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7001802	0	0
T12	3346	1191	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	304	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7004103	0	0
T12	3346	1194	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	310	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	38	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T36	3492	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T69	697	0	0	0
T70	0	2	0	0
T78	0	1	0	0
T107	0	1	0	0
T175	0	1	0	0
T197	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	35	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T70	0	2	0	0
T78	0	1	0	0
T107	0	1	0	0
T152	0	1	0	0
T175	0	1	0	0
T197	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T70	0	2	0	0
T78	0	1	0	0
T107	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T197	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34	0	0
T12	3346	1	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T70	0	2	0	0
T78	0	1	0	0
T107	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T197	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	26472	0	0
T12	3346	60	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	39	0	0
T47	0	42	0	0
T48	0	43	0	0
T70	0	79	0	0
T78	0	54	0	0
T107	0	144	0	0
T149	0	115	0	0
T152	0	38	0	0
T197	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6264	0	0
T12	3346	5	0	0
T13	11876	24	0	0
T15	0	12	0	0
T17	0	12	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	26	0	0
T28	0	1	0	0
T29	0	31	0	0
T34	5421	25	0	0
T35	12415	28	0	0
T36	3492	20	0	0
T69	697	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	14	0	0
T41	37823	0	0	0
T47	1027	1	0	0
T48	20236	1	0	0
T70	0	1	0	0
T71	26972	0	0	0
T116	14654	0	0	0
T122	26513	0	0	0
T161	0	1	0	0
T163	0	2	0	0
T165	982	0	0	0
T166	853	0	0	0
T172	0	1	0	0
T196	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	594	0	0	0
T212	930	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T16,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T12,T16,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T50
0	1	Covered	T159
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T50
0	1	Covered	T12,T50,T46
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T50
1	-	Covered	T12,T50,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T50
0	1	Covered	T12,T16,T50
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T50
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T50
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T114,T213,T191
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T50
DetectSt	-	-	-	-	1	-	-	Covered	T159
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T50,T46
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	109	0	0
CntIncr_A	7945094	135846	0	0
CntNoWrap_A	7945094	7278621	0	0
DetectStDropOut_A	7945094	1	0	0
DetectedOut_A	7945094	282678	0	0
DetectedPulseOut_A	7945094	51	0	0
DisabledIdleSt_A	7945094	6828736	0	0
DisabledNoDetection_A	7945094	6831043	0	0
EnterDebounceSt_A	7945094	57	0	0
EnterDetectSt_A	7945094	52	0	0
EnterStableSt_A	7945094	51	0	0
PulseIsPulse_A	7945094	51	0	0
StayInStableSt	7945094	282608	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	109	0	0
T12	3346	8	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T50	0	4	0	0
T114	0	1	0	0
T168	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	135846	0	0
T12	3346	214	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	20	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	55	0	0
T46	0	38	0	0
T47	0	152	0	0
T48	0	22	0	0
T50	0	114	0	0
T114	0	54	0	0
T168	0	99	0	0
T175	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278621	0	0
T12	3346	1334	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1	0	0
T159	13368	1	0	0
T214	718	0	0	0
T215	722	0	0	0
T216	15858	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	282678	0	0
T12	3346	352	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	37	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	274	0	0
T46	0	1	0	0
T47	0	39	0	0
T48	0	102	0	0
T50	0	483	0	0
T156	0	375	0	0
T168	0	44	0	0
T175	0	58	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	51	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T156	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6828736	0	0
T12	3346	402	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6831043	0	0
T12	3346	404	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	57	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T114	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	52	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T156	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	51	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T156	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	51	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T156	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	282608	0	0
T12	3346	346	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	35	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	273	0	0
T47	0	36	0	0
T48	0	101	0	0
T50	0	481	0	0
T151	0	114	0	0
T156	0	374	0	0
T168	0	42	0	0
T175	0	57	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	31	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T151	0	2	0	0
T156	0	1	0	0
T158	0	2	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T46,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T46,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T46,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T12,T46,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T46,T45
0	1	Covered	T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T46,T45
0	1	Covered	T12,T48,T49
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T46,T45
1	-	Covered	T12,T48,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T46,T45
0	1	Covered	T12,T46,T45
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T46,T45
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T46,T45
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T46,T45
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T46,T45
DetectSt	-	-	-	-	1	-	-	Covered	T189
DetectSt	-	-	-	-	0	1	-	Covered	T12,T46,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T48,T49
StableSt	-	-	-	-	-	-	0	Covered	T12,T46,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	69	0	0
CntIncr_A	7945094	1721	0	0
CntNoWrap_A	7945094	7278661	0	0
DetectStDropOut_A	7945094	1	0	0
DetectedOut_A	7945094	2280	0	0
DetectedPulseOut_A	7945094	33	0	0
DisabledIdleSt_A	7945094	7260592	0	0
DisabledNoDetection_A	7945094	7262897	0	0
EnterDebounceSt_A	7945094	35	0	0
EnterDetectSt_A	7945094	34	0	0
EnterStableSt_A	7945094	33	0	0
PulseIsPulse_A	7945094	33	0	0
StayInStableSt	7945094	2231	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	6261	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	69	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	14	0	0
T49	0	2	0	0
T151	0	4	0	0
T158	0	4	0	0
T159	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1721	0	0
T12	3346	107	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	55	0	0
T46	0	38	0	0
T48	0	140	0	0
T49	0	86	0	0
T151	0	186	0	0
T158	0	44	0	0
T159	0	76	0	0
T187	0	94	0	0
T189	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278661	0	0
T12	3346	1338	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1	0	0
T189	615	1	0	0
T217	522	0	0	0
T218	526	0	0	0
T219	405	0	0	0
T220	638	0	0	0
T221	13233	0	0	0
T222	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2280	0	0
T12	3346	252	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	119	0	0
T46	0	40	0	0
T48	0	297	0	0
T49	0	128	0	0
T151	0	133	0	0
T158	0	75	0	0
T159	0	87	0	0
T187	0	83	0	0
T189	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	33	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	7	0	0
T49	0	1	0	0
T151	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T187	0	2	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7260592	0	0
T12	3346	402	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7262897	0	0
T12	3346	404	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	35	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	7	0	0
T49	0	1	0	0
T151	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T187	0	2	0	0
T189	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	34	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	7	0	0
T49	0	1	0	0
T151	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T187	0	2	0	0
T189	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	33	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	7	0	0
T49	0	1	0	0
T151	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T187	0	2	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	33	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	7	0	0
T49	0	1	0	0
T151	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T187	0	2	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2231	0	0
T12	3346	250	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	117	0	0
T46	0	38	0	0
T48	0	287	0	0
T49	0	127	0	0
T151	0	131	0	0
T158	0	73	0	0
T159	0	84	0	0
T187	0	80	0	0
T189	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6261	0	0
T12	3346	8	0	0
T13	11876	23	0	0
T15	0	9	0	0
T17	0	15	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	21	0	0
T28	0	1	0	0
T29	0	32	0	0
T34	5421	26	0	0
T35	12415	28	0	0
T36	3492	18	0	0
T69	697	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	16	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T48	0	4	0	0
T49	0	1	0	0
T100	0	1	0	0
T151	0	2	0	0
T158	0	2	0	0
T159	0	1	0	0
T179	0	1	0	0
T187	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T50,T46,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T50,T46,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T50,T46,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T46,T45
1	0	Covered	T34,T35,T36
1	1	Covered	T50,T46,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T46,T45
0	1	Covered	T49,T200,T163
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T46,T45
0	1	Covered	T45,T47,T107
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T46,T45
1	-	Covered	T45,T47,T107

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T50,T46,T45
0	1	Covered	T50,T46,T45
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T46,T45
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T50,T46,T45
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T46,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T107,T78,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T46,T45
DetectSt	-	-	-	-	1	-	-	Covered	T49,T200,T163
DetectSt	-	-	-	-	0	1	-	Covered	T50,T46,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T47,T107
StableSt	-	-	-	-	-	-	0	Covered	T50,T46,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	88	0	0
CntIncr_A	7945094	4080	0	0
CntNoWrap_A	7945094	7278642	0	0
DetectStDropOut_A	7945094	5	0	0
DetectedOut_A	7945094	2882	0	0
DetectedPulseOut_A	7945094	36	0	0
DisabledIdleSt_A	7945094	7167956	0	0
DisabledNoDetection_A	7945094	7170274	0	0
EnterDebounceSt_A	7945094	48	0	0
EnterDetectSt_A	7945094	41	0	0
EnterStableSt_A	7945094	36	0	0
PulseIsPulse_A	7945094	36	0	0
StayInStableSt	7945094	2832	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	88	0	0
T39	1821	0	0	0
T45	0	2	0	0
T46	527	2	0	0
T47	0	4	0	0
T49	0	2	0	0
T50	9079	2	0	0
T52	31582	0	0	0
T55	0	2	0	0
T78	0	1	0	0
T87	58787	0	0	0
T107	0	3	0	0
T114	0	2	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	4080	0	0
T39	1821	0	0	0
T45	0	23	0	0
T46	527	38	0	0
T47	0	152	0	0
T49	0	86	0	0
T50	9079	82	0	0
T52	31582	0	0	0
T55	0	80	0	0
T78	0	72	0	0
T87	58787	0	0	0
T107	0	48	0	0
T114	0	54	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T171	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278642	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	5	0	0
T49	843	1	0	0
T163	0	1	0	0
T193	12684	0	0	0
T196	0	1	0	0
T200	616	1	0	0
T223	0	1	0	0
T224	408	0	0	0
T225	540	0	0	0
T226	423	0	0	0
T227	434	0	0	0
T228	402	0	0	0
T229	621	0	0	0
T230	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2882	0	0
T39	1821	0	0	0
T45	0	15	0	0
T46	527	79	0	0
T47	0	266	0	0
T50	9079	127	0	0
T52	31582	0	0	0
T55	0	44	0	0
T87	58787	0	0	0
T107	0	39	0	0
T114	0	2	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T158	0	122	0	0
T171	0	122	0	0
T175	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	36	0	0
T39	1821	0	0	0
T45	0	1	0	0
T46	527	1	0	0
T47	0	2	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T55	0	1	0	0
T87	58787	0	0	0
T107	0	1	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T158	0	2	0	0
T171	0	1	0	0
T175	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7167956	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7170274	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	48	0	0
T39	1821	0	0	0
T45	0	1	0	0
T46	527	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T55	0	1	0	0
T78	0	1	0	0
T87	58787	0	0	0
T107	0	2	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	41	0	0
T39	1821	0	0	0
T45	0	1	0	0
T46	527	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T55	0	1	0	0
T87	58787	0	0	0
T107	0	1	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T171	0	1	0	0
T175	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	36	0	0
T39	1821	0	0	0
T45	0	1	0	0
T46	527	1	0	0
T47	0	2	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T55	0	1	0	0
T87	58787	0	0	0
T107	0	1	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T158	0	2	0	0
T171	0	1	0	0
T175	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	36	0	0
T39	1821	0	0	0
T45	0	1	0	0
T46	527	1	0	0
T47	0	2	0	0
T50	9079	1	0	0
T52	31582	0	0	0
T55	0	1	0	0
T87	58787	0	0	0
T107	0	1	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T158	0	2	0	0
T171	0	1	0	0
T175	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2832	0	0
T39	1821	0	0	0
T45	0	14	0	0
T46	527	77	0	0
T47	0	263	0	0
T50	9079	125	0	0
T52	31582	0	0	0
T55	0	42	0	0
T87	58787	0	0	0
T107	0	38	0	0
T114	0	1	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T136	498	0	0	0
T158	0	119	0	0
T171	0	120	0	0
T175	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	21	0	0
T45	163943	1	0	0
T47	1027	1	0	0
T61	7777	0	0	0
T62	1883	0	0	0
T103	522	0	0	0
T104	505	0	0	0
T105	497	0	0	0
T106	616	0	0	0
T107	0	1	0	0
T114	0	1	0	0
T128	440	0	0	0
T129	16674	0	0	0
T149	0	1	0	0
T158	0	1	0	0
T163	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T190	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T12,T16,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T16
1	0	Covered	T34,T35,T36
1	1	Covered	T12,T16,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T45
0	1	Covered	T107,T156,T151
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T45
1	-	Covered	T107,T156,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T45
0	1	Covered	T12,T16,T45
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T45
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T45
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T45
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T107,T156,T151
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	83	0	0
CntIncr_A	7945094	68758	0	0
CntNoWrap_A	7945094	7278647	0	0
DetectStDropOut_A	7945094	0	0	0
DetectedOut_A	7945094	2843	0	0
DetectedPulseOut_A	7945094	41	0	0
DisabledIdleSt_A	7945094	7098544	0	0
DisabledNoDetection_A	7945094	7100853	0	0
EnterDebounceSt_A	7945094	42	0	0
EnterDetectSt_A	7945094	41	0	0
EnterStableSt_A	7945094	41	0	0
PulseIsPulse_A	7945094	41	0	0
StayInStableSt	7945094	2779	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7945094	6963	0	0
gen_low_level_sva.LowLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	83	0	0
T12	3346	4	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	2	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T107	0	4	0	0
T114	0	2	0	0
T151	0	6	0	0
T156	0	4	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	68758	0	0
T12	3346	107	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	20	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	23	0	0
T48	0	29	0	0
T49	0	86	0	0
T107	0	48	0	0
T114	0	54	0	0
T151	0	279	0	0
T156	0	122	0	0
T168	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7278647	0	0
T12	3346	1338	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2843	0	0
T12	3346	231	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	37	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	43	0	0
T48	0	44	0	0
T49	0	261	0	0
T107	0	151	0	0
T114	0	194	0	0
T151	0	117	0	0
T156	0	149	0	0
T168	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	41	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T107	0	2	0	0
T114	0	1	0	0
T151	0	3	0	0
T156	0	2	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7098544	0	0
T12	3346	402	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	304	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7100853	0	0
T12	3346	404	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	310	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	42	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T107	0	2	0	0
T114	0	1	0	0
T151	0	3	0	0
T156	0	2	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	41	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T107	0	2	0	0
T114	0	1	0	0
T151	0	3	0	0
T156	0	2	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	41	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T107	0	2	0	0
T114	0	1	0	0
T151	0	3	0	0
T156	0	2	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	41	0	0
T12	3346	2	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	1	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T107	0	2	0	0
T114	0	1	0	0
T151	0	3	0	0
T156	0	2	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2779	0	0
T12	3346	227	0	0
T13	11876	0	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T16	0	35	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T45	0	41	0	0
T48	0	42	0	0
T49	0	259	0	0
T107	0	148	0	0
T114	0	192	0	0
T151	0	113	0	0
T156	0	147	0	0
T168	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6963	0	0
T12	3346	8	0	0
T13	11876	33	0	0
T14	0	6	0	0
T24	526	0	0	0
T25	715	3	0	0
T26	678	3	0	0
T27	4565	19	0	0
T34	5421	21	0	0
T35	12415	27	0	0
T36	3492	19	0	0
T69	697	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	17	0	0
T78	28973	0	0	0
T107	697	1	0	0
T108	22954	0	0	0
T109	686	0	0	0
T110	678	0	0	0
T111	693	0	0	0
T112	29772	0	0	0
T113	522	0	0	0
T114	715	0	0	0
T115	15724	0	0	0
T151	0	2	0	0
T156	0	2	0	0
T161	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T196	0	2	0	0
T209	0	1	0	0
T223	0	1	0	0
T231	0	1	0	0