Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T29,T15
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T15
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T58,T82,T94

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T58,T82,T94

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T58,T82,T94

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T58,T82,T94
1	0	Covered	T14,T28,T29
1	1	Covered	T58,T82,T94

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T58,T82,T94
0	1	Covered	T120
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T58,T82,T94
0	1	Covered	T58,T82,T94
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T58,T82,T94
1	-	Covered	T58,T82,T94

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T58,T82,T94
0	1	Covered	T58,T82,T94
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T58,T82,T94
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T58,T82,T94
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T58,T82,T94
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T93,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T58,T82,T94
DetectSt	-	-	-	-	1	-	-	Covered	T120
DetectSt	-	-	-	-	0	1	-	Covered	T58,T82,T94
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T58,T82,T94
StableSt	-	-	-	-	-	-	0	Covered	T58,T82,T94
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	257	0	0
CntIncr_A	6912820	93684	0	0
CntNoWrap_A	6912820	6250394	0	0
DetectStDropOut_A	6912820	1	0	0
DetectedOut_A	6912820	791	0	0
DetectedPulseOut_A	6912820	115	0	0
DisabledIdleSt_A	6912820	6150917	0	0
DisabledNoDetection_A	6912820	6153114	0	0
EnterDebounceSt_A	6912820	143	0	0
EnterDetectSt_A	6912820	116	0	0
EnterStableSt_A	6912820	115	0	0
PulseIsPulse_A	6912820	115	0	0
StayInStableSt	6912820	676	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	7124	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	115	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	257	0	0
T23	5841	0	0	0
T58	685	4	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	4	0	0
T82	713	2	0	0
T92	0	5	0	0
T94	1531	2	0	0
T95	0	2	0	0
T96	0	6	0	0
T97	0	2	0	0
T99	0	4	0	0
T100	0	4	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	93684	0	0
T23	5841	0	0	0
T58	685	85	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	91	0	0
T82	713	14	0	0
T92	0	199	0	0
T94	1531	43	0	0
T95	0	98	0	0
T96	0	57435	0	0
T97	0	91	0	0
T99	0	116	0	0
T100	0	83	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250394	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1	0	0
T120	10556	1	0	0
T127	5772	0	0	0
T128	489	0	0	0
T129	715	0	0	0
T130	523	0	0	0
T131	1216	0	0	0
T132	422	0	0	0
T133	402	0	0	0
T134	502	0	0	0
T135	647	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	791	0	0
T23	5841	0	0	0
T58	685	13	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	18	0	0
T82	713	11	0	0
T92	0	14	0	0
T94	1531	6	0	0
T95	0	1	0	0
T96	0	10	0	0
T97	0	8	0	0
T99	0	20	0	0
T100	0	13	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	115	0	0
T23	5841	0	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6150917	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6153114	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	143	0	0
T23	5841	0	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	3	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	116	0	0
T23	5841	0	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	115	0	0
T23	5841	0	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	115	0	0
T23	5841	0	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	676	0	0
T23	5841	0	0	0
T58	685	11	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	16	0	0
T82	713	10	0	0
T92	0	12	0	0
T94	1531	5	0	0
T96	0	7	0	0
T97	0	7	0	0
T99	0	18	0	0
T100	0	11	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T136	0	20	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	7124	0	0
T15	72309	1	0	0
T16	25996	25	0	0
T17	1089	5	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	0	21	0	0
T28	424	3	0	0
T29	427	2	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	3	0	0
T55	0	3	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	115	0	0
T23	5841	0	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T29,T15
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T15
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T15,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T17,T20,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T20
1	0	Covered	T14,T28,T29
1	1	Covered	T15,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T62
0	1	Covered	T89,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T62
0	1	Unreachable
1	0	Covered	T17,T20,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T20
0	1	Covered	T15,T17,T20
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T20,T62
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T20
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T20,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T67,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T20
DetectSt	-	-	-	-	1	-	-	Covered	T89,T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T17,T20,T62
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T20,T62
StableSt	-	-	-	-	-	-	0	Covered	T17,T20,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	191	0	0
CntIncr_A	6912820	96968	0	0
CntNoWrap_A	6912820	6250460	0	0
DetectStDropOut_A	6912820	8	0	0
DetectedOut_A	6912820	484033	0	0
DetectedPulseOut_A	6912820	70	0	0
DisabledIdleSt_A	6912820	5017953	0	0
DisabledNoDetection_A	6912820	5020196	0	0
EnterDebounceSt_A	6912820	114	0	0
EnterDetectSt_A	6912820	78	0	0
EnterStableSt_A	6912820	70	0	0
PulseIsPulse_A	6912820	70	0	0
StayInStableSt	6912820	483963	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	7124	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_sticky_sva.StableStDropOut_A	6912820	349237	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	191	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	2	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	2	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	96968	0	0
T15	72309	28	0	0
T16	25996	0	0	0
T17	1089	73	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	22	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	58	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	34	0	0
T63	0	60	0	0
T64	0	64	0	0
T65	0	43	0	0
T66	0	60	0	0
T67	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250460	0	0
T14	3575	667	0	0
T15	72309	71907	0	0
T16	25996	25535	0	0
T17	1089	686	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	8	0	0
T87	1165	0	0	0
T89	560	1	0	0
T90	0	3	0	0
T91	0	2	0	0
T113	16287	0	0	0
T142	0	2	0	0
T143	144967	0	0	0
T144	505	0	0	0
T145	405	0	0	0
T146	435	0	0	0
T147	823	0	0	0
T148	10279	0	0	0
T149	527	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	484033	0	0
T17	1089	406	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	76	0	0
T21	571	0	0	0
T32	416	0	0	0
T51	0	163	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T62	0	13	0	0
T63	0	114	0	0
T64	0	244	0	0
T65	0	200	0	0
T66	0	147	0	0
T137	0	62	0	0
T138	0	231	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	70	0	0
T17	1089	1	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	1	0	0
T21	571	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5017953	0	0
T14	3575	667	0	0
T15	72309	31	0	0
T16	25996	25535	0	0
T17	1089	39	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5020196	0	0
T14	3575	675	0	0
T15	72309	32	0	0
T16	25996	25544	0	0
T17	1089	40	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	114	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	1	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	1	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	78	0	0
T17	1089	1	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	1	0	0
T21	571	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	70	0	0
T17	1089	1	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	1	0	0
T21	571	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	70	0	0
T17	1089	1	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	1	0	0
T21	571	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	483963	0	0
T17	1089	405	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	75	0	0
T21	571	0	0	0
T32	416	0	0	0
T51	0	162	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T62	0	12	0	0
T63	0	113	0	0
T64	0	242	0	0
T65	0	199	0	0
T66	0	146	0	0
T137	0	61	0	0
T138	0	230	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	7124	0	0
T15	72309	1	0	0
T16	25996	25	0	0
T17	1089	5	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	0	21	0	0
T28	424	3	0	0
T29	427	2	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	3	0	0
T55	0	3	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	349237	0	0
T17	1089	153	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	654	0	0
T21	571	0	0	0
T32	416	0	0	0
T51	0	202	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T62	0	92	0	0
T63	0	65	0	0
T64	0	721	0	0
T65	0	294	0	0
T66	0	58	0	0
T137	0	81	0	0
T138	0	463	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T28,T29,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T28,T29,T15
1	1	Covered	T28,T29,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T15,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T20,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T20
1	0	Covered	T28,T29,T32
1	1	Covered	T15,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T63
0	1	Covered	T15,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T63
0	1	Unreachable
1	0	Covered	T20,T62,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T20
0	1	Covered	T15,T17,T20
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T20,T62
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T20
IdleSt	0	-	-	-	-	-	-	Covered	T28,T29,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T20,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T86,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T20
DetectSt	-	-	-	-	1	-	-	Covered	T15,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T20,T62,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T62,T63
StableSt	-	-	-	-	-	-	0	Covered	T20,T62,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	207	0	0
CntIncr_A	6912820	94315	0	0
CntNoWrap_A	6912820	6250444	0	0
DetectStDropOut_A	6912820	13	0	0
DetectedOut_A	6912820	52776	0	0
DetectedPulseOut_A	6912820	67	0	0
DisabledIdleSt_A	6912820	5017953	0	0
DisabledNoDetection_A	6912820	5020196	0	0
EnterDebounceSt_A	6912820	128	0	0
EnterDetectSt_A	6912820	80	0	0
EnterStableSt_A	6912820	67	0	0
PulseIsPulse_A	6912820	67	0	0
StayInStableSt	6912820	52709	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_sticky_sva.StableStDropOut_A	6912820	1007336	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	207	0	0
T15	72309	2	0	0
T16	25996	0	0	0
T17	1089	5	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	2	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	94315	0	0
T15	72309	84	0	0
T16	25996	0	0	0
T17	1089	335	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	54	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	99	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	82	0	0
T63	0	83	0	0
T64	0	40	0	0
T65	0	10	0	0
T66	0	27	0	0
T67	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250444	0	0
T14	3575	667	0	0
T15	72309	71906	0	0
T16	25996	25535	0	0
T17	1089	683	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	13	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T87	0	2	0	0
T88	0	4	0	0
T151	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	52776	0	0
T20	14380	350	0	0
T21	571	0	0	0
T40	21099	0	0	0
T51	0	295	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T62	866	37	0	0
T63	0	105	0	0
T64	0	226	0	0
T65	0	68	0	0
T66	0	40	0	0
T67	0	69	0	0
T92	720	0	0	0
T137	0	87	0	0
T138	0	606	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	67	0	0
T20	14380	1	0	0
T21	571	0	0	0
T40	21099	0	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T62	866	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T92	720	0	0	0
T137	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5017953	0	0
T14	3575	667	0	0
T15	72309	31	0	0
T16	25996	25535	0	0
T17	1089	39	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5020196	0	0
T14	3575	675	0	0
T15	72309	32	0	0
T16	25996	25544	0	0
T17	1089	40	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	128	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	5	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	1	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	80	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	1	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T137	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	67	0	0
T20	14380	1	0	0
T21	571	0	0	0
T40	21099	0	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T62	866	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T92	720	0	0	0
T137	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	67	0	0
T20	14380	1	0	0
T21	571	0	0	0
T40	21099	0	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T62	866	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T92	720	0	0	0
T137	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	52709	0	0
T20	14380	349	0	0
T21	571	0	0	0
T40	21099	0	0	0
T51	0	294	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T62	866	36	0	0
T63	0	104	0	0
T64	0	224	0	0
T65	0	67	0	0
T66	0	39	0	0
T67	0	68	0	0
T92	720	0	0	0
T137	0	86	0	0
T138	0	605	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1007336	0	0
T20	14380	531	0	0
T21	571	0	0	0
T40	21099	0	0	0
T51	0	38	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T62	866	29	0	0
T63	0	41	0	0
T64	0	768	0	0
T65	0	458	0	0
T66	0	199	0	0
T67	0	187	0	0
T92	720	0	0	0
T137	0	43	0	0
T138	0	69	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T28,T29,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T15,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T62,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T20
1	0	Covered	T28,T29,T16
1	1	Covered	T15,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T62,T63
0	1	Covered	T63,T51,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T62,T63
0	1	Unreachable
1	0	Covered	T15,T62,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T20
0	1	Covered	T15,T17,T20
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T62,T63
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T20
IdleSt	0	-	-	-	-	-	-	Covered	T28,T29,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T62,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T20,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T20
DetectSt	-	-	-	-	1	-	-	Covered	T63,T51,T86
DetectSt	-	-	-	-	0	1	-	Covered	T15,T62,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T62,T63
StableSt	-	-	-	-	-	-	0	Covered	T15,T62,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	218	0	0
CntIncr_A	6912820	257233	0	0
CntNoWrap_A	6912820	6250433	0	0
DetectStDropOut_A	6912820	17	0	0
DetectedOut_A	6912820	268902	0	0
DetectedPulseOut_A	6912820	57	0	0
DisabledIdleSt_A	6912820	5017953	0	0
DisabledNoDetection_A	6912820	5020196	0	0
EnterDebounceSt_A	6912820	145	0	0
EnterDetectSt_A	6912820	74	0	0
EnterStableSt_A	6912820	57	0	0
PulseIsPulse_A	6912820	57	0	0
StayInStableSt	6912820	268845	0	0
gen_high_event_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_sticky_sva.StableStDropOut_A	6912820	569810	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	218	0	0
T15	72309	2	0	0
T16	25996	0	0	0
T17	1089	5	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	3	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	257233	0	0
T15	72309	63309	0	0
T16	25996	0	0	0
T17	1089	80	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	172	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	126	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	46	0	0
T63	0	22	0	0
T64	0	178	0	0
T65	0	77	0	0
T66	0	188	0	0
T67	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250433	0	0
T14	3575	667	0	0
T15	72309	71906	0	0
T16	25996	25535	0	0
T17	1089	683	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	17	0	0
T51	9681	1	0	0
T63	2248	1	0	0
T86	0	2	0	0
T98	27090	0	0	0
T117	0	2	0	0
T150	0	2	0	0
T154	0	1	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	406	0	0	0
T159	29196	0	0	0
T160	404	0	0	0
T161	412	0	0	0
T162	428	0	0	0
T163	422	0	0	0
T164	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	268902	0	0
T15	72309	8522	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	22	0	0
T63	0	1	0	0
T64	0	772	0	0
T65	0	413	0	0
T67	0	141	0	0
T137	0	25	0	0
T138	0	404	0	0
T139	0	262	0	0
T140	0	221	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	57	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5017953	0	0
T14	3575	667	0	0
T15	72309	31	0	0
T16	25996	25535	0	0
T17	1089	39	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5020196	0	0
T14	3575	675	0	0
T15	72309	32	0	0
T16	25996	25544	0	0
T17	1089	40	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	145	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	5	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	2	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	74	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	57	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	57	0	0
T15	72309	1	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	268845	0	0
T15	72309	8521	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	21	0	0
T64	0	770	0	0
T65	0	412	0	0
T67	0	140	0	0
T89	0	38	0	0
T137	0	24	0	0
T138	0	403	0	0
T139	0	261	0	0
T140	0	220	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	569810	0	0
T15	72309	39	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T62	0	84	0	0
T63	0	119	0	0
T64	0	96	0	0
T65	0	54	0	0
T67	0	104	0	0
T137	0	151	0	0
T138	0	266	0	0
T139	0	257	0	0
T140	0	52	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T49,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T49,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T49,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T49
1	0	Covered	T14,T28,T29
1	1	Covered	T49,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T45,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T45,T46
0	1	Covered	T46,T67,T165
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T45,T46
1	-	Covered	T46,T67,T165

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T49,T45,T46
0	1	Covered	T49,T45,T46
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T45,T46
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T49,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T45,T46
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T49,T45,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T49,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T67,T165
StableSt	-	-	-	-	-	-	0	Covered	T49,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	72	0	0
CntIncr_A	6912820	103711	0	0
CntNoWrap_A	6912820	6250579	0	0
DetectStDropOut_A	6912820	0	0	0
DetectedOut_A	6912820	2593	0	0
DetectedPulseOut_A	6912820	36	0	0
DisabledIdleSt_A	6912820	5601435	0	0
DisabledNoDetection_A	6912820	5603623	0	0
EnterDebounceSt_A	6912820	36	0	0
EnterDetectSt_A	6912820	36	0	0
EnterStableSt_A	6912820	36	0	0
PulseIsPulse_A	6912820	36	0	0
StayInStableSt	6912820	2540	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	72	0	0
T40	21099	0	0	0
T45	881	2	0	0
T46	0	2	0	0
T49	3627	2	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	4	0	0
T78	0	2	0	0
T81	0	2	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	103711	0	0
T40	21099	0	0	0
T45	881	94	0	0
T46	0	36	0	0
T49	3627	14	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	66	0	0
T78	0	33	0	0
T81	0	63180	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	90	0	0
T166	0	49	0	0
T167	0	53	0	0
T168	0	47	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250579	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2593	0	0
T40	21099	0	0	0
T45	881	40	0	0
T46	0	43	0	0
T49	3627	131	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	91	0	0
T78	0	14	0	0
T81	0	41	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	133	0	0
T166	0	44	0	0
T167	0	38	0	0
T168	0	122	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	36	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	2	0	0
T78	0	1	0	0
T81	0	1	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5601435	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5603623	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	36	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	2	0	0
T78	0	1	0	0
T81	0	1	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	36	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	2	0	0
T78	0	1	0	0
T81	0	1	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	36	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	2	0	0
T78	0	1	0	0
T81	0	1	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	36	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	2	0	0
T78	0	1	0	0
T81	0	1	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2540	0	0
T40	21099	0	0	0
T45	881	38	0	0
T46	0	42	0	0
T49	3627	129	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	89	0	0
T78	0	13	0	0
T81	0	39	0	0
T92	720	0	0	0
T95	724	0	0	0
T165	0	132	0	0
T166	0	42	0	0
T167	0	36	0	0
T168	0	120	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	17	0	0
T46	756	1	0	0
T54	24414	0	0	0
T67	29422	2	0	0
T117	0	2	0	0
T119	0	2	0	0
T125	522	0	0	0
T135	0	1	0	0
T155	0	1	0	0
T165	10761	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T179	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T19,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T22
1	0	Covered	T14,T28,T29
1	1	Covered	T19,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T22
0	1	Covered	T67,T180,T119
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T22
0	1	Covered	T49,T45,T46
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T22
1	-	Covered	T49,T45,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T21,T22
0	1	Covered	T19,T21,T22
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T22
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T144
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T67,T180,T119
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T49,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	117	0	0
CntIncr_A	6912820	50621	0	0
CntNoWrap_A	6912820	6250534	0	0
DetectStDropOut_A	6912820	3	0	0
DetectedOut_A	6912820	53341	0	0
DetectedPulseOut_A	6912820	55	0	0
DisabledIdleSt_A	6912820	6137557	0	0
DisabledNoDetection_A	6912820	6139750	0	0
EnterDebounceSt_A	6912820	59	0	0
EnterDetectSt_A	6912820	58	0	0
EnterStableSt_A	6912820	55	0	0
PulseIsPulse_A	6912820	55	0	0
StayInStableSt	6912820	53258	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	2745	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	117	0	0
T19	96134	2	0	0
T20	14380	0	0	0
T21	571	2	0	0
T22	0	2	0	0
T45	0	2	0	0
T46	0	4	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	0	2	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	50621	0	0
T19	96134	47248	0	0
T20	14380	0	0	0
T21	571	46	0	0
T22	0	34	0	0
T45	0	94	0	0
T46	0	72	0	0
T47	0	100	0	0
T48	0	28	0	0
T49	0	14	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	65	0	0
T182	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250534	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3	0	0
T67	29422	1	0	0
T119	17593	1	0	0
T125	522	0	0	0
T180	820	1	0	0
T183	634	0	0	0
T184	444	0	0	0
T185	449	0	0	0
T186	506	0	0	0
T187	59481	0	0	0
T188	23680	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53341	0	0
T19	96134	48476	0	0
T20	14380	0	0	0
T21	571	39	0	0
T22	0	185	0	0
T45	0	243	0	0
T46	0	109	0	0
T47	0	161	0	0
T48	0	80	0	0
T49	0	69	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	228	0	0
T182	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	55	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	1	0	0
T22	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6137557	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6139750	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	59	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	1	0	0
T22	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	58	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	1	0	0
T22	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	55	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	1	0	0
T22	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	55	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	1	0	0
T22	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53258	0	0
T19	96134	48474	0	0
T20	14380	0	0	0
T21	571	37	0	0
T22	0	183	0	0
T45	0	242	0	0
T46	0	106	0	0
T47	0	159	0	0
T48	0	78	0	0
T49	0	68	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T181	0	226	0	0
T182	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2745	0	0
T15	72309	0	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T28	424	1	0	0
T29	427	2	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	1	0	0
T55	0	3	0	0
T56	0	6	0	0
T57	0	4	0	0
T59	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	25	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	1	0	0
T80	0	1	0	0
T92	720	0	0	0
T95	724	0	0	0
T166	0	1	0	0
T168	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T189	0	1	0	0
T190	0	1	0	0