Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	84.92	89.13	90.48		66.67	85.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	92.41	93.48	95.24		83.33	90.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
92.41	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
84.92	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T16,T18
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T18
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T16,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T16,T18

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T16,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T18
1	0	Covered	T14,T16,T18
1	1	Covered	T14,T16,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T18
0	1	Covered	T76,T50,T77
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T18
0	1	Covered	T14,T16,T18
1	0	Covered	T43,T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T16,T18
1	-	Covered	T14,T16,T18

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
92.41	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T21,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T21,T58

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T21,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T58
1	0	Covered	T14,T28,T29
1	1	Covered	T19,T21,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T58
0	1	Covered	T67,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T58
0	1	Covered	T58,T22,T82
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T58
1	-	Covered	T58,T22,T82

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T23
1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T23
1	0	Covered	T16,T18,T23
1	1	Covered	T16,T18,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T23
0	1	Covered	T16,T23,T52
1	0	Covered	T16,T18,T23

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T23
0	1	Covered	T16,T18,T23
1	0	Covered	T83,T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T23
1	-	Covered	T16,T18,T23

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T28,T29,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T62,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T20
1	0	Covered	T28,T29,T16
1	1	Covered	T15,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T62,T63
0	1	Covered	T63,T51,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T62,T63
0	1	Unreachable
1	0	Covered	T15,T62,T63

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
84.92	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T22,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T22,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T22,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T22
1	0	Covered	T14,T28,T29
1	1	Covered	T19,T22,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T49,T45
0	1	Covered	T22,T48,T66
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T49,T45
0	1	Covered	T45,T46,T48
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T49,T45
1	-	Covered	T45,T46,T48

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T28,T29,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T28,T29,T15
1	1	Covered	T28,T29,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T20,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T20
1	0	Covered	T28,T29,T32
1	1	Covered	T15,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T63
0	1	Covered	T15,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T63
0	1	Unreachable
1	0	Covered	T20,T62,T63

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T29,T15
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T15
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T15,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T17,T20,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T20
1	0	Covered	T14,T28,T29
1	1	Covered	T15,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T62
0	1	Covered	T89,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T62
0	1	Unreachable
1	0	Covered	T17,T20,T62

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
92.41	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
84.92	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T58
0	1	Covered	T19,T21,T58
0	0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T58
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T58
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T92,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T58
DetectSt	-	-	-	-	1	-	-	Covered	T15,T67,T80
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T58
DetectSt	-	-	-	-	0	0	-	Covered	T14,T16,T18
StableSt	-	-	-	-	-	-	1	Covered	T58,T22,T82
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T58
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T16,T17
0	1	Covered	T15,T16,T17
0	0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T18
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T28,T29,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T20,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T17
DetectSt	-	-	-	-	1	-	-	Covered	T16,T18,T23
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T18
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T23
StableSt	-	-	-	-	-	-	1	Covered	T15,T16,T18
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T18
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	179733320	18431	0	0
CntIncr_A	179733320	3350919	0	0
CntNoWrap_A	179733320	162498495	0	0
DetectStDropOut_A	179733320	2183	0	0
DetectedOut_A	179733320	2141087	0	0
DetectedPulseOut_A	179733320	5797	0	0
DisabledIdleSt_A	179733320	148157289	0	0
DisabledNoDetection_A	179733320	148211713	0	0
EnterDebounceSt_A	179733320	9500	0	0
EnterDetectSt_A	179733320	8948	0	0
EnterStableSt_A	179733320	5797	0	0
PulseIsPulse_A	179733320	5797	0	0
StayInStableSt	179733320	2134591	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	62215380	53080	0	0
gen_high_event_sva.HighLevelEvent_A	34564100	31264485	0	0
gen_high_level_sva.HighLevelEvent_A	117517940	106299249	0	0
gen_low_level_sva.LowLevelEvent_A	62215380	56276073	0	0
gen_not_sticky_sva.StableStDropOut_A	158994860	4818	0	0
gen_sticky_sva.StableStDropOut_A	20738460	1926383	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	18431	0	0
T14	3575	5	0	0
T15	72309	0	0	0
T16	51992	18	0	0
T17	2178	0	0	0
T18	13400	48	0	0
T19	96134	0	0	0
T20	0	8	0	0
T23	5841	34	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	23	0	0
T41	0	34	0	0
T42	0	6	0	0
T51	0	1	0	0
T54	0	7	0	0
T58	685	4	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	4	0	0
T82	713	2	0	0
T92	0	5	0	0
T94	1531	3	0	0
T95	0	2	0	0
T96	0	6	0	0
T97	0	2	0	0
T98	0	21	0	0
T99	0	4	0	0
T100	0	4	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	3350919	0	0
T14	3575	70	0	0
T15	72309	0	0	0
T16	51992	564	0	0
T17	2178	0	0	0
T18	13400	1320	0	0
T19	96134	0	0	0
T20	0	444	0	0
T23	5841	842	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	1463	0	0
T41	0	1047	0	0
T42	0	525	0	0
T51	0	20	0	0
T54	0	289	0	0
T58	685	85	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	91	0	0
T82	713	14	0	0
T92	0	199	0	0
T94	1531	63	0	0
T95	0	98	0	0
T96	0	57435	0	0
T97	0	91	0	0
T98	0	1597	0	0
T99	0	116	0	0
T100	0	83	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	162498495	0	0
T14	92950	17337	0	0
T15	1880034	1869603	0	0
T16	675896	663791	0	0
T17	28314	17876	0	0
T18	174200	163632	0	0
T28	11024	598	0	0
T29	11102	676	0	0
T30	218452	26	0	0
T31	16172	5746	0	0
T32	10816	390	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	2183	0	0
T23	5841	10	0	0
T52	0	6	0	0
T67	29422	3	0	0
T76	5942	1	0	0
T104	0	22	0	0
T105	0	11	0	0
T106	0	19	0	0
T107	0	5	0	0
T108	0	11	0	0
T109	5372	2	0	0
T110	0	5	0	0
T111	0	20	0	0
T112	8436	9	0	0
T113	0	6	0	0
T114	0	3	0	0
T115	0	7	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	5	0	0
T119	0	1	0	0
T120	10556	1	0	0
T121	177592	0	0	0
T122	427	0	0	0
T123	403	0	0	0
T124	492	0	0	0
T125	522	0	0	0
T126	6466	0	0	0
T127	5772	0	0	0
T128	489	0	0	0
T129	715	0	0	0
T130	523	0	0	0
T131	1216	0	0	0
T132	422	0	0	0
T133	402	0	0	0
T134	502	0	0	0
T135	647	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	2141087	0	0
T14	3575	8	0	0
T15	72309	0	0	0
T16	51992	791	0	0
T17	2178	0	0	0
T18	13400	93	0	0
T19	96134	0	0	0
T20	0	113	0	0
T23	5841	0	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	266	0	0
T41	0	3244	0	0
T42	0	25	0	0
T44	0	344	0	0
T50	0	57	0	0
T54	0	174	0	0
T58	685	13	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	18	0	0
T82	713	11	0	0
T92	0	14	0	0
T94	1531	6	0	0
T95	0	1	0	0
T96	0	10	0	0
T97	0	8	0	0
T98	0	214	0	0
T99	0	20	0	0
T100	0	13	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	5797	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	51992	9	0	0
T17	2178	0	0	0
T18	13400	24	0	0
T19	96134	0	0	0
T20	0	3	0	0
T23	5841	0	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	10	0	0
T41	0	17	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	10	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	148157289	0	0
T14	92950	17159	0	0
T15	1880034	1653977	0	0
T16	675896	634340	0	0
T17	28314	15941	0	0
T18	174200	148861	0	0
T28	11024	598	0	0
T29	11102	676	0	0
T30	218452	26	0	0
T31	16172	5746	0	0
T32	10816	390	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	148211713	0	0
T14	92950	17364	0	0
T15	1880034	1654003	0	0
T16	675896	634544	0	0
T17	28314	15967	0	0
T18	174200	148883	0	0
T28	11024	624	0	0
T29	11102	702	0	0
T30	218452	52	0	0
T31	16172	5772	0	0
T32	10816	416	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	9500	0	0
T14	3575	3	0	0
T15	72309	0	0	0
T16	51992	9	0	0
T17	2178	0	0	0
T18	13400	24	0	0
T19	96134	0	0	0
T20	0	5	0	0
T23	5841	17	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	13	0	0
T41	0	17	0	0
T42	0	3	0	0
T51	0	1	0	0
T54	0	4	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	3	0	0
T94	1531	2	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	11	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	8948	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	51992	9	0	0
T17	2178	0	0	0
T18	13400	24	0	0
T19	96134	0	0	0
T20	0	3	0	0
T23	5841	0	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	10	0	0
T41	0	17	0	0
T42	0	3	0	0
T44	0	7	0	0
T54	0	3	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T76	0	1	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	10	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	5797	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	51992	9	0	0
T17	2178	0	0	0
T18	13400	24	0	0
T19	96134	0	0	0
T20	0	3	0	0
T23	5841	0	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	10	0	0
T41	0	17	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	10	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	5797	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	51992	9	0	0
T17	2178	0	0	0
T18	13400	24	0	0
T19	96134	0	0	0
T20	0	3	0	0
T23	5841	0	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	10	0	0
T41	0	17	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	10	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	179733320	2134591	0	0
T14	3575	6	0	0
T15	72309	0	0	0
T16	51992	781	0	0
T17	2178	0	0	0
T18	13400	69	0	0
T19	96134	0	0	0
T20	0	110	0	0
T23	5841	0	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	256	0	0
T41	0	3221	0	0
T42	0	22	0	0
T44	0	337	0	0
T50	0	49	0	0
T54	0	171	0	0
T58	685	11	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	16	0	0
T82	713	10	0	0
T92	0	12	0	0
T94	1531	5	0	0
T96	0	7	0	0
T97	0	7	0	0
T98	0	204	0	0
T99	0	18	0	0
T100	0	11	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T136	0	20	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62215380	53080	0	0
T14	10725	9	0	0
T15	650781	4	0	0
T16	233964	185	0	0
T17	9801	20	0	0
T18	60300	197	0	0
T19	576804	1	0	0
T20	0	118	0	0
T21	0	2	0	0
T28	3816	21	0	0
T29	3843	17	0	0
T30	75618	0	0	0
T31	5598	5	0	0
T32	3744	21	0	0
T55	0	26	0	0
T56	0	47	0	0
T57	0	13	0	0
T59	0	7	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34564100	31264485	0	0
T14	17875	3375	0	0
T15	361545	359545	0	0
T16	129980	127720	0	0
T17	5445	3445	0	0
T18	33500	31500	0	0
T28	2120	120	0	0
T29	2135	135	0	0
T30	42010	10	0	0
T31	3110	1110	0	0
T32	2080	80	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117517940	106299249	0	0
T14	60775	11475	0	0
T15	1229253	1222453	0	0
T16	441932	434248	0	0
T17	18513	11713	0	0
T18	113900	107100	0	0
T28	7208	408	0	0
T29	7259	459	0	0
T30	142834	34	0	0
T31	10574	3774	0	0
T32	7072	272	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62215380	56276073	0	0
T14	32175	6075	0	0
T15	650781	647181	0	0
T16	233964	229896	0	0
T17	9801	6201	0	0
T18	60300	56700	0	0
T28	3816	216	0	0
T29	3843	243	0	0
T30	75618	18	0	0
T31	5598	1998	0	0
T32	3744	144	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158994860	4818	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	51992	8	0	0
T17	2178	0	0	0
T18	13400	24	0	0
T19	96134	0	0	0
T20	0	3	0	0
T23	5841	0	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	0	10	0	0
T41	0	11	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T58	685	2	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T63	0	2	0	0
T82	713	1	0	0
T92	0	2	0	0
T94	1531	1	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	10	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20738460	1926383	0	0
T15	72309	39	0	0
T16	25996	0	0	0
T17	2178	153	0	0
T18	13400	0	0	0
T19	192268	0	0	0
T20	43140	1185	0	0
T21	1142	0	0	0
T31	622	0	0	0
T32	832	0	0	0
T40	21099	0	0	0
T51	0	240	0	0
T55	844	0	0	0
T56	1002	0	0	0
T57	852	0	0	0
T58	1370	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T62	866	205	0	0
T63	0	225	0	0
T64	0	1585	0	0
T65	0	806	0	0
T66	0	257	0	0
T67	0	291	0	0
T92	720	0	0	0
T137	0	275	0	0
T138	0	798	0	0
T139	0	257	0	0
T140	0	52	0	0