Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T51,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T22,T51,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T51,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T49
1	0	Covered	T14,T28,T29
1	1	Covered	T22,T51,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T51,T48
0	1	Covered	T81,T155,T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T51,T48
0	1	Covered	T48,T47,T192
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T51,T48
1	-	Covered	T48,T47,T192

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T51,T48
0	1	Covered	T22,T51,T48
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T51,T48
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T51,T48
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T51,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T67,T143,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T51,T48
DetectSt	-	-	-	-	1	-	-	Covered	T81,T155,T191
DetectSt	-	-	-	-	0	1	-	Covered	T22,T51,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T47,T192
StableSt	-	-	-	-	-	-	0	Covered	T22,T51,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	90	0	0
CntIncr_A	6912820	244855	0	0
CntNoWrap_A	6912820	6250561	0	0
DetectStDropOut_A	6912820	3	0	0
DetectedOut_A	6912820	69344	0	0
DetectedPulseOut_A	6912820	40	0	0
DisabledIdleSt_A	6912820	5458572	0	0
DisabledNoDetection_A	6912820	5460763	0	0
EnterDebounceSt_A	6912820	47	0	0
EnterDetectSt_A	6912820	43	0	0
EnterStableSt_A	6912820	40	0	0
PulseIsPulse_A	6912820	40	0	0
StayInStableSt	6912820	69285	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	90	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T51	0	2	0	0
T67	0	3	0	0
T80	0	2	0	0
T81	0	4	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T143	0	1	0	0
T165	0	2	0	0
T192	0	4	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	244855	0	0
T22	4822	34	0	0
T23	5841	0	0	0
T47	0	100	0	0
T48	0	28	0	0
T51	0	24	0	0
T67	0	66	0	0
T80	0	62	0	0
T81	0	126360	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T143	0	38789	0	0
T165	0	73	0	0
T192	0	100	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250561	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3	0	0
T81	341286	1	0	0
T155	14840	1	0	0
T191	11136	1	0	0
T196	428	0	0	0
T197	522	0	0	0
T198	404	0	0	0
T199	522	0	0	0
T200	402	0	0	0
T201	669	0	0	0
T202	409	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	69344	0	0
T22	4822	185	0	0
T23	5841	0	0	0
T47	0	81	0	0
T48	0	11	0	0
T51	0	43	0	0
T67	0	101	0	0
T80	0	43	0	0
T81	0	65069	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T144	0	43	0	0
T165	0	185	0	0
T192	0	79	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	40	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T144	0	1	0	0
T165	0	1	0	0
T192	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5458572	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5460763	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T67	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T143	0	1	0	0
T165	0	1	0	0
T192	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	43	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T144	0	1	0	0
T165	0	1	0	0
T192	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	40	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T144	0	1	0	0
T165	0	1	0	0
T192	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	40	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T144	0	1	0	0
T165	0	1	0	0
T192	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	69285	0	0
T22	4822	183	0	0
T23	5841	0	0	0
T47	0	78	0	0
T48	0	10	0	0
T51	0	41	0	0
T67	0	99	0	0
T80	0	41	0	0
T81	0	65067	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T144	0	41	0	0
T165	0	183	0	0
T192	0	76	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	19	0	0
T47	867	1	0	0
T48	615	1	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T76	5942	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T131	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0
T192	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	409	0	0	0
T208	507	0	0	0
T209	506	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T21,T22,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T21,T22,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T21,T22,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T45
1	0	Covered	T14,T28,T29
1	1	Covered	T21,T22,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T45
0	1	Covered	T22,T51,T48
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T22,T45
1	-	Covered	T22,T51,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T45
0	1	Covered	T21,T22,T45
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T45
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T45
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T22,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T210,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T21,T22,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T51,T48
StableSt	-	-	-	-	-	-	0	Covered	T21,T22,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	120	0	0
CntIncr_A	6912820	49370	0	0
CntNoWrap_A	6912820	6250531	0	0
DetectStDropOut_A	6912820	0	0	0
DetectedOut_A	6912820	43243	0	0
DetectedPulseOut_A	6912820	57	0	0
DisabledIdleSt_A	6912820	6149217	0	0
DisabledNoDetection_A	6912820	6151413	0	0
EnterDebounceSt_A	6912820	63	0	0
EnterDetectSt_A	6912820	57	0	0
EnterStableSt_A	6912820	57	0	0
PulseIsPulse_A	6912820	57	0	0
StayInStableSt	6912820	43163	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	3005	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	120	0	0
T21	571	2	0	0
T22	4822	2	0	0
T45	0	2	0	0
T47	0	4	0	0
T48	0	4	0	0
T51	0	2	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	4	0	0
T67	0	4	0	0
T166	0	2	0	0
T192	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	49370	0	0
T21	571	46	0	0
T22	4822	34	0	0
T45	0	94	0	0
T47	0	100	0	0
T48	0	56	0	0
T51	0	24	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	194	0	0
T67	0	66	0	0
T166	0	49	0	0
T192	0	28	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250531	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	43243	0	0
T21	571	40	0	0
T22	4822	18	0	0
T45	0	378	0	0
T47	0	174	0	0
T48	0	108	0	0
T51	0	8	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	299	0	0
T67	0	86	0	0
T166	0	225	0	0
T192	0	92	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	57	0	0
T21	571	1	0	0
T22	4822	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T166	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6149217	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6151413	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	63	0	0
T21	571	1	0	0
T22	4822	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T166	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	57	0	0
T21	571	1	0	0
T22	4822	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T166	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	57	0	0
T21	571	1	0	0
T22	4822	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T166	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	57	0	0
T21	571	1	0	0
T22	4822	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	1	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T166	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	43163	0	0
T21	571	38	0	0
T22	4822	17	0	0
T45	0	376	0	0
T47	0	172	0	0
T48	0	105	0	0
T51	0	7	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	297	0	0
T67	0	84	0	0
T166	0	223	0	0
T192	0	90	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3005	0	0
T15	72309	0	0	0
T16	25996	0	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	0	3	0	0
T21	0	1	0	0
T28	424	2	0	0
T29	427	1	0	0
T30	8402	0	0	0
T31	622	5	0	0
T32	416	2	0	0
T55	0	2	0	0
T56	0	6	0	0
T57	0	3	0	0
T59	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	32	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T180	0	1	0	0
T190	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T203	0	2	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T28,T29,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T28,T29,T15
1	1	Covered	T28,T29,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T45,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T22,T45,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T45,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T45,T51
1	0	Covered	T28,T29,T15
1	1	Covered	T22,T45,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T48,T50
0	1	Covered	T22,T48,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T48,T50
0	1	Covered	T45,T50,T80
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T48,T50
1	-	Covered	T45,T50,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T45,T48
0	1	Covered	T22,T45,T48
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T45,T48
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T45,T48
IdleSt	0	-	-	-	-	-	-	Covered	T28,T29,T15
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T45,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T81,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T45,T48
DetectSt	-	-	-	-	1	-	-	Covered	T22,T48,T180
DetectSt	-	-	-	-	0	1	-	Covered	T45,T48,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T50,T80
StableSt	-	-	-	-	-	-	0	Covered	T45,T48,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	115	0	0
CntIncr_A	6912820	264148	0	0
CntNoWrap_A	6912820	6250536	0	0
DetectStDropOut_A	6912820	3	0	0
DetectedOut_A	6912820	193240	0	0
DetectedPulseOut_A	6912820	50	0	0
DisabledIdleSt_A	6912820	5471494	0	0
DisabledNoDetection_A	6912820	5473689	0	0
EnterDebounceSt_A	6912820	62	0	0
EnterDetectSt_A	6912820	53	0	0
EnterStableSt_A	6912820	50	0	0
PulseIsPulse_A	6912820	50	0	0
StayInStableSt	6912820	193172	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	115	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T45	0	4	0	0
T48	0	4	0	0
T50	0	5	0	0
T80	0	2	0	0
T81	0	3	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	4	0	0
T167	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T211	0	2	0	0
T212	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	264148	0	0
T22	4822	34	0	0
T23	5841	0	0	0
T45	0	188	0	0
T48	0	56	0	0
T50	0	144	0	0
T80	0	62	0	0
T81	0	126360	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	163	0	0
T167	0	53	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T211	0	17	0	0
T212	0	144	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250536	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T48	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T180	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	193240	0	0
T45	881	144	0	0
T47	867	0	0	0
T48	615	79	0	0
T50	0	113	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T80	0	43	0	0
T81	0	128250	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T165	0	213	0	0
T167	0	116	0	0
T171	505	0	0	0
T189	0	39	0	0
T207	409	0	0	0
T211	0	41	0	0
T212	0	361	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	50	0	0
T45	881	2	0	0
T47	867	0	0	0
T48	615	1	0	0
T50	0	2	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T171	505	0	0	0
T189	0	1	0	0
T207	409	0	0	0
T211	0	1	0	0
T212	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5471494	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5473689	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	62	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	0	3	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T211	0	1	0	0
T212	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T211	0	1	0	0
T212	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	50	0	0
T45	881	2	0	0
T47	867	0	0	0
T48	615	1	0	0
T50	0	2	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T171	505	0	0	0
T189	0	1	0	0
T207	409	0	0	0
T211	0	1	0	0
T212	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	50	0	0
T45	881	2	0	0
T47	867	0	0	0
T48	615	1	0	0
T50	0	2	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T171	505	0	0	0
T189	0	1	0	0
T207	409	0	0	0
T211	0	1	0	0
T212	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	193172	0	0
T45	881	141	0	0
T47	867	0	0	0
T48	615	77	0	0
T50	0	110	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T80	0	42	0	0
T81	0	128249	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T165	0	211	0	0
T167	0	114	0	0
T171	505	0	0	0
T189	0	38	0	0
T207	409	0	0	0
T211	0	39	0	0
T212	0	358	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	30	0	0
T45	881	1	0	0
T50	47826	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T143	0	1	0	0
T165	0	2	0	0
T171	505	0	0	0
T189	0	1	0	0
T203	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	491	0	0	0
T215	496	0	0	0
T216	504	0	0	0
T217	406	0	0	0
T218	11491	0	0	0
T219	491	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T29,T15
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T15
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T45,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T22,T45,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T45,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T49
1	0	Covered	T14,T28,T29
1	1	Covered	T22,T45,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T45,T48
0	1	Covered	T220
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T45,T48
0	1	Covered	T45,T48,T50
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T45,T48
1	-	Covered	T45,T48,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T45,T48
0	1	Covered	T22,T45,T48
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T45,T48
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T45,T48
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T45,T48
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T45,T48
DetectSt	-	-	-	-	1	-	-	Covered	T220
DetectSt	-	-	-	-	0	1	-	Covered	T22,T45,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T48,T50
StableSt	-	-	-	-	-	-	0	Covered	T22,T45,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	52	0	0
CntIncr_A	6912820	1644	0	0
CntNoWrap_A	6912820	6250599	0	0
DetectStDropOut_A	6912820	1	0	0
DetectedOut_A	6912820	2024	0	0
DetectedPulseOut_A	6912820	25	0	0
DisabledIdleSt_A	6912820	6197673	0	0
DisabledNoDetection_A	6912820	6199873	0	0
EnterDebounceSt_A	6912820	26	0	0
EnterDetectSt_A	6912820	26	0	0
EnterStableSt_A	6912820	25	0	0
PulseIsPulse_A	6912820	25	0	0
StayInStableSt	6912820	1987	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	6780	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	52	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	0	4	0	0
T78	0	2	0	0
T80	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	4	0	0
T168	0	4	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	2	0	0
T221	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1644	0	0
T22	4822	34	0	0
T23	5841	0	0	0
T45	0	94	0	0
T48	0	28	0	0
T50	0	114	0	0
T78	0	33	0	0
T80	0	62	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	163	0	0
T168	0	94	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	96	0	0
T221	0	122	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250599	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1	0	0
T220	11806	1	0	0
T222	675	0	0	0
T223	16215	0	0	0
T224	1076	0	0	0
T225	563	0	0	0
T226	486	0	0	0
T227	446	0	0	0
T228	1770	0	0	0
T229	22139	0	0	0
T230	645	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2024	0	0
T22	4822	72	0	0
T23	5841	0	0	0
T45	0	44	0	0
T48	0	40	0	0
T50	0	289	0	0
T78	0	14	0	0
T80	0	77	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	330	0	0
T168	0	83	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	165	0	0
T221	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	25	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T168	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	1	0	0
T221	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6197673	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6199873	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	26	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T168	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	1	0	0
T221	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	26	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T168	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	1	0	0
T221	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	25	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T168	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	1	0	0
T221	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	25	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T168	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	1	0	0
T221	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1987	0	0
T22	4822	70	0	0
T23	5841	0	0	0
T45	0	43	0	0
T48	0	39	0	0
T50	0	286	0	0
T78	0	13	0	0
T80	0	75	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	326	0	0
T168	0	81	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T213	0	164	0	0
T221	0	84	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6780	0	0
T15	72309	1	0	0
T16	25996	26	0	0
T17	1089	5	0	0
T18	6700	33	0	0
T19	96134	0	0	0
T20	0	14	0	0
T28	424	3	0	0
T29	427	3	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	2	0	0
T55	0	4	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	11	0	0
T45	881	1	0	0
T47	867	0	0	0
T48	615	1	0	0
T50	0	1	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T117	0	1	0	0
T131	0	1	0	0
T155	0	1	0	0
T168	0	2	0	0
T171	505	0	0	0
T207	409	0	0	0
T213	0	1	0	0
T221	0	1	0	0
T231	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T19,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T19,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T45,T46
1	0	Covered	T14,T28,T29
1	1	Covered	T19,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T45,T46
0	1	Covered	T190
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T45,T46
0	1	Covered	T45,T46,T50
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T45,T46
1	-	Covered	T45,T46,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T45,T46
0	1	Covered	T19,T45,T46
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T45,T46
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T221,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T45,T46
DetectSt	-	-	-	-	1	-	-	Covered	T190
DetectSt	-	-	-	-	0	1	-	Covered	T19,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T46,T50
StableSt	-	-	-	-	-	-	0	Covered	T19,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	104	0	0
CntIncr_A	6912820	331173	0	0
CntNoWrap_A	6912820	6250547	0	0
DetectStDropOut_A	6912820	1	0	0
DetectedOut_A	6912820	53833	0	0
DetectedPulseOut_A	6912820	49	0	0
DisabledIdleSt_A	6912820	5331512	0	0
DisabledNoDetection_A	6912820	5333715	0	0
EnterDebounceSt_A	6912820	54	0	0
EnterDetectSt_A	6912820	50	0	0
EnterStableSt_A	6912820	49	0	0
PulseIsPulse_A	6912820	49	0	0
StayInStableSt	6912820	53770	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	104	0	0
T19	96134	2	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	3	0	0
T46	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	4	0	0
T166	0	2	0	0
T167	0	2	0	0
T211	0	2	0	0
T232	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	331173	0	0
T19	96134	47248	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	188	0	0
T46	0	36	0	0
T50	0	57	0	0
T51	0	24	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	126360	0	0
T166	0	49	0	0
T167	0	53	0	0
T211	0	17	0	0
T232	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250547	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1	0	0
T180	820	0	0	0
T183	634	0	0	0
T184	444	0	0	0
T185	449	0	0	0
T186	506	0	0	0
T187	59481	0	0	0
T188	23680	0	0	0
T190	279986	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53833	0	0
T19	96134	41	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	28	0	0
T46	0	144	0	0
T50	0	274	0	0
T51	0	43	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	1885	0	0
T166	0	224	0	0
T167	0	115	0	0
T211	0	3	0	0
T232	0	206	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	49	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T211	0	1	0	0
T232	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5331512	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5333715	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	54	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	2	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T211	0	1	0	0
T232	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	50	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T211	0	1	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	49	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T211	0	1	0	0
T232	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	49	0	0
T19	96134	1	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T211	0	1	0	0
T232	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53770	0	0
T19	96134	39	0	0
T20	14380	0	0	0
T21	571	0	0	0
T45	0	27	0	0
T46	0	143	0	0
T50	0	273	0	0
T51	0	41	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T81	0	1883	0	0
T166	0	222	0	0
T167	0	113	0	0
T211	0	2	0	0
T232	0	205	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	33	0	0
T45	881	1	0	0
T46	756	1	0	0
T50	47826	1	0	0
T54	24414	0	0	0
T81	0	2	0	0
T95	724	0	0	0
T143	0	1	0	0
T165	0	1	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T211	0	1	0	0
T213	0	2	0	0
T221	0	1	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T49,T45,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T49,T45,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T49,T45,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T49
1	0	Covered	T14,T28,T29
1	1	Covered	T49,T45,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T45,T48
0	1	Covered	T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T45,T48
0	1	Covered	T45,T48,T47
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T45,T48
1	-	Covered	T45,T48,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T49,T45,T48
0	1	Covered	T49,T45,T48
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T45,T48
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T49,T45,T48
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T45,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T190
DebounceSt	-	0	0	-	-	-	-	Covered	T49,T45,T48
DetectSt	-	-	-	-	1	-	-	Covered	T80
DetectSt	-	-	-	-	0	1	-	Covered	T49,T45,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T48,T47
StableSt	-	-	-	-	-	-	0	Covered	T49,T45,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	97	0	0
CntIncr_A	6912820	206224	0	0
CntNoWrap_A	6912820	6250554	0	0
DetectStDropOut_A	6912820	1	0	0
DetectedOut_A	6912820	66973	0	0
DetectedPulseOut_A	6912820	47	0	0
DisabledIdleSt_A	6912820	5470978	0	0
DisabledNoDetection_A	6912820	5473167	0	0
EnterDebounceSt_A	6912820	49	0	0
EnterDetectSt_A	6912820	48	0	0
EnterStableSt_A	6912820	47	0	0
PulseIsPulse_A	6912820	47	0	0
StayInStableSt	6912820	66899	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	6361	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	97	0	0
T40	21099	0	0	0
T45	881	4	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	3627	2	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	2	0	0
T67	0	4	0	0
T80	0	6	0	0
T81	0	4	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	2	0	0
T211	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	206224	0	0
T40	21099	0	0	0
T45	881	188	0	0
T47	0	50	0	0
T48	0	28	0	0
T49	3627	14	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	97	0	0
T67	0	66	0	0
T80	0	170	0	0
T81	0	126360	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	84	0	0
T211	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250554	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1	0	0
T80	1789	1	0	0
T81	341286	0	0	0
T137	1047	0	0	0
T196	428	0	0	0
T197	522	0	0	0
T232	1202	0	0	0
T233	14558	0	0	0
T234	502	0	0	0
T235	522	0	0	0
T236	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	66973	0	0
T40	21099	0	0	0
T45	881	83	0	0
T47	0	34	0	0
T48	0	39	0	0
T49	3627	146	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	298	0	0
T67	0	191	0	0
T80	0	86	0	0
T81	0	63266	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	41	0	0
T211	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47	0	0
T40	21099	0	0	0
T45	881	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	1	0	0
T211	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5470978	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5473167	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	49	0	0
T40	21099	0	0	0
T45	881	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T80	0	3	0	0
T81	0	2	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	1	0	0
T211	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	48	0	0
T40	21099	0	0	0
T45	881	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T80	0	3	0	0
T81	0	2	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	1	0	0
T211	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47	0	0
T40	21099	0	0	0
T45	881	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	1	0	0
T211	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47	0	0
T40	21099	0	0	0
T45	881	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	1	0	0
T211	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	66899	0	0
T40	21099	0	0	0
T45	881	80	0	0
T47	0	33	0	0
T48	0	38	0	0
T49	3627	144	0	0
T52	7733	0	0	0
T62	866	0	0	0
T66	0	297	0	0
T67	0	188	0	0
T80	0	83	0	0
T81	0	63263	0	0
T92	720	0	0	0
T95	724	0	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T182	0	39	0	0
T211	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6361	0	0
T14	3575	3	0	0
T15	72309	0	0	0
T16	25996	20	0	0
T17	1089	0	0	0
T18	6700	29	0	0
T20	0	12	0	0
T28	424	2	0	0
T29	427	2	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	3	0	0
T55	0	3	0	0
T56	0	5	0	0
T57	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	18	0	0
T45	881	1	0	0
T47	867	1	0	0
T48	615	1	0	0
T64	2095	0	0	0
T65	1640	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T171	505	0	0	0
T190	0	1	0	0
T207	409	0	0	0
T221	0	1	0	0
T237	0	1	0	0